Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
1da177e4 LT |
24 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
25 | */ | |
b6ec26fb | 26 | #define pr_fmt(fmt) "ACPI: " fmt |
1da177e4 | 27 | |
1da177e4 | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | #include <linux/acpi.h> |
30 | #include <linux/dmi.h> | |
e2668fb5 | 31 | #include <linux/sched.h> /* need_resched() */ |
ee41eebf | 32 | #include <linux/tick.h> |
4f86d3a8 | 33 | #include <linux/cpuidle.h> |
8b48463f | 34 | #include <acpi/processor.h> |
1da177e4 | 35 | |
3434933b TG |
36 | /* |
37 | * Include the apic definitions for x86 to have the APIC timer related defines | |
38 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
39 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
40 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
41 | */ | |
42 | #ifdef CONFIG_X86 | |
43 | #include <asm/apic.h> | |
44 | #endif | |
45 | ||
1da177e4 | 46 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 47 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 48 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 49 | |
4f86d3a8 LB |
50 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
51 | module_param(max_cstate, uint, 0000); | |
b6835052 | 52 | static unsigned int nocst __read_mostly; |
1da177e4 | 53 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
54 | static int bm_check_disable __read_mostly; |
55 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 56 | |
25de5718 | 57 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 58 | module_param(latency_factor, uint, 0644); |
1da177e4 | 59 | |
3d339dcb DL |
60 | static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); |
61 | ||
25528213 PZ |
62 | static |
63 | DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], acpi_cstate); | |
ac3ebafa | 64 | |
d1896049 TR |
65 | static int disabled_by_idle_boot_param(void) |
66 | { | |
67 | return boot_option_idle_override == IDLE_POLL || | |
d1896049 TR |
68 | boot_option_idle_override == IDLE_HALT; |
69 | } | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
73 | * For now disable this. Probably a bug somewhere else. | |
74 | * | |
75 | * To skip this limit, boot/load with a large max_cstate limit. | |
76 | */ | |
1855256c | 77 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
78 | { |
79 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
80 | return 0; | |
81 | ||
b6ec26fb SH |
82 | pr_notice("%s detected - limiting to C%ld max_cstate." |
83 | " Override with \"processor.max_cstate=%d\"\n", id->ident, | |
84 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 85 | |
3d35600a | 86 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
b0346688 | 91 | static const struct dmi_system_id processor_power_dmi_table[] = { |
876c184b TR |
92 | { set_max_cstate, "Clevo 5600D", { |
93 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
94 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 95 | (void *)2}, |
370d5cd8 AV |
96 | { set_max_cstate, "Pavilion zv5000", { |
97 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
98 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
99 | (void *)1}, | |
100 | { set_max_cstate, "Asus L8400B", { | |
101 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
102 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
103 | (void *)1}, | |
1da177e4 LT |
104 | {}, |
105 | }; | |
106 | ||
4f86d3a8 | 107 | |
2e906655 | 108 | /* |
109 | * Callers should disable interrupts before the call and enable | |
110 | * interrupts after return. | |
111 | */ | |
ddc081a1 VP |
112 | static void acpi_safe_halt(void) |
113 | { | |
ea811747 | 114 | if (!tif_need_resched()) { |
ddc081a1 | 115 | safe_halt(); |
71e93d15 VP |
116 | local_irq_disable(); |
117 | } | |
ddc081a1 VP |
118 | } |
119 | ||
169a0abb TG |
120 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
121 | ||
122 | /* | |
123 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
124 | * This seems to be a common problem on AMD boxen, but other vendors |
125 | * are affected too. We pick the most conservative approach: we assume | |
126 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 127 | */ |
7e275cc4 | 128 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
129 | struct acpi_processor_cx *cx) |
130 | { | |
131 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 132 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 133 | |
db954b58 VP |
134 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
135 | return; | |
136 | ||
02c68a02 | 137 | if (amd_e400_c1e_detected) |
87ad57ba SL |
138 | type = ACPI_STATE_C1; |
139 | ||
169a0abb TG |
140 | /* |
141 | * Check, if one of the previous states already marked the lapic | |
142 | * unstable | |
143 | */ | |
144 | if (pwr->timer_broadcast_on_state < state) | |
145 | return; | |
146 | ||
e585bef8 | 147 | if (cx->type >= type) |
296d93cd | 148 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
149 | } |
150 | ||
918aae42 | 151 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 152 | { |
f833bab8 | 153 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 | 154 | |
ee41eebf TG |
155 | if (pr->power.timer_broadcast_on_state < INT_MAX) |
156 | tick_broadcast_enable(); | |
157 | else | |
158 | tick_broadcast_disable(); | |
e9e2cdb4 TG |
159 | } |
160 | ||
918aae42 HS |
161 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
162 | { | |
163 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
164 | (void *)pr, 1); | |
165 | } | |
166 | ||
e9e2cdb4 | 167 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 168 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
169 | struct acpi_processor_cx *cx, |
170 | int broadcast) | |
171 | { | |
e9e2cdb4 TG |
172 | int state = cx - pr->power.states; |
173 | ||
174 | if (state >= pr->power.timer_broadcast_on_state) { | |
7815701c TG |
175 | if (broadcast) |
176 | tick_broadcast_enter(); | |
177 | else | |
178 | tick_broadcast_exit(); | |
e9e2cdb4 | 179 | } |
169a0abb TG |
180 | } |
181 | ||
182 | #else | |
183 | ||
7e275cc4 | 184 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 185 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
186 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
187 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
188 | struct acpi_processor_cx *cx, |
189 | int broadcast) | |
190 | { | |
191 | } | |
169a0abb TG |
192 | |
193 | #endif | |
194 | ||
592913ec | 195 | #if defined(CONFIG_X86) |
520daf72 | 196 | static void tsc_check_state(int state) |
ddb25f9a AK |
197 | { |
198 | switch (boot_cpu_data.x86_vendor) { | |
199 | case X86_VENDOR_AMD: | |
40fb1715 | 200 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
201 | /* |
202 | * AMD Fam10h TSC will tick in all | |
203 | * C/P/S0/S1 states when this bit is set. | |
204 | */ | |
40fb1715 | 205 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 206 | return; |
40fb1715 | 207 | |
ddb25f9a | 208 | /*FALL THROUGH*/ |
ddb25f9a | 209 | default: |
520daf72 LB |
210 | /* TSC could halt in idle, so notify users */ |
211 | if (state > ACPI_STATE_C1) | |
212 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
213 | } |
214 | } | |
520daf72 LB |
215 | #else |
216 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
217 | #endif |
218 | ||
4be44fcd | 219 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 220 | { |
1da177e4 | 221 | |
1da177e4 | 222 | if (!pr->pblk) |
d550d98d | 223 | return -ENODEV; |
1da177e4 | 224 | |
1da177e4 | 225 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
226 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
227 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
228 | ||
4c033552 VP |
229 | #ifndef CONFIG_HOTPLUG_CPU |
230 | /* | |
231 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 232 | * an SMP system. |
4c033552 | 233 | */ |
ad71860a | 234 | if ((num_online_cpus() > 1) && |
cee324b1 | 235 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 236 | return -ENODEV; |
4c033552 VP |
237 | #endif |
238 | ||
1da177e4 LT |
239 | /* determine C2 and C3 address from pblk */ |
240 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
241 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
242 | ||
243 | /* determine latencies from FADT */ | |
ba494bee BM |
244 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; |
245 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; | |
1da177e4 | 246 | |
5d76b6f6 LB |
247 | /* |
248 | * FADT specified C2 latency must be less than or equal to | |
249 | * 100 microseconds. | |
250 | */ | |
ba494bee | 251 | if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
5d76b6f6 | 252 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 253 | "C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency)); |
5d76b6f6 LB |
254 | /* invalidate C2 */ |
255 | pr->power.states[ACPI_STATE_C2].address = 0; | |
256 | } | |
257 | ||
a6d72c18 LB |
258 | /* |
259 | * FADT supplied C3 latency must be less than or equal to | |
260 | * 1000 microseconds. | |
261 | */ | |
ba494bee | 262 | if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
a6d72c18 | 263 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 264 | "C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency)); |
a6d72c18 LB |
265 | /* invalidate C3 */ |
266 | pr->power.states[ACPI_STATE_C3].address = 0; | |
267 | } | |
268 | ||
1da177e4 LT |
269 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
270 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
271 | pr->power.states[ACPI_STATE_C2].address, | |
272 | pr->power.states[ACPI_STATE_C3].address)); | |
273 | ||
d550d98d | 274 | return 0; |
1da177e4 LT |
275 | } |
276 | ||
991528d7 | 277 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 278 | { |
991528d7 VP |
279 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
280 | /* set the first C-State to C1 */ | |
281 | /* all processors need to support C1 */ | |
282 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
283 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 284 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
285 | } |
286 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 287 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 288 | return 0; |
acf05f4b VP |
289 | } |
290 | ||
4be44fcd | 291 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 292 | { |
6fd8050a | 293 | acpi_status status; |
439913ff | 294 | u64 count; |
cf824788 | 295 | int current_count; |
6fd8050a | 296 | int i, ret = 0; |
4be44fcd LB |
297 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; |
298 | union acpi_object *cst; | |
1da177e4 | 299 | |
1da177e4 | 300 | |
1da177e4 | 301 | if (nocst) |
d550d98d | 302 | return -ENODEV; |
1da177e4 | 303 | |
991528d7 | 304 | current_count = 0; |
1da177e4 LT |
305 | |
306 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
307 | if (ACPI_FAILURE(status)) { | |
308 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 309 | return -ENODEV; |
4be44fcd | 310 | } |
1da177e4 | 311 | |
50dd0969 | 312 | cst = buffer.pointer; |
1da177e4 LT |
313 | |
314 | /* There must be at least 2 elements */ | |
315 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
b6ec26fb | 316 | pr_err("not enough elements in _CST\n"); |
6fd8050a | 317 | ret = -EFAULT; |
1da177e4 LT |
318 | goto end; |
319 | } | |
320 | ||
321 | count = cst->package.elements[0].integer.value; | |
322 | ||
323 | /* Validate number of power states. */ | |
324 | if (count < 1 || count != cst->package.count - 1) { | |
b6ec26fb | 325 | pr_err("count given by _CST is not valid\n"); |
6fd8050a | 326 | ret = -EFAULT; |
1da177e4 LT |
327 | goto end; |
328 | } | |
329 | ||
1da177e4 LT |
330 | /* Tell driver that at least _CST is supported. */ |
331 | pr->flags.has_cst = 1; | |
332 | ||
333 | for (i = 1; i <= count; i++) { | |
334 | union acpi_object *element; | |
335 | union acpi_object *obj; | |
336 | struct acpi_power_register *reg; | |
337 | struct acpi_processor_cx cx; | |
338 | ||
339 | memset(&cx, 0, sizeof(cx)); | |
340 | ||
50dd0969 | 341 | element = &(cst->package.elements[i]); |
1da177e4 LT |
342 | if (element->type != ACPI_TYPE_PACKAGE) |
343 | continue; | |
344 | ||
345 | if (element->package.count != 4) | |
346 | continue; | |
347 | ||
50dd0969 | 348 | obj = &(element->package.elements[0]); |
1da177e4 LT |
349 | |
350 | if (obj->type != ACPI_TYPE_BUFFER) | |
351 | continue; | |
352 | ||
4be44fcd | 353 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
354 | |
355 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 356 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
357 | continue; |
358 | ||
1da177e4 | 359 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 360 | obj = &(element->package.elements[1]); |
1da177e4 LT |
361 | if (obj->type != ACPI_TYPE_INTEGER) |
362 | continue; | |
363 | ||
364 | cx.type = obj->integer.value; | |
991528d7 VP |
365 | /* |
366 | * Some buggy BIOSes won't list C1 in _CST - | |
367 | * Let acpi_processor_get_power_info_default() handle them later | |
368 | */ | |
369 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
370 | current_count++; | |
371 | ||
372 | cx.address = reg->address; | |
373 | cx.index = current_count + 1; | |
374 | ||
bc71bec9 | 375 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
376 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
377 | if (acpi_processor_ffh_cstate_probe | |
378 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 379 | cx.entry_method = ACPI_CSTATE_FFH; |
380 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
381 | /* |
382 | * C1 is a special case where FIXED_HARDWARE | |
383 | * can be handled in non-MWAIT way as well. | |
384 | * In that case, save this _CST entry info. | |
991528d7 VP |
385 | * Otherwise, ignore this info and continue. |
386 | */ | |
bc71bec9 | 387 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 388 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 389 | } else { |
991528d7 VP |
390 | continue; |
391 | } | |
da5e09a1 | 392 | if (cx.type == ACPI_STATE_C1 && |
d1896049 | 393 | (boot_option_idle_override == IDLE_NOMWAIT)) { |
c1e3b377 ZY |
394 | /* |
395 | * In most cases the C1 space_id obtained from | |
396 | * _CST object is FIXED_HARDWARE access mode. | |
397 | * But when the option of idle=halt is added, | |
398 | * the entry_method type should be changed from | |
399 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
400 | * When the option of idle=nomwait is added, |
401 | * the C1 entry_method type should be | |
402 | * CSTATE_HALT. | |
c1e3b377 ZY |
403 | */ |
404 | cx.entry_method = ACPI_CSTATE_HALT; | |
405 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
406 | } | |
4fcb2fcd VP |
407 | } else { |
408 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
409 | cx.address); | |
991528d7 | 410 | } |
1da177e4 | 411 | |
0fda6b40 VP |
412 | if (cx.type == ACPI_STATE_C1) { |
413 | cx.valid = 1; | |
414 | } | |
4fcb2fcd | 415 | |
50dd0969 | 416 | obj = &(element->package.elements[2]); |
1da177e4 LT |
417 | if (obj->type != ACPI_TYPE_INTEGER) |
418 | continue; | |
419 | ||
420 | cx.latency = obj->integer.value; | |
421 | ||
50dd0969 | 422 | obj = &(element->package.elements[3]); |
1da177e4 LT |
423 | if (obj->type != ACPI_TYPE_INTEGER) |
424 | continue; | |
425 | ||
cf824788 JM |
426 | current_count++; |
427 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
428 | ||
429 | /* | |
430 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
431 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
432 | */ | |
433 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
b6ec26fb SH |
434 | pr_warn("Limiting number of power states to max (%d)\n", |
435 | ACPI_PROCESSOR_MAX_POWER); | |
436 | pr_warn("Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
cf824788 JM |
437 | break; |
438 | } | |
1da177e4 LT |
439 | } |
440 | ||
4be44fcd | 441 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 442 | current_count)); |
1da177e4 LT |
443 | |
444 | /* Validate number of power states discovered */ | |
cf824788 | 445 | if (current_count < 2) |
6fd8050a | 446 | ret = -EFAULT; |
1da177e4 | 447 | |
4be44fcd | 448 | end: |
02438d87 | 449 | kfree(buffer.pointer); |
1da177e4 | 450 | |
6fd8050a | 451 | return ret; |
1da177e4 LT |
452 | } |
453 | ||
4be44fcd LB |
454 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
455 | struct acpi_processor_cx *cx) | |
1da177e4 | 456 | { |
ee1ca48f PV |
457 | static int bm_check_flag = -1; |
458 | static int bm_control_flag = -1; | |
02df8b93 | 459 | |
1da177e4 LT |
460 | |
461 | if (!cx->address) | |
d550d98d | 462 | return; |
1da177e4 | 463 | |
1da177e4 LT |
464 | /* |
465 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
466 | * DMA transfers are used by any ISA device to avoid livelock. | |
467 | * Note that we could disable Type-F DMA (as recommended by | |
468 | * the erratum), but this is known to disrupt certain ISA | |
469 | * devices thus we take the conservative approach. | |
470 | */ | |
471 | else if (errata.piix4.fdma) { | |
472 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 473 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 474 | return; |
1da177e4 LT |
475 | } |
476 | ||
02df8b93 | 477 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 478 | if (bm_check_flag == -1) { |
02df8b93 VP |
479 | /* Determine whether bm_check is needed based on CPU */ |
480 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
481 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 482 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
483 | } else { |
484 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 485 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
486 | } |
487 | ||
488 | if (pr->flags.bm_check) { | |
02df8b93 | 489 | if (!pr->flags.bm_control) { |
ed3110ef VP |
490 | if (pr->flags.has_cst != 1) { |
491 | /* bus mastering control is necessary */ | |
492 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
493 | "C3 support requires BM control\n")); | |
494 | return; | |
495 | } else { | |
496 | /* Here we enter C3 without bus mastering */ | |
497 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
498 | "C3 support without BM control\n")); | |
499 | } | |
02df8b93 VP |
500 | } |
501 | } else { | |
02df8b93 VP |
502 | /* |
503 | * WBINVD should be set in fadt, for C3 state to be | |
504 | * supported on when bm_check is not required. | |
505 | */ | |
cee324b1 | 506 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 507 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
508 | "Cache invalidation should work properly" |
509 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 510 | return; |
02df8b93 | 511 | } |
02df8b93 VP |
512 | } |
513 | ||
1da177e4 LT |
514 | /* |
515 | * Otherwise we've met all of our C3 requirements. | |
516 | * Normalize the C3 latency to expidite policy. Enable | |
517 | * checking of bus mastering status (bm_check) so we can | |
518 | * use this in our C3 policy | |
519 | */ | |
520 | cx->valid = 1; | |
4f86d3a8 | 521 | |
31878dd8 LB |
522 | /* |
523 | * On older chipsets, BM_RLD needs to be set | |
524 | * in order for Bus Master activity to wake the | |
525 | * system from C3. Newer chipsets handle DMA | |
526 | * during C3 automatically and BM_RLD is a NOP. | |
527 | * In either case, the proper way to | |
528 | * handle BM_RLD is to set it and leave it set. | |
529 | */ | |
50ffba1b | 530 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 531 | |
d550d98d | 532 | return; |
1da177e4 LT |
533 | } |
534 | ||
1da177e4 LT |
535 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
536 | { | |
537 | unsigned int i; | |
538 | unsigned int working = 0; | |
6eb0a0fd | 539 | |
169a0abb | 540 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 541 | |
a0bf284b | 542 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
543 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
544 | ||
545 | switch (cx->type) { | |
546 | case ACPI_STATE_C1: | |
547 | cx->valid = 1; | |
548 | break; | |
549 | ||
550 | case ACPI_STATE_C2: | |
d22edd29 LB |
551 | if (!cx->address) |
552 | break; | |
cad1525a | 553 | cx->valid = 1; |
1da177e4 LT |
554 | break; |
555 | ||
556 | case ACPI_STATE_C3: | |
557 | acpi_processor_power_verify_c3(pr, cx); | |
558 | break; | |
559 | } | |
7e275cc4 LB |
560 | if (!cx->valid) |
561 | continue; | |
1da177e4 | 562 | |
7e275cc4 LB |
563 | lapic_timer_check_state(i, pr, cx); |
564 | tsc_check_state(cx->type); | |
565 | working++; | |
1da177e4 | 566 | } |
bd663347 | 567 | |
918aae42 | 568 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
569 | |
570 | return (working); | |
571 | } | |
572 | ||
4be44fcd | 573 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
574 | { |
575 | unsigned int i; | |
576 | int result; | |
577 | ||
1da177e4 LT |
578 | |
579 | /* NOTE: the idle thread may not be running while calling | |
580 | * this function */ | |
581 | ||
991528d7 VP |
582 | /* Zero initialize all the C-states info. */ |
583 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
584 | ||
1da177e4 | 585 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 586 | if (result == -ENODEV) |
c5a114f1 | 587 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 588 | |
991528d7 VP |
589 | if (result) |
590 | return result; | |
591 | ||
592 | acpi_processor_get_power_info_default(pr); | |
593 | ||
cf824788 | 594 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 595 | |
1da177e4 LT |
596 | /* |
597 | * if one state of type C2 or C3 is available, mark this | |
598 | * CPU as being "idle manageable" | |
599 | */ | |
600 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 601 | if (pr->power.states[i].valid) { |
1da177e4 | 602 | pr->power.count = i; |
2203d6ed LT |
603 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
604 | pr->flags.power = 1; | |
acf05f4b | 605 | } |
1da177e4 LT |
606 | } |
607 | ||
d550d98d | 608 | return 0; |
1da177e4 LT |
609 | } |
610 | ||
4f86d3a8 LB |
611 | /** |
612 | * acpi_idle_bm_check - checks if bus master activity was detected | |
613 | */ | |
614 | static int acpi_idle_bm_check(void) | |
615 | { | |
616 | u32 bm_status = 0; | |
617 | ||
d3e7e99f LB |
618 | if (bm_check_disable) |
619 | return 0; | |
620 | ||
50ffba1b | 621 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 622 | if (bm_status) |
50ffba1b | 623 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
624 | /* |
625 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
626 | * the true state of bus mastering activity; forcing us to | |
627 | * manually check the BMIDEA bit of each IDE channel. | |
628 | */ | |
629 | else if (errata.piix4.bmisx) { | |
630 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
631 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
632 | bm_status = 1; | |
633 | } | |
634 | return bm_status; | |
635 | } | |
636 | ||
4f86d3a8 | 637 | /** |
b00783fd | 638 | * acpi_idle_do_entry - enter idle state using the appropriate method |
4f86d3a8 | 639 | * @cx: cstate data |
bc71bec9 | 640 | * |
641 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 | 642 | */ |
b00783fd | 643 | static void acpi_idle_do_entry(struct acpi_processor_cx *cx) |
4f86d3a8 | 644 | { |
bc71bec9 | 645 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
646 | /* Call into architectural FFH based C-state */ |
647 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 648 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
649 | acpi_safe_halt(); | |
4f86d3a8 | 650 | } else { |
4f86d3a8 LB |
651 | /* IO port based C-state */ |
652 | inb(cx->address); | |
653 | /* Dummy wait op - must do something useless after P_LVL2 read | |
654 | because chipsets cannot guarantee that STPCLK# signal | |
655 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 656 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 LB |
657 | } |
658 | } | |
659 | ||
1a022e3f BO |
660 | /** |
661 | * acpi_idle_play_dead - enters an ACPI state for long-term idle (i.e. off-lining) | |
662 | * @dev: the target CPU | |
663 | * @index: the index of suggested state | |
664 | */ | |
665 | static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) | |
666 | { | |
6240a10d | 667 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
1a022e3f BO |
668 | |
669 | ACPI_FLUSH_CPU_CACHE(); | |
670 | ||
671 | while (1) { | |
672 | ||
673 | if (cx->entry_method == ACPI_CSTATE_HALT) | |
54f70077 | 674 | safe_halt(); |
1a022e3f BO |
675 | else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { |
676 | inb(cx->address); | |
677 | /* See comment in acpi_idle_do_entry() */ | |
678 | inl(acpi_gbl_FADT.xpm_timer_block.address); | |
679 | } else | |
680 | return -ENODEV; | |
681 | } | |
682 | ||
683 | /* Never reached */ | |
684 | return 0; | |
685 | } | |
686 | ||
adcb2623 RW |
687 | static bool acpi_idle_fallback_to_c1(struct acpi_processor *pr) |
688 | { | |
5f508185 RW |
689 | return IS_ENABLED(CONFIG_HOTPLUG_CPU) && !pr->flags.has_cst && |
690 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED); | |
adcb2623 RW |
691 | } |
692 | ||
4f86d3a8 | 693 | static int c3_cpu_count; |
e12f65f7 | 694 | static DEFINE_RAW_SPINLOCK(c3_lock); |
4f86d3a8 LB |
695 | |
696 | /** | |
697 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
6491bc0c RW |
698 | * @pr: Target processor |
699 | * @cx: Target state context | |
5f508185 | 700 | * @timer_bc: Whether or not to change timer mode to broadcast |
4f86d3a8 | 701 | */ |
6491bc0c | 702 | static void acpi_idle_enter_bm(struct acpi_processor *pr, |
5f508185 | 703 | struct acpi_processor_cx *cx, bool timer_bc) |
4f86d3a8 | 704 | { |
996520c1 VP |
705 | acpi_unlazy_tlb(smp_processor_id()); |
706 | ||
4f86d3a8 LB |
707 | /* |
708 | * Must be done before busmaster disable as we might need to | |
709 | * access HPET ! | |
710 | */ | |
5f508185 RW |
711 | if (timer_bc) |
712 | lapic_timer_state_broadcast(pr, cx, 1); | |
4f86d3a8 | 713 | |
ddc081a1 VP |
714 | /* |
715 | * disable bus master | |
716 | * bm_check implies we need ARB_DIS | |
ddc081a1 VP |
717 | * bm_control implies whether we can do ARB_DIS |
718 | * | |
719 | * That leaves a case where bm_check is set and bm_control is | |
720 | * not set. In that case we cannot do much, we enter C3 | |
721 | * without doing anything. | |
722 | */ | |
2a738352 | 723 | if (pr->flags.bm_control) { |
e12f65f7 | 724 | raw_spin_lock(&c3_lock); |
4f86d3a8 LB |
725 | c3_cpu_count++; |
726 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
727 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 728 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
e12f65f7 | 729 | raw_spin_unlock(&c3_lock); |
ddc081a1 | 730 | } |
4f86d3a8 | 731 | |
ddc081a1 | 732 | acpi_idle_do_entry(cx); |
4f86d3a8 | 733 | |
ddc081a1 | 734 | /* Re-enable bus master arbitration */ |
2a738352 | 735 | if (pr->flags.bm_control) { |
e12f65f7 | 736 | raw_spin_lock(&c3_lock); |
50ffba1b | 737 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 | 738 | c3_cpu_count--; |
e12f65f7 | 739 | raw_spin_unlock(&c3_lock); |
4f86d3a8 | 740 | } |
e978aa7d | 741 | |
5f508185 RW |
742 | if (timer_bc) |
743 | lapic_timer_state_broadcast(pr, cx, 0); | |
6491bc0c RW |
744 | } |
745 | ||
746 | static int acpi_idle_enter(struct cpuidle_device *dev, | |
747 | struct cpuidle_driver *drv, int index) | |
748 | { | |
749 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); | |
750 | struct acpi_processor *pr; | |
751 | ||
752 | pr = __this_cpu_read(processors); | |
753 | if (unlikely(!pr)) | |
754 | return -EINVAL; | |
755 | ||
756 | if (cx->type != ACPI_STATE_C1) { | |
5f508185 | 757 | if (acpi_idle_fallback_to_c1(pr) && num_online_cpus() > 1) { |
6491bc0c RW |
758 | index = CPUIDLE_DRIVER_STATE_START; |
759 | cx = per_cpu(acpi_cstate[index], dev->cpu); | |
760 | } else if (cx->type == ACPI_STATE_C3 && pr->flags.bm_check) { | |
761 | if (cx->bm_sts_skip || !acpi_idle_bm_check()) { | |
5f508185 | 762 | acpi_idle_enter_bm(pr, cx, true); |
6491bc0c RW |
763 | return index; |
764 | } else if (drv->safe_state_index >= 0) { | |
765 | index = drv->safe_state_index; | |
766 | cx = per_cpu(acpi_cstate[index], dev->cpu); | |
767 | } else { | |
768 | acpi_safe_halt(); | |
769 | return -EBUSY; | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
774 | lapic_timer_state_broadcast(pr, cx, 1); | |
775 | ||
776 | if (cx->type == ACPI_STATE_C3) | |
777 | ACPI_FLUSH_CPU_CACHE(); | |
778 | ||
779 | acpi_idle_do_entry(cx); | |
780 | ||
781 | lapic_timer_state_broadcast(pr, cx, 0); | |
782 | ||
e978aa7d | 783 | return index; |
4f86d3a8 LB |
784 | } |
785 | ||
5f508185 RW |
786 | static void acpi_idle_enter_freeze(struct cpuidle_device *dev, |
787 | struct cpuidle_driver *drv, int index) | |
788 | { | |
789 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); | |
790 | ||
791 | if (cx->type == ACPI_STATE_C3) { | |
792 | struct acpi_processor *pr = __this_cpu_read(processors); | |
793 | ||
794 | if (unlikely(!pr)) | |
795 | return; | |
796 | ||
797 | if (pr->flags.bm_check) { | |
798 | acpi_idle_enter_bm(pr, cx, false); | |
799 | return; | |
800 | } else { | |
801 | ACPI_FLUSH_CPU_CACHE(); | |
802 | } | |
803 | } | |
804 | acpi_idle_do_entry(cx); | |
805 | } | |
806 | ||
4f86d3a8 LB |
807 | struct cpuidle_driver acpi_idle_driver = { |
808 | .name = "acpi_idle", | |
809 | .owner = THIS_MODULE, | |
810 | }; | |
811 | ||
812 | /** | |
46bcfad7 DD |
813 | * acpi_processor_setup_cpuidle_cx - prepares and configures CPUIDLE |
814 | * device i.e. per-cpu data | |
815 | * | |
4f86d3a8 | 816 | * @pr: the ACPI processor |
6ef0f086 | 817 | * @dev : the cpuidle device |
4f86d3a8 | 818 | */ |
6ef0f086 DL |
819 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, |
820 | struct cpuidle_device *dev) | |
4f86d3a8 | 821 | { |
9a0b8415 | 822 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 | 823 | struct acpi_processor_cx *cx; |
4f86d3a8 LB |
824 | |
825 | if (!pr->flags.power_setup_done) | |
826 | return -EINVAL; | |
827 | ||
828 | if (pr->flags.power == 0) { | |
829 | return -EINVAL; | |
830 | } | |
831 | ||
b88a634a KRW |
832 | if (!dev) |
833 | return -EINVAL; | |
834 | ||
dcb84f33 | 835 | dev->cpu = pr->id; |
4fcb2fcd | 836 | |
615dfd93 LB |
837 | if (max_cstate == 0) |
838 | max_cstate = 1; | |
839 | ||
4f86d3a8 LB |
840 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
841 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
842 | |
843 | if (!cx->valid) | |
844 | continue; | |
845 | ||
6240a10d | 846 | per_cpu(acpi_cstate[count], dev->cpu) = cx; |
4f86d3a8 | 847 | |
46bcfad7 DD |
848 | count++; |
849 | if (count == CPUIDLE_STATE_MAX) | |
850 | break; | |
851 | } | |
852 | ||
46bcfad7 DD |
853 | if (!count) |
854 | return -EINVAL; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | /** | |
860 | * acpi_processor_setup_cpuidle states- prepares and configures cpuidle | |
861 | * global state data i.e. idle routines | |
862 | * | |
863 | * @pr: the ACPI processor | |
864 | */ | |
865 | static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr) | |
866 | { | |
867 | int i, count = CPUIDLE_DRIVER_STATE_START; | |
868 | struct acpi_processor_cx *cx; | |
869 | struct cpuidle_state *state; | |
870 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
871 | ||
872 | if (!pr->flags.power_setup_done) | |
873 | return -EINVAL; | |
874 | ||
875 | if (pr->flags.power == 0) | |
876 | return -EINVAL; | |
877 | ||
878 | drv->safe_state_index = -1; | |
c7e8bdf5 | 879 | for (i = CPUIDLE_DRIVER_STATE_START; i < CPUIDLE_STATE_MAX; i++) { |
46bcfad7 DD |
880 | drv->states[i].name[0] = '\0'; |
881 | drv->states[i].desc[0] = '\0'; | |
4fcb2fcd VP |
882 | } |
883 | ||
615dfd93 LB |
884 | if (max_cstate == 0) |
885 | max_cstate = 1; | |
886 | ||
4f86d3a8 LB |
887 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
888 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
889 | |
890 | if (!cx->valid) | |
891 | continue; | |
892 | ||
46bcfad7 | 893 | state = &drv->states[count]; |
4f86d3a8 | 894 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
4fcb2fcd | 895 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 896 | state->exit_latency = cx->latency; |
4963f620 | 897 | state->target_residency = cx->latency * latency_factor; |
6491bc0c | 898 | state->enter = acpi_idle_enter; |
4f86d3a8 LB |
899 | |
900 | state->flags = 0; | |
6491bc0c | 901 | if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2) { |
1a022e3f | 902 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 903 | drv->safe_state_index = count; |
4f86d3a8 | 904 | } |
5f508185 RW |
905 | /* |
906 | * Halt-induced C1 is not good for ->enter_freeze, because it | |
907 | * re-enables interrupts on exit. Moreover, C1 is generally not | |
908 | * particularly interesting from the suspend-to-idle angle, so | |
909 | * avoid C1 and the situations in which we may need to fall back | |
910 | * to it altogether. | |
911 | */ | |
912 | if (cx->type != ACPI_STATE_C1 && !acpi_idle_fallback_to_c1(pr)) | |
913 | state->enter_freeze = acpi_idle_enter_freeze; | |
4f86d3a8 LB |
914 | |
915 | count++; | |
9a0b8415 | 916 | if (count == CPUIDLE_STATE_MAX) |
917 | break; | |
4f86d3a8 LB |
918 | } |
919 | ||
46bcfad7 | 920 | drv->state_count = count; |
4f86d3a8 LB |
921 | |
922 | if (!count) | |
923 | return -EINVAL; | |
924 | ||
4f86d3a8 LB |
925 | return 0; |
926 | } | |
927 | ||
46bcfad7 | 928 | int acpi_processor_hotplug(struct acpi_processor *pr) |
4f86d3a8 | 929 | { |
dcb84f33 | 930 | int ret = 0; |
e8b1b59d | 931 | struct cpuidle_device *dev; |
4f86d3a8 | 932 | |
d1896049 | 933 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
934 | return 0; |
935 | ||
bf9b59f2 | 936 | if (nocst) |
4f86d3a8 | 937 | return -ENODEV; |
4f86d3a8 LB |
938 | |
939 | if (!pr->flags.power_setup_done) | |
940 | return -ENODEV; | |
941 | ||
e8b1b59d | 942 | dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 | 943 | cpuidle_pause_and_lock(); |
3d339dcb | 944 | cpuidle_disable_device(dev); |
4f86d3a8 | 945 | acpi_processor_get_power_info(pr); |
dcb84f33 | 946 | if (pr->flags.power) { |
6ef0f086 | 947 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 948 | ret = cpuidle_enable_device(dev); |
dcb84f33 | 949 | } |
4f86d3a8 LB |
950 | cpuidle_resume_and_unlock(); |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
46bcfad7 DD |
955 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
956 | { | |
957 | int cpu; | |
958 | struct acpi_processor *_pr; | |
3d339dcb | 959 | struct cpuidle_device *dev; |
46bcfad7 DD |
960 | |
961 | if (disabled_by_idle_boot_param()) | |
962 | return 0; | |
963 | ||
46bcfad7 DD |
964 | if (nocst) |
965 | return -ENODEV; | |
966 | ||
967 | if (!pr->flags.power_setup_done) | |
968 | return -ENODEV; | |
969 | ||
970 | /* | |
971 | * FIXME: Design the ACPI notification to make it once per | |
972 | * system instead of once per-cpu. This condition is a hack | |
973 | * to make the code that updates C-States be called once. | |
974 | */ | |
975 | ||
9505626d | 976 | if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) { |
46bcfad7 | 977 | |
46bcfad7 DD |
978 | /* Protect against cpu-hotplug */ |
979 | get_online_cpus(); | |
6726655d | 980 | cpuidle_pause_and_lock(); |
46bcfad7 DD |
981 | |
982 | /* Disable all cpuidle devices */ | |
983 | for_each_online_cpu(cpu) { | |
984 | _pr = per_cpu(processors, cpu); | |
985 | if (!_pr || !_pr->flags.power_setup_done) | |
986 | continue; | |
3d339dcb DL |
987 | dev = per_cpu(acpi_cpuidle_device, cpu); |
988 | cpuidle_disable_device(dev); | |
46bcfad7 DD |
989 | } |
990 | ||
991 | /* Populate Updated C-state information */ | |
f427e5f1 | 992 | acpi_processor_get_power_info(pr); |
46bcfad7 DD |
993 | acpi_processor_setup_cpuidle_states(pr); |
994 | ||
995 | /* Enable all cpuidle devices */ | |
996 | for_each_online_cpu(cpu) { | |
997 | _pr = per_cpu(processors, cpu); | |
998 | if (!_pr || !_pr->flags.power_setup_done) | |
999 | continue; | |
1000 | acpi_processor_get_power_info(_pr); | |
1001 | if (_pr->flags.power) { | |
3d339dcb | 1002 | dev = per_cpu(acpi_cpuidle_device, cpu); |
6ef0f086 | 1003 | acpi_processor_setup_cpuidle_cx(_pr, dev); |
3d339dcb | 1004 | cpuidle_enable_device(dev); |
46bcfad7 DD |
1005 | } |
1006 | } | |
46bcfad7 | 1007 | cpuidle_resume_and_unlock(); |
6726655d | 1008 | put_online_cpus(); |
46bcfad7 DD |
1009 | } |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static int acpi_processor_registered; | |
1015 | ||
fe7bf106 | 1016 | int acpi_processor_power_init(struct acpi_processor *pr) |
1da177e4 | 1017 | { |
6fd8050a | 1018 | acpi_status status; |
46bcfad7 | 1019 | int retval; |
3d339dcb | 1020 | struct cpuidle_device *dev; |
b6835052 | 1021 | static int first_run; |
1da177e4 | 1022 | |
d1896049 | 1023 | if (disabled_by_idle_boot_param()) |
36a91358 | 1024 | return 0; |
1da177e4 LT |
1025 | |
1026 | if (!first_run) { | |
1027 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1028 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1029 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1030 | printk(KERN_NOTICE |
1031 | "ACPI: processor limited to max C-state %d\n", | |
1032 | max_cstate); | |
1da177e4 LT |
1033 | first_run++; |
1034 | } | |
1035 | ||
cee324b1 | 1036 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1037 | status = |
cee324b1 | 1038 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1039 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1040 | ACPI_EXCEPTION((AE_INFO, status, |
1041 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1042 | } |
1043 | } | |
1044 | ||
1045 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1046 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1047 | |
1048 | /* | |
1049 | * Install the idle handler if processor power management is supported. | |
1050 | * Note that we use previously set idle handler will be used on | |
1051 | * platforms that only support C1. | |
1052 | */ | |
36a91358 | 1053 | if (pr->flags.power) { |
46bcfad7 DD |
1054 | /* Register acpi_idle_driver if not already registered */ |
1055 | if (!acpi_processor_registered) { | |
1056 | acpi_processor_setup_cpuidle_states(pr); | |
1057 | retval = cpuidle_register_driver(&acpi_idle_driver); | |
1058 | if (retval) | |
1059 | return retval; | |
b6ec26fb SH |
1060 | pr_debug("%s registered with cpuidle\n", |
1061 | acpi_idle_driver.name); | |
46bcfad7 | 1062 | } |
3d339dcb DL |
1063 | |
1064 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1065 | if (!dev) | |
1066 | return -ENOMEM; | |
1067 | per_cpu(acpi_cpuidle_device, pr->id) = dev; | |
1068 | ||
6ef0f086 | 1069 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 1070 | |
46bcfad7 DD |
1071 | /* Register per-cpu cpuidle_device. Cpuidle driver |
1072 | * must already be registered before registering device | |
1073 | */ | |
3d339dcb | 1074 | retval = cpuidle_register_device(dev); |
46bcfad7 DD |
1075 | if (retval) { |
1076 | if (acpi_processor_registered == 0) | |
1077 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1078 | return retval; | |
1079 | } | |
1080 | acpi_processor_registered++; | |
1da177e4 | 1081 | } |
d550d98d | 1082 | return 0; |
1da177e4 LT |
1083 | } |
1084 | ||
38a991b6 | 1085 | int acpi_processor_power_exit(struct acpi_processor *pr) |
1da177e4 | 1086 | { |
3d339dcb DL |
1087 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
1088 | ||
d1896049 | 1089 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1090 | return 0; |
1091 | ||
46bcfad7 | 1092 | if (pr->flags.power) { |
3d339dcb | 1093 | cpuidle_unregister_device(dev); |
46bcfad7 DD |
1094 | acpi_processor_registered--; |
1095 | if (acpi_processor_registered == 0) | |
1096 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1097 | } | |
1da177e4 | 1098 | |
46bcfad7 | 1099 | pr->flags.power_setup_done = 0; |
d550d98d | 1100 | return 0; |
1da177e4 | 1101 | } |