Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
1da177e4 | 31 | #include <linux/module.h> |
1da177e4 LT |
32 | #include <linux/acpi.h> |
33 | #include <linux/dmi.h> | |
e2668fb5 | 34 | #include <linux/sched.h> /* need_resched() */ |
e9e2cdb4 | 35 | #include <linux/clockchips.h> |
4f86d3a8 | 36 | #include <linux/cpuidle.h> |
0a3b15ac | 37 | #include <linux/syscore_ops.h> |
1da177e4 | 38 | |
3434933b TG |
39 | /* |
40 | * Include the apic definitions for x86 to have the APIC timer related defines | |
41 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
42 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
43 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
44 | */ | |
45 | #ifdef CONFIG_X86 | |
46 | #include <asm/apic.h> | |
47 | #endif | |
48 | ||
1da177e4 LT |
49 | #include <acpi/acpi_bus.h> |
50 | #include <acpi/processor.h> | |
51 | ||
a192a958 LB |
52 | #define PREFIX "ACPI: " |
53 | ||
1da177e4 | 54 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 55 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 56 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 57 | |
4f86d3a8 LB |
58 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
59 | module_param(max_cstate, uint, 0000); | |
b6835052 | 60 | static unsigned int nocst __read_mostly; |
1da177e4 | 61 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
62 | static int bm_check_disable __read_mostly; |
63 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 64 | |
25de5718 | 65 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 66 | module_param(latency_factor, uint, 0644); |
1da177e4 | 67 | |
3d339dcb DL |
68 | static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); |
69 | ||
6240a10d AS |
70 | static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], |
71 | acpi_cstate); | |
ac3ebafa | 72 | |
d1896049 TR |
73 | static int disabled_by_idle_boot_param(void) |
74 | { | |
75 | return boot_option_idle_override == IDLE_POLL || | |
d1896049 TR |
76 | boot_option_idle_override == IDLE_HALT; |
77 | } | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
81 | * For now disable this. Probably a bug somewhere else. | |
82 | * | |
83 | * To skip this limit, boot/load with a large max_cstate limit. | |
84 | */ | |
1855256c | 85 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
86 | { |
87 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
88 | return 0; | |
89 | ||
3d35600a | 90 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
91 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
92 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 93 | |
3d35600a | 94 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
95 | |
96 | return 0; | |
97 | } | |
98 | ||
fe7bf106 | 99 | static struct dmi_system_id processor_power_dmi_table[] = { |
876c184b TR |
100 | { set_max_cstate, "Clevo 5600D", { |
101 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
102 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 103 | (void *)2}, |
370d5cd8 AV |
104 | { set_max_cstate, "Pavilion zv5000", { |
105 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
106 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
107 | (void *)1}, | |
108 | { set_max_cstate, "Asus L8400B", { | |
109 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
110 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
111 | (void *)1}, | |
1da177e4 LT |
112 | {}, |
113 | }; | |
114 | ||
4f86d3a8 | 115 | |
2e906655 | 116 | /* |
117 | * Callers should disable interrupts before the call and enable | |
118 | * interrupts after return. | |
119 | */ | |
ddc081a1 VP |
120 | static void acpi_safe_halt(void) |
121 | { | |
122 | current_thread_info()->status &= ~TS_POLLING; | |
123 | /* | |
124 | * TS_POLLING-cleared state must be visible before we | |
125 | * test NEED_RESCHED: | |
126 | */ | |
127 | smp_mb(); | |
71e93d15 | 128 | if (!need_resched()) { |
ddc081a1 | 129 | safe_halt(); |
71e93d15 VP |
130 | local_irq_disable(); |
131 | } | |
ddc081a1 VP |
132 | current_thread_info()->status |= TS_POLLING; |
133 | } | |
134 | ||
169a0abb TG |
135 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
136 | ||
137 | /* | |
138 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
139 | * This seems to be a common problem on AMD boxen, but other vendors |
140 | * are affected too. We pick the most conservative approach: we assume | |
141 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 142 | */ |
7e275cc4 | 143 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
144 | struct acpi_processor_cx *cx) |
145 | { | |
146 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 147 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 148 | |
db954b58 VP |
149 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
150 | return; | |
151 | ||
02c68a02 | 152 | if (amd_e400_c1e_detected) |
87ad57ba SL |
153 | type = ACPI_STATE_C1; |
154 | ||
169a0abb TG |
155 | /* |
156 | * Check, if one of the previous states already marked the lapic | |
157 | * unstable | |
158 | */ | |
159 | if (pwr->timer_broadcast_on_state < state) | |
160 | return; | |
161 | ||
e585bef8 | 162 | if (cx->type >= type) |
296d93cd | 163 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
164 | } |
165 | ||
918aae42 | 166 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 167 | { |
f833bab8 | 168 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
169 | unsigned long reason; |
170 | ||
171 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
172 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
173 | ||
174 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
175 | } |
176 | ||
918aae42 HS |
177 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
178 | { | |
179 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
180 | (void *)pr, 1); | |
181 | } | |
182 | ||
e9e2cdb4 | 183 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 184 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
185 | struct acpi_processor_cx *cx, |
186 | int broadcast) | |
187 | { | |
e9e2cdb4 TG |
188 | int state = cx - pr->power.states; |
189 | ||
190 | if (state >= pr->power.timer_broadcast_on_state) { | |
191 | unsigned long reason; | |
192 | ||
193 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
194 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
195 | clockevents_notify(reason, &pr->id); | |
196 | } | |
169a0abb TG |
197 | } |
198 | ||
199 | #else | |
200 | ||
7e275cc4 | 201 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 202 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
203 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
204 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
205 | struct acpi_processor_cx *cx, |
206 | int broadcast) | |
207 | { | |
208 | } | |
169a0abb TG |
209 | |
210 | #endif | |
211 | ||
0a3b15ac | 212 | #ifdef CONFIG_PM_SLEEP |
815ab0fd LB |
213 | static u32 saved_bm_rld; |
214 | ||
95d45d4c | 215 | static int acpi_processor_suspend(void) |
815ab0fd LB |
216 | { |
217 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
0a3b15ac | 218 | return 0; |
815ab0fd | 219 | } |
0a3b15ac | 220 | |
95d45d4c | 221 | static void acpi_processor_resume(void) |
815ab0fd LB |
222 | { |
223 | u32 resumed_bm_rld; | |
224 | ||
225 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
0a3b15ac RW |
226 | if (resumed_bm_rld == saved_bm_rld) |
227 | return; | |
815ab0fd | 228 | |
0a3b15ac | 229 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); |
815ab0fd | 230 | } |
b04e7bdb | 231 | |
0a3b15ac RW |
232 | static struct syscore_ops acpi_processor_syscore_ops = { |
233 | .suspend = acpi_processor_suspend, | |
234 | .resume = acpi_processor_resume, | |
235 | }; | |
236 | ||
237 | void acpi_processor_syscore_init(void) | |
b04e7bdb | 238 | { |
0a3b15ac | 239 | register_syscore_ops(&acpi_processor_syscore_ops); |
b04e7bdb TG |
240 | } |
241 | ||
0a3b15ac | 242 | void acpi_processor_syscore_exit(void) |
b04e7bdb | 243 | { |
0a3b15ac | 244 | unregister_syscore_ops(&acpi_processor_syscore_ops); |
b04e7bdb | 245 | } |
0a3b15ac | 246 | #endif /* CONFIG_PM_SLEEP */ |
b04e7bdb | 247 | |
592913ec | 248 | #if defined(CONFIG_X86) |
520daf72 | 249 | static void tsc_check_state(int state) |
ddb25f9a AK |
250 | { |
251 | switch (boot_cpu_data.x86_vendor) { | |
252 | case X86_VENDOR_AMD: | |
40fb1715 | 253 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
254 | /* |
255 | * AMD Fam10h TSC will tick in all | |
256 | * C/P/S0/S1 states when this bit is set. | |
257 | */ | |
40fb1715 | 258 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 259 | return; |
40fb1715 | 260 | |
ddb25f9a | 261 | /*FALL THROUGH*/ |
ddb25f9a | 262 | default: |
520daf72 LB |
263 | /* TSC could halt in idle, so notify users */ |
264 | if (state > ACPI_STATE_C1) | |
265 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
266 | } |
267 | } | |
520daf72 LB |
268 | #else |
269 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
270 | #endif |
271 | ||
4be44fcd | 272 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 273 | { |
1da177e4 LT |
274 | |
275 | if (!pr) | |
d550d98d | 276 | return -EINVAL; |
1da177e4 LT |
277 | |
278 | if (!pr->pblk) | |
d550d98d | 279 | return -ENODEV; |
1da177e4 | 280 | |
1da177e4 | 281 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
282 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
283 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
284 | ||
4c033552 VP |
285 | #ifndef CONFIG_HOTPLUG_CPU |
286 | /* | |
287 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 288 | * an SMP system. |
4c033552 | 289 | */ |
ad71860a | 290 | if ((num_online_cpus() > 1) && |
cee324b1 | 291 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 292 | return -ENODEV; |
4c033552 VP |
293 | #endif |
294 | ||
1da177e4 LT |
295 | /* determine C2 and C3 address from pblk */ |
296 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
297 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
298 | ||
299 | /* determine latencies from FADT */ | |
ba494bee BM |
300 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; |
301 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; | |
1da177e4 | 302 | |
5d76b6f6 LB |
303 | /* |
304 | * FADT specified C2 latency must be less than or equal to | |
305 | * 100 microseconds. | |
306 | */ | |
ba494bee | 307 | if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
5d76b6f6 | 308 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 309 | "C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency)); |
5d76b6f6 LB |
310 | /* invalidate C2 */ |
311 | pr->power.states[ACPI_STATE_C2].address = 0; | |
312 | } | |
313 | ||
a6d72c18 LB |
314 | /* |
315 | * FADT supplied C3 latency must be less than or equal to | |
316 | * 1000 microseconds. | |
317 | */ | |
ba494bee | 318 | if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
a6d72c18 | 319 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 320 | "C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency)); |
a6d72c18 LB |
321 | /* invalidate C3 */ |
322 | pr->power.states[ACPI_STATE_C3].address = 0; | |
323 | } | |
324 | ||
1da177e4 LT |
325 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
326 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
327 | pr->power.states[ACPI_STATE_C2].address, | |
328 | pr->power.states[ACPI_STATE_C3].address)); | |
329 | ||
d550d98d | 330 | return 0; |
1da177e4 LT |
331 | } |
332 | ||
991528d7 | 333 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 334 | { |
991528d7 VP |
335 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
336 | /* set the first C-State to C1 */ | |
337 | /* all processors need to support C1 */ | |
338 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
339 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 340 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
341 | } |
342 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 343 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 344 | return 0; |
acf05f4b VP |
345 | } |
346 | ||
4be44fcd | 347 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 348 | { |
4be44fcd | 349 | acpi_status status = 0; |
439913ff | 350 | u64 count; |
cf824788 | 351 | int current_count; |
4be44fcd LB |
352 | int i; |
353 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
354 | union acpi_object *cst; | |
1da177e4 | 355 | |
1da177e4 | 356 | |
1da177e4 | 357 | if (nocst) |
d550d98d | 358 | return -ENODEV; |
1da177e4 | 359 | |
991528d7 | 360 | current_count = 0; |
1da177e4 LT |
361 | |
362 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
363 | if (ACPI_FAILURE(status)) { | |
364 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 365 | return -ENODEV; |
4be44fcd | 366 | } |
1da177e4 | 367 | |
50dd0969 | 368 | cst = buffer.pointer; |
1da177e4 LT |
369 | |
370 | /* There must be at least 2 elements */ | |
371 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 372 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
373 | status = -EFAULT; |
374 | goto end; | |
375 | } | |
376 | ||
377 | count = cst->package.elements[0].integer.value; | |
378 | ||
379 | /* Validate number of power states. */ | |
380 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 381 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
382 | status = -EFAULT; |
383 | goto end; | |
384 | } | |
385 | ||
1da177e4 LT |
386 | /* Tell driver that at least _CST is supported. */ |
387 | pr->flags.has_cst = 1; | |
388 | ||
389 | for (i = 1; i <= count; i++) { | |
390 | union acpi_object *element; | |
391 | union acpi_object *obj; | |
392 | struct acpi_power_register *reg; | |
393 | struct acpi_processor_cx cx; | |
394 | ||
395 | memset(&cx, 0, sizeof(cx)); | |
396 | ||
50dd0969 | 397 | element = &(cst->package.elements[i]); |
1da177e4 LT |
398 | if (element->type != ACPI_TYPE_PACKAGE) |
399 | continue; | |
400 | ||
401 | if (element->package.count != 4) | |
402 | continue; | |
403 | ||
50dd0969 | 404 | obj = &(element->package.elements[0]); |
1da177e4 LT |
405 | |
406 | if (obj->type != ACPI_TYPE_BUFFER) | |
407 | continue; | |
408 | ||
4be44fcd | 409 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
410 | |
411 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 412 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
413 | continue; |
414 | ||
1da177e4 | 415 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 416 | obj = &(element->package.elements[1]); |
1da177e4 LT |
417 | if (obj->type != ACPI_TYPE_INTEGER) |
418 | continue; | |
419 | ||
420 | cx.type = obj->integer.value; | |
991528d7 VP |
421 | /* |
422 | * Some buggy BIOSes won't list C1 in _CST - | |
423 | * Let acpi_processor_get_power_info_default() handle them later | |
424 | */ | |
425 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
426 | current_count++; | |
427 | ||
428 | cx.address = reg->address; | |
429 | cx.index = current_count + 1; | |
430 | ||
bc71bec9 | 431 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
432 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
433 | if (acpi_processor_ffh_cstate_probe | |
434 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 435 | cx.entry_method = ACPI_CSTATE_FFH; |
436 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
437 | /* |
438 | * C1 is a special case where FIXED_HARDWARE | |
439 | * can be handled in non-MWAIT way as well. | |
440 | * In that case, save this _CST entry info. | |
991528d7 VP |
441 | * Otherwise, ignore this info and continue. |
442 | */ | |
bc71bec9 | 443 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 444 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 445 | } else { |
991528d7 VP |
446 | continue; |
447 | } | |
da5e09a1 | 448 | if (cx.type == ACPI_STATE_C1 && |
d1896049 | 449 | (boot_option_idle_override == IDLE_NOMWAIT)) { |
c1e3b377 ZY |
450 | /* |
451 | * In most cases the C1 space_id obtained from | |
452 | * _CST object is FIXED_HARDWARE access mode. | |
453 | * But when the option of idle=halt is added, | |
454 | * the entry_method type should be changed from | |
455 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
456 | * When the option of idle=nomwait is added, |
457 | * the C1 entry_method type should be | |
458 | * CSTATE_HALT. | |
c1e3b377 ZY |
459 | */ |
460 | cx.entry_method = ACPI_CSTATE_HALT; | |
461 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
462 | } | |
4fcb2fcd VP |
463 | } else { |
464 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
465 | cx.address); | |
991528d7 | 466 | } |
1da177e4 | 467 | |
0fda6b40 VP |
468 | if (cx.type == ACPI_STATE_C1) { |
469 | cx.valid = 1; | |
470 | } | |
4fcb2fcd | 471 | |
50dd0969 | 472 | obj = &(element->package.elements[2]); |
1da177e4 LT |
473 | if (obj->type != ACPI_TYPE_INTEGER) |
474 | continue; | |
475 | ||
476 | cx.latency = obj->integer.value; | |
477 | ||
50dd0969 | 478 | obj = &(element->package.elements[3]); |
1da177e4 LT |
479 | if (obj->type != ACPI_TYPE_INTEGER) |
480 | continue; | |
481 | ||
cf824788 JM |
482 | current_count++; |
483 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
484 | ||
485 | /* | |
486 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
487 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
488 | */ | |
489 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
490 | printk(KERN_WARNING | |
491 | "Limiting number of power states to max (%d)\n", | |
492 | ACPI_PROCESSOR_MAX_POWER); | |
493 | printk(KERN_WARNING | |
494 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
495 | break; | |
496 | } | |
1da177e4 LT |
497 | } |
498 | ||
4be44fcd | 499 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 500 | current_count)); |
1da177e4 LT |
501 | |
502 | /* Validate number of power states discovered */ | |
cf824788 | 503 | if (current_count < 2) |
6d93c648 | 504 | status = -EFAULT; |
1da177e4 | 505 | |
4be44fcd | 506 | end: |
02438d87 | 507 | kfree(buffer.pointer); |
1da177e4 | 508 | |
d550d98d | 509 | return status; |
1da177e4 LT |
510 | } |
511 | ||
4be44fcd LB |
512 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
513 | struct acpi_processor_cx *cx) | |
1da177e4 | 514 | { |
ee1ca48f PV |
515 | static int bm_check_flag = -1; |
516 | static int bm_control_flag = -1; | |
02df8b93 | 517 | |
1da177e4 LT |
518 | |
519 | if (!cx->address) | |
d550d98d | 520 | return; |
1da177e4 | 521 | |
1da177e4 LT |
522 | /* |
523 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
524 | * DMA transfers are used by any ISA device to avoid livelock. | |
525 | * Note that we could disable Type-F DMA (as recommended by | |
526 | * the erratum), but this is known to disrupt certain ISA | |
527 | * devices thus we take the conservative approach. | |
528 | */ | |
529 | else if (errata.piix4.fdma) { | |
530 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 531 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 532 | return; |
1da177e4 LT |
533 | } |
534 | ||
02df8b93 | 535 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 536 | if (bm_check_flag == -1) { |
02df8b93 VP |
537 | /* Determine whether bm_check is needed based on CPU */ |
538 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
539 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 540 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
541 | } else { |
542 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 543 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
544 | } |
545 | ||
546 | if (pr->flags.bm_check) { | |
02df8b93 | 547 | if (!pr->flags.bm_control) { |
ed3110ef VP |
548 | if (pr->flags.has_cst != 1) { |
549 | /* bus mastering control is necessary */ | |
550 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
551 | "C3 support requires BM control\n")); | |
552 | return; | |
553 | } else { | |
554 | /* Here we enter C3 without bus mastering */ | |
555 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
556 | "C3 support without BM control\n")); | |
557 | } | |
02df8b93 VP |
558 | } |
559 | } else { | |
02df8b93 VP |
560 | /* |
561 | * WBINVD should be set in fadt, for C3 state to be | |
562 | * supported on when bm_check is not required. | |
563 | */ | |
cee324b1 | 564 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 565 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
566 | "Cache invalidation should work properly" |
567 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 568 | return; |
02df8b93 | 569 | } |
02df8b93 VP |
570 | } |
571 | ||
1da177e4 LT |
572 | /* |
573 | * Otherwise we've met all of our C3 requirements. | |
574 | * Normalize the C3 latency to expidite policy. Enable | |
575 | * checking of bus mastering status (bm_check) so we can | |
576 | * use this in our C3 policy | |
577 | */ | |
578 | cx->valid = 1; | |
4f86d3a8 | 579 | |
31878dd8 LB |
580 | /* |
581 | * On older chipsets, BM_RLD needs to be set | |
582 | * in order for Bus Master activity to wake the | |
583 | * system from C3. Newer chipsets handle DMA | |
584 | * during C3 automatically and BM_RLD is a NOP. | |
585 | * In either case, the proper way to | |
586 | * handle BM_RLD is to set it and leave it set. | |
587 | */ | |
50ffba1b | 588 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 589 | |
d550d98d | 590 | return; |
1da177e4 LT |
591 | } |
592 | ||
1da177e4 LT |
593 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
594 | { | |
595 | unsigned int i; | |
596 | unsigned int working = 0; | |
6eb0a0fd | 597 | |
169a0abb | 598 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 599 | |
a0bf284b | 600 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
601 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
602 | ||
603 | switch (cx->type) { | |
604 | case ACPI_STATE_C1: | |
605 | cx->valid = 1; | |
606 | break; | |
607 | ||
608 | case ACPI_STATE_C2: | |
d22edd29 LB |
609 | if (!cx->address) |
610 | break; | |
611 | cx->valid = 1; | |
1da177e4 LT |
612 | break; |
613 | ||
614 | case ACPI_STATE_C3: | |
615 | acpi_processor_power_verify_c3(pr, cx); | |
616 | break; | |
617 | } | |
7e275cc4 LB |
618 | if (!cx->valid) |
619 | continue; | |
1da177e4 | 620 | |
7e275cc4 LB |
621 | lapic_timer_check_state(i, pr, cx); |
622 | tsc_check_state(cx->type); | |
623 | working++; | |
1da177e4 | 624 | } |
bd663347 | 625 | |
918aae42 | 626 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
627 | |
628 | return (working); | |
629 | } | |
630 | ||
4be44fcd | 631 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
632 | { |
633 | unsigned int i; | |
634 | int result; | |
635 | ||
1da177e4 LT |
636 | |
637 | /* NOTE: the idle thread may not be running while calling | |
638 | * this function */ | |
639 | ||
991528d7 VP |
640 | /* Zero initialize all the C-states info. */ |
641 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
642 | ||
1da177e4 | 643 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 644 | if (result == -ENODEV) |
c5a114f1 | 645 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 646 | |
991528d7 VP |
647 | if (result) |
648 | return result; | |
649 | ||
650 | acpi_processor_get_power_info_default(pr); | |
651 | ||
cf824788 | 652 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 653 | |
1da177e4 LT |
654 | /* |
655 | * if one state of type C2 or C3 is available, mark this | |
656 | * CPU as being "idle manageable" | |
657 | */ | |
658 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 659 | if (pr->power.states[i].valid) { |
1da177e4 | 660 | pr->power.count = i; |
2203d6ed LT |
661 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
662 | pr->flags.power = 1; | |
acf05f4b | 663 | } |
1da177e4 LT |
664 | } |
665 | ||
d550d98d | 666 | return 0; |
1da177e4 LT |
667 | } |
668 | ||
4f86d3a8 LB |
669 | /** |
670 | * acpi_idle_bm_check - checks if bus master activity was detected | |
671 | */ | |
672 | static int acpi_idle_bm_check(void) | |
673 | { | |
674 | u32 bm_status = 0; | |
675 | ||
d3e7e99f LB |
676 | if (bm_check_disable) |
677 | return 0; | |
678 | ||
50ffba1b | 679 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 680 | if (bm_status) |
50ffba1b | 681 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
682 | /* |
683 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
684 | * the true state of bus mastering activity; forcing us to | |
685 | * manually check the BMIDEA bit of each IDE channel. | |
686 | */ | |
687 | else if (errata.piix4.bmisx) { | |
688 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
689 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
690 | bm_status = 1; | |
691 | } | |
692 | return bm_status; | |
693 | } | |
694 | ||
4f86d3a8 LB |
695 | /** |
696 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
697 | * @cx: cstate data | |
bc71bec9 | 698 | * |
699 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
700 | */ |
701 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
702 | { | |
dcf30997 SR |
703 | /* Don't trace irqs off for idle */ |
704 | stop_critical_timings(); | |
bc71bec9 | 705 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
706 | /* Call into architectural FFH based C-state */ |
707 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 708 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
709 | acpi_safe_halt(); | |
4f86d3a8 | 710 | } else { |
4f86d3a8 LB |
711 | /* IO port based C-state */ |
712 | inb(cx->address); | |
713 | /* Dummy wait op - must do something useless after P_LVL2 read | |
714 | because chipsets cannot guarantee that STPCLK# signal | |
715 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 716 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 717 | } |
dcf30997 | 718 | start_critical_timings(); |
4f86d3a8 LB |
719 | } |
720 | ||
721 | /** | |
722 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
723 | * @dev: the target CPU | |
46bcfad7 | 724 | * @drv: cpuidle driver containing cpuidle state info |
e978aa7d | 725 | * @index: index of target state |
4f86d3a8 LB |
726 | * |
727 | * This is equivalent to the HALT instruction. | |
728 | */ | |
729 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
46bcfad7 | 730 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
731 | { |
732 | struct acpi_processor *pr; | |
6240a10d | 733 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
9b12e18c | 734 | |
4a6f4fe8 | 735 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
736 | |
737 | if (unlikely(!pr)) | |
e978aa7d | 738 | return -EINVAL; |
4f86d3a8 | 739 | |
7e275cc4 | 740 | lapic_timer_state_broadcast(pr, cx, 1); |
bc71bec9 | 741 | acpi_idle_do_entry(cx); |
e978aa7d | 742 | |
7e275cc4 | 743 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 744 | |
e978aa7d | 745 | return index; |
4f86d3a8 LB |
746 | } |
747 | ||
1a022e3f BO |
748 | |
749 | /** | |
750 | * acpi_idle_play_dead - enters an ACPI state for long-term idle (i.e. off-lining) | |
751 | * @dev: the target CPU | |
752 | * @index: the index of suggested state | |
753 | */ | |
754 | static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) | |
755 | { | |
6240a10d | 756 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
1a022e3f BO |
757 | |
758 | ACPI_FLUSH_CPU_CACHE(); | |
759 | ||
760 | while (1) { | |
761 | ||
762 | if (cx->entry_method == ACPI_CSTATE_HALT) | |
54f70077 | 763 | safe_halt(); |
1a022e3f BO |
764 | else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { |
765 | inb(cx->address); | |
766 | /* See comment in acpi_idle_do_entry() */ | |
767 | inl(acpi_gbl_FADT.xpm_timer_block.address); | |
768 | } else | |
769 | return -ENODEV; | |
770 | } | |
771 | ||
772 | /* Never reached */ | |
773 | return 0; | |
774 | } | |
775 | ||
4f86d3a8 LB |
776 | /** |
777 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
778 | * @dev: the target CPU | |
46bcfad7 | 779 | * @drv: cpuidle driver with cpuidle state information |
e978aa7d | 780 | * @index: the index of suggested state |
4f86d3a8 LB |
781 | */ |
782 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
46bcfad7 | 783 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
784 | { |
785 | struct acpi_processor *pr; | |
6240a10d | 786 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
50629118 | 787 | |
4a6f4fe8 | 788 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
789 | |
790 | if (unlikely(!pr)) | |
e978aa7d | 791 | return -EINVAL; |
e196441b | 792 | |
d306ebc2 PV |
793 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
794 | current_thread_info()->status &= ~TS_POLLING; | |
795 | /* | |
796 | * TS_POLLING-cleared state must be visible before we test | |
797 | * NEED_RESCHED: | |
798 | */ | |
799 | smp_mb(); | |
4f86d3a8 | 800 | |
02cf4f98 LB |
801 | if (unlikely(need_resched())) { |
802 | current_thread_info()->status |= TS_POLLING; | |
e978aa7d | 803 | return -EINVAL; |
02cf4f98 | 804 | } |
4f86d3a8 LB |
805 | } |
806 | ||
e17bcb43 TG |
807 | /* |
808 | * Must be done before busmaster disable as we might need to | |
809 | * access HPET ! | |
810 | */ | |
7e275cc4 | 811 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 812 | |
4f86d3a8 LB |
813 | if (cx->type == ACPI_STATE_C3) |
814 | ACPI_FLUSH_CPU_CACHE(); | |
815 | ||
50629118 VP |
816 | /* Tell the scheduler that we are going deep-idle: */ |
817 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 818 | acpi_idle_do_entry(cx); |
4f86d3a8 | 819 | |
a474a515 | 820 | sched_clock_idle_wakeup_event(0); |
e978aa7d | 821 | |
02cf4f98 LB |
822 | if (cx->entry_method != ACPI_CSTATE_FFH) |
823 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 | 824 | |
7e275cc4 | 825 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 826 | return index; |
4f86d3a8 LB |
827 | } |
828 | ||
829 | static int c3_cpu_count; | |
e12f65f7 | 830 | static DEFINE_RAW_SPINLOCK(c3_lock); |
4f86d3a8 LB |
831 | |
832 | /** | |
833 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
834 | * @dev: the target CPU | |
46bcfad7 | 835 | * @drv: cpuidle driver containing state data |
e978aa7d | 836 | * @index: the index of suggested state |
4f86d3a8 LB |
837 | * |
838 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
839 | */ | |
840 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
46bcfad7 | 841 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
842 | { |
843 | struct acpi_processor *pr; | |
6240a10d | 844 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
50629118 | 845 | |
4a6f4fe8 | 846 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
847 | |
848 | if (unlikely(!pr)) | |
e978aa7d | 849 | return -EINVAL; |
4f86d3a8 | 850 | |
718be4aa | 851 | if (!cx->bm_sts_skip && acpi_idle_bm_check()) { |
46bcfad7 DD |
852 | if (drv->safe_state_index >= 0) { |
853 | return drv->states[drv->safe_state_index].enter(dev, | |
854 | drv, drv->safe_state_index); | |
ddc081a1 | 855 | } else { |
8651f97b | 856 | acpi_safe_halt(); |
75cc5235 | 857 | return -EBUSY; |
ddc081a1 VP |
858 | } |
859 | } | |
860 | ||
d306ebc2 PV |
861 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
862 | current_thread_info()->status &= ~TS_POLLING; | |
863 | /* | |
864 | * TS_POLLING-cleared state must be visible before we test | |
865 | * NEED_RESCHED: | |
866 | */ | |
867 | smp_mb(); | |
4f86d3a8 | 868 | |
02cf4f98 LB |
869 | if (unlikely(need_resched())) { |
870 | current_thread_info()->status |= TS_POLLING; | |
e978aa7d | 871 | return -EINVAL; |
02cf4f98 | 872 | } |
4f86d3a8 LB |
873 | } |
874 | ||
996520c1 VP |
875 | acpi_unlazy_tlb(smp_processor_id()); |
876 | ||
50629118 VP |
877 | /* Tell the scheduler that we are going deep-idle: */ |
878 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
879 | /* |
880 | * Must be done before busmaster disable as we might need to | |
881 | * access HPET ! | |
882 | */ | |
7e275cc4 | 883 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 884 | |
ddc081a1 VP |
885 | /* |
886 | * disable bus master | |
887 | * bm_check implies we need ARB_DIS | |
888 | * !bm_check implies we need cache flush | |
889 | * bm_control implies whether we can do ARB_DIS | |
890 | * | |
891 | * That leaves a case where bm_check is set and bm_control is | |
892 | * not set. In that case we cannot do much, we enter C3 | |
893 | * without doing anything. | |
894 | */ | |
895 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 896 | raw_spin_lock(&c3_lock); |
4f86d3a8 LB |
897 | c3_cpu_count++; |
898 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
899 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 900 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
e12f65f7 | 901 | raw_spin_unlock(&c3_lock); |
ddc081a1 VP |
902 | } else if (!pr->flags.bm_check) { |
903 | ACPI_FLUSH_CPU_CACHE(); | |
904 | } | |
4f86d3a8 | 905 | |
ddc081a1 | 906 | acpi_idle_do_entry(cx); |
4f86d3a8 | 907 | |
ddc081a1 VP |
908 | /* Re-enable bus master arbitration */ |
909 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 910 | raw_spin_lock(&c3_lock); |
50ffba1b | 911 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 | 912 | c3_cpu_count--; |
e12f65f7 | 913 | raw_spin_unlock(&c3_lock); |
4f86d3a8 | 914 | } |
e978aa7d | 915 | |
a474a515 | 916 | sched_clock_idle_wakeup_event(0); |
4f86d3a8 | 917 | |
02cf4f98 LB |
918 | if (cx->entry_method != ACPI_CSTATE_FFH) |
919 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 | 920 | |
7e275cc4 | 921 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 922 | return index; |
4f86d3a8 LB |
923 | } |
924 | ||
925 | struct cpuidle_driver acpi_idle_driver = { | |
926 | .name = "acpi_idle", | |
927 | .owner = THIS_MODULE, | |
928 | }; | |
929 | ||
930 | /** | |
46bcfad7 DD |
931 | * acpi_processor_setup_cpuidle_cx - prepares and configures CPUIDLE |
932 | * device i.e. per-cpu data | |
933 | * | |
4f86d3a8 | 934 | * @pr: the ACPI processor |
6ef0f086 | 935 | * @dev : the cpuidle device |
4f86d3a8 | 936 | */ |
6ef0f086 DL |
937 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, |
938 | struct cpuidle_device *dev) | |
4f86d3a8 | 939 | { |
9a0b8415 | 940 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 | 941 | struct acpi_processor_cx *cx; |
4f86d3a8 LB |
942 | |
943 | if (!pr->flags.power_setup_done) | |
944 | return -EINVAL; | |
945 | ||
946 | if (pr->flags.power == 0) { | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
b88a634a KRW |
950 | if (!dev) |
951 | return -EINVAL; | |
952 | ||
dcb84f33 | 953 | dev->cpu = pr->id; |
4fcb2fcd | 954 | |
615dfd93 LB |
955 | if (max_cstate == 0) |
956 | max_cstate = 1; | |
957 | ||
4f86d3a8 LB |
958 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
959 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
960 | |
961 | if (!cx->valid) | |
962 | continue; | |
963 | ||
964 | #ifdef CONFIG_HOTPLUG_CPU | |
965 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
966 | !pr->flags.has_cst && | |
967 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
968 | continue; | |
1fec74a9 | 969 | #endif |
6240a10d | 970 | per_cpu(acpi_cstate[count], dev->cpu) = cx; |
4f86d3a8 | 971 | |
46bcfad7 DD |
972 | count++; |
973 | if (count == CPUIDLE_STATE_MAX) | |
974 | break; | |
975 | } | |
976 | ||
977 | dev->state_count = count; | |
978 | ||
979 | if (!count) | |
980 | return -EINVAL; | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | /** | |
986 | * acpi_processor_setup_cpuidle states- prepares and configures cpuidle | |
987 | * global state data i.e. idle routines | |
988 | * | |
989 | * @pr: the ACPI processor | |
990 | */ | |
991 | static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr) | |
992 | { | |
993 | int i, count = CPUIDLE_DRIVER_STATE_START; | |
994 | struct acpi_processor_cx *cx; | |
995 | struct cpuidle_state *state; | |
996 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
997 | ||
998 | if (!pr->flags.power_setup_done) | |
999 | return -EINVAL; | |
1000 | ||
1001 | if (pr->flags.power == 0) | |
1002 | return -EINVAL; | |
1003 | ||
1004 | drv->safe_state_index = -1; | |
4fcb2fcd | 1005 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
46bcfad7 DD |
1006 | drv->states[i].name[0] = '\0'; |
1007 | drv->states[i].desc[0] = '\0'; | |
4fcb2fcd VP |
1008 | } |
1009 | ||
615dfd93 LB |
1010 | if (max_cstate == 0) |
1011 | max_cstate = 1; | |
1012 | ||
4f86d3a8 LB |
1013 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1014 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
1015 | |
1016 | if (!cx->valid) | |
1017 | continue; | |
1018 | ||
1019 | #ifdef CONFIG_HOTPLUG_CPU | |
1020 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1021 | !pr->flags.has_cst && | |
1022 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1023 | continue; | |
1fec74a9 | 1024 | #endif |
4f86d3a8 | 1025 | |
46bcfad7 | 1026 | state = &drv->states[count]; |
4f86d3a8 | 1027 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
4fcb2fcd | 1028 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1029 | state->exit_latency = cx->latency; |
4963f620 | 1030 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1031 | |
1032 | state->flags = 0; | |
1033 | switch (cx->type) { | |
1034 | case ACPI_STATE_C1: | |
8e92b660 VP |
1035 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1036 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1037 | ||
4f86d3a8 | 1038 | state->enter = acpi_idle_enter_c1; |
1a022e3f | 1039 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1040 | drv->safe_state_index = count; |
4f86d3a8 LB |
1041 | break; |
1042 | ||
1043 | case ACPI_STATE_C2: | |
4f86d3a8 LB |
1044 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1045 | state->enter = acpi_idle_enter_simple; | |
1a022e3f | 1046 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1047 | drv->safe_state_index = count; |
4f86d3a8 LB |
1048 | break; |
1049 | ||
1050 | case ACPI_STATE_C3: | |
4f86d3a8 | 1051 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
4f86d3a8 LB |
1052 | state->enter = pr->flags.bm_check ? |
1053 | acpi_idle_enter_bm : | |
1054 | acpi_idle_enter_simple; | |
1055 | break; | |
1056 | } | |
1057 | ||
1058 | count++; | |
9a0b8415 | 1059 | if (count == CPUIDLE_STATE_MAX) |
1060 | break; | |
4f86d3a8 LB |
1061 | } |
1062 | ||
46bcfad7 | 1063 | drv->state_count = count; |
4f86d3a8 LB |
1064 | |
1065 | if (!count) | |
1066 | return -EINVAL; | |
1067 | ||
4f86d3a8 LB |
1068 | return 0; |
1069 | } | |
1070 | ||
46bcfad7 | 1071 | int acpi_processor_hotplug(struct acpi_processor *pr) |
4f86d3a8 | 1072 | { |
dcb84f33 | 1073 | int ret = 0; |
e8b1b59d | 1074 | struct cpuidle_device *dev; |
4f86d3a8 | 1075 | |
d1896049 | 1076 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1077 | return 0; |
1078 | ||
4f86d3a8 LB |
1079 | if (!pr) |
1080 | return -EINVAL; | |
1081 | ||
1082 | if (nocst) { | |
1083 | return -ENODEV; | |
1084 | } | |
1085 | ||
1086 | if (!pr->flags.power_setup_done) | |
1087 | return -ENODEV; | |
1088 | ||
e8b1b59d | 1089 | dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 | 1090 | cpuidle_pause_and_lock(); |
3d339dcb | 1091 | cpuidle_disable_device(dev); |
4f86d3a8 | 1092 | acpi_processor_get_power_info(pr); |
dcb84f33 | 1093 | if (pr->flags.power) { |
6ef0f086 | 1094 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 1095 | ret = cpuidle_enable_device(dev); |
dcb84f33 | 1096 | } |
4f86d3a8 LB |
1097 | cpuidle_resume_and_unlock(); |
1098 | ||
1099 | return ret; | |
1100 | } | |
1101 | ||
46bcfad7 DD |
1102 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1103 | { | |
1104 | int cpu; | |
1105 | struct acpi_processor *_pr; | |
3d339dcb | 1106 | struct cpuidle_device *dev; |
46bcfad7 DD |
1107 | |
1108 | if (disabled_by_idle_boot_param()) | |
1109 | return 0; | |
1110 | ||
1111 | if (!pr) | |
1112 | return -EINVAL; | |
1113 | ||
1114 | if (nocst) | |
1115 | return -ENODEV; | |
1116 | ||
1117 | if (!pr->flags.power_setup_done) | |
1118 | return -ENODEV; | |
1119 | ||
1120 | /* | |
1121 | * FIXME: Design the ACPI notification to make it once per | |
1122 | * system instead of once per-cpu. This condition is a hack | |
1123 | * to make the code that updates C-States be called once. | |
1124 | */ | |
1125 | ||
9505626d | 1126 | if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) { |
46bcfad7 DD |
1127 | |
1128 | cpuidle_pause_and_lock(); | |
1129 | /* Protect against cpu-hotplug */ | |
1130 | get_online_cpus(); | |
1131 | ||
1132 | /* Disable all cpuidle devices */ | |
1133 | for_each_online_cpu(cpu) { | |
1134 | _pr = per_cpu(processors, cpu); | |
1135 | if (!_pr || !_pr->flags.power_setup_done) | |
1136 | continue; | |
3d339dcb DL |
1137 | dev = per_cpu(acpi_cpuidle_device, cpu); |
1138 | cpuidle_disable_device(dev); | |
46bcfad7 DD |
1139 | } |
1140 | ||
1141 | /* Populate Updated C-state information */ | |
f427e5f1 | 1142 | acpi_processor_get_power_info(pr); |
46bcfad7 DD |
1143 | acpi_processor_setup_cpuidle_states(pr); |
1144 | ||
1145 | /* Enable all cpuidle devices */ | |
1146 | for_each_online_cpu(cpu) { | |
1147 | _pr = per_cpu(processors, cpu); | |
1148 | if (!_pr || !_pr->flags.power_setup_done) | |
1149 | continue; | |
1150 | acpi_processor_get_power_info(_pr); | |
1151 | if (_pr->flags.power) { | |
3d339dcb | 1152 | dev = per_cpu(acpi_cpuidle_device, cpu); |
6ef0f086 | 1153 | acpi_processor_setup_cpuidle_cx(_pr, dev); |
3d339dcb | 1154 | cpuidle_enable_device(dev); |
46bcfad7 DD |
1155 | } |
1156 | } | |
1157 | put_online_cpus(); | |
1158 | cpuidle_resume_and_unlock(); | |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | static int acpi_processor_registered; | |
1165 | ||
fe7bf106 | 1166 | int acpi_processor_power_init(struct acpi_processor *pr) |
1da177e4 | 1167 | { |
4be44fcd | 1168 | acpi_status status = 0; |
46bcfad7 | 1169 | int retval; |
3d339dcb | 1170 | struct cpuidle_device *dev; |
b6835052 | 1171 | static int first_run; |
1da177e4 | 1172 | |
d1896049 | 1173 | if (disabled_by_idle_boot_param()) |
36a91358 | 1174 | return 0; |
1da177e4 LT |
1175 | |
1176 | if (!first_run) { | |
1177 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1178 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1179 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1180 | printk(KERN_NOTICE |
1181 | "ACPI: processor limited to max C-state %d\n", | |
1182 | max_cstate); | |
1da177e4 LT |
1183 | first_run++; |
1184 | } | |
1185 | ||
02df8b93 | 1186 | if (!pr) |
d550d98d | 1187 | return -EINVAL; |
02df8b93 | 1188 | |
cee324b1 | 1189 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1190 | status = |
cee324b1 | 1191 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1192 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1193 | ACPI_EXCEPTION((AE_INFO, status, |
1194 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1195 | } |
1196 | } | |
1197 | ||
1198 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1199 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1200 | |
1201 | /* | |
1202 | * Install the idle handler if processor power management is supported. | |
1203 | * Note that we use previously set idle handler will be used on | |
1204 | * platforms that only support C1. | |
1205 | */ | |
36a91358 | 1206 | if (pr->flags.power) { |
46bcfad7 DD |
1207 | /* Register acpi_idle_driver if not already registered */ |
1208 | if (!acpi_processor_registered) { | |
1209 | acpi_processor_setup_cpuidle_states(pr); | |
1210 | retval = cpuidle_register_driver(&acpi_idle_driver); | |
1211 | if (retval) | |
1212 | return retval; | |
1213 | printk(KERN_DEBUG "ACPI: %s registered with cpuidle\n", | |
1214 | acpi_idle_driver.name); | |
1215 | } | |
3d339dcb DL |
1216 | |
1217 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1218 | if (!dev) | |
1219 | return -ENOMEM; | |
1220 | per_cpu(acpi_cpuidle_device, pr->id) = dev; | |
1221 | ||
6ef0f086 | 1222 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 1223 | |
46bcfad7 DD |
1224 | /* Register per-cpu cpuidle_device. Cpuidle driver |
1225 | * must already be registered before registering device | |
1226 | */ | |
3d339dcb | 1227 | retval = cpuidle_register_device(dev); |
46bcfad7 DD |
1228 | if (retval) { |
1229 | if (acpi_processor_registered == 0) | |
1230 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1231 | return retval; | |
1232 | } | |
1233 | acpi_processor_registered++; | |
1da177e4 | 1234 | } |
d550d98d | 1235 | return 0; |
1da177e4 LT |
1236 | } |
1237 | ||
38a991b6 | 1238 | int acpi_processor_power_exit(struct acpi_processor *pr) |
1da177e4 | 1239 | { |
3d339dcb DL |
1240 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
1241 | ||
d1896049 | 1242 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1243 | return 0; |
1244 | ||
46bcfad7 | 1245 | if (pr->flags.power) { |
3d339dcb | 1246 | cpuidle_unregister_device(dev); |
46bcfad7 DD |
1247 | acpi_processor_registered--; |
1248 | if (acpi_processor_registered == 0) | |
1249 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1250 | } | |
1da177e4 | 1251 | |
46bcfad7 | 1252 | pr->flags.power_setup_done = 0; |
d550d98d | 1253 | return 0; |
1da177e4 | 1254 | } |