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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
5c87579e | 41 | #include <linux/latency.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
1da177e4 | 43 | |
3434933b TG |
44 | /* |
45 | * Include the apic definitions for x86 to have the APIC timer related defines | |
46 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
47 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
48 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
49 | */ | |
50 | #ifdef CONFIG_X86 | |
51 | #include <asm/apic.h> | |
52 | #endif | |
53 | ||
5c95d3f5 TG |
54 | /* |
55 | * Include the apic definitions for x86 to have the APIC timer related defines | |
56 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
57 | */ | |
58 | #ifdef CONFIG_X86 | |
59 | #include <asm/apic.h> | |
60 | #endif | |
61 | ||
1da177e4 LT |
62 | #include <asm/io.h> |
63 | #include <asm/uaccess.h> | |
64 | ||
65 | #include <acpi/acpi_bus.h> | |
66 | #include <acpi/processor.h> | |
67 | ||
68 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
69 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 70 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 71 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 72 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 LT |
73 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
74 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
75 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 76 | static void (*pm_idle_save) (void) __read_mostly; |
1da177e4 LT |
77 | module_param(max_cstate, uint, 0644); |
78 | ||
b6835052 | 79 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
80 | module_param(nocst, uint, 0000); |
81 | ||
82 | /* | |
83 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
84 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
85 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
86 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
87 | * reduce history for more aggressive entry into C3 | |
88 | */ | |
b6835052 | 89 | static unsigned int bm_history __read_mostly = |
4be44fcd | 90 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 91 | module_param(bm_history, uint, 0644); |
25496cae TR |
92 | |
93 | static unsigned use_ipi = 2; | |
94 | module_param(use_ipi, uint, 0644); | |
95 | MODULE_PARM_DESC(use_ipi, "IPI (vs. LAPIC) irqs for not waking up from C2/C3" | |
96 | " machines. 0=apic, 1=ipi, 2=auto\n"); | |
97 | ||
1da177e4 LT |
98 | /* -------------------------------------------------------------------------- |
99 | Power Management | |
100 | -------------------------------------------------------------------------- */ | |
101 | ||
102 | /* | |
103 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
104 | * For now disable this. Probably a bug somewhere else. | |
105 | * | |
106 | * To skip this limit, boot/load with a large max_cstate limit. | |
107 | */ | |
335f16be | 108 | static int set_max_cstate(struct dmi_system_id *id) |
1da177e4 LT |
109 | { |
110 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
111 | return 0; | |
112 | ||
3d35600a | 113 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
114 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
115 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 116 | |
3d35600a | 117 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
118 | |
119 | return 0; | |
120 | } | |
121 | ||
7ded5689 AR |
122 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
123 | callers to only run once -AK */ | |
124 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
125 | { set_max_cstate, "IBM ThinkPad R40e", { |
126 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
127 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
128 | { set_max_cstate, "IBM ThinkPad R40e", { |
129 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
130 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
131 | { set_max_cstate, "IBM ThinkPad R40e", { | |
132 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
133 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
134 | { set_max_cstate, "IBM ThinkPad R40e", { | |
135 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
136 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
137 | { set_max_cstate, "IBM ThinkPad R40e", { | |
138 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
139 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
140 | { set_max_cstate, "IBM ThinkPad R40e", { | |
141 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
142 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
143 | { set_max_cstate, "IBM ThinkPad R40e", { | |
144 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
145 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
146 | { set_max_cstate, "IBM ThinkPad R40e", { | |
147 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
148 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
149 | { set_max_cstate, "IBM ThinkPad R40e", { | |
150 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
151 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
152 | { set_max_cstate, "IBM ThinkPad R40e", { | |
153 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
154 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
155 | { set_max_cstate, "IBM ThinkPad R40e", { | |
156 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
157 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
158 | { set_max_cstate, "IBM ThinkPad R40e", { | |
159 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
160 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
161 | { set_max_cstate, "IBM ThinkPad R40e", { | |
162 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
163 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
164 | { set_max_cstate, "IBM ThinkPad R40e", { | |
165 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
166 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
167 | { set_max_cstate, "IBM ThinkPad R40e", { | |
168 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
169 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
170 | { set_max_cstate, "IBM ThinkPad R40e", { | |
171 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
172 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
173 | { set_max_cstate, "Medion 41700", { | |
174 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
175 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
176 | { set_max_cstate, "Clevo 5600D", { | |
177 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
178 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 179 | (void *)2}, |
1da177e4 LT |
180 | {}, |
181 | }; | |
182 | ||
4be44fcd | 183 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
184 | { |
185 | if (t2 >= t1) | |
186 | return (t2 - t1); | |
cee324b1 | 187 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
188 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
189 | else | |
190 | return ((0xFFFFFFFF - t1) + t2); | |
191 | } | |
192 | ||
1da177e4 | 193 | static void |
4be44fcd LB |
194 | acpi_processor_power_activate(struct acpi_processor *pr, |
195 | struct acpi_processor_cx *new) | |
1da177e4 | 196 | { |
4be44fcd | 197 | struct acpi_processor_cx *old; |
1da177e4 LT |
198 | |
199 | if (!pr || !new) | |
200 | return; | |
201 | ||
202 | old = pr->power.state; | |
203 | ||
204 | if (old) | |
205 | old->promotion.count = 0; | |
4be44fcd | 206 | new->demotion.count = 0; |
1da177e4 LT |
207 | |
208 | /* Cleanup from old state. */ | |
209 | if (old) { | |
210 | switch (old->type) { | |
211 | case ACPI_STATE_C3: | |
212 | /* Disable bus master reload */ | |
02df8b93 | 213 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 214 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
215 | break; |
216 | } | |
217 | } | |
218 | ||
219 | /* Prepare to use new state. */ | |
220 | switch (new->type) { | |
221 | case ACPI_STATE_C3: | |
222 | /* Enable bus master reload */ | |
02df8b93 | 223 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 224 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
225 | break; |
226 | } | |
227 | ||
228 | pr->power.state = new; | |
229 | ||
230 | return; | |
231 | } | |
232 | ||
64c7c8f8 NP |
233 | static void acpi_safe_halt(void) |
234 | { | |
495ab9c0 | 235 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
236 | /* |
237 | * TS_POLLING-cleared state must be visible before we | |
238 | * test NEED_RESCHED: | |
239 | */ | |
240 | smp_mb(); | |
64c7c8f8 NP |
241 | if (!need_resched()) |
242 | safe_halt(); | |
495ab9c0 | 243 | current_thread_info()->status |= TS_POLLING; |
64c7c8f8 NP |
244 | } |
245 | ||
4be44fcd | 246 | static atomic_t c3_cpu_count; |
1da177e4 | 247 | |
991528d7 VP |
248 | /* Common C-state entry for C2, C3, .. */ |
249 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
250 | { | |
251 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
252 | /* Call into architectural FFH based C-state */ | |
253 | acpi_processor_ffh_cstate_enter(cstate); | |
254 | } else { | |
255 | int unused; | |
256 | /* IO port based C-state */ | |
257 | inb(cstate->address); | |
258 | /* Dummy wait op - must do something useless after P_LVL2 read | |
259 | because chipsets cannot guarantee that STPCLK# signal | |
260 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 261 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
262 | } |
263 | } | |
264 | ||
169a0abb TG |
265 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
266 | ||
267 | /* | |
268 | * Some BIOS implementations switch to C3 in the published C2 state. | |
25496cae TR |
269 | * This seems to be a common problem on AMD boxen and Intel Dothan/Banias |
270 | * Pentium M machines. | |
169a0abb TG |
271 | */ |
272 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
273 | struct acpi_processor_cx *cx) | |
274 | { | |
275 | struct acpi_processor_power *pwr = &pr->power; | |
276 | ||
277 | /* | |
278 | * Check, if one of the previous states already marked the lapic | |
279 | * unstable | |
280 | */ | |
281 | if (pwr->timer_broadcast_on_state < state) | |
282 | return; | |
283 | ||
25496cae TR |
284 | if (cx->type >= ACPI_STATE_C2) { |
285 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
286 | pr->power.timer_broadcast_on_state = state; | |
287 | else if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
288 | boot_cpu_data.x86 == 6) && | |
289 | (boot_cpu_data.x86_model == 13 || | |
290 | boot_cpu_data.x86_model == 9)) | |
291 | { | |
292 | pr->power.timer_broadcast_on_state = state; | |
293 | } | |
294 | } | |
169a0abb TG |
295 | } |
296 | ||
297 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
298 | { | |
e9e2cdb4 TG |
299 | #ifdef CONFIG_GENERIC_CLOCKEVENTS |
300 | unsigned long reason; | |
301 | ||
302 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
303 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
304 | ||
305 | clockevents_notify(reason, &pr->id); | |
306 | #else | |
169a0abb TG |
307 | cpumask_t mask = cpumask_of_cpu(pr->id); |
308 | ||
25496cae | 309 | if (use_ipi == 0) |
169a0abb | 310 | on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1); |
25496cae | 311 | else if (use_ipi == 1) |
169a0abb | 312 | on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1); |
25496cae TR |
313 | else { |
314 | if (pr->power.timer_broadcast_on_state < INT_MAX) | |
315 | on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1); | |
316 | else | |
317 | on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1); | |
318 | } | |
e9e2cdb4 TG |
319 | #endif |
320 | } | |
321 | ||
322 | /* Power(C) State timer broadcast control */ | |
323 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
324 | struct acpi_processor_cx *cx, | |
325 | int broadcast) | |
326 | { | |
327 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | |
328 | ||
329 | int state = cx - pr->power.states; | |
330 | ||
331 | if (state >= pr->power.timer_broadcast_on_state) { | |
332 | unsigned long reason; | |
333 | ||
334 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
335 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
336 | clockevents_notify(reason, &pr->id); | |
337 | } | |
338 | #endif | |
169a0abb TG |
339 | } |
340 | ||
341 | #else | |
342 | ||
343 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
344 | struct acpi_processor_cx *cstate) { } | |
345 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
346 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
347 | struct acpi_processor_cx *cx, | |
348 | int broadcast) | |
349 | { | |
350 | } | |
169a0abb TG |
351 | |
352 | #endif | |
353 | ||
4be44fcd | 354 | static void acpi_processor_idle(void) |
1da177e4 | 355 | { |
4be44fcd | 356 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
357 | struct acpi_processor_cx *cx = NULL; |
358 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
359 | int sleep_ticks = 0; |
360 | u32 t1, t2 = 0; | |
1da177e4 | 361 | |
64c7c8f8 | 362 | pr = processors[smp_processor_id()]; |
1da177e4 LT |
363 | if (!pr) |
364 | return; | |
365 | ||
366 | /* | |
367 | * Interrupts must be disabled during bus mastering calculations and | |
368 | * for C2/C3 transitions. | |
369 | */ | |
370 | local_irq_disable(); | |
371 | ||
372 | /* | |
373 | * Check whether we truly need to go idle, or should | |
374 | * reschedule: | |
375 | */ | |
376 | if (unlikely(need_resched())) { | |
377 | local_irq_enable(); | |
378 | return; | |
379 | } | |
380 | ||
381 | cx = pr->power.state; | |
64c7c8f8 NP |
382 | if (!cx) { |
383 | if (pm_idle_save) | |
384 | pm_idle_save(); | |
385 | else | |
386 | acpi_safe_halt(); | |
387 | return; | |
388 | } | |
1da177e4 LT |
389 | |
390 | /* | |
391 | * Check BM Activity | |
392 | * ----------------- | |
393 | * Check for bus mastering activity (if required), record, and check | |
394 | * for demotion. | |
395 | */ | |
396 | if (pr->flags.bm_check) { | |
4be44fcd LB |
397 | u32 bm_status = 0; |
398 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 399 | |
c5ab81ca DB |
400 | if (diff > 31) |
401 | diff = 31; | |
1da177e4 | 402 | |
c5ab81ca | 403 | pr->power.bm_activity <<= diff; |
1da177e4 | 404 | |
d8c71b6d | 405 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 406 | if (bm_status) { |
c5ab81ca | 407 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 408 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
409 | } |
410 | /* | |
411 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
412 | * the true state of bus mastering activity; forcing us to | |
413 | * manually check the BMIDEA bit of each IDE channel. | |
414 | */ | |
415 | else if (errata.piix4.bmisx) { | |
416 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 417 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 418 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
419 | } |
420 | ||
421 | pr->power.bm_check_timestamp = jiffies; | |
422 | ||
423 | /* | |
c4a001b1 | 424 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
425 | * to avoid a faulty transition. Note that the processor |
426 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 427 | * function) but should upon the next. |
1da177e4 LT |
428 | * |
429 | * TBD: A better policy might be to fallback to the demotion | |
430 | * state (use it for this quantum only) istead of | |
431 | * demoting -- and rely on duration as our sole demotion | |
432 | * qualification. This may, however, introduce DMA | |
433 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
434 | */ | |
c4a001b1 DB |
435 | if ((pr->power.bm_activity & 0x1) && |
436 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
437 | local_irq_enable(); |
438 | next_state = cx->demotion.state; | |
439 | goto end; | |
440 | } | |
441 | } | |
442 | ||
4c033552 VP |
443 | #ifdef CONFIG_HOTPLUG_CPU |
444 | /* | |
445 | * Check for P_LVL2_UP flag before entering C2 and above on | |
446 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
447 | * detection phase, to work cleanly with logical CPU hotplug. | |
448 | */ | |
449 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 450 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 451 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 452 | #endif |
1e483969 | 453 | |
1da177e4 LT |
454 | /* |
455 | * Sleep: | |
456 | * ------ | |
457 | * Invoke the current Cx state to put the processor to sleep. | |
458 | */ | |
2a298a35 | 459 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 460 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
461 | /* |
462 | * TS_POLLING-cleared state must be visible before we | |
463 | * test NEED_RESCHED: | |
464 | */ | |
465 | smp_mb(); | |
2a298a35 | 466 | if (need_resched()) { |
495ab9c0 | 467 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 468 | local_irq_enable(); |
2a298a35 NP |
469 | return; |
470 | } | |
471 | } | |
472 | ||
1da177e4 LT |
473 | switch (cx->type) { |
474 | ||
475 | case ACPI_STATE_C1: | |
476 | /* | |
477 | * Invoke C1. | |
478 | * Use the appropriate idle routine, the one that would | |
479 | * be used without acpi C-states. | |
480 | */ | |
481 | if (pm_idle_save) | |
482 | pm_idle_save(); | |
483 | else | |
64c7c8f8 NP |
484 | acpi_safe_halt(); |
485 | ||
1da177e4 | 486 | /* |
4be44fcd | 487 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
488 | * go to an ISR rather than here. Need to instrument |
489 | * base interrupt handler. | |
490 | */ | |
491 | sleep_ticks = 0xFFFFFFFF; | |
492 | break; | |
493 | ||
494 | case ACPI_STATE_C2: | |
495 | /* Get start time (ticks) */ | |
cee324b1 | 496 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 497 | /* Invoke C2 */ |
e9e2cdb4 | 498 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 499 | acpi_cstate_enter(cx); |
1da177e4 | 500 | /* Get end time (ticks) */ |
cee324b1 | 501 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 502 | |
503 | #ifdef CONFIG_GENERIC_TIME | |
504 | /* TSC halts in C2, so notify users */ | |
505 | mark_tsc_unstable(); | |
506 | #endif | |
1da177e4 LT |
507 | /* Re-enable interrupts */ |
508 | local_irq_enable(); | |
495ab9c0 | 509 | current_thread_info()->status |= TS_POLLING; |
1da177e4 | 510 | /* Compute time (ticks) that we were actually asleep */ |
4be44fcd LB |
511 | sleep_ticks = |
512 | ticks_elapsed(t1, t2) - cx->latency_ticks - C2_OVERHEAD; | |
e9e2cdb4 | 513 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
514 | break; |
515 | ||
516 | case ACPI_STATE_C3: | |
4be44fcd | 517 | |
02df8b93 VP |
518 | if (pr->flags.bm_check) { |
519 | if (atomic_inc_return(&c3_cpu_count) == | |
4be44fcd | 520 | num_online_cpus()) { |
02df8b93 VP |
521 | /* |
522 | * All CPUs are trying to go to C3 | |
523 | * Disable bus master arbitration | |
524 | */ | |
d8c71b6d | 525 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 VP |
526 | } |
527 | } else { | |
528 | /* SMP with no shared cache... Invalidate cache */ | |
529 | ACPI_FLUSH_CPU_CACHE(); | |
530 | } | |
4be44fcd | 531 | |
1da177e4 | 532 | /* Get start time (ticks) */ |
cee324b1 | 533 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 534 | /* Invoke C3 */ |
e9e2cdb4 | 535 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 536 | acpi_cstate_enter(cx); |
1da177e4 | 537 | /* Get end time (ticks) */ |
cee324b1 | 538 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
02df8b93 VP |
539 | if (pr->flags.bm_check) { |
540 | /* Enable bus master arbitration */ | |
541 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 542 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
543 | } |
544 | ||
539eb11e | 545 | #ifdef CONFIG_GENERIC_TIME |
546 | /* TSC halts in C3, so notify users */ | |
547 | mark_tsc_unstable(); | |
548 | #endif | |
1da177e4 LT |
549 | /* Re-enable interrupts */ |
550 | local_irq_enable(); | |
495ab9c0 | 551 | current_thread_info()->status |= TS_POLLING; |
1da177e4 | 552 | /* Compute time (ticks) that we were actually asleep */ |
4be44fcd LB |
553 | sleep_ticks = |
554 | ticks_elapsed(t1, t2) - cx->latency_ticks - C3_OVERHEAD; | |
e9e2cdb4 | 555 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
556 | break; |
557 | ||
558 | default: | |
559 | local_irq_enable(); | |
560 | return; | |
561 | } | |
a3c6598f DB |
562 | cx->usage++; |
563 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
564 | cx->time += sleep_ticks; | |
1da177e4 LT |
565 | |
566 | next_state = pr->power.state; | |
567 | ||
1e483969 DSL |
568 | #ifdef CONFIG_HOTPLUG_CPU |
569 | /* Don't do promotion/demotion */ | |
570 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 571 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
572 | next_state = cx; |
573 | goto end; | |
574 | } | |
575 | #endif | |
576 | ||
1da177e4 LT |
577 | /* |
578 | * Promotion? | |
579 | * ---------- | |
580 | * Track the number of longs (time asleep is greater than threshold) | |
581 | * and promote when the count threshold is reached. Note that bus | |
582 | * mastering activity may prevent promotions. | |
583 | * Do not promote above max_cstate. | |
584 | */ | |
585 | if (cx->promotion.state && | |
586 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e AV |
587 | if (sleep_ticks > cx->promotion.threshold.ticks && |
588 | cx->promotion.state->latency <= system_latency_constraint()) { | |
1da177e4 | 589 | cx->promotion.count++; |
4be44fcd LB |
590 | cx->demotion.count = 0; |
591 | if (cx->promotion.count >= | |
592 | cx->promotion.threshold.count) { | |
1da177e4 | 593 | if (pr->flags.bm_check) { |
4be44fcd LB |
594 | if (! |
595 | (pr->power.bm_activity & cx-> | |
596 | promotion.threshold.bm)) { | |
597 | next_state = | |
598 | cx->promotion.state; | |
1da177e4 LT |
599 | goto end; |
600 | } | |
4be44fcd | 601 | } else { |
1da177e4 LT |
602 | next_state = cx->promotion.state; |
603 | goto end; | |
604 | } | |
605 | } | |
606 | } | |
607 | } | |
608 | ||
609 | /* | |
610 | * Demotion? | |
611 | * --------- | |
612 | * Track the number of shorts (time asleep is less than time threshold) | |
613 | * and demote when the usage threshold is reached. | |
614 | */ | |
615 | if (cx->demotion.state) { | |
616 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
617 | cx->demotion.count++; | |
618 | cx->promotion.count = 0; | |
619 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
620 | next_state = cx->demotion.state; | |
621 | goto end; | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
4be44fcd | 626 | end: |
1da177e4 LT |
627 | /* |
628 | * Demote if current state exceeds max_cstate | |
5c87579e | 629 | * or if the latency of the current state is unacceptable |
1da177e4 | 630 | */ |
5c87579e AV |
631 | if ((pr->power.state - pr->power.states) > max_cstate || |
632 | pr->power.state->latency > system_latency_constraint()) { | |
1da177e4 LT |
633 | if (cx->demotion.state) |
634 | next_state = cx->demotion.state; | |
635 | } | |
636 | ||
637 | /* | |
638 | * New Cx State? | |
639 | * ------------- | |
640 | * If we're going to start using a new Cx state we must clean up | |
641 | * from the previous and prepare to use the new. | |
642 | */ | |
643 | if (next_state != pr->power.state) | |
644 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
645 | } |
646 | ||
4be44fcd | 647 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
648 | { |
649 | unsigned int i; | |
650 | unsigned int state_is_set = 0; | |
651 | struct acpi_processor_cx *lower = NULL; | |
652 | struct acpi_processor_cx *higher = NULL; | |
653 | struct acpi_processor_cx *cx; | |
654 | ||
1da177e4 LT |
655 | |
656 | if (!pr) | |
d550d98d | 657 | return -EINVAL; |
1da177e4 LT |
658 | |
659 | /* | |
660 | * This function sets the default Cx state policy (OS idle handler). | |
661 | * Our scheme is to promote quickly to C2 but more conservatively | |
662 | * to C3. We're favoring C2 for its characteristics of low latency | |
663 | * (quick response), good power savings, and ability to allow bus | |
664 | * mastering activity. Note that the Cx state policy is completely | |
665 | * customizable and can be altered dynamically. | |
666 | */ | |
667 | ||
668 | /* startup state */ | |
4be44fcd | 669 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
670 | cx = &pr->power.states[i]; |
671 | if (!cx->valid) | |
672 | continue; | |
673 | ||
674 | if (!state_is_set) | |
675 | pr->power.state = cx; | |
676 | state_is_set++; | |
677 | break; | |
4be44fcd | 678 | } |
1da177e4 LT |
679 | |
680 | if (!state_is_set) | |
d550d98d | 681 | return -ENODEV; |
1da177e4 LT |
682 | |
683 | /* demotion */ | |
4be44fcd | 684 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
685 | cx = &pr->power.states[i]; |
686 | if (!cx->valid) | |
687 | continue; | |
688 | ||
689 | if (lower) { | |
690 | cx->demotion.state = lower; | |
691 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
692 | cx->demotion.threshold.count = 1; | |
693 | if (cx->type == ACPI_STATE_C3) | |
694 | cx->demotion.threshold.bm = bm_history; | |
695 | } | |
696 | ||
697 | lower = cx; | |
698 | } | |
699 | ||
700 | /* promotion */ | |
701 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
702 | cx = &pr->power.states[i]; | |
703 | if (!cx->valid) | |
704 | continue; | |
705 | ||
706 | if (higher) { | |
4be44fcd | 707 | cx->promotion.state = higher; |
1da177e4 LT |
708 | cx->promotion.threshold.ticks = cx->latency_ticks; |
709 | if (cx->type >= ACPI_STATE_C2) | |
710 | cx->promotion.threshold.count = 4; | |
711 | else | |
712 | cx->promotion.threshold.count = 10; | |
713 | if (higher->type == ACPI_STATE_C3) | |
714 | cx->promotion.threshold.bm = bm_history; | |
715 | } | |
716 | ||
717 | higher = cx; | |
718 | } | |
719 | ||
d550d98d | 720 | return 0; |
1da177e4 LT |
721 | } |
722 | ||
4be44fcd | 723 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 724 | { |
1da177e4 LT |
725 | |
726 | if (!pr) | |
d550d98d | 727 | return -EINVAL; |
1da177e4 LT |
728 | |
729 | if (!pr->pblk) | |
d550d98d | 730 | return -ENODEV; |
1da177e4 | 731 | |
1da177e4 | 732 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
733 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
734 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
735 | ||
4c033552 VP |
736 | #ifndef CONFIG_HOTPLUG_CPU |
737 | /* | |
738 | * Check for P_LVL2_UP flag before entering C2 and above on | |
739 | * an SMP system. | |
740 | */ | |
ad71860a | 741 | if ((num_online_cpus() > 1) && |
cee324b1 | 742 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 743 | return -ENODEV; |
4c033552 VP |
744 | #endif |
745 | ||
1da177e4 LT |
746 | /* determine C2 and C3 address from pblk */ |
747 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
748 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
749 | ||
750 | /* determine latencies from FADT */ | |
cee324b1 AS |
751 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
752 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
753 | |
754 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
755 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
756 | pr->power.states[ACPI_STATE_C2].address, | |
757 | pr->power.states[ACPI_STATE_C3].address)); | |
758 | ||
d550d98d | 759 | return 0; |
1da177e4 LT |
760 | } |
761 | ||
991528d7 | 762 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 763 | { |
991528d7 VP |
764 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
765 | /* set the first C-State to C1 */ | |
766 | /* all processors need to support C1 */ | |
767 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
768 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
769 | } | |
770 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 771 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 772 | return 0; |
acf05f4b VP |
773 | } |
774 | ||
4be44fcd | 775 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 776 | { |
4be44fcd LB |
777 | acpi_status status = 0; |
778 | acpi_integer count; | |
cf824788 | 779 | int current_count; |
4be44fcd LB |
780 | int i; |
781 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
782 | union acpi_object *cst; | |
1da177e4 | 783 | |
1da177e4 | 784 | |
1da177e4 | 785 | if (nocst) |
d550d98d | 786 | return -ENODEV; |
1da177e4 | 787 | |
991528d7 | 788 | current_count = 0; |
1da177e4 LT |
789 | |
790 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
791 | if (ACPI_FAILURE(status)) { | |
792 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 793 | return -ENODEV; |
4be44fcd | 794 | } |
1da177e4 | 795 | |
50dd0969 | 796 | cst = buffer.pointer; |
1da177e4 LT |
797 | |
798 | /* There must be at least 2 elements */ | |
799 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 800 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
801 | status = -EFAULT; |
802 | goto end; | |
803 | } | |
804 | ||
805 | count = cst->package.elements[0].integer.value; | |
806 | ||
807 | /* Validate number of power states. */ | |
808 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 809 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
810 | status = -EFAULT; |
811 | goto end; | |
812 | } | |
813 | ||
1da177e4 LT |
814 | /* Tell driver that at least _CST is supported. */ |
815 | pr->flags.has_cst = 1; | |
816 | ||
817 | for (i = 1; i <= count; i++) { | |
818 | union acpi_object *element; | |
819 | union acpi_object *obj; | |
820 | struct acpi_power_register *reg; | |
821 | struct acpi_processor_cx cx; | |
822 | ||
823 | memset(&cx, 0, sizeof(cx)); | |
824 | ||
50dd0969 | 825 | element = &(cst->package.elements[i]); |
1da177e4 LT |
826 | if (element->type != ACPI_TYPE_PACKAGE) |
827 | continue; | |
828 | ||
829 | if (element->package.count != 4) | |
830 | continue; | |
831 | ||
50dd0969 | 832 | obj = &(element->package.elements[0]); |
1da177e4 LT |
833 | |
834 | if (obj->type != ACPI_TYPE_BUFFER) | |
835 | continue; | |
836 | ||
4be44fcd | 837 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
838 | |
839 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 840 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
841 | continue; |
842 | ||
1da177e4 | 843 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 844 | obj = &(element->package.elements[1]); |
1da177e4 LT |
845 | if (obj->type != ACPI_TYPE_INTEGER) |
846 | continue; | |
847 | ||
848 | cx.type = obj->integer.value; | |
991528d7 VP |
849 | /* |
850 | * Some buggy BIOSes won't list C1 in _CST - | |
851 | * Let acpi_processor_get_power_info_default() handle them later | |
852 | */ | |
853 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
854 | current_count++; | |
855 | ||
856 | cx.address = reg->address; | |
857 | cx.index = current_count + 1; | |
858 | ||
859 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
860 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
861 | if (acpi_processor_ffh_cstate_probe | |
862 | (pr->id, &cx, reg) == 0) { | |
863 | cx.space_id = ACPI_CSTATE_FFH; | |
864 | } else if (cx.type != ACPI_STATE_C1) { | |
865 | /* | |
866 | * C1 is a special case where FIXED_HARDWARE | |
867 | * can be handled in non-MWAIT way as well. | |
868 | * In that case, save this _CST entry info. | |
869 | * That is, we retain space_id of SYSTEM_IO for | |
870 | * halt based C1. | |
871 | * Otherwise, ignore this info and continue. | |
872 | */ | |
873 | continue; | |
874 | } | |
875 | } | |
1da177e4 | 876 | |
50dd0969 | 877 | obj = &(element->package.elements[2]); |
1da177e4 LT |
878 | if (obj->type != ACPI_TYPE_INTEGER) |
879 | continue; | |
880 | ||
881 | cx.latency = obj->integer.value; | |
882 | ||
50dd0969 | 883 | obj = &(element->package.elements[3]); |
1da177e4 LT |
884 | if (obj->type != ACPI_TYPE_INTEGER) |
885 | continue; | |
886 | ||
887 | cx.power = obj->integer.value; | |
888 | ||
cf824788 JM |
889 | current_count++; |
890 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
891 | ||
892 | /* | |
893 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
894 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
895 | */ | |
896 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
897 | printk(KERN_WARNING | |
898 | "Limiting number of power states to max (%d)\n", | |
899 | ACPI_PROCESSOR_MAX_POWER); | |
900 | printk(KERN_WARNING | |
901 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
902 | break; | |
903 | } | |
1da177e4 LT |
904 | } |
905 | ||
4be44fcd | 906 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 907 | current_count)); |
1da177e4 LT |
908 | |
909 | /* Validate number of power states discovered */ | |
cf824788 | 910 | if (current_count < 2) |
6d93c648 | 911 | status = -EFAULT; |
1da177e4 | 912 | |
4be44fcd | 913 | end: |
02438d87 | 914 | kfree(buffer.pointer); |
1da177e4 | 915 | |
d550d98d | 916 | return status; |
1da177e4 LT |
917 | } |
918 | ||
1da177e4 LT |
919 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
920 | { | |
1da177e4 LT |
921 | |
922 | if (!cx->address) | |
d550d98d | 923 | return; |
1da177e4 LT |
924 | |
925 | /* | |
926 | * C2 latency must be less than or equal to 100 | |
927 | * microseconds. | |
928 | */ | |
929 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
930 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 931 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 932 | return; |
1da177e4 LT |
933 | } |
934 | ||
1da177e4 LT |
935 | /* |
936 | * Otherwise we've met all of our C2 requirements. | |
937 | * Normalize the C2 latency to expidite policy | |
938 | */ | |
939 | cx->valid = 1; | |
940 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); | |
941 | ||
d550d98d | 942 | return; |
1da177e4 LT |
943 | } |
944 | ||
4be44fcd LB |
945 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
946 | struct acpi_processor_cx *cx) | |
1da177e4 | 947 | { |
02df8b93 VP |
948 | static int bm_check_flag; |
949 | ||
1da177e4 LT |
950 | |
951 | if (!cx->address) | |
d550d98d | 952 | return; |
1da177e4 LT |
953 | |
954 | /* | |
955 | * C3 latency must be less than or equal to 1000 | |
956 | * microseconds. | |
957 | */ | |
958 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
959 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 960 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 961 | return; |
1da177e4 LT |
962 | } |
963 | ||
1da177e4 LT |
964 | /* |
965 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
966 | * DMA transfers are used by any ISA device to avoid livelock. | |
967 | * Note that we could disable Type-F DMA (as recommended by | |
968 | * the erratum), but this is known to disrupt certain ISA | |
969 | * devices thus we take the conservative approach. | |
970 | */ | |
971 | else if (errata.piix4.fdma) { | |
972 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 973 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 974 | return; |
1da177e4 LT |
975 | } |
976 | ||
02df8b93 VP |
977 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
978 | if (!bm_check_flag) { | |
979 | /* Determine whether bm_check is needed based on CPU */ | |
980 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
981 | bm_check_flag = pr->flags.bm_check; | |
982 | } else { | |
983 | pr->flags.bm_check = bm_check_flag; | |
984 | } | |
985 | ||
986 | if (pr->flags.bm_check) { | |
02df8b93 VP |
987 | /* bus mastering control is necessary */ |
988 | if (!pr->flags.bm_control) { | |
989 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 990 | "C3 support requires bus mastering control\n")); |
d550d98d | 991 | return; |
02df8b93 VP |
992 | } |
993 | } else { | |
02df8b93 VP |
994 | /* |
995 | * WBINVD should be set in fadt, for C3 state to be | |
996 | * supported on when bm_check is not required. | |
997 | */ | |
cee324b1 | 998 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 999 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1000 | "Cache invalidation should work properly" |
1001 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1002 | return; |
02df8b93 | 1003 | } |
d8c71b6d | 1004 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1005 | } |
1006 | ||
1da177e4 LT |
1007 | /* |
1008 | * Otherwise we've met all of our C3 requirements. | |
1009 | * Normalize the C3 latency to expidite policy. Enable | |
1010 | * checking of bus mastering status (bm_check) so we can | |
1011 | * use this in our C3 policy | |
1012 | */ | |
1013 | cx->valid = 1; | |
1014 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); | |
1da177e4 | 1015 | |
d550d98d | 1016 | return; |
1da177e4 LT |
1017 | } |
1018 | ||
1da177e4 LT |
1019 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1020 | { | |
1021 | unsigned int i; | |
1022 | unsigned int working = 0; | |
6eb0a0fd | 1023 | |
169a0abb | 1024 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1025 | |
4be44fcd | 1026 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1027 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1028 | ||
1029 | switch (cx->type) { | |
1030 | case ACPI_STATE_C1: | |
1031 | cx->valid = 1; | |
1032 | break; | |
1033 | ||
1034 | case ACPI_STATE_C2: | |
1035 | acpi_processor_power_verify_c2(cx); | |
25496cae | 1036 | if (cx->valid && use_ipi != 0 && use_ipi != 1) |
169a0abb | 1037 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1038 | break; |
1039 | ||
1040 | case ACPI_STATE_C3: | |
1041 | acpi_processor_power_verify_c3(pr, cx); | |
25496cae | 1042 | if (cx->valid && use_ipi != 0 && use_ipi != 1) |
169a0abb | 1043 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1044 | break; |
1045 | } | |
1046 | ||
1047 | if (cx->valid) | |
1048 | working++; | |
1049 | } | |
bd663347 | 1050 | |
169a0abb | 1051 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1052 | |
1053 | return (working); | |
1054 | } | |
1055 | ||
4be44fcd | 1056 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1057 | { |
1058 | unsigned int i; | |
1059 | int result; | |
1060 | ||
1da177e4 LT |
1061 | |
1062 | /* NOTE: the idle thread may not be running while calling | |
1063 | * this function */ | |
1064 | ||
991528d7 VP |
1065 | /* Zero initialize all the C-states info. */ |
1066 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1067 | ||
1da177e4 | 1068 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1069 | if (result == -ENODEV) |
c5a114f1 | 1070 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1071 | |
991528d7 VP |
1072 | if (result) |
1073 | return result; | |
1074 | ||
1075 | acpi_processor_get_power_info_default(pr); | |
1076 | ||
cf824788 | 1077 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 LT |
1078 | |
1079 | /* | |
1080 | * Set Default Policy | |
1081 | * ------------------ | |
1082 | * Now that we know which states are supported, set the default | |
1083 | * policy. Note that this policy can be changed dynamically | |
1084 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1085 | * not on AC). | |
1086 | */ | |
1087 | result = acpi_processor_set_power_policy(pr); | |
1088 | if (result) | |
d550d98d | 1089 | return result; |
1da177e4 LT |
1090 | |
1091 | /* | |
1092 | * if one state of type C2 or C3 is available, mark this | |
1093 | * CPU as being "idle manageable" | |
1094 | */ | |
1095 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1096 | if (pr->power.states[i].valid) { |
1da177e4 | 1097 | pr->power.count = i; |
2203d6ed LT |
1098 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1099 | pr->flags.power = 1; | |
acf05f4b | 1100 | } |
1da177e4 LT |
1101 | } |
1102 | ||
d550d98d | 1103 | return 0; |
1da177e4 LT |
1104 | } |
1105 | ||
4be44fcd | 1106 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1da177e4 | 1107 | { |
4be44fcd | 1108 | int result = 0; |
1da177e4 | 1109 | |
1da177e4 LT |
1110 | |
1111 | if (!pr) | |
d550d98d | 1112 | return -EINVAL; |
1da177e4 | 1113 | |
4be44fcd | 1114 | if (nocst) { |
d550d98d | 1115 | return -ENODEV; |
1da177e4 LT |
1116 | } |
1117 | ||
1118 | if (!pr->flags.power_setup_done) | |
d550d98d | 1119 | return -ENODEV; |
1da177e4 LT |
1120 | |
1121 | /* Fall back to the default idle loop */ | |
1122 | pm_idle = pm_idle_save; | |
4be44fcd | 1123 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ |
1da177e4 LT |
1124 | |
1125 | pr->flags.power = 0; | |
1126 | result = acpi_processor_get_power_info(pr); | |
1127 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1128 | pm_idle = acpi_processor_idle; | |
1129 | ||
d550d98d | 1130 | return result; |
1da177e4 LT |
1131 | } |
1132 | ||
1133 | /* proc interface */ | |
1134 | ||
1135 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) | |
1136 | { | |
50dd0969 | 1137 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1138 | unsigned int i; |
1da177e4 | 1139 | |
1da177e4 LT |
1140 | |
1141 | if (!pr) | |
1142 | goto end; | |
1143 | ||
1144 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1145 | "max_cstate: C%d\n" |
5c87579e AV |
1146 | "bus master activity: %08x\n" |
1147 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1148 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e AV |
1149 | max_cstate, (unsigned)pr->power.bm_activity, |
1150 | system_latency_constraint()); | |
1da177e4 LT |
1151 | |
1152 | seq_puts(seq, "states:\n"); | |
1153 | ||
1154 | for (i = 1; i <= pr->power.count; i++) { | |
1155 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1156 | (&pr->power.states[i] == |
1157 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1158 | |
1159 | if (!pr->power.states[i].valid) { | |
1160 | seq_puts(seq, "<not supported>\n"); | |
1161 | continue; | |
1162 | } | |
1163 | ||
1164 | switch (pr->power.states[i].type) { | |
1165 | case ACPI_STATE_C1: | |
1166 | seq_printf(seq, "type[C1] "); | |
1167 | break; | |
1168 | case ACPI_STATE_C2: | |
1169 | seq_printf(seq, "type[C2] "); | |
1170 | break; | |
1171 | case ACPI_STATE_C3: | |
1172 | seq_printf(seq, "type[C3] "); | |
1173 | break; | |
1174 | default: | |
1175 | seq_printf(seq, "type[--] "); | |
1176 | break; | |
1177 | } | |
1178 | ||
1179 | if (pr->power.states[i].promotion.state) | |
1180 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1181 | (pr->power.states[i].promotion.state - |
1182 | pr->power.states)); | |
1da177e4 LT |
1183 | else |
1184 | seq_puts(seq, "promotion[--] "); | |
1185 | ||
1186 | if (pr->power.states[i].demotion.state) | |
1187 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1188 | (pr->power.states[i].demotion.state - |
1189 | pr->power.states)); | |
1da177e4 LT |
1190 | else |
1191 | seq_puts(seq, "demotion[--] "); | |
1192 | ||
a3c6598f | 1193 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1194 | pr->power.states[i].latency, |
a3c6598f | 1195 | pr->power.states[i].usage, |
b0b7eaaf | 1196 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1197 | } |
1198 | ||
4be44fcd | 1199 | end: |
d550d98d | 1200 | return 0; |
1da177e4 LT |
1201 | } |
1202 | ||
1203 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1204 | { | |
1205 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1206 | PDE(inode)->data); |
1da177e4 LT |
1207 | } |
1208 | ||
d7508032 | 1209 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1210 | .open = acpi_processor_power_open_fs, |
1211 | .read = seq_read, | |
1212 | .llseek = seq_lseek, | |
1213 | .release = single_release, | |
1da177e4 LT |
1214 | }; |
1215 | ||
1fec74a9 | 1216 | #ifdef CONFIG_SMP |
5c87579e AV |
1217 | static void smp_callback(void *v) |
1218 | { | |
1219 | /* we already woke the CPU up, nothing more to do */ | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * This function gets called when a part of the kernel has a new latency | |
1224 | * requirement. This means we need to get all processors out of their C-state, | |
1225 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1226 | * wakes them all right up. | |
1227 | */ | |
1228 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1229 | unsigned long l, void *v) | |
1230 | { | |
1231 | smp_call_function(smp_callback, NULL, 0, 1); | |
1232 | return NOTIFY_OK; | |
1233 | } | |
1234 | ||
1235 | static struct notifier_block acpi_processor_latency_notifier = { | |
1236 | .notifier_call = acpi_processor_latency_notify, | |
1237 | }; | |
1fec74a9 | 1238 | #endif |
5c87579e | 1239 | |
7af8b660 | 1240 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1241 | struct acpi_device *device) |
1da177e4 | 1242 | { |
4be44fcd | 1243 | acpi_status status = 0; |
b6835052 | 1244 | static int first_run; |
4be44fcd | 1245 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1246 | unsigned int i; |
1247 | ||
1da177e4 LT |
1248 | |
1249 | if (!first_run) { | |
1250 | dmi_check_system(processor_power_dmi_table); | |
1251 | if (max_cstate < ACPI_C_STATES_MAX) | |
4be44fcd LB |
1252 | printk(KERN_NOTICE |
1253 | "ACPI: processor limited to max C-state %d\n", | |
1254 | max_cstate); | |
1da177e4 | 1255 | first_run++; |
1fec74a9 | 1256 | #ifdef CONFIG_SMP |
5c87579e | 1257 | register_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1258 | #endif |
1da177e4 LT |
1259 | } |
1260 | ||
02df8b93 | 1261 | if (!pr) |
d550d98d | 1262 | return -EINVAL; |
02df8b93 | 1263 | |
cee324b1 | 1264 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1265 | status = |
cee324b1 | 1266 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1267 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1268 | ACPI_EXCEPTION((AE_INFO, status, |
1269 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1270 | } |
1271 | } | |
1272 | ||
1273 | acpi_processor_get_power_info(pr); | |
1274 | ||
1275 | /* | |
1276 | * Install the idle handler if processor power management is supported. | |
1277 | * Note that we use previously set idle handler will be used on | |
1278 | * platforms that only support C1. | |
1279 | */ | |
1280 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
1281 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); | |
1282 | for (i = 1; i <= pr->power.count; i++) | |
1283 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1284 | printk(" C%d[C%d]", i, |
1285 | pr->power.states[i].type); | |
1da177e4 LT |
1286 | printk(")\n"); |
1287 | ||
1288 | if (pr->id == 0) { | |
1289 | pm_idle_save = pm_idle; | |
1290 | pm_idle = acpi_processor_idle; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | /* 'power' [R] */ | |
1295 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1296 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1297 | if (!entry) |
a6fc6720 | 1298 | return -EIO; |
1da177e4 LT |
1299 | else { |
1300 | entry->proc_fops = &acpi_processor_power_fops; | |
1301 | entry->data = acpi_driver_data(device); | |
1302 | entry->owner = THIS_MODULE; | |
1303 | } | |
1304 | ||
1305 | pr->flags.power_setup_done = 1; | |
1306 | ||
d550d98d | 1307 | return 0; |
1da177e4 LT |
1308 | } |
1309 | ||
4be44fcd LB |
1310 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1311 | struct acpi_device *device) | |
1da177e4 | 1312 | { |
1da177e4 LT |
1313 | |
1314 | pr->flags.power_setup_done = 0; | |
1315 | ||
1316 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1317 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1318 | acpi_device_dir(device)); | |
1da177e4 LT |
1319 | |
1320 | /* Unregister the idle handler when processor #0 is removed. */ | |
1321 | if (pr->id == 0) { | |
1322 | pm_idle = pm_idle_save; | |
1323 | ||
1324 | /* | |
1325 | * We are about to unload the current idle thread pm callback | |
1326 | * (pm_idle), Wait for all processors to update cached/local | |
1327 | * copies of pm_idle before proceeding. | |
1328 | */ | |
1329 | cpu_idle_wait(); | |
1fec74a9 | 1330 | #ifdef CONFIG_SMP |
5c87579e | 1331 | unregister_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1332 | #endif |
1da177e4 LT |
1333 | } |
1334 | ||
d550d98d | 1335 | return 0; |
1da177e4 | 1336 | } |