Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
5c87579e | 41 | #include <linux/latency.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
1da177e4 | 43 | |
3434933b TG |
44 | /* |
45 | * Include the apic definitions for x86 to have the APIC timer related defines | |
46 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
47 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
48 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
49 | */ | |
50 | #ifdef CONFIG_X86 | |
51 | #include <asm/apic.h> | |
52 | #endif | |
53 | ||
1da177e4 LT |
54 | #include <asm/io.h> |
55 | #include <asm/uaccess.h> | |
56 | ||
57 | #include <acpi/acpi_bus.h> | |
58 | #include <acpi/processor.h> | |
59 | ||
60 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
61 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 62 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 63 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 64 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 LT |
65 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
66 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
67 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 68 | static void (*pm_idle_save) (void) __read_mostly; |
1da177e4 LT |
69 | module_param(max_cstate, uint, 0644); |
70 | ||
b6835052 | 71 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
72 | module_param(nocst, uint, 0000); |
73 | ||
74 | /* | |
75 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
76 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
77 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
78 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
79 | * reduce history for more aggressive entry into C3 | |
80 | */ | |
b6835052 | 81 | static unsigned int bm_history __read_mostly = |
4be44fcd | 82 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 LT |
83 | module_param(bm_history, uint, 0644); |
84 | /* -------------------------------------------------------------------------- | |
85 | Power Management | |
86 | -------------------------------------------------------------------------- */ | |
87 | ||
88 | /* | |
89 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
90 | * For now disable this. Probably a bug somewhere else. | |
91 | * | |
92 | * To skip this limit, boot/load with a large max_cstate limit. | |
93 | */ | |
335f16be | 94 | static int set_max_cstate(struct dmi_system_id *id) |
1da177e4 LT |
95 | { |
96 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
97 | return 0; | |
98 | ||
3d35600a | 99 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
100 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
101 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 102 | |
3d35600a | 103 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
7ded5689 AR |
108 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
109 | callers to only run once -AK */ | |
110 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
111 | { set_max_cstate, "IBM ThinkPad R40e", { |
112 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
113 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
114 | { set_max_cstate, "IBM ThinkPad R40e", { |
115 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
116 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
117 | { set_max_cstate, "IBM ThinkPad R40e", { | |
118 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
119 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
120 | { set_max_cstate, "IBM ThinkPad R40e", { | |
121 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
122 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
123 | { set_max_cstate, "IBM ThinkPad R40e", { | |
124 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
125 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
126 | { set_max_cstate, "IBM ThinkPad R40e", { | |
127 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
128 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
129 | { set_max_cstate, "IBM ThinkPad R40e", { | |
130 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
131 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
132 | { set_max_cstate, "IBM ThinkPad R40e", { | |
133 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
134 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
135 | { set_max_cstate, "IBM ThinkPad R40e", { | |
136 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
137 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
138 | { set_max_cstate, "IBM ThinkPad R40e", { | |
139 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
140 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
141 | { set_max_cstate, "IBM ThinkPad R40e", { | |
142 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
143 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
144 | { set_max_cstate, "IBM ThinkPad R40e", { | |
145 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
146 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
147 | { set_max_cstate, "IBM ThinkPad R40e", { | |
148 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
149 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
150 | { set_max_cstate, "IBM ThinkPad R40e", { | |
151 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
152 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
153 | { set_max_cstate, "IBM ThinkPad R40e", { | |
154 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
155 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
156 | { set_max_cstate, "IBM ThinkPad R40e", { | |
157 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
158 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
159 | { set_max_cstate, "Medion 41700", { | |
160 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
161 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
162 | { set_max_cstate, "Clevo 5600D", { | |
163 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
164 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 165 | (void *)2}, |
1da177e4 LT |
166 | {}, |
167 | }; | |
168 | ||
4be44fcd | 169 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
170 | { |
171 | if (t2 >= t1) | |
172 | return (t2 - t1); | |
cee324b1 | 173 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
174 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
175 | else | |
176 | return ((0xFFFFFFFF - t1) + t2); | |
177 | } | |
178 | ||
1da177e4 | 179 | static void |
4be44fcd LB |
180 | acpi_processor_power_activate(struct acpi_processor *pr, |
181 | struct acpi_processor_cx *new) | |
1da177e4 | 182 | { |
4be44fcd | 183 | struct acpi_processor_cx *old; |
1da177e4 LT |
184 | |
185 | if (!pr || !new) | |
186 | return; | |
187 | ||
188 | old = pr->power.state; | |
189 | ||
190 | if (old) | |
191 | old->promotion.count = 0; | |
4be44fcd | 192 | new->demotion.count = 0; |
1da177e4 LT |
193 | |
194 | /* Cleanup from old state. */ | |
195 | if (old) { | |
196 | switch (old->type) { | |
197 | case ACPI_STATE_C3: | |
198 | /* Disable bus master reload */ | |
02df8b93 | 199 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 200 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
201 | break; |
202 | } | |
203 | } | |
204 | ||
205 | /* Prepare to use new state. */ | |
206 | switch (new->type) { | |
207 | case ACPI_STATE_C3: | |
208 | /* Enable bus master reload */ | |
02df8b93 | 209 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 210 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
211 | break; |
212 | } | |
213 | ||
214 | pr->power.state = new; | |
215 | ||
216 | return; | |
217 | } | |
218 | ||
64c7c8f8 NP |
219 | static void acpi_safe_halt(void) |
220 | { | |
495ab9c0 | 221 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
222 | /* |
223 | * TS_POLLING-cleared state must be visible before we | |
224 | * test NEED_RESCHED: | |
225 | */ | |
226 | smp_mb(); | |
64c7c8f8 NP |
227 | if (!need_resched()) |
228 | safe_halt(); | |
495ab9c0 | 229 | current_thread_info()->status |= TS_POLLING; |
64c7c8f8 NP |
230 | } |
231 | ||
4be44fcd | 232 | static atomic_t c3_cpu_count; |
1da177e4 | 233 | |
991528d7 VP |
234 | /* Common C-state entry for C2, C3, .. */ |
235 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
236 | { | |
237 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
238 | /* Call into architectural FFH based C-state */ | |
239 | acpi_processor_ffh_cstate_enter(cstate); | |
240 | } else { | |
241 | int unused; | |
242 | /* IO port based C-state */ | |
243 | inb(cstate->address); | |
244 | /* Dummy wait op - must do something useless after P_LVL2 read | |
245 | because chipsets cannot guarantee that STPCLK# signal | |
246 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 247 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
248 | } |
249 | } | |
250 | ||
169a0abb TG |
251 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
252 | ||
253 | /* | |
254 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
255 | * This seems to be a common problem on AMD boxen, but other vendors |
256 | * are affected too. We pick the most conservative approach: we assume | |
257 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
258 | */ |
259 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
260 | struct acpi_processor_cx *cx) | |
261 | { | |
262 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 263 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
264 | |
265 | /* | |
266 | * Check, if one of the previous states already marked the lapic | |
267 | * unstable | |
268 | */ | |
269 | if (pwr->timer_broadcast_on_state < state) | |
270 | return; | |
271 | ||
e585bef8 | 272 | if (cx->type >= type) |
296d93cd | 273 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
274 | } |
275 | ||
276 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
277 | { | |
e9e2cdb4 TG |
278 | #ifdef CONFIG_GENERIC_CLOCKEVENTS |
279 | unsigned long reason; | |
280 | ||
281 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
282 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
283 | ||
284 | clockevents_notify(reason, &pr->id); | |
285 | #else | |
169a0abb TG |
286 | cpumask_t mask = cpumask_of_cpu(pr->id); |
287 | ||
296d93cd | 288 | if (pr->power.timer_broadcast_on_state < INT_MAX) |
169a0abb | 289 | on_each_cpu(switch_APIC_timer_to_ipi, &mask, 1, 1); |
296d93cd | 290 | else |
169a0abb | 291 | on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1); |
e9e2cdb4 TG |
292 | #endif |
293 | } | |
294 | ||
295 | /* Power(C) State timer broadcast control */ | |
296 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
297 | struct acpi_processor_cx *cx, | |
298 | int broadcast) | |
299 | { | |
300 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | |
301 | ||
302 | int state = cx - pr->power.states; | |
303 | ||
304 | if (state >= pr->power.timer_broadcast_on_state) { | |
305 | unsigned long reason; | |
306 | ||
307 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
308 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
309 | clockevents_notify(reason, &pr->id); | |
310 | } | |
311 | #endif | |
169a0abb TG |
312 | } |
313 | ||
314 | #else | |
315 | ||
316 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
317 | struct acpi_processor_cx *cstate) { } | |
318 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
319 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
320 | struct acpi_processor_cx *cx, | |
321 | int broadcast) | |
322 | { | |
323 | } | |
169a0abb TG |
324 | |
325 | #endif | |
326 | ||
4be44fcd | 327 | static void acpi_processor_idle(void) |
1da177e4 | 328 | { |
4be44fcd | 329 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
330 | struct acpi_processor_cx *cx = NULL; |
331 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
332 | int sleep_ticks = 0; |
333 | u32 t1, t2 = 0; | |
1da177e4 | 334 | |
64c7c8f8 | 335 | pr = processors[smp_processor_id()]; |
1da177e4 LT |
336 | if (!pr) |
337 | return; | |
338 | ||
339 | /* | |
340 | * Interrupts must be disabled during bus mastering calculations and | |
341 | * for C2/C3 transitions. | |
342 | */ | |
343 | local_irq_disable(); | |
344 | ||
345 | /* | |
346 | * Check whether we truly need to go idle, or should | |
347 | * reschedule: | |
348 | */ | |
349 | if (unlikely(need_resched())) { | |
350 | local_irq_enable(); | |
351 | return; | |
352 | } | |
353 | ||
354 | cx = pr->power.state; | |
64c7c8f8 NP |
355 | if (!cx) { |
356 | if (pm_idle_save) | |
357 | pm_idle_save(); | |
358 | else | |
359 | acpi_safe_halt(); | |
360 | return; | |
361 | } | |
1da177e4 LT |
362 | |
363 | /* | |
364 | * Check BM Activity | |
365 | * ----------------- | |
366 | * Check for bus mastering activity (if required), record, and check | |
367 | * for demotion. | |
368 | */ | |
369 | if (pr->flags.bm_check) { | |
4be44fcd LB |
370 | u32 bm_status = 0; |
371 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 372 | |
c5ab81ca DB |
373 | if (diff > 31) |
374 | diff = 31; | |
1da177e4 | 375 | |
c5ab81ca | 376 | pr->power.bm_activity <<= diff; |
1da177e4 | 377 | |
d8c71b6d | 378 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 379 | if (bm_status) { |
c5ab81ca | 380 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 381 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
382 | } |
383 | /* | |
384 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
385 | * the true state of bus mastering activity; forcing us to | |
386 | * manually check the BMIDEA bit of each IDE channel. | |
387 | */ | |
388 | else if (errata.piix4.bmisx) { | |
389 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 390 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 391 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
392 | } |
393 | ||
394 | pr->power.bm_check_timestamp = jiffies; | |
395 | ||
396 | /* | |
c4a001b1 | 397 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
398 | * to avoid a faulty transition. Note that the processor |
399 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 400 | * function) but should upon the next. |
1da177e4 LT |
401 | * |
402 | * TBD: A better policy might be to fallback to the demotion | |
403 | * state (use it for this quantum only) istead of | |
404 | * demoting -- and rely on duration as our sole demotion | |
405 | * qualification. This may, however, introduce DMA | |
406 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
407 | */ | |
c4a001b1 DB |
408 | if ((pr->power.bm_activity & 0x1) && |
409 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
410 | local_irq_enable(); |
411 | next_state = cx->demotion.state; | |
412 | goto end; | |
413 | } | |
414 | } | |
415 | ||
4c033552 VP |
416 | #ifdef CONFIG_HOTPLUG_CPU |
417 | /* | |
418 | * Check for P_LVL2_UP flag before entering C2 and above on | |
419 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
420 | * detection phase, to work cleanly with logical CPU hotplug. | |
421 | */ | |
422 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 423 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 424 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 425 | #endif |
1e483969 | 426 | |
1da177e4 LT |
427 | /* |
428 | * Sleep: | |
429 | * ------ | |
430 | * Invoke the current Cx state to put the processor to sleep. | |
431 | */ | |
2a298a35 | 432 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 433 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
434 | /* |
435 | * TS_POLLING-cleared state must be visible before we | |
436 | * test NEED_RESCHED: | |
437 | */ | |
438 | smp_mb(); | |
2a298a35 | 439 | if (need_resched()) { |
495ab9c0 | 440 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 441 | local_irq_enable(); |
2a298a35 NP |
442 | return; |
443 | } | |
444 | } | |
445 | ||
1da177e4 LT |
446 | switch (cx->type) { |
447 | ||
448 | case ACPI_STATE_C1: | |
449 | /* | |
450 | * Invoke C1. | |
451 | * Use the appropriate idle routine, the one that would | |
452 | * be used without acpi C-states. | |
453 | */ | |
454 | if (pm_idle_save) | |
455 | pm_idle_save(); | |
456 | else | |
64c7c8f8 NP |
457 | acpi_safe_halt(); |
458 | ||
1da177e4 | 459 | /* |
4be44fcd | 460 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
461 | * go to an ISR rather than here. Need to instrument |
462 | * base interrupt handler. | |
463 | */ | |
464 | sleep_ticks = 0xFFFFFFFF; | |
465 | break; | |
466 | ||
467 | case ACPI_STATE_C2: | |
468 | /* Get start time (ticks) */ | |
cee324b1 | 469 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 470 | /* Invoke C2 */ |
e9e2cdb4 | 471 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 472 | acpi_cstate_enter(cx); |
1da177e4 | 473 | /* Get end time (ticks) */ |
cee324b1 | 474 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 475 | |
476 | #ifdef CONFIG_GENERIC_TIME | |
477 | /* TSC halts in C2, so notify users */ | |
5a90cf20 | 478 | mark_tsc_unstable("possible TSC halt in C2"); |
539eb11e | 479 | #endif |
1da177e4 LT |
480 | /* Re-enable interrupts */ |
481 | local_irq_enable(); | |
495ab9c0 | 482 | current_thread_info()->status |= TS_POLLING; |
1da177e4 | 483 | /* Compute time (ticks) that we were actually asleep */ |
4be44fcd LB |
484 | sleep_ticks = |
485 | ticks_elapsed(t1, t2) - cx->latency_ticks - C2_OVERHEAD; | |
e9e2cdb4 | 486 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
487 | break; |
488 | ||
489 | case ACPI_STATE_C3: | |
4be44fcd | 490 | |
18eab855 VP |
491 | /* |
492 | * disable bus master | |
493 | * bm_check implies we need ARB_DIS | |
494 | * !bm_check implies we need cache flush | |
495 | * bm_control implies whether we can do ARB_DIS | |
496 | * | |
497 | * That leaves a case where bm_check is set and bm_control is | |
498 | * not set. In that case we cannot do much, we enter C3 | |
499 | * without doing anything. | |
500 | */ | |
501 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 502 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 503 | num_online_cpus()) { |
02df8b93 VP |
504 | /* |
505 | * All CPUs are trying to go to C3 | |
506 | * Disable bus master arbitration | |
507 | */ | |
d8c71b6d | 508 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 509 | } |
18eab855 | 510 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
511 | /* SMP with no shared cache... Invalidate cache */ |
512 | ACPI_FLUSH_CPU_CACHE(); | |
513 | } | |
4be44fcd | 514 | |
1da177e4 | 515 | /* Get start time (ticks) */ |
cee324b1 | 516 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 517 | /* Invoke C3 */ |
e9e2cdb4 | 518 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 519 | acpi_cstate_enter(cx); |
1da177e4 | 520 | /* Get end time (ticks) */ |
cee324b1 | 521 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 522 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
523 | /* Enable bus master arbitration */ |
524 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 525 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
526 | } |
527 | ||
539eb11e | 528 | #ifdef CONFIG_GENERIC_TIME |
529 | /* TSC halts in C3, so notify users */ | |
5a90cf20 | 530 | mark_tsc_unstable("TSC halts in C3"); |
539eb11e | 531 | #endif |
1da177e4 LT |
532 | /* Re-enable interrupts */ |
533 | local_irq_enable(); | |
495ab9c0 | 534 | current_thread_info()->status |= TS_POLLING; |
1da177e4 | 535 | /* Compute time (ticks) that we were actually asleep */ |
4be44fcd LB |
536 | sleep_ticks = |
537 | ticks_elapsed(t1, t2) - cx->latency_ticks - C3_OVERHEAD; | |
e9e2cdb4 | 538 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
539 | break; |
540 | ||
541 | default: | |
542 | local_irq_enable(); | |
543 | return; | |
544 | } | |
a3c6598f DB |
545 | cx->usage++; |
546 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
547 | cx->time += sleep_ticks; | |
1da177e4 LT |
548 | |
549 | next_state = pr->power.state; | |
550 | ||
1e483969 DSL |
551 | #ifdef CONFIG_HOTPLUG_CPU |
552 | /* Don't do promotion/demotion */ | |
553 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 554 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
555 | next_state = cx; |
556 | goto end; | |
557 | } | |
558 | #endif | |
559 | ||
1da177e4 LT |
560 | /* |
561 | * Promotion? | |
562 | * ---------- | |
563 | * Track the number of longs (time asleep is greater than threshold) | |
564 | * and promote when the count threshold is reached. Note that bus | |
565 | * mastering activity may prevent promotions. | |
566 | * Do not promote above max_cstate. | |
567 | */ | |
568 | if (cx->promotion.state && | |
569 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e AV |
570 | if (sleep_ticks > cx->promotion.threshold.ticks && |
571 | cx->promotion.state->latency <= system_latency_constraint()) { | |
1da177e4 | 572 | cx->promotion.count++; |
4be44fcd LB |
573 | cx->demotion.count = 0; |
574 | if (cx->promotion.count >= | |
575 | cx->promotion.threshold.count) { | |
1da177e4 | 576 | if (pr->flags.bm_check) { |
4be44fcd LB |
577 | if (! |
578 | (pr->power.bm_activity & cx-> | |
579 | promotion.threshold.bm)) { | |
580 | next_state = | |
581 | cx->promotion.state; | |
1da177e4 LT |
582 | goto end; |
583 | } | |
4be44fcd | 584 | } else { |
1da177e4 LT |
585 | next_state = cx->promotion.state; |
586 | goto end; | |
587 | } | |
588 | } | |
589 | } | |
590 | } | |
591 | ||
592 | /* | |
593 | * Demotion? | |
594 | * --------- | |
595 | * Track the number of shorts (time asleep is less than time threshold) | |
596 | * and demote when the usage threshold is reached. | |
597 | */ | |
598 | if (cx->demotion.state) { | |
599 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
600 | cx->demotion.count++; | |
601 | cx->promotion.count = 0; | |
602 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
603 | next_state = cx->demotion.state; | |
604 | goto end; | |
605 | } | |
606 | } | |
607 | } | |
608 | ||
4be44fcd | 609 | end: |
1da177e4 LT |
610 | /* |
611 | * Demote if current state exceeds max_cstate | |
5c87579e | 612 | * or if the latency of the current state is unacceptable |
1da177e4 | 613 | */ |
5c87579e AV |
614 | if ((pr->power.state - pr->power.states) > max_cstate || |
615 | pr->power.state->latency > system_latency_constraint()) { | |
1da177e4 LT |
616 | if (cx->demotion.state) |
617 | next_state = cx->demotion.state; | |
618 | } | |
619 | ||
620 | /* | |
621 | * New Cx State? | |
622 | * ------------- | |
623 | * If we're going to start using a new Cx state we must clean up | |
624 | * from the previous and prepare to use the new. | |
625 | */ | |
626 | if (next_state != pr->power.state) | |
627 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
628 | } |
629 | ||
4be44fcd | 630 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
631 | { |
632 | unsigned int i; | |
633 | unsigned int state_is_set = 0; | |
634 | struct acpi_processor_cx *lower = NULL; | |
635 | struct acpi_processor_cx *higher = NULL; | |
636 | struct acpi_processor_cx *cx; | |
637 | ||
1da177e4 LT |
638 | |
639 | if (!pr) | |
d550d98d | 640 | return -EINVAL; |
1da177e4 LT |
641 | |
642 | /* | |
643 | * This function sets the default Cx state policy (OS idle handler). | |
644 | * Our scheme is to promote quickly to C2 but more conservatively | |
645 | * to C3. We're favoring C2 for its characteristics of low latency | |
646 | * (quick response), good power savings, and ability to allow bus | |
647 | * mastering activity. Note that the Cx state policy is completely | |
648 | * customizable and can be altered dynamically. | |
649 | */ | |
650 | ||
651 | /* startup state */ | |
4be44fcd | 652 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
653 | cx = &pr->power.states[i]; |
654 | if (!cx->valid) | |
655 | continue; | |
656 | ||
657 | if (!state_is_set) | |
658 | pr->power.state = cx; | |
659 | state_is_set++; | |
660 | break; | |
4be44fcd | 661 | } |
1da177e4 LT |
662 | |
663 | if (!state_is_set) | |
d550d98d | 664 | return -ENODEV; |
1da177e4 LT |
665 | |
666 | /* demotion */ | |
4be44fcd | 667 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
668 | cx = &pr->power.states[i]; |
669 | if (!cx->valid) | |
670 | continue; | |
671 | ||
672 | if (lower) { | |
673 | cx->demotion.state = lower; | |
674 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
675 | cx->demotion.threshold.count = 1; | |
676 | if (cx->type == ACPI_STATE_C3) | |
677 | cx->demotion.threshold.bm = bm_history; | |
678 | } | |
679 | ||
680 | lower = cx; | |
681 | } | |
682 | ||
683 | /* promotion */ | |
684 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
685 | cx = &pr->power.states[i]; | |
686 | if (!cx->valid) | |
687 | continue; | |
688 | ||
689 | if (higher) { | |
4be44fcd | 690 | cx->promotion.state = higher; |
1da177e4 LT |
691 | cx->promotion.threshold.ticks = cx->latency_ticks; |
692 | if (cx->type >= ACPI_STATE_C2) | |
693 | cx->promotion.threshold.count = 4; | |
694 | else | |
695 | cx->promotion.threshold.count = 10; | |
696 | if (higher->type == ACPI_STATE_C3) | |
697 | cx->promotion.threshold.bm = bm_history; | |
698 | } | |
699 | ||
700 | higher = cx; | |
701 | } | |
702 | ||
d550d98d | 703 | return 0; |
1da177e4 LT |
704 | } |
705 | ||
4be44fcd | 706 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 707 | { |
1da177e4 LT |
708 | |
709 | if (!pr) | |
d550d98d | 710 | return -EINVAL; |
1da177e4 LT |
711 | |
712 | if (!pr->pblk) | |
d550d98d | 713 | return -ENODEV; |
1da177e4 | 714 | |
1da177e4 | 715 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
716 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
717 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
718 | ||
4c033552 VP |
719 | #ifndef CONFIG_HOTPLUG_CPU |
720 | /* | |
721 | * Check for P_LVL2_UP flag before entering C2 and above on | |
722 | * an SMP system. | |
723 | */ | |
ad71860a | 724 | if ((num_online_cpus() > 1) && |
cee324b1 | 725 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 726 | return -ENODEV; |
4c033552 VP |
727 | #endif |
728 | ||
1da177e4 LT |
729 | /* determine C2 and C3 address from pblk */ |
730 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
731 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
732 | ||
733 | /* determine latencies from FADT */ | |
cee324b1 AS |
734 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
735 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
736 | |
737 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
738 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
739 | pr->power.states[ACPI_STATE_C2].address, | |
740 | pr->power.states[ACPI_STATE_C3].address)); | |
741 | ||
d550d98d | 742 | return 0; |
1da177e4 LT |
743 | } |
744 | ||
991528d7 | 745 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 746 | { |
991528d7 VP |
747 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
748 | /* set the first C-State to C1 */ | |
749 | /* all processors need to support C1 */ | |
750 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
751 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
752 | } | |
753 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 754 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 755 | return 0; |
acf05f4b VP |
756 | } |
757 | ||
4be44fcd | 758 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 759 | { |
4be44fcd LB |
760 | acpi_status status = 0; |
761 | acpi_integer count; | |
cf824788 | 762 | int current_count; |
4be44fcd LB |
763 | int i; |
764 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
765 | union acpi_object *cst; | |
1da177e4 | 766 | |
1da177e4 | 767 | |
1da177e4 | 768 | if (nocst) |
d550d98d | 769 | return -ENODEV; |
1da177e4 | 770 | |
991528d7 | 771 | current_count = 0; |
1da177e4 LT |
772 | |
773 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
774 | if (ACPI_FAILURE(status)) { | |
775 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 776 | return -ENODEV; |
4be44fcd | 777 | } |
1da177e4 | 778 | |
50dd0969 | 779 | cst = buffer.pointer; |
1da177e4 LT |
780 | |
781 | /* There must be at least 2 elements */ | |
782 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 783 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
784 | status = -EFAULT; |
785 | goto end; | |
786 | } | |
787 | ||
788 | count = cst->package.elements[0].integer.value; | |
789 | ||
790 | /* Validate number of power states. */ | |
791 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 792 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
793 | status = -EFAULT; |
794 | goto end; | |
795 | } | |
796 | ||
1da177e4 LT |
797 | /* Tell driver that at least _CST is supported. */ |
798 | pr->flags.has_cst = 1; | |
799 | ||
800 | for (i = 1; i <= count; i++) { | |
801 | union acpi_object *element; | |
802 | union acpi_object *obj; | |
803 | struct acpi_power_register *reg; | |
804 | struct acpi_processor_cx cx; | |
805 | ||
806 | memset(&cx, 0, sizeof(cx)); | |
807 | ||
50dd0969 | 808 | element = &(cst->package.elements[i]); |
1da177e4 LT |
809 | if (element->type != ACPI_TYPE_PACKAGE) |
810 | continue; | |
811 | ||
812 | if (element->package.count != 4) | |
813 | continue; | |
814 | ||
50dd0969 | 815 | obj = &(element->package.elements[0]); |
1da177e4 LT |
816 | |
817 | if (obj->type != ACPI_TYPE_BUFFER) | |
818 | continue; | |
819 | ||
4be44fcd | 820 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
821 | |
822 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 823 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
824 | continue; |
825 | ||
1da177e4 | 826 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 827 | obj = &(element->package.elements[1]); |
1da177e4 LT |
828 | if (obj->type != ACPI_TYPE_INTEGER) |
829 | continue; | |
830 | ||
831 | cx.type = obj->integer.value; | |
991528d7 VP |
832 | /* |
833 | * Some buggy BIOSes won't list C1 in _CST - | |
834 | * Let acpi_processor_get_power_info_default() handle them later | |
835 | */ | |
836 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
837 | current_count++; | |
838 | ||
839 | cx.address = reg->address; | |
840 | cx.index = current_count + 1; | |
841 | ||
842 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
843 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
844 | if (acpi_processor_ffh_cstate_probe | |
845 | (pr->id, &cx, reg) == 0) { | |
846 | cx.space_id = ACPI_CSTATE_FFH; | |
847 | } else if (cx.type != ACPI_STATE_C1) { | |
848 | /* | |
849 | * C1 is a special case where FIXED_HARDWARE | |
850 | * can be handled in non-MWAIT way as well. | |
851 | * In that case, save this _CST entry info. | |
852 | * That is, we retain space_id of SYSTEM_IO for | |
853 | * halt based C1. | |
854 | * Otherwise, ignore this info and continue. | |
855 | */ | |
856 | continue; | |
857 | } | |
858 | } | |
1da177e4 | 859 | |
50dd0969 | 860 | obj = &(element->package.elements[2]); |
1da177e4 LT |
861 | if (obj->type != ACPI_TYPE_INTEGER) |
862 | continue; | |
863 | ||
864 | cx.latency = obj->integer.value; | |
865 | ||
50dd0969 | 866 | obj = &(element->package.elements[3]); |
1da177e4 LT |
867 | if (obj->type != ACPI_TYPE_INTEGER) |
868 | continue; | |
869 | ||
870 | cx.power = obj->integer.value; | |
871 | ||
cf824788 JM |
872 | current_count++; |
873 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
874 | ||
875 | /* | |
876 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
877 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
878 | */ | |
879 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
880 | printk(KERN_WARNING | |
881 | "Limiting number of power states to max (%d)\n", | |
882 | ACPI_PROCESSOR_MAX_POWER); | |
883 | printk(KERN_WARNING | |
884 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
885 | break; | |
886 | } | |
1da177e4 LT |
887 | } |
888 | ||
4be44fcd | 889 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 890 | current_count)); |
1da177e4 LT |
891 | |
892 | /* Validate number of power states discovered */ | |
cf824788 | 893 | if (current_count < 2) |
6d93c648 | 894 | status = -EFAULT; |
1da177e4 | 895 | |
4be44fcd | 896 | end: |
02438d87 | 897 | kfree(buffer.pointer); |
1da177e4 | 898 | |
d550d98d | 899 | return status; |
1da177e4 LT |
900 | } |
901 | ||
1da177e4 LT |
902 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
903 | { | |
1da177e4 LT |
904 | |
905 | if (!cx->address) | |
d550d98d | 906 | return; |
1da177e4 LT |
907 | |
908 | /* | |
909 | * C2 latency must be less than or equal to 100 | |
910 | * microseconds. | |
911 | */ | |
912 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
913 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 914 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 915 | return; |
1da177e4 LT |
916 | } |
917 | ||
1da177e4 LT |
918 | /* |
919 | * Otherwise we've met all of our C2 requirements. | |
920 | * Normalize the C2 latency to expidite policy | |
921 | */ | |
922 | cx->valid = 1; | |
923 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); | |
924 | ||
d550d98d | 925 | return; |
1da177e4 LT |
926 | } |
927 | ||
4be44fcd LB |
928 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
929 | struct acpi_processor_cx *cx) | |
1da177e4 | 930 | { |
02df8b93 VP |
931 | static int bm_check_flag; |
932 | ||
1da177e4 LT |
933 | |
934 | if (!cx->address) | |
d550d98d | 935 | return; |
1da177e4 LT |
936 | |
937 | /* | |
938 | * C3 latency must be less than or equal to 1000 | |
939 | * microseconds. | |
940 | */ | |
941 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
942 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 943 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 944 | return; |
1da177e4 LT |
945 | } |
946 | ||
1da177e4 LT |
947 | /* |
948 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
949 | * DMA transfers are used by any ISA device to avoid livelock. | |
950 | * Note that we could disable Type-F DMA (as recommended by | |
951 | * the erratum), but this is known to disrupt certain ISA | |
952 | * devices thus we take the conservative approach. | |
953 | */ | |
954 | else if (errata.piix4.fdma) { | |
955 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 956 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 957 | return; |
1da177e4 LT |
958 | } |
959 | ||
02df8b93 VP |
960 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
961 | if (!bm_check_flag) { | |
962 | /* Determine whether bm_check is needed based on CPU */ | |
963 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
964 | bm_check_flag = pr->flags.bm_check; | |
965 | } else { | |
966 | pr->flags.bm_check = bm_check_flag; | |
967 | } | |
968 | ||
969 | if (pr->flags.bm_check) { | |
02df8b93 VP |
970 | /* bus mastering control is necessary */ |
971 | if (!pr->flags.bm_control) { | |
18eab855 | 972 | /* In this case we enter C3 without bus mastering */ |
02df8b93 | 973 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
18eab855 | 974 | "C3 support without bus mastering control\n")); |
02df8b93 VP |
975 | } |
976 | } else { | |
02df8b93 VP |
977 | /* |
978 | * WBINVD should be set in fadt, for C3 state to be | |
979 | * supported on when bm_check is not required. | |
980 | */ | |
cee324b1 | 981 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 982 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
983 | "Cache invalidation should work properly" |
984 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 985 | return; |
02df8b93 | 986 | } |
d8c71b6d | 987 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
988 | } |
989 | ||
1da177e4 LT |
990 | /* |
991 | * Otherwise we've met all of our C3 requirements. | |
992 | * Normalize the C3 latency to expidite policy. Enable | |
993 | * checking of bus mastering status (bm_check) so we can | |
994 | * use this in our C3 policy | |
995 | */ | |
996 | cx->valid = 1; | |
997 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); | |
1da177e4 | 998 | |
d550d98d | 999 | return; |
1da177e4 LT |
1000 | } |
1001 | ||
1da177e4 LT |
1002 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1003 | { | |
1004 | unsigned int i; | |
1005 | unsigned int working = 0; | |
6eb0a0fd | 1006 | |
169a0abb | 1007 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1008 | |
4be44fcd | 1009 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1010 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1011 | ||
1012 | switch (cx->type) { | |
1013 | case ACPI_STATE_C1: | |
1014 | cx->valid = 1; | |
1015 | break; | |
1016 | ||
1017 | case ACPI_STATE_C2: | |
1018 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1019 | if (cx->valid) |
169a0abb | 1020 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1021 | break; |
1022 | ||
1023 | case ACPI_STATE_C3: | |
1024 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1025 | if (cx->valid) |
169a0abb | 1026 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1027 | break; |
1028 | } | |
1029 | ||
1030 | if (cx->valid) | |
1031 | working++; | |
1032 | } | |
bd663347 | 1033 | |
169a0abb | 1034 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1035 | |
1036 | return (working); | |
1037 | } | |
1038 | ||
4be44fcd | 1039 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1040 | { |
1041 | unsigned int i; | |
1042 | int result; | |
1043 | ||
1da177e4 LT |
1044 | |
1045 | /* NOTE: the idle thread may not be running while calling | |
1046 | * this function */ | |
1047 | ||
991528d7 VP |
1048 | /* Zero initialize all the C-states info. */ |
1049 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1050 | ||
1da177e4 | 1051 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1052 | if (result == -ENODEV) |
c5a114f1 | 1053 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1054 | |
991528d7 VP |
1055 | if (result) |
1056 | return result; | |
1057 | ||
1058 | acpi_processor_get_power_info_default(pr); | |
1059 | ||
cf824788 | 1060 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 LT |
1061 | |
1062 | /* | |
1063 | * Set Default Policy | |
1064 | * ------------------ | |
1065 | * Now that we know which states are supported, set the default | |
1066 | * policy. Note that this policy can be changed dynamically | |
1067 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1068 | * not on AC). | |
1069 | */ | |
1070 | result = acpi_processor_set_power_policy(pr); | |
1071 | if (result) | |
d550d98d | 1072 | return result; |
1da177e4 LT |
1073 | |
1074 | /* | |
1075 | * if one state of type C2 or C3 is available, mark this | |
1076 | * CPU as being "idle manageable" | |
1077 | */ | |
1078 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1079 | if (pr->power.states[i].valid) { |
1da177e4 | 1080 | pr->power.count = i; |
2203d6ed LT |
1081 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1082 | pr->flags.power = 1; | |
acf05f4b | 1083 | } |
1da177e4 LT |
1084 | } |
1085 | ||
d550d98d | 1086 | return 0; |
1da177e4 LT |
1087 | } |
1088 | ||
4be44fcd | 1089 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1da177e4 | 1090 | { |
4be44fcd | 1091 | int result = 0; |
1da177e4 | 1092 | |
1da177e4 LT |
1093 | |
1094 | if (!pr) | |
d550d98d | 1095 | return -EINVAL; |
1da177e4 | 1096 | |
4be44fcd | 1097 | if (nocst) { |
d550d98d | 1098 | return -ENODEV; |
1da177e4 LT |
1099 | } |
1100 | ||
1101 | if (!pr->flags.power_setup_done) | |
d550d98d | 1102 | return -ENODEV; |
1da177e4 LT |
1103 | |
1104 | /* Fall back to the default idle loop */ | |
1105 | pm_idle = pm_idle_save; | |
4be44fcd | 1106 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ |
1da177e4 LT |
1107 | |
1108 | pr->flags.power = 0; | |
1109 | result = acpi_processor_get_power_info(pr); | |
1110 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1111 | pm_idle = acpi_processor_idle; | |
1112 | ||
d550d98d | 1113 | return result; |
1da177e4 LT |
1114 | } |
1115 | ||
1116 | /* proc interface */ | |
1117 | ||
1118 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) | |
1119 | { | |
50dd0969 | 1120 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1121 | unsigned int i; |
1da177e4 | 1122 | |
1da177e4 LT |
1123 | |
1124 | if (!pr) | |
1125 | goto end; | |
1126 | ||
1127 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1128 | "max_cstate: C%d\n" |
5c87579e AV |
1129 | "bus master activity: %08x\n" |
1130 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1131 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e AV |
1132 | max_cstate, (unsigned)pr->power.bm_activity, |
1133 | system_latency_constraint()); | |
1da177e4 LT |
1134 | |
1135 | seq_puts(seq, "states:\n"); | |
1136 | ||
1137 | for (i = 1; i <= pr->power.count; i++) { | |
1138 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1139 | (&pr->power.states[i] == |
1140 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1141 | |
1142 | if (!pr->power.states[i].valid) { | |
1143 | seq_puts(seq, "<not supported>\n"); | |
1144 | continue; | |
1145 | } | |
1146 | ||
1147 | switch (pr->power.states[i].type) { | |
1148 | case ACPI_STATE_C1: | |
1149 | seq_printf(seq, "type[C1] "); | |
1150 | break; | |
1151 | case ACPI_STATE_C2: | |
1152 | seq_printf(seq, "type[C2] "); | |
1153 | break; | |
1154 | case ACPI_STATE_C3: | |
1155 | seq_printf(seq, "type[C3] "); | |
1156 | break; | |
1157 | default: | |
1158 | seq_printf(seq, "type[--] "); | |
1159 | break; | |
1160 | } | |
1161 | ||
1162 | if (pr->power.states[i].promotion.state) | |
1163 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1164 | (pr->power.states[i].promotion.state - |
1165 | pr->power.states)); | |
1da177e4 LT |
1166 | else |
1167 | seq_puts(seq, "promotion[--] "); | |
1168 | ||
1169 | if (pr->power.states[i].demotion.state) | |
1170 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1171 | (pr->power.states[i].demotion.state - |
1172 | pr->power.states)); | |
1da177e4 LT |
1173 | else |
1174 | seq_puts(seq, "demotion[--] "); | |
1175 | ||
a3c6598f | 1176 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1177 | pr->power.states[i].latency, |
a3c6598f | 1178 | pr->power.states[i].usage, |
b0b7eaaf | 1179 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1180 | } |
1181 | ||
4be44fcd | 1182 | end: |
d550d98d | 1183 | return 0; |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1187 | { | |
1188 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1189 | PDE(inode)->data); |
1da177e4 LT |
1190 | } |
1191 | ||
d7508032 | 1192 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1193 | .open = acpi_processor_power_open_fs, |
1194 | .read = seq_read, | |
1195 | .llseek = seq_lseek, | |
1196 | .release = single_release, | |
1da177e4 LT |
1197 | }; |
1198 | ||
1fec74a9 | 1199 | #ifdef CONFIG_SMP |
5c87579e AV |
1200 | static void smp_callback(void *v) |
1201 | { | |
1202 | /* we already woke the CPU up, nothing more to do */ | |
1203 | } | |
1204 | ||
1205 | /* | |
1206 | * This function gets called when a part of the kernel has a new latency | |
1207 | * requirement. This means we need to get all processors out of their C-state, | |
1208 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1209 | * wakes them all right up. | |
1210 | */ | |
1211 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1212 | unsigned long l, void *v) | |
1213 | { | |
1214 | smp_call_function(smp_callback, NULL, 0, 1); | |
1215 | return NOTIFY_OK; | |
1216 | } | |
1217 | ||
1218 | static struct notifier_block acpi_processor_latency_notifier = { | |
1219 | .notifier_call = acpi_processor_latency_notify, | |
1220 | }; | |
1fec74a9 | 1221 | #endif |
5c87579e | 1222 | |
7af8b660 | 1223 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1224 | struct acpi_device *device) |
1da177e4 | 1225 | { |
4be44fcd | 1226 | acpi_status status = 0; |
b6835052 | 1227 | static int first_run; |
4be44fcd | 1228 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1229 | unsigned int i; |
1230 | ||
1da177e4 LT |
1231 | |
1232 | if (!first_run) { | |
1233 | dmi_check_system(processor_power_dmi_table); | |
1234 | if (max_cstate < ACPI_C_STATES_MAX) | |
4be44fcd LB |
1235 | printk(KERN_NOTICE |
1236 | "ACPI: processor limited to max C-state %d\n", | |
1237 | max_cstate); | |
1da177e4 | 1238 | first_run++; |
1fec74a9 | 1239 | #ifdef CONFIG_SMP |
5c87579e | 1240 | register_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1241 | #endif |
1da177e4 LT |
1242 | } |
1243 | ||
02df8b93 | 1244 | if (!pr) |
d550d98d | 1245 | return -EINVAL; |
02df8b93 | 1246 | |
cee324b1 | 1247 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1248 | status = |
cee324b1 | 1249 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1250 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1251 | ACPI_EXCEPTION((AE_INFO, status, |
1252 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1253 | } |
1254 | } | |
1255 | ||
1256 | acpi_processor_get_power_info(pr); | |
1257 | ||
1258 | /* | |
1259 | * Install the idle handler if processor power management is supported. | |
1260 | * Note that we use previously set idle handler will be used on | |
1261 | * platforms that only support C1. | |
1262 | */ | |
1263 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
1264 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); | |
1265 | for (i = 1; i <= pr->power.count; i++) | |
1266 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1267 | printk(" C%d[C%d]", i, |
1268 | pr->power.states[i].type); | |
1da177e4 LT |
1269 | printk(")\n"); |
1270 | ||
1271 | if (pr->id == 0) { | |
1272 | pm_idle_save = pm_idle; | |
1273 | pm_idle = acpi_processor_idle; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | /* 'power' [R] */ | |
1278 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1279 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1280 | if (!entry) |
a6fc6720 | 1281 | return -EIO; |
1da177e4 LT |
1282 | else { |
1283 | entry->proc_fops = &acpi_processor_power_fops; | |
1284 | entry->data = acpi_driver_data(device); | |
1285 | entry->owner = THIS_MODULE; | |
1286 | } | |
1287 | ||
1288 | pr->flags.power_setup_done = 1; | |
1289 | ||
d550d98d | 1290 | return 0; |
1da177e4 LT |
1291 | } |
1292 | ||
4be44fcd LB |
1293 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1294 | struct acpi_device *device) | |
1da177e4 | 1295 | { |
1da177e4 LT |
1296 | |
1297 | pr->flags.power_setup_done = 0; | |
1298 | ||
1299 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1300 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1301 | acpi_device_dir(device)); | |
1da177e4 LT |
1302 | |
1303 | /* Unregister the idle handler when processor #0 is removed. */ | |
1304 | if (pr->id == 0) { | |
1305 | pm_idle = pm_idle_save; | |
1306 | ||
1307 | /* | |
1308 | * We are about to unload the current idle thread pm callback | |
1309 | * (pm_idle), Wait for all processors to update cached/local | |
1310 | * copies of pm_idle before proceeding. | |
1311 | */ | |
1312 | cpu_idle_wait(); | |
1fec74a9 | 1313 | #ifdef CONFIG_SMP |
5c87579e | 1314 | unregister_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1315 | #endif |
1da177e4 LT |
1316 | } |
1317 | ||
d550d98d | 1318 | return 0; |
1da177e4 | 1319 | } |