Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
ba84be23 | 44 | #include <linux/irqflags.h> |
1da177e4 | 45 | |
3434933b TG |
46 | /* |
47 | * Include the apic definitions for x86 to have the APIC timer related defines | |
48 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
49 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
50 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
51 | */ | |
52 | #ifdef CONFIG_X86 | |
53 | #include <asm/apic.h> | |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include <asm/io.h> |
57 | #include <asm/uaccess.h> | |
58 | ||
59 | #include <acpi/acpi_bus.h> | |
60 | #include <acpi/processor.h> | |
c1e3b377 | 61 | #include <asm/processor.h> |
1da177e4 | 62 | |
1da177e4 | 63 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 64 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 65 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 66 | #define ACPI_PROCESSOR_FILE_POWER "power" |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
68 | #define C2_OVERHEAD 1 /* 1us */ |
69 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 70 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 71 | |
4f86d3a8 LB |
72 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
73 | module_param(max_cstate, uint, 0000); | |
b6835052 | 74 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
75 | module_param(nocst, uint, 0000); |
76 | ||
25de5718 | 77 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 78 | module_param(latency_factor, uint, 0644); |
1da177e4 | 79 | |
ff69f2bb | 80 | static s64 us_to_pm_timer_ticks(s64 t) |
81 | { | |
82 | return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); | |
83 | } | |
1da177e4 LT |
84 | /* |
85 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
86 | * For now disable this. Probably a bug somewhere else. | |
87 | * | |
88 | * To skip this limit, boot/load with a large max_cstate limit. | |
89 | */ | |
1855256c | 90 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
91 | { |
92 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
93 | return 0; | |
94 | ||
3d35600a | 95 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
96 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
97 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 98 | |
3d35600a | 99 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
7ded5689 AR |
104 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
105 | callers to only run once -AK */ | |
106 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
107 | { set_max_cstate, "Clevo 5600D", { |
108 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
109 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 110 | (void *)2}, |
1da177e4 LT |
111 | {}, |
112 | }; | |
113 | ||
4f86d3a8 | 114 | |
2e906655 | 115 | /* |
116 | * Callers should disable interrupts before the call and enable | |
117 | * interrupts after return. | |
118 | */ | |
ddc081a1 VP |
119 | static void acpi_safe_halt(void) |
120 | { | |
121 | current_thread_info()->status &= ~TS_POLLING; | |
122 | /* | |
123 | * TS_POLLING-cleared state must be visible before we | |
124 | * test NEED_RESCHED: | |
125 | */ | |
126 | smp_mb(); | |
71e93d15 | 127 | if (!need_resched()) { |
ddc081a1 | 128 | safe_halt(); |
71e93d15 VP |
129 | local_irq_disable(); |
130 | } | |
ddc081a1 VP |
131 | current_thread_info()->status |= TS_POLLING; |
132 | } | |
133 | ||
169a0abb TG |
134 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
135 | ||
136 | /* | |
137 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
138 | * This seems to be a common problem on AMD boxen, but other vendors |
139 | * are affected too. We pick the most conservative approach: we assume | |
140 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
141 | */ |
142 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
143 | struct acpi_processor_cx *cx) | |
144 | { | |
145 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 146 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
147 | |
148 | /* | |
149 | * Check, if one of the previous states already marked the lapic | |
150 | * unstable | |
151 | */ | |
152 | if (pwr->timer_broadcast_on_state < state) | |
153 | return; | |
154 | ||
e585bef8 | 155 | if (cx->type >= type) |
296d93cd | 156 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
157 | } |
158 | ||
159 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
160 | { | |
e9e2cdb4 TG |
161 | unsigned long reason; |
162 | ||
163 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
164 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
165 | ||
166 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
167 | } |
168 | ||
169 | /* Power(C) State timer broadcast control */ | |
170 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
171 | struct acpi_processor_cx *cx, | |
172 | int broadcast) | |
173 | { | |
e9e2cdb4 TG |
174 | int state = cx - pr->power.states; |
175 | ||
176 | if (state >= pr->power.timer_broadcast_on_state) { | |
177 | unsigned long reason; | |
178 | ||
179 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
180 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
181 | clockevents_notify(reason, &pr->id); | |
182 | } | |
169a0abb TG |
183 | } |
184 | ||
185 | #else | |
186 | ||
187 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
188 | struct acpi_processor_cx *cstate) { } | |
189 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
190 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
191 | struct acpi_processor_cx *cx, | |
192 | int broadcast) | |
193 | { | |
194 | } | |
169a0abb TG |
195 | |
196 | #endif | |
197 | ||
b04e7bdb TG |
198 | /* |
199 | * Suspend / resume control | |
200 | */ | |
201 | static int acpi_idle_suspend; | |
202 | ||
203 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
204 | { | |
205 | acpi_idle_suspend = 1; | |
206 | return 0; | |
207 | } | |
208 | ||
209 | int acpi_processor_resume(struct acpi_device * device) | |
210 | { | |
211 | acpi_idle_suspend = 0; | |
212 | return 0; | |
213 | } | |
214 | ||
61331168 | 215 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
ddb25f9a AK |
216 | static int tsc_halts_in_c(int state) |
217 | { | |
218 | switch (boot_cpu_data.x86_vendor) { | |
219 | case X86_VENDOR_AMD: | |
40fb1715 | 220 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
221 | /* |
222 | * AMD Fam10h TSC will tick in all | |
223 | * C/P/S0/S1 states when this bit is set. | |
224 | */ | |
40fb1715 | 225 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
ddb25f9a | 226 | return 0; |
40fb1715 | 227 | |
ddb25f9a | 228 | /*FALL THROUGH*/ |
ddb25f9a AK |
229 | default: |
230 | return state > ACPI_STATE_C1; | |
231 | } | |
232 | } | |
233 | #endif | |
234 | ||
4be44fcd | 235 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 236 | { |
1da177e4 LT |
237 | |
238 | if (!pr) | |
d550d98d | 239 | return -EINVAL; |
1da177e4 LT |
240 | |
241 | if (!pr->pblk) | |
d550d98d | 242 | return -ENODEV; |
1da177e4 | 243 | |
1da177e4 | 244 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
245 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
246 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
247 | ||
4c033552 VP |
248 | #ifndef CONFIG_HOTPLUG_CPU |
249 | /* | |
250 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 251 | * an SMP system. |
4c033552 | 252 | */ |
ad71860a | 253 | if ((num_online_cpus() > 1) && |
cee324b1 | 254 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 255 | return -ENODEV; |
4c033552 VP |
256 | #endif |
257 | ||
1da177e4 LT |
258 | /* determine C2 and C3 address from pblk */ |
259 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
260 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
261 | ||
262 | /* determine latencies from FADT */ | |
cee324b1 AS |
263 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
264 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
265 | |
266 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
267 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
268 | pr->power.states[ACPI_STATE_C2].address, | |
269 | pr->power.states[ACPI_STATE_C3].address)); | |
270 | ||
d550d98d | 271 | return 0; |
1da177e4 LT |
272 | } |
273 | ||
991528d7 | 274 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 275 | { |
991528d7 VP |
276 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
277 | /* set the first C-State to C1 */ | |
278 | /* all processors need to support C1 */ | |
279 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
280 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 281 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
282 | } |
283 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 284 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 285 | return 0; |
acf05f4b VP |
286 | } |
287 | ||
4be44fcd | 288 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 289 | { |
4be44fcd LB |
290 | acpi_status status = 0; |
291 | acpi_integer count; | |
cf824788 | 292 | int current_count; |
4be44fcd LB |
293 | int i; |
294 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
295 | union acpi_object *cst; | |
1da177e4 | 296 | |
1da177e4 | 297 | |
1da177e4 | 298 | if (nocst) |
d550d98d | 299 | return -ENODEV; |
1da177e4 | 300 | |
991528d7 | 301 | current_count = 0; |
1da177e4 LT |
302 | |
303 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
304 | if (ACPI_FAILURE(status)) { | |
305 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 306 | return -ENODEV; |
4be44fcd | 307 | } |
1da177e4 | 308 | |
50dd0969 | 309 | cst = buffer.pointer; |
1da177e4 LT |
310 | |
311 | /* There must be at least 2 elements */ | |
312 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 313 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
314 | status = -EFAULT; |
315 | goto end; | |
316 | } | |
317 | ||
318 | count = cst->package.elements[0].integer.value; | |
319 | ||
320 | /* Validate number of power states. */ | |
321 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 322 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
323 | status = -EFAULT; |
324 | goto end; | |
325 | } | |
326 | ||
1da177e4 LT |
327 | /* Tell driver that at least _CST is supported. */ |
328 | pr->flags.has_cst = 1; | |
329 | ||
330 | for (i = 1; i <= count; i++) { | |
331 | union acpi_object *element; | |
332 | union acpi_object *obj; | |
333 | struct acpi_power_register *reg; | |
334 | struct acpi_processor_cx cx; | |
335 | ||
336 | memset(&cx, 0, sizeof(cx)); | |
337 | ||
50dd0969 | 338 | element = &(cst->package.elements[i]); |
1da177e4 LT |
339 | if (element->type != ACPI_TYPE_PACKAGE) |
340 | continue; | |
341 | ||
342 | if (element->package.count != 4) | |
343 | continue; | |
344 | ||
50dd0969 | 345 | obj = &(element->package.elements[0]); |
1da177e4 LT |
346 | |
347 | if (obj->type != ACPI_TYPE_BUFFER) | |
348 | continue; | |
349 | ||
4be44fcd | 350 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
351 | |
352 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 353 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
354 | continue; |
355 | ||
1da177e4 | 356 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 357 | obj = &(element->package.elements[1]); |
1da177e4 LT |
358 | if (obj->type != ACPI_TYPE_INTEGER) |
359 | continue; | |
360 | ||
361 | cx.type = obj->integer.value; | |
991528d7 VP |
362 | /* |
363 | * Some buggy BIOSes won't list C1 in _CST - | |
364 | * Let acpi_processor_get_power_info_default() handle them later | |
365 | */ | |
366 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
367 | current_count++; | |
368 | ||
369 | cx.address = reg->address; | |
370 | cx.index = current_count + 1; | |
371 | ||
bc71bec9 | 372 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
373 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
374 | if (acpi_processor_ffh_cstate_probe | |
375 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 376 | cx.entry_method = ACPI_CSTATE_FFH; |
377 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
378 | /* |
379 | * C1 is a special case where FIXED_HARDWARE | |
380 | * can be handled in non-MWAIT way as well. | |
381 | * In that case, save this _CST entry info. | |
991528d7 VP |
382 | * Otherwise, ignore this info and continue. |
383 | */ | |
bc71bec9 | 384 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 385 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 386 | } else { |
991528d7 VP |
387 | continue; |
388 | } | |
da5e09a1 ZY |
389 | if (cx.type == ACPI_STATE_C1 && |
390 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
391 | /* |
392 | * In most cases the C1 space_id obtained from | |
393 | * _CST object is FIXED_HARDWARE access mode. | |
394 | * But when the option of idle=halt is added, | |
395 | * the entry_method type should be changed from | |
396 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
397 | * When the option of idle=nomwait is added, |
398 | * the C1 entry_method type should be | |
399 | * CSTATE_HALT. | |
c1e3b377 ZY |
400 | */ |
401 | cx.entry_method = ACPI_CSTATE_HALT; | |
402 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
403 | } | |
4fcb2fcd VP |
404 | } else { |
405 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
406 | cx.address); | |
991528d7 | 407 | } |
1da177e4 | 408 | |
0fda6b40 VP |
409 | if (cx.type == ACPI_STATE_C1) { |
410 | cx.valid = 1; | |
411 | } | |
4fcb2fcd | 412 | |
50dd0969 | 413 | obj = &(element->package.elements[2]); |
1da177e4 LT |
414 | if (obj->type != ACPI_TYPE_INTEGER) |
415 | continue; | |
416 | ||
417 | cx.latency = obj->integer.value; | |
418 | ||
50dd0969 | 419 | obj = &(element->package.elements[3]); |
1da177e4 LT |
420 | if (obj->type != ACPI_TYPE_INTEGER) |
421 | continue; | |
422 | ||
423 | cx.power = obj->integer.value; | |
424 | ||
cf824788 JM |
425 | current_count++; |
426 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
427 | ||
428 | /* | |
429 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
430 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
431 | */ | |
432 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
433 | printk(KERN_WARNING | |
434 | "Limiting number of power states to max (%d)\n", | |
435 | ACPI_PROCESSOR_MAX_POWER); | |
436 | printk(KERN_WARNING | |
437 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
438 | break; | |
439 | } | |
1da177e4 LT |
440 | } |
441 | ||
4be44fcd | 442 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 443 | current_count)); |
1da177e4 LT |
444 | |
445 | /* Validate number of power states discovered */ | |
cf824788 | 446 | if (current_count < 2) |
6d93c648 | 447 | status = -EFAULT; |
1da177e4 | 448 | |
4be44fcd | 449 | end: |
02438d87 | 450 | kfree(buffer.pointer); |
1da177e4 | 451 | |
d550d98d | 452 | return status; |
1da177e4 LT |
453 | } |
454 | ||
1da177e4 LT |
455 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
456 | { | |
1da177e4 LT |
457 | |
458 | if (!cx->address) | |
d550d98d | 459 | return; |
1da177e4 LT |
460 | |
461 | /* | |
462 | * C2 latency must be less than or equal to 100 | |
463 | * microseconds. | |
464 | */ | |
465 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
466 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 467 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 468 | return; |
1da177e4 LT |
469 | } |
470 | ||
1da177e4 LT |
471 | /* |
472 | * Otherwise we've met all of our C2 requirements. | |
473 | * Normalize the C2 latency to expidite policy | |
474 | */ | |
475 | cx->valid = 1; | |
4f86d3a8 | 476 | |
4f86d3a8 | 477 | cx->latency_ticks = cx->latency; |
1da177e4 | 478 | |
d550d98d | 479 | return; |
1da177e4 LT |
480 | } |
481 | ||
4be44fcd LB |
482 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
483 | struct acpi_processor_cx *cx) | |
1da177e4 | 484 | { |
02df8b93 VP |
485 | static int bm_check_flag; |
486 | ||
1da177e4 LT |
487 | |
488 | if (!cx->address) | |
d550d98d | 489 | return; |
1da177e4 LT |
490 | |
491 | /* | |
492 | * C3 latency must be less than or equal to 1000 | |
493 | * microseconds. | |
494 | */ | |
495 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
496 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 497 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 498 | return; |
1da177e4 LT |
499 | } |
500 | ||
1da177e4 LT |
501 | /* |
502 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
503 | * DMA transfers are used by any ISA device to avoid livelock. | |
504 | * Note that we could disable Type-F DMA (as recommended by | |
505 | * the erratum), but this is known to disrupt certain ISA | |
506 | * devices thus we take the conservative approach. | |
507 | */ | |
508 | else if (errata.piix4.fdma) { | |
509 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 510 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 511 | return; |
1da177e4 LT |
512 | } |
513 | ||
02df8b93 VP |
514 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
515 | if (!bm_check_flag) { | |
516 | /* Determine whether bm_check is needed based on CPU */ | |
517 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
518 | bm_check_flag = pr->flags.bm_check; | |
519 | } else { | |
520 | pr->flags.bm_check = bm_check_flag; | |
521 | } | |
522 | ||
523 | if (pr->flags.bm_check) { | |
02df8b93 | 524 | if (!pr->flags.bm_control) { |
ed3110ef VP |
525 | if (pr->flags.has_cst != 1) { |
526 | /* bus mastering control is necessary */ | |
527 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
528 | "C3 support requires BM control\n")); | |
529 | return; | |
530 | } else { | |
531 | /* Here we enter C3 without bus mastering */ | |
532 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
533 | "C3 support without BM control\n")); | |
534 | } | |
02df8b93 VP |
535 | } |
536 | } else { | |
02df8b93 VP |
537 | /* |
538 | * WBINVD should be set in fadt, for C3 state to be | |
539 | * supported on when bm_check is not required. | |
540 | */ | |
cee324b1 | 541 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 542 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
543 | "Cache invalidation should work properly" |
544 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 545 | return; |
02df8b93 | 546 | } |
02df8b93 VP |
547 | } |
548 | ||
1da177e4 LT |
549 | /* |
550 | * Otherwise we've met all of our C3 requirements. | |
551 | * Normalize the C3 latency to expidite policy. Enable | |
552 | * checking of bus mastering status (bm_check) so we can | |
553 | * use this in our C3 policy | |
554 | */ | |
555 | cx->valid = 1; | |
4f86d3a8 | 556 | |
4f86d3a8 | 557 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
558 | /* |
559 | * On older chipsets, BM_RLD needs to be set | |
560 | * in order for Bus Master activity to wake the | |
561 | * system from C3. Newer chipsets handle DMA | |
562 | * during C3 automatically and BM_RLD is a NOP. | |
563 | * In either case, the proper way to | |
564 | * handle BM_RLD is to set it and leave it set. | |
565 | */ | |
50ffba1b | 566 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 567 | |
d550d98d | 568 | return; |
1da177e4 LT |
569 | } |
570 | ||
1da177e4 LT |
571 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
572 | { | |
573 | unsigned int i; | |
574 | unsigned int working = 0; | |
6eb0a0fd | 575 | |
169a0abb | 576 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 577 | |
4be44fcd | 578 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
579 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
580 | ||
581 | switch (cx->type) { | |
582 | case ACPI_STATE_C1: | |
583 | cx->valid = 1; | |
584 | break; | |
585 | ||
586 | case ACPI_STATE_C2: | |
587 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 588 | if (cx->valid) |
169a0abb | 589 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
590 | break; |
591 | ||
592 | case ACPI_STATE_C3: | |
593 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 594 | if (cx->valid) |
169a0abb | 595 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
596 | break; |
597 | } | |
598 | ||
599 | if (cx->valid) | |
600 | working++; | |
601 | } | |
bd663347 | 602 | |
169a0abb | 603 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
604 | |
605 | return (working); | |
606 | } | |
607 | ||
4be44fcd | 608 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
609 | { |
610 | unsigned int i; | |
611 | int result; | |
612 | ||
1da177e4 LT |
613 | |
614 | /* NOTE: the idle thread may not be running while calling | |
615 | * this function */ | |
616 | ||
991528d7 VP |
617 | /* Zero initialize all the C-states info. */ |
618 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
619 | ||
1da177e4 | 620 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 621 | if (result == -ENODEV) |
c5a114f1 | 622 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 623 | |
991528d7 VP |
624 | if (result) |
625 | return result; | |
626 | ||
627 | acpi_processor_get_power_info_default(pr); | |
628 | ||
cf824788 | 629 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 630 | |
1da177e4 LT |
631 | /* |
632 | * if one state of type C2 or C3 is available, mark this | |
633 | * CPU as being "idle manageable" | |
634 | */ | |
635 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 636 | if (pr->power.states[i].valid) { |
1da177e4 | 637 | pr->power.count = i; |
2203d6ed LT |
638 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
639 | pr->flags.power = 1; | |
acf05f4b | 640 | } |
1da177e4 LT |
641 | } |
642 | ||
d550d98d | 643 | return 0; |
1da177e4 LT |
644 | } |
645 | ||
1da177e4 LT |
646 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
647 | { | |
50dd0969 | 648 | struct acpi_processor *pr = seq->private; |
4be44fcd | 649 | unsigned int i; |
1da177e4 | 650 | |
1da177e4 LT |
651 | |
652 | if (!pr) | |
653 | goto end; | |
654 | ||
655 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 656 | "max_cstate: C%d\n" |
5c87579e AV |
657 | "bus master activity: %08x\n" |
658 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 659 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e | 660 | max_cstate, (unsigned)pr->power.bm_activity, |
f011e2e2 | 661 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
662 | |
663 | seq_puts(seq, "states:\n"); | |
664 | ||
665 | for (i = 1; i <= pr->power.count; i++) { | |
666 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
667 | (&pr->power.states[i] == |
668 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
669 | |
670 | if (!pr->power.states[i].valid) { | |
671 | seq_puts(seq, "<not supported>\n"); | |
672 | continue; | |
673 | } | |
674 | ||
675 | switch (pr->power.states[i].type) { | |
676 | case ACPI_STATE_C1: | |
677 | seq_printf(seq, "type[C1] "); | |
678 | break; | |
679 | case ACPI_STATE_C2: | |
680 | seq_printf(seq, "type[C2] "); | |
681 | break; | |
682 | case ACPI_STATE_C3: | |
683 | seq_printf(seq, "type[C3] "); | |
684 | break; | |
685 | default: | |
686 | seq_printf(seq, "type[--] "); | |
687 | break; | |
688 | } | |
689 | ||
690 | if (pr->power.states[i].promotion.state) | |
691 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
692 | (pr->power.states[i].promotion.state - |
693 | pr->power.states)); | |
1da177e4 LT |
694 | else |
695 | seq_puts(seq, "promotion[--] "); | |
696 | ||
697 | if (pr->power.states[i].demotion.state) | |
698 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
699 | (pr->power.states[i].demotion.state - |
700 | pr->power.states)); | |
1da177e4 LT |
701 | else |
702 | seq_puts(seq, "demotion[--] "); | |
703 | ||
a3c6598f | 704 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 705 | pr->power.states[i].latency, |
a3c6598f | 706 | pr->power.states[i].usage, |
b0b7eaaf | 707 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
708 | } |
709 | ||
4be44fcd | 710 | end: |
d550d98d | 711 | return 0; |
1da177e4 LT |
712 | } |
713 | ||
714 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
715 | { | |
716 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 717 | PDE(inode)->data); |
1da177e4 LT |
718 | } |
719 | ||
d7508032 | 720 | static const struct file_operations acpi_processor_power_fops = { |
cf7acfab | 721 | .owner = THIS_MODULE, |
4be44fcd LB |
722 | .open = acpi_processor_power_open_fs, |
723 | .read = seq_read, | |
724 | .llseek = seq_lseek, | |
725 | .release = single_release, | |
1da177e4 LT |
726 | }; |
727 | ||
4f86d3a8 LB |
728 | |
729 | /** | |
730 | * acpi_idle_bm_check - checks if bus master activity was detected | |
731 | */ | |
732 | static int acpi_idle_bm_check(void) | |
733 | { | |
734 | u32 bm_status = 0; | |
735 | ||
50ffba1b | 736 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 737 | if (bm_status) |
50ffba1b | 738 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
739 | /* |
740 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
741 | * the true state of bus mastering activity; forcing us to | |
742 | * manually check the BMIDEA bit of each IDE channel. | |
743 | */ | |
744 | else if (errata.piix4.bmisx) { | |
745 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
746 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
747 | bm_status = 1; | |
748 | } | |
749 | return bm_status; | |
750 | } | |
751 | ||
4f86d3a8 LB |
752 | /** |
753 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
754 | * @cx: cstate data | |
bc71bec9 | 755 | * |
756 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
757 | */ |
758 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
759 | { | |
dcf30997 SR |
760 | /* Don't trace irqs off for idle */ |
761 | stop_critical_timings(); | |
bc71bec9 | 762 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
763 | /* Call into architectural FFH based C-state */ |
764 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 765 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
766 | acpi_safe_halt(); | |
4f86d3a8 LB |
767 | } else { |
768 | int unused; | |
769 | /* IO port based C-state */ | |
770 | inb(cx->address); | |
771 | /* Dummy wait op - must do something useless after P_LVL2 read | |
772 | because chipsets cannot guarantee that STPCLK# signal | |
773 | gets asserted in time to freeze execution properly. */ | |
774 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
775 | } | |
dcf30997 | 776 | start_critical_timings(); |
4f86d3a8 LB |
777 | } |
778 | ||
779 | /** | |
780 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
781 | * @dev: the target CPU | |
782 | * @state: the state data | |
783 | * | |
784 | * This is equivalent to the HALT instruction. | |
785 | */ | |
786 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
787 | struct cpuidle_state *state) | |
788 | { | |
ff69f2bb | 789 | ktime_t kt1, kt2; |
790 | s64 idle_time; | |
4f86d3a8 LB |
791 | struct acpi_processor *pr; |
792 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 793 | |
706546d0 | 794 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
795 | |
796 | if (unlikely(!pr)) | |
797 | return 0; | |
798 | ||
2e906655 | 799 | local_irq_disable(); |
b077fbad VP |
800 | |
801 | /* Do not access any ACPI IO ports in suspend path */ | |
802 | if (acpi_idle_suspend) { | |
803 | acpi_safe_halt(); | |
804 | local_irq_enable(); | |
805 | return 0; | |
806 | } | |
807 | ||
ff69f2bb | 808 | kt1 = ktime_get_real(); |
bc71bec9 | 809 | acpi_idle_do_entry(cx); |
ff69f2bb | 810 | kt2 = ktime_get_real(); |
811 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 812 | |
2e906655 | 813 | local_irq_enable(); |
4f86d3a8 LB |
814 | cx->usage++; |
815 | ||
ff69f2bb | 816 | return idle_time; |
4f86d3a8 LB |
817 | } |
818 | ||
819 | /** | |
820 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
821 | * @dev: the target CPU | |
822 | * @state: the state data | |
823 | */ | |
824 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
825 | struct cpuidle_state *state) | |
826 | { | |
827 | struct acpi_processor *pr; | |
828 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 829 | ktime_t kt1, kt2; |
830 | s64 idle_time; | |
831 | s64 sleep_ticks = 0; | |
50629118 | 832 | |
706546d0 | 833 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
834 | |
835 | if (unlikely(!pr)) | |
836 | return 0; | |
837 | ||
e196441b LB |
838 | if (acpi_idle_suspend) |
839 | return(acpi_idle_enter_c1(dev, state)); | |
840 | ||
4f86d3a8 LB |
841 | local_irq_disable(); |
842 | current_thread_info()->status &= ~TS_POLLING; | |
843 | /* | |
844 | * TS_POLLING-cleared state must be visible before we test | |
845 | * NEED_RESCHED: | |
846 | */ | |
847 | smp_mb(); | |
848 | ||
849 | if (unlikely(need_resched())) { | |
850 | current_thread_info()->status |= TS_POLLING; | |
851 | local_irq_enable(); | |
852 | return 0; | |
853 | } | |
854 | ||
e17bcb43 TG |
855 | /* |
856 | * Must be done before busmaster disable as we might need to | |
857 | * access HPET ! | |
858 | */ | |
859 | acpi_state_timer_broadcast(pr, cx, 1); | |
860 | ||
4f86d3a8 LB |
861 | if (cx->type == ACPI_STATE_C3) |
862 | ACPI_FLUSH_CPU_CACHE(); | |
863 | ||
ff69f2bb | 864 | kt1 = ktime_get_real(); |
50629118 VP |
865 | /* Tell the scheduler that we are going deep-idle: */ |
866 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 867 | acpi_idle_do_entry(cx); |
ff69f2bb | 868 | kt2 = ktime_get_real(); |
869 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 870 | |
61331168 | 871 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
4f86d3a8 | 872 | /* TSC could halt in idle, so notify users */ |
ddb25f9a AK |
873 | if (tsc_halts_in_c(cx->type)) |
874 | mark_tsc_unstable("TSC halts in idle");; | |
4f86d3a8 | 875 | #endif |
ff69f2bb | 876 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
877 | |
878 | /* Tell the scheduler how much we idled: */ | |
879 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
880 | |
881 | local_irq_enable(); | |
882 | current_thread_info()->status |= TS_POLLING; | |
883 | ||
884 | cx->usage++; | |
885 | ||
886 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 887 | cx->time += sleep_ticks; |
ff69f2bb | 888 | return idle_time; |
4f86d3a8 LB |
889 | } |
890 | ||
891 | static int c3_cpu_count; | |
892 | static DEFINE_SPINLOCK(c3_lock); | |
893 | ||
894 | /** | |
895 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
896 | * @dev: the target CPU | |
897 | * @state: the state data | |
898 | * | |
899 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
900 | */ | |
901 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
902 | struct cpuidle_state *state) | |
903 | { | |
904 | struct acpi_processor *pr; | |
905 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 906 | ktime_t kt1, kt2; |
907 | s64 idle_time; | |
908 | s64 sleep_ticks = 0; | |
909 | ||
50629118 | 910 | |
706546d0 | 911 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
912 | |
913 | if (unlikely(!pr)) | |
914 | return 0; | |
915 | ||
e196441b LB |
916 | if (acpi_idle_suspend) |
917 | return(acpi_idle_enter_c1(dev, state)); | |
918 | ||
ddc081a1 VP |
919 | if (acpi_idle_bm_check()) { |
920 | if (dev->safe_state) { | |
addbad46 | 921 | dev->last_state = dev->safe_state; |
ddc081a1 VP |
922 | return dev->safe_state->enter(dev, dev->safe_state); |
923 | } else { | |
2e906655 | 924 | local_irq_disable(); |
ddc081a1 | 925 | acpi_safe_halt(); |
2e906655 | 926 | local_irq_enable(); |
ddc081a1 VP |
927 | return 0; |
928 | } | |
929 | } | |
930 | ||
4f86d3a8 LB |
931 | local_irq_disable(); |
932 | current_thread_info()->status &= ~TS_POLLING; | |
933 | /* | |
934 | * TS_POLLING-cleared state must be visible before we test | |
935 | * NEED_RESCHED: | |
936 | */ | |
937 | smp_mb(); | |
938 | ||
939 | if (unlikely(need_resched())) { | |
940 | current_thread_info()->status |= TS_POLLING; | |
941 | local_irq_enable(); | |
942 | return 0; | |
943 | } | |
944 | ||
996520c1 VP |
945 | acpi_unlazy_tlb(smp_processor_id()); |
946 | ||
50629118 VP |
947 | /* Tell the scheduler that we are going deep-idle: */ |
948 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
949 | /* |
950 | * Must be done before busmaster disable as we might need to | |
951 | * access HPET ! | |
952 | */ | |
953 | acpi_state_timer_broadcast(pr, cx, 1); | |
954 | ||
ddc081a1 VP |
955 | /* |
956 | * disable bus master | |
957 | * bm_check implies we need ARB_DIS | |
958 | * !bm_check implies we need cache flush | |
959 | * bm_control implies whether we can do ARB_DIS | |
960 | * | |
961 | * That leaves a case where bm_check is set and bm_control is | |
962 | * not set. In that case we cannot do much, we enter C3 | |
963 | * without doing anything. | |
964 | */ | |
965 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
966 | spin_lock(&c3_lock); |
967 | c3_cpu_count++; | |
968 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
969 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 970 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 971 | spin_unlock(&c3_lock); |
ddc081a1 VP |
972 | } else if (!pr->flags.bm_check) { |
973 | ACPI_FLUSH_CPU_CACHE(); | |
974 | } | |
4f86d3a8 | 975 | |
ff69f2bb | 976 | kt1 = ktime_get_real(); |
ddc081a1 | 977 | acpi_idle_do_entry(cx); |
ff69f2bb | 978 | kt2 = ktime_get_real(); |
979 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 980 | |
ddc081a1 VP |
981 | /* Re-enable bus master arbitration */ |
982 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 983 | spin_lock(&c3_lock); |
50ffba1b | 984 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
985 | c3_cpu_count--; |
986 | spin_unlock(&c3_lock); | |
987 | } | |
988 | ||
61331168 | 989 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
4f86d3a8 | 990 | /* TSC could halt in idle, so notify users */ |
ddb25f9a AK |
991 | if (tsc_halts_in_c(ACPI_STATE_C3)) |
992 | mark_tsc_unstable("TSC halts in idle"); | |
4f86d3a8 | 993 | #endif |
ff69f2bb | 994 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
995 | /* Tell the scheduler how much we idled: */ |
996 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
997 | |
998 | local_irq_enable(); | |
999 | current_thread_info()->status |= TS_POLLING; | |
1000 | ||
1001 | cx->usage++; | |
1002 | ||
1003 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1004 | cx->time += sleep_ticks; |
ff69f2bb | 1005 | return idle_time; |
4f86d3a8 LB |
1006 | } |
1007 | ||
1008 | struct cpuidle_driver acpi_idle_driver = { | |
1009 | .name = "acpi_idle", | |
1010 | .owner = THIS_MODULE, | |
1011 | }; | |
1012 | ||
1013 | /** | |
1014 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1015 | * @pr: the ACPI processor | |
1016 | */ | |
1017 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1018 | { | |
9a0b8415 | 1019 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1020 | struct acpi_processor_cx *cx; |
1021 | struct cpuidle_state *state; | |
1022 | struct cpuidle_device *dev = &pr->power.dev; | |
1023 | ||
1024 | if (!pr->flags.power_setup_done) | |
1025 | return -EINVAL; | |
1026 | ||
1027 | if (pr->flags.power == 0) { | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | ||
dcb84f33 | 1031 | dev->cpu = pr->id; |
4fcb2fcd VP |
1032 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1033 | dev->states[i].name[0] = '\0'; | |
1034 | dev->states[i].desc[0] = '\0'; | |
1035 | } | |
1036 | ||
4f86d3a8 LB |
1037 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1038 | cx = &pr->power.states[i]; | |
1039 | state = &dev->states[count]; | |
1040 | ||
1041 | if (!cx->valid) | |
1042 | continue; | |
1043 | ||
1044 | #ifdef CONFIG_HOTPLUG_CPU | |
1045 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1046 | !pr->flags.has_cst && | |
1047 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1048 | continue; | |
1fec74a9 | 1049 | #endif |
4f86d3a8 LB |
1050 | cpuidle_set_statedata(state, cx); |
1051 | ||
1052 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1053 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1054 | state->exit_latency = cx->latency; |
4963f620 | 1055 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1056 | state->power_usage = cx->power; |
1057 | ||
1058 | state->flags = 0; | |
1059 | switch (cx->type) { | |
1060 | case ACPI_STATE_C1: | |
1061 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1062 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1063 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1064 | ||
4f86d3a8 | 1065 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1066 | dev->safe_state = state; |
4f86d3a8 LB |
1067 | break; |
1068 | ||
1069 | case ACPI_STATE_C2: | |
1070 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1071 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1072 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1073 | dev->safe_state = state; |
4f86d3a8 LB |
1074 | break; |
1075 | ||
1076 | case ACPI_STATE_C3: | |
1077 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1078 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1079 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1080 | state->enter = pr->flags.bm_check ? | |
1081 | acpi_idle_enter_bm : | |
1082 | acpi_idle_enter_simple; | |
1083 | break; | |
1084 | } | |
1085 | ||
1086 | count++; | |
9a0b8415 | 1087 | if (count == CPUIDLE_STATE_MAX) |
1088 | break; | |
4f86d3a8 LB |
1089 | } |
1090 | ||
1091 | dev->state_count = count; | |
1092 | ||
1093 | if (!count) | |
1094 | return -EINVAL; | |
1095 | ||
4f86d3a8 LB |
1096 | return 0; |
1097 | } | |
1098 | ||
1099 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1100 | { | |
dcb84f33 | 1101 | int ret = 0; |
4f86d3a8 | 1102 | |
36a91358 VP |
1103 | if (boot_option_idle_override) |
1104 | return 0; | |
1105 | ||
4f86d3a8 LB |
1106 | if (!pr) |
1107 | return -EINVAL; | |
1108 | ||
1109 | if (nocst) { | |
1110 | return -ENODEV; | |
1111 | } | |
1112 | ||
1113 | if (!pr->flags.power_setup_done) | |
1114 | return -ENODEV; | |
1115 | ||
1116 | cpuidle_pause_and_lock(); | |
1117 | cpuidle_disable_device(&pr->power.dev); | |
1118 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1119 | if (pr->flags.power) { |
1120 | acpi_processor_setup_cpuidle(pr); | |
1121 | ret = cpuidle_enable_device(&pr->power.dev); | |
1122 | } | |
4f86d3a8 LB |
1123 | cpuidle_resume_and_unlock(); |
1124 | ||
1125 | return ret; | |
1126 | } | |
1127 | ||
7af8b660 | 1128 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1129 | struct acpi_device *device) |
1da177e4 | 1130 | { |
4be44fcd | 1131 | acpi_status status = 0; |
b6835052 | 1132 | static int first_run; |
4be44fcd | 1133 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1134 | unsigned int i; |
1135 | ||
36a91358 VP |
1136 | if (boot_option_idle_override) |
1137 | return 0; | |
1da177e4 LT |
1138 | |
1139 | if (!first_run) { | |
c1e3b377 ZY |
1140 | if (idle_halt) { |
1141 | /* | |
1142 | * When the boot option of "idle=halt" is added, halt | |
1143 | * is used for CPU IDLE. | |
1144 | * In such case C2/C3 is meaningless. So the max_cstate | |
1145 | * is set to one. | |
1146 | */ | |
1147 | max_cstate = 1; | |
1148 | } | |
1da177e4 | 1149 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1150 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1151 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1152 | printk(KERN_NOTICE |
1153 | "ACPI: processor limited to max C-state %d\n", | |
1154 | max_cstate); | |
1da177e4 LT |
1155 | first_run++; |
1156 | } | |
1157 | ||
02df8b93 | 1158 | if (!pr) |
d550d98d | 1159 | return -EINVAL; |
02df8b93 | 1160 | |
cee324b1 | 1161 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1162 | status = |
cee324b1 | 1163 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1164 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1165 | ACPI_EXCEPTION((AE_INFO, status, |
1166 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1167 | } |
1168 | } | |
1169 | ||
1170 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1171 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1172 | |
1173 | /* | |
1174 | * Install the idle handler if processor power management is supported. | |
1175 | * Note that we use previously set idle handler will be used on | |
1176 | * platforms that only support C1. | |
1177 | */ | |
36a91358 | 1178 | if (pr->flags.power) { |
4f86d3a8 | 1179 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1180 | if (cpuidle_register_device(&pr->power.dev)) |
1181 | return -EIO; | |
4f86d3a8 | 1182 | |
1da177e4 LT |
1183 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1184 | for (i = 1; i <= pr->power.count; i++) | |
1185 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1186 | printk(" C%d[C%d]", i, |
1187 | pr->power.states[i].type); | |
1da177e4 | 1188 | printk(")\n"); |
1da177e4 LT |
1189 | } |
1190 | ||
1191 | /* 'power' [R] */ | |
cf7acfab DL |
1192 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1193 | S_IRUGO, acpi_device_dir(device), | |
1194 | &acpi_processor_power_fops, | |
1195 | acpi_driver_data(device)); | |
1da177e4 | 1196 | if (!entry) |
a6fc6720 | 1197 | return -EIO; |
d550d98d | 1198 | return 0; |
1da177e4 LT |
1199 | } |
1200 | ||
4be44fcd LB |
1201 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1202 | struct acpi_device *device) | |
1da177e4 | 1203 | { |
36a91358 VP |
1204 | if (boot_option_idle_override) |
1205 | return 0; | |
1206 | ||
dcb84f33 | 1207 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1208 | pr->flags.power_setup_done = 0; |
1209 | ||
1210 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1211 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1212 | acpi_device_dir(device)); | |
1da177e4 | 1213 | |
d550d98d | 1214 | return 0; |
1da177e4 | 1215 | } |