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[deliverable/linux.git] / drivers / ata / ahci.c
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1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
98ac62de 106static const struct ata_port_info ahci_port_info[] = {
441577ef 107 /* by features */
4da646b7 108 [board_ahci] =
1da177e4 109 {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
441577ef 115 [board_ahci_ign_iferr] =
bf2af2a2 116 {
441577ef 117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 118 .flags = AHCI_FLAG_COMMON,
14bdef98 119 .pio_mask = ATA_PIO4,
469248ab 120 .udma_mask = ATA_UDMA6,
441577ef 121 .port_ops = &ahci_ops,
bf2af2a2 122 },
441577ef 123 [board_ahci_nosntf] =
41669553 124 {
441577ef 125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 126 .flags = AHCI_FLAG_COMMON,
14bdef98 127 .pio_mask = ATA_PIO4,
469248ab 128 .udma_mask = ATA_UDMA6,
41669553
TH		 129 .port_ops = &ahci_ops,
130 },
5f173107
TH		 131 [board_ahci_yes_fbs] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
441577ef
TH		 139 /* by chipsets */
140 [board_ahci_mcp65] =
55a61604 141 {
83f2b963
TH		 142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
ae01b249 144 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
441577ef 163 .port_ops = &ahci_ops,
55a61604 164 },
4da646b7 165 [board_ahci_mv] =
cd70c266 166 {
417a1a6d 167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 169 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 170 .pio_mask = ATA_PIO4,
cd70c266
JG		 171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
441577ef 174 [board_ahci_sb600] =
e39fc8c9 175 {
441577ef
TH		 176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 179 .flags = AHCI_FLAG_COMMON,
14bdef98 180 .pio_mask = ATA_PIO4,
e39fc8c9 181 .udma_mask = ATA_UDMA6,
345347c5 182 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 183 },
441577ef 184 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 185 {
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
441577ef 192 [board_ahci_vt8251] =
1b677afd 193 {
441577ef 194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
441577ef 198 .port_ops = &ahci_vt8251_ops,
1b677afd 199 },
1da177e4
LT		 200};
201
3b7d697d 202static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 203 /* Intel */
54bb3a94
JG		 204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
fe7fa31a 270
e34bb370
TH		 271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 274
275 /* ATI */
c65ec1c2 276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 283
e2dd90b1 284 /* AMD */
5deab536 285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
fe7fa31a 290 /* VIA */
54bb3a94 291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 293
294 /* NVIDIA */
e297d99e
TH		 295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 379
95916edd 380 /* SiS */
20e2de4a
TH		 381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 384
318893e1
AR		 385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
cd70c266
JG		 388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 391 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
5f173107 394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 397 { PCI_DEVICE(0x1b4b, 0x91a3),
398 .driver_data = board_ahci_yes_fbs },
cd70c266 399
c77a036b
MN		 400 /* Promise */
401 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
402
c9703765
KYL		 403 /* Asmedia */
404 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
405
415ae2b5
JG		 406 /* Generic, PCI class code for AHCI */
407 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 408 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 409
1da177e4
LT		 410 { } /* terminate list */
411};
412
413
414static struct pci_driver ahci_pci_driver = {
415 .name = DRV_NAME,
416 .id_table = ahci_pci_tbl,
417 .probe = ahci_init_one,
24dc5f33 418 .remove = ata_pci_remove_one,
438ac6d5 419#ifdef CONFIG_PM
c1332875 420 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 421 .resume = ahci_pci_device_resume,
422#endif
423};
1da177e4 424
365cfa1e
AV		 425#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
426static int marvell_enable;
427#else
428static int marvell_enable = 1;
429#endif
430module_param(marvell_enable, int, 0644);
431MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 432
1da177e4 433
365cfa1e
AV		 434static void ahci_pci_save_initial_config(struct pci_dev *pdev,
435 struct ahci_host_priv *hpriv)
436{
437 unsigned int force_port_map = 0;
438 unsigned int mask_port_map = 0;
67846b30 439
365cfa1e
AV		 440 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
441 dev_info(&pdev->dev, "JMB361 has only one port\n");
442 force_port_map = 1;
1da177e4
LT		 443 }
444
365cfa1e
AV		 445 /*
446 * Temporary Marvell 6145 hack: PATA port presence
447 * is asserted through the standard AHCI port
448 * presence register, as bit 4 (counting from 0)
d28f87aa 449 */
365cfa1e
AV		 450 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
451 if (pdev->device == 0x6121)
452 mask_port_map = 0x3;
453 else
454 mask_port_map = 0xf;
455 dev_info(&pdev->dev,
456 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
457 }
1da177e4 458
365cfa1e
AV		 459 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
460 mask_port_map);
1da177e4
LT		 461}
462
365cfa1e 463static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 464{
365cfa1e 465 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 466
365cfa1e 467 ahci_reset_controller(host);
1da177e4 468
365cfa1e
AV		 469 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
470 struct ahci_host_priv *hpriv = host->private_data;
471 u16 tmp16;
d6ef3153 472
365cfa1e
AV		 473 /* configure PCS */
474 pci_read_config_word(pdev, 0x92, &tmp16);
475 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
476 tmp16 |= hpriv->port_map;
477 pci_write_config_word(pdev, 0x92, tmp16);
478 }
d6ef3153
SH		 479 }
480
1da177e4
LT		 481 return 0;
482}
483
365cfa1e 484static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 485{
365cfa1e
AV		 486 struct ahci_host_priv *hpriv = host->private_data;
487 struct pci_dev *pdev = to_pci_dev(host->dev);
488 void __iomem *port_mmio;
78cd52d0 489 u32 tmp;
365cfa1e 490 int mv;
78cd52d0 491
365cfa1e
AV		 492 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
493 if (pdev->device == 0x6121)
494 mv = 2;
495 else
496 mv = 4;
497 port_mmio = __ahci_port_base(host, mv);
78cd52d0 498
365cfa1e 499 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 500
365cfa1e
AV		 501 /* clear port IRQ */
502 tmp = readl(port_mmio + PORT_IRQ_STAT);
503 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
504 if (tmp)
505 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 506 }
507
365cfa1e 508 ahci_init_controller(host);
edc93052
TH		 509}
510
365cfa1e
AV		 511static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
512 unsigned long deadline)
d6ef3153 513{
365cfa1e
AV		 514 struct ata_port *ap = link->ap;
515 bool online;
d6ef3153
SH		 516 int rc;
517
365cfa1e 518 DPRINTK("ENTER\n");
d6ef3153 519
365cfa1e 520 ahci_stop_engine(ap);
d6ef3153 521
365cfa1e
AV		 522 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
523 deadline, &online, NULL);
d6ef3153
SH		 524
525 ahci_start_engine(ap);
d6ef3153 526
365cfa1e 527 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 528
365cfa1e
AV		 529 /* vt8251 doesn't clear BSY on signature FIS reception,
530 * request follow-up softreset.
531 */
532 return online ? -EAGAIN : rc;
7d50b60b
TH		 533}
534
365cfa1e
AV		 535static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
536 unsigned long deadline)
7d50b60b 537{
365cfa1e 538 struct ata_port *ap = link->ap;
1c954a4d 539 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 540 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
541 struct ata_taskfile tf;
542 bool online;
543 int rc;
7d50b60b 544
365cfa1e 545 ahci_stop_engine(ap);
028a2596 546
365cfa1e
AV		 547 /* clear D2H reception area to properly wait for D2H FIS */
548 ata_tf_init(link->device, &tf);
549 tf.command = 0x80;
550 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 551
365cfa1e
AV		 552 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
553 deadline, &online, NULL);
028a2596 554
365cfa1e 555 ahci_start_engine(ap);
c1332875 556
365cfa1e
AV		 557 /* The pseudo configuration device on SIMG4726 attached to
558 * ASUS P5W-DH Deluxe doesn't send signature FIS after
559 * hardreset if no device is attached to the first downstream
560 * port && the pseudo device locks up on SRST w/ PMP==0. To
561 * work around this, wait for !BSY only briefly. If BSY isn't
562 * cleared, perform CLO and proceed to IDENTIFY (achieved by
563 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
564 *
565 * Wait for two seconds. Devices attached to downstream port
566 * which can't process the following IDENTIFY after this will
567 * have to be reset again. For most cases, this should
568 * suffice while making probing snappish enough.
569 */
570 if (online) {
571 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
572 ahci_check_ready);
573 if (rc)
574 ahci_kick_engine(ap);
c1332875 575 }
c1332875
TH		 576 return rc;
577}
578
365cfa1e 579#ifdef CONFIG_PM
c1332875
TH		 580static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
581{
cca3974e 582 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 583 struct ahci_host_priv *hpriv = host->private_data;
d8993349 584 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 585 u32 ctl;
586
9b10ae86
TH		 587 if (mesg.event & PM_EVENT_SUSPEND &&
588 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 589 dev_err(&pdev->dev,
590 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 591 return -EIO;
592 }
593
3a2d5b70 594 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 595 /* AHCI spec rev1.1 section 8.3.3:
596 * Software must disable interrupts prior to requesting a
597 * transition of the HBA to D3 state.
598 */
599 ctl = readl(mmio + HOST_CTL);
600 ctl &= ~HOST_IRQ_EN;
601 writel(ctl, mmio + HOST_CTL);
602 readl(mmio + HOST_CTL); /* flush */
603 }
604
605 return ata_pci_device_suspend(pdev, mesg);
606}
607
608static int ahci_pci_device_resume(struct pci_dev *pdev)
609{
cca3974e 610 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 611 int rc;
612
553c4aa6
TH		 613 rc = ata_pci_device_do_resume(pdev);
614 if (rc)
615 return rc;
c1332875
TH		 616
617 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 618 rc = ahci_pci_reset_controller(host);
c1332875
TH		 619 if (rc)
620 return rc;
621
781d6550 622 ahci_pci_init_controller(host);
c1332875
TH		 623 }
624
cca3974e 625 ata_host_resume(host);
c1332875
TH		 626
627 return 0;
628}
438ac6d5 629#endif
c1332875 630
4447d351 631static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 632{
1da177e4 633 int rc;
1da177e4 634
318893e1
AR		 635 /*
636 * If the device fixup already set the dma_mask to some non-standard
637 * value, don't extend it here. This happens on STA2X11, for example.
638 */
639 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
640 return 0;
641
1da177e4 642 if (using_dac &&
6a35528a
YH		 643 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
644 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 645 if (rc) {
284901a9 646 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 647 if (rc) {
a44fec1f
JP		 648 dev_err(&pdev->dev,
649 "64-bit DMA enable failed\n");
1da177e4
LT		 650 return rc;
651 }
652 }
1da177e4 653 } else {
284901a9 654 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 655 if (rc) {
a44fec1f 656 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 657 return rc;
658 }
284901a9 659 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 660 if (rc) {
a44fec1f
JP		 661 dev_err(&pdev->dev,
662 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 663 return rc;
664 }
665 }
1da177e4
LT		 666 return 0;
667}
668
439fcaec
AV		 669static void ahci_pci_print_info(struct ata_host *host)
670{
671 struct pci_dev *pdev = to_pci_dev(host->dev);
672 u16 cc;
673 const char *scc_s;
674
675 pci_read_config_word(pdev, 0x0a, &cc);
676 if (cc == PCI_CLASS_STORAGE_IDE)
677 scc_s = "IDE";
678 else if (cc == PCI_CLASS_STORAGE_SATA)
679 scc_s = "SATA";
680 else if (cc == PCI_CLASS_STORAGE_RAID)
681 scc_s = "RAID";
682 else
683 scc_s = "unknown";
684
685 ahci_print_info(host, scc_s);
686}
687
edc93052
TH		 688/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
689 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
690 * support PMP and the 4726 either directly exports the device
691 * attached to the first downstream port or acts as a hardware storage
692 * controller and emulate a single ATA device (can be RAID 0/1 or some
693 * other configuration).
694 *
695 * When there's no device attached to the first downstream port of the
696 * 4726, "Config Disk" appears, which is a pseudo ATA device to
697 * configure the 4726. However, ATA emulation of the device is very
698 * lame. It doesn't send signature D2H Reg FIS after the initial
699 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
700 *
701 * The following function works around the problem by always using
702 * hardreset on the port and not depending on receiving signature FIS
703 * afterward. If signature FIS isn't received soon, ATA class is
704 * assumed without follow-up softreset.
705 */
706static void ahci_p5wdh_workaround(struct ata_host *host)
707{
708 static struct dmi_system_id sysids[] = {
709 {
710 .ident = "P5W DH Deluxe",
711 .matches = {
712 DMI_MATCH(DMI_SYS_VENDOR,
713 "ASUSTEK COMPUTER INC"),
714 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
715 },
716 },
717 { }
718 };
719 struct pci_dev *pdev = to_pci_dev(host->dev);
720
721 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
722 dmi_check_system(sysids)) {
723 struct ata_port *ap = host->ports[1];
724
a44fec1f
JP		 725 dev_info(&pdev->dev,
726 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 727
728 ap->ops = &ahci_p5wdh_ops;
729 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
730 }
731}
732
2fcad9d2
TH		 733/* only some SB600 ahci controllers can do 64bit DMA */
734static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 735{
736 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 737 /*
738 * The oldest version known to be broken is 0901 and
739 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 740 * Enable 64bit DMA on 1501 and anything newer.
741 *
03d783bf
TH		 742 * Please read bko#9412 for more info.
743 */
58a09b38
SH		 744 {
745 .ident = "ASUS M2A-VM",
746 .matches = {
747 DMI_MATCH(DMI_BOARD_VENDOR,
748 "ASUSTeK Computer INC."),
749 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
750 },
03d783bf 751 .driver_data = "20071026", /* yyyymmdd */
58a09b38 752 },
e65cc194
MN		 753 /*
754 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
755 * support 64bit DMA.
756 *
757 * BIOS versions earlier than 1.5 had the Manufacturer DMI
758 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
759 * This spelling mistake was fixed in BIOS version 1.5, so
760 * 1.5 and later have the Manufacturer as
761 * "MICRO-STAR INTERNATIONAL CO.,LTD".
762 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
763 *
764 * BIOS versions earlier than 1.9 had a Board Product Name
765 * DMI field of "MS-7376". This was changed to be
766 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
767 * match on DMI_BOARD_NAME of "MS-7376".
768 */
769 {
770 .ident = "MSI K9A2 Platinum",
771 .matches = {
772 DMI_MATCH(DMI_BOARD_VENDOR,
773 "MICRO-STAR INTER"),
774 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
775 },
776 },
3c4aa91f
MN		 777 /*
778 * All BIOS versions for the Asus M3A support 64bit DMA.
779 * (all release versions from 0301 to 1206 were tested)
780 */
781 {
782 .ident = "ASUS M3A",
783 .matches = {
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
787 },
788 },
58a09b38
SH		 789 { }
790 };
03d783bf 791 const struct dmi_system_id *match;
2fcad9d2
TH		 792 int year, month, date;
793 char buf[9];
58a09b38 794
03d783bf 795 match = dmi_first_match(sysids);
58a09b38 796 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 797 !match)
58a09b38
SH		 798 return false;
799
e65cc194
MN		 800 if (!match->driver_data)
801 goto enable_64bit;
802
2fcad9d2
TH		 803 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
804 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 805
e65cc194
MN		 806 if (strcmp(buf, match->driver_data) >= 0)
807 goto enable_64bit;
808 else {
a44fec1f
JP		 809 dev_warn(&pdev->dev,
810 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
811 match->ident);
2fcad9d2
TH		 812 return false;
813 }
e65cc194
MN		 814
815enable_64bit:
a44fec1f 816 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 817 return true;
58a09b38
SH		 818}
819
1fd68434
RW		 820static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
821{
822 static const struct dmi_system_id broken_systems[] = {
823 {
824 .ident = "HP Compaq nx6310",
825 .matches = {
826 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
827 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
828 },
829 /* PCI slot number of the controller */
830 .driver_data = (void *)0x1FUL,
831 },
d2f9c061
MR		 832 {
833 .ident = "HP Compaq 6720s",
834 .matches = {
835 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
836 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
837 },
838 /* PCI slot number of the controller */
839 .driver_data = (void *)0x1FUL,
840 },
1fd68434
RW		 841
842 { } /* terminate list */
843 };
844 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
845
846 if (dmi) {
847 unsigned long slot = (unsigned long)dmi->driver_data;
848 /* apply the quirk only to on-board controllers */
849 return slot == PCI_SLOT(pdev->devfn);
850 }
851
852 return false;
853}
854
9b10ae86
TH		 855static bool ahci_broken_suspend(struct pci_dev *pdev)
856{
857 static const struct dmi_system_id sysids[] = {
858 /*
859 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
860 * to the harddisk doesn't become online after
861 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 862 *
863 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
864 *
865 * Use dates instead of versions to match as HP is
866 * apparently recycling both product and version
867 * strings.
868 *
869 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 870 */
871 {
872 .ident = "dv4",
873 .matches = {
874 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
875 DMI_MATCH(DMI_PRODUCT_NAME,
876 "HP Pavilion dv4 Notebook PC"),
877 },
9deb3431 878 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 879 },
880 {
881 .ident = "dv5",
882 .matches = {
883 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
884 DMI_MATCH(DMI_PRODUCT_NAME,
885 "HP Pavilion dv5 Notebook PC"),
886 },
9deb3431 887 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 888 },
889 {
890 .ident = "dv6",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME,
894 "HP Pavilion dv6 Notebook PC"),
895 },
9deb3431 896 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 897 },
898 {
899 .ident = "HDX18",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
902 DMI_MATCH(DMI_PRODUCT_NAME,
903 "HP HDX18 Notebook PC"),
904 },
9deb3431 905 .driver_data = "20090430", /* F.23 */
9b10ae86 906 },
cedc9bf9
TH		 907 /*
908 * Acer eMachines G725 has the same problem. BIOS
909 * V1.03 is known to be broken. V3.04 is known to
25985edc 910 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 911 * that we don't have much idea about. For now,
912 * blacklist anything older than V3.04.
9deb3431
TH		 913 *
914 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 915 */
916 {
917 .ident = "G725",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
921 },
9deb3431 922 .driver_data = "20091216", /* V3.04 */
cedc9bf9 923 },
9b10ae86
TH		 924 { } /* terminate list */
925 };
926 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 927 int year, month, date;
928 char buf[9];
9b10ae86
TH		 929
930 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
931 return false;
932
9deb3431
TH		 933 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
934 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 935
9deb3431 936 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 937}
938
5594639a
TH		 939static bool ahci_broken_online(struct pci_dev *pdev)
940{
941#define ENCODE_BUSDEVFN(bus, slot, func) \
942 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
943 static const struct dmi_system_id sysids[] = {
944 /*
945 * There are several gigabyte boards which use
946 * SIMG5723s configured as hardware RAID. Certain
947 * 5723 firmware revisions shipped there keep the link
948 * online but fail to answer properly to SRST or
949 * IDENTIFY when no device is attached downstream
950 * causing libata to retry quite a few times leading
951 * to excessive detection delay.
952 *
953 * As these firmwares respond to the second reset try
954 * with invalid device signature, considering unknown
955 * sig as offline works around the problem acceptably.
956 */
957 {
958 .ident = "EP45-DQ6",
959 .matches = {
960 DMI_MATCH(DMI_BOARD_VENDOR,
961 "Gigabyte Technology Co., Ltd."),
962 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
963 },
964 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
965 },
966 {
967 .ident = "EP45-DS5",
968 .matches = {
969 DMI_MATCH(DMI_BOARD_VENDOR,
970 "Gigabyte Technology Co., Ltd."),
971 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
972 },
973 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
974 },
975 { } /* terminate list */
976 };
977#undef ENCODE_BUSDEVFN
978 const struct dmi_system_id *dmi = dmi_first_match(sysids);
979 unsigned int val;
980
981 if (!dmi)
982 return false;
983
984 val = (unsigned long)dmi->driver_data;
985
986 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
987}
988
8e513217 989#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 990static void ahci_gtf_filter_workaround(struct ata_host *host)
991{
992 static const struct dmi_system_id sysids[] = {
993 /*
994 * Aspire 3810T issues a bunch of SATA enable commands
995 * via _GTF including an invalid one and one which is
996 * rejected by the device. Among the successful ones
997 * is FPDMA non-zero offset enable which when enabled
998 * only on the drive side leads to NCQ command
999 * failures. Filter it out.
1000 */
1001 {
1002 .ident = "Aspire 3810T",
1003 .matches = {
1004 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1005 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1006 },
1007 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1008 },
1009 { }
1010 };
1011 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1012 unsigned int filter;
1013 int i;
1014
1015 if (!dmi)
1016 return;
1017
1018 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1019 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1020 filter, dmi->ident);
f80ae7e4
TH		 1021
1022 for (i = 0; i < host->n_ports; i++) {
1023 struct ata_port *ap = host->ports[i];
1024 struct ata_link *link;
1025 struct ata_device *dev;
1026
1027 ata_for_each_link(link, ap, EDGE)
1028 ata_for_each_dev(dev, link, ALL)
1029 dev->gtf_filter |= filter;
1030 }
1031}
8e513217
MT		 1032#else
1033static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1034{}
1035#endif
f80ae7e4 1036
24dc5f33 1037static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1038{
e297d99e
TH		 1039 unsigned int board_id = ent->driver_data;
1040 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1041 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1042 struct device *dev = &pdev->dev;
1da177e4 1043 struct ahci_host_priv *hpriv;
4447d351 1044 struct ata_host *host;
837f5f8f 1045 int n_ports, i, rc;
318893e1 1046 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1047
1048 VPRINTK("ENTER\n");
1049
b429dd59 1050 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1051
06296a1e 1052 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1053
5b66c829
AC		 1054 /* The AHCI driver can only drive the SATA ports, the PATA driver
1055 can drive them all so if both drivers are selected make sure
1056 AHCI stays out of the way */
1057 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1058 return -ENODEV;
1059
c6353b45
TH		 1060 /*
1061 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1062 * ahci, use ata_generic instead.
1063 */
1064 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1065 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1066 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1067 pdev->subsystem_device == 0xcb89)
1068 return -ENODEV;
1069
7a02267e
MN		 1070 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1071 * At the moment, we can only use the AHCI mode. Let the users know
1072 * that for SAS drives they're out of luck.
1073 */
1074 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1075 dev_info(&pdev->dev,
1076 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1077
318893e1
AR		 1078 /* The Connext uses non-standard BAR */
1079 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1080 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1081
4447d351 1082 /* acquire resources */
24dc5f33 1083 rc = pcim_enable_device(pdev);
1da177e4
LT		 1084 if (rc)
1085 return rc;
1086
dea55137
TH		 1087 /* AHCI controllers often implement SFF compatible interface.
1088 * Grab all PCI BARs just in case.
1089 */
318893e1 1090 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1091 if (rc == -EBUSY)
24dc5f33 1092 pcim_pin_device(pdev);
0d5ff566 1093 if (rc)
24dc5f33 1094 return rc;
1da177e4 1095
c4f7792c
TH		 1096 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1097 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1098 u8 map;
1099
1100 /* ICH6s share the same PCI ID for both piix and ahci
1101 * modes. Enabling ahci mode while MAP indicates
1102 * combined mode is a bad idea. Yield to ata_piix.
1103 */
1104 pci_read_config_byte(pdev, ICH_MAP, &map);
1105 if (map & 0x3) {
a44fec1f
JP		 1106 dev_info(&pdev->dev,
1107 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1108 return -ENODEV;
1109 }
1110 }
1111
24dc5f33
TH		 1112 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1113 if (!hpriv)
1114 return -ENOMEM;
417a1a6d
TH		 1115 hpriv->flags |= (unsigned long)pi.private_data;
1116
e297d99e
TH		 1117 /* MCP65 revision A1 and A2 can't do MSI */
1118 if (board_id == board_ahci_mcp65 &&
1119 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1120 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1121
e427fe04
SH		 1122 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1123 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1124 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1125
2fcad9d2
TH		 1126 /* only some SB600s can do 64bit DMA */
1127 if (ahci_sb600_enable_64bit(pdev))
1128 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1129
31b239ad
TH		 1130 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1131 pci_intx(pdev, 1);
1da177e4 1132
318893e1 1133 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1134
4447d351 1135 /* save initial config */
394d6e53 1136 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1137
4447d351 1138 /* prepare host */
453d3131
RH		 1139 if (hpriv->cap & HOST_CAP_NCQ) {
1140 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1141 /*
1142 * Auto-activate optimization is supposed to be
1143 * supported on all AHCI controllers indicating NCQ
1144 * capability, but it seems to be broken on some
1145 * chipsets including NVIDIAs.
1146 */
1147 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1148 pi.flags |= ATA_FLAG_FPDMA_AA;
1149 }
1da177e4 1150
7d50b60b
TH		 1151 if (hpriv->cap & HOST_CAP_PMP)
1152 pi.flags |= ATA_FLAG_PMP;
1153
0cbb0e77 1154 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1155
1fd68434
RW		 1156 if (ahci_broken_system_poweroff(pdev)) {
1157 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1158 dev_info(&pdev->dev,
1159 "quirky BIOS, skipping spindown on poweroff\n");
1160 }
1161
9b10ae86
TH		 1162 if (ahci_broken_suspend(pdev)) {
1163 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1164 dev_warn(&pdev->dev,
1165 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1166 }
1167
5594639a
TH		 1168 if (ahci_broken_online(pdev)) {
1169 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1170 dev_info(&pdev->dev,
1171 "online status unreliable, applying workaround\n");
1172 }
1173
837f5f8f
TH		 1174 /* CAP.NP sometimes indicate the index of the last enabled
1175 * port, at other times, that of the last possible port, so
1176 * determining the maximum port number requires looking at
1177 * both CAP.NP and port_map.
1178 */
1179 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1180
1181 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1182 if (!host)
1183 return -ENOMEM;
4447d351
TH		 1184 host->private_data = hpriv;
1185
f3d7f23f 1186 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1187 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1188 else
1189 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1190
18f7ba4c
KCA		 1191 if (pi.flags & ATA_FLAG_EM)
1192 ahci_reset_em(host);
1193
4447d351 1194 for (i = 0; i < host->n_ports; i++) {
dab632e8 1195 struct ata_port *ap = host->ports[i];
4447d351 1196
318893e1
AR		 1197 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1198 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1199 0x100 + ap->port_no * 0x80, "port");
1200
18f7ba4c
KCA		 1201 /* set enclosure management message type */
1202 if (ap->flags & ATA_FLAG_EM)
008dbd61 1203 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1204
1205
dab632e8 1206 /* disabled/not-implemented port */
350756f6 1207 if (!(hpriv->port_map & (1 << i)))
dab632e8 1208 ap->ops = &ata_dummy_port_ops;
4447d351 1209 }
d447df14 1210
edc93052
TH		 1211 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1212 ahci_p5wdh_workaround(host);
1213
f80ae7e4
TH		 1214 /* apply gtf filter quirk */
1215 ahci_gtf_filter_workaround(host);
1216
4447d351
TH		 1217 /* initialize adapter */
1218 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1219 if (rc)
24dc5f33 1220 return rc;
1da177e4 1221
3303040d 1222 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1223 if (rc)
1224 return rc;
1da177e4 1225
781d6550 1226 ahci_pci_init_controller(host);
439fcaec 1227 ahci_pci_print_info(host);
1da177e4 1228
4447d351
TH		 1229 pci_set_master(pdev);
1230 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1231 &ahci_sht);
907f4678 1232}
1da177e4
LT		 1233
1234static int __init ahci_init(void)
1235{
b7887196 1236 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1237}
1238
1da177e4
LT		 1239static void __exit ahci_exit(void)
1240{
1241 pci_unregister_driver(&ahci_pci_driver);
1242}
1243
1244
1245MODULE_AUTHOR("Jeff Garzik");
1246MODULE_DESCRIPTION("AHCI SATA low-level driver");
1247MODULE_LICENSE("GPL");
1248MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1249MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1250
1251module_init(ahci_init);
1252module_exit(ahci_exit);
Linux kernel - Deliverables
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