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ahci: Add alternate identifier for the 88SE9172
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
98ac62de 106static const struct ata_port_info ahci_port_info[] = {
441577ef 107 /* by features */
facb8fa6 108 [board_ahci] = {
1188c0d8 109 .flags = AHCI_FLAG_COMMON,
14bdef98 110 .pio_mask = ATA_PIO4,
469248ab 111 .udma_mask = ATA_UDMA6,
1da177e4
LT		 112 .port_ops = &ahci_ops,
113 },
facb8fa6 114 [board_ahci_ign_iferr] = {
441577ef 115 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 116 .flags = AHCI_FLAG_COMMON,
14bdef98 117 .pio_mask = ATA_PIO4,
469248ab 118 .udma_mask = ATA_UDMA6,
441577ef 119 .port_ops = &ahci_ops,
bf2af2a2 120 },
facb8fa6 121 [board_ahci_nosntf] = {
441577ef 122 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 123 .flags = AHCI_FLAG_COMMON,
14bdef98 124 .pio_mask = ATA_PIO4,
469248ab 125 .udma_mask = ATA_UDMA6,
41669553
TH		 126 .port_ops = &ahci_ops,
127 },
facb8fa6 128 [board_ahci_yes_fbs] = {
5f173107
TH		 129 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
441577ef 135 /* by chipsets */
facb8fa6 136 [board_ahci_mcp65] = {
83f2b963
TH		 137 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
138 AHCI_HFLAG_YES_NCQ),
ae01b249 139 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
facb8fa6 144 [board_ahci_mcp77] = {
83f2b963
TH		 145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
facb8fa6 151 [board_ahci_mcp89] = {
83f2b963 152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 153 .flags = AHCI_FLAG_COMMON,
14bdef98 154 .pio_mask = ATA_PIO4,
469248ab 155 .udma_mask = ATA_UDMA6,
441577ef 156 .port_ops = &ahci_ops,
55a61604 157 },
facb8fa6 158 [board_ahci_mv] = {
417a1a6d 159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 160 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 162 .pio_mask = ATA_PIO4,
cd70c266
JG		 163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
facb8fa6 166 [board_ahci_sb600] = {
441577ef
TH		 167 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
168 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
169 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 170 .flags = AHCI_FLAG_COMMON,
14bdef98 171 .pio_mask = ATA_PIO4,
e39fc8c9 172 .udma_mask = ATA_UDMA6,
345347c5 173 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 174 },
facb8fa6 175 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
345347c5 180 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 181 },
facb8fa6 182 [board_ahci_vt8251] = {
441577ef 183 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
441577ef 187 .port_ops = &ahci_vt8251_ops,
1b677afd 188 },
1da177e4
LT		 189};
190
3b7d697d 191static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 192 /* Intel */
54bb3a94
JG		 193 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
194 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
195 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
196 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
197 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 198 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 199 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
200 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 203 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 204 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 205 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
207 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
209 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 220 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
221 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 222 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 223 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 224 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 225 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
226 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 227 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 228 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 229 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 230 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 231 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 232 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 233 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
236 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 239 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
240 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
241 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 242 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 243 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 244 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
247 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 250 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 251 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
252 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 259 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
260 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
262 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
fe7fa31a 267
e34bb370
TH		 268 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
269 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
270 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 271 /* JMicron 362B and 362C have an AHCI function with IDE class code */
272 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
273 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 274
275 /* ATI */
c65ec1c2 276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 283
e2dd90b1 284 /* AMD */
5deab536 285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
fe7fa31a 290 /* VIA */
54bb3a94 291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 293
294 /* NVIDIA */
e297d99e
TH		 295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 379
95916edd 380 /* SiS */
20e2de4a
TH		 381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 384
318893e1
AR		 385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
cd70c266
JG		 388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 391 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
5f173107 394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
17c60c6b
AC		 399 { PCI_DEVICE(0x1b4b, 0x9192),
400 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
50be5e36
TH		 401 { PCI_DEVICE(0x1b4b, 0x91a3),
402 .driver_data = board_ahci_yes_fbs },
cd70c266 403
c77a036b
MN		 404 /* Promise */
405 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
406
c9703765
KYL		 407 /* Asmedia */
408 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
409
415ae2b5
JG		 410 /* Generic, PCI class code for AHCI */
411 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 412 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 413
1da177e4
LT		 414 { } /* terminate list */
415};
416
417
418static struct pci_driver ahci_pci_driver = {
419 .name = DRV_NAME,
420 .id_table = ahci_pci_tbl,
421 .probe = ahci_init_one,
24dc5f33 422 .remove = ata_pci_remove_one,
438ac6d5 423#ifdef CONFIG_PM
c1332875 424 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 425 .resume = ahci_pci_device_resume,
426#endif
427};
1da177e4 428
365cfa1e
AV		 429#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
430static int marvell_enable;
431#else
432static int marvell_enable = 1;
433#endif
434module_param(marvell_enable, int, 0644);
435MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 436
1da177e4 437
365cfa1e
AV		 438static void ahci_pci_save_initial_config(struct pci_dev *pdev,
439 struct ahci_host_priv *hpriv)
440{
441 unsigned int force_port_map = 0;
442 unsigned int mask_port_map = 0;
67846b30 443
365cfa1e
AV		 444 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
445 dev_info(&pdev->dev, "JMB361 has only one port\n");
446 force_port_map = 1;
1da177e4
LT		 447 }
448
365cfa1e
AV		 449 /*
450 * Temporary Marvell 6145 hack: PATA port presence
451 * is asserted through the standard AHCI port
452 * presence register, as bit 4 (counting from 0)
d28f87aa 453 */
365cfa1e
AV		 454 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
455 if (pdev->device == 0x6121)
456 mask_port_map = 0x3;
457 else
458 mask_port_map = 0xf;
459 dev_info(&pdev->dev,
460 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
461 }
1da177e4 462
365cfa1e
AV		 463 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
464 mask_port_map);
1da177e4
LT		 465}
466
365cfa1e 467static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 468{
365cfa1e 469 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 470
365cfa1e 471 ahci_reset_controller(host);
1da177e4 472
365cfa1e
AV		 473 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
474 struct ahci_host_priv *hpriv = host->private_data;
475 u16 tmp16;
d6ef3153 476
365cfa1e
AV		 477 /* configure PCS */
478 pci_read_config_word(pdev, 0x92, &tmp16);
479 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
480 tmp16 |= hpriv->port_map;
481 pci_write_config_word(pdev, 0x92, tmp16);
482 }
d6ef3153
SH		 483 }
484
1da177e4
LT		 485 return 0;
486}
487
365cfa1e 488static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 489{
365cfa1e
AV		 490 struct ahci_host_priv *hpriv = host->private_data;
491 struct pci_dev *pdev = to_pci_dev(host->dev);
492 void __iomem *port_mmio;
78cd52d0 493 u32 tmp;
365cfa1e 494 int mv;
78cd52d0 495
365cfa1e
AV		 496 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
497 if (pdev->device == 0x6121)
498 mv = 2;
499 else
500 mv = 4;
501 port_mmio = __ahci_port_base(host, mv);
78cd52d0 502
365cfa1e 503 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 504
365cfa1e
AV		 505 /* clear port IRQ */
506 tmp = readl(port_mmio + PORT_IRQ_STAT);
507 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
508 if (tmp)
509 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 510 }
511
365cfa1e 512 ahci_init_controller(host);
edc93052
TH		 513}
514
365cfa1e
AV		 515static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
516 unsigned long deadline)
d6ef3153 517{
365cfa1e
AV		 518 struct ata_port *ap = link->ap;
519 bool online;
d6ef3153
SH		 520 int rc;
521
365cfa1e 522 DPRINTK("ENTER\n");
d6ef3153 523
365cfa1e 524 ahci_stop_engine(ap);
d6ef3153 525
365cfa1e
AV		 526 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
527 deadline, &online, NULL);
d6ef3153
SH		 528
529 ahci_start_engine(ap);
d6ef3153 530
365cfa1e 531 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 532
365cfa1e
AV		 533 /* vt8251 doesn't clear BSY on signature FIS reception,
534 * request follow-up softreset.
535 */
536 return online ? -EAGAIN : rc;
7d50b60b
TH		 537}
538
365cfa1e
AV		 539static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline)
7d50b60b 541{
365cfa1e 542 struct ata_port *ap = link->ap;
1c954a4d 543 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 544 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
545 struct ata_taskfile tf;
546 bool online;
547 int rc;
7d50b60b 548
365cfa1e 549 ahci_stop_engine(ap);
028a2596 550
365cfa1e
AV		 551 /* clear D2H reception area to properly wait for D2H FIS */
552 ata_tf_init(link->device, &tf);
553 tf.command = 0x80;
554 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 555
365cfa1e
AV		 556 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
557 deadline, &online, NULL);
028a2596 558
365cfa1e 559 ahci_start_engine(ap);
c1332875 560
365cfa1e
AV		 561 /* The pseudo configuration device on SIMG4726 attached to
562 * ASUS P5W-DH Deluxe doesn't send signature FIS after
563 * hardreset if no device is attached to the first downstream
564 * port && the pseudo device locks up on SRST w/ PMP==0. To
565 * work around this, wait for !BSY only briefly. If BSY isn't
566 * cleared, perform CLO and proceed to IDENTIFY (achieved by
567 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
568 *
569 * Wait for two seconds. Devices attached to downstream port
570 * which can't process the following IDENTIFY after this will
571 * have to be reset again. For most cases, this should
572 * suffice while making probing snappish enough.
573 */
574 if (online) {
575 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
576 ahci_check_ready);
577 if (rc)
578 ahci_kick_engine(ap);
c1332875 579 }
c1332875
TH		 580 return rc;
581}
582
365cfa1e 583#ifdef CONFIG_PM
c1332875
TH		 584static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
585{
cca3974e 586 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 587 struct ahci_host_priv *hpriv = host->private_data;
d8993349 588 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 589 u32 ctl;
590
9b10ae86
TH		 591 if (mesg.event & PM_EVENT_SUSPEND &&
592 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 593 dev_err(&pdev->dev,
594 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 595 return -EIO;
596 }
597
3a2d5b70 598 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 599 /* AHCI spec rev1.1 section 8.3.3:
600 * Software must disable interrupts prior to requesting a
601 * transition of the HBA to D3 state.
602 */
603 ctl = readl(mmio + HOST_CTL);
604 ctl &= ~HOST_IRQ_EN;
605 writel(ctl, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
607 }
608
609 return ata_pci_device_suspend(pdev, mesg);
610}
611
612static int ahci_pci_device_resume(struct pci_dev *pdev)
613{
cca3974e 614 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 615 int rc;
616
553c4aa6
TH		 617 rc = ata_pci_device_do_resume(pdev);
618 if (rc)
619 return rc;
c1332875
TH		 620
621 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 622 rc = ahci_pci_reset_controller(host);
c1332875
TH		 623 if (rc)
624 return rc;
625
781d6550 626 ahci_pci_init_controller(host);
c1332875
TH		 627 }
628
cca3974e 629 ata_host_resume(host);
c1332875
TH		 630
631 return 0;
632}
438ac6d5 633#endif
c1332875 634
4447d351 635static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 636{
1da177e4 637 int rc;
1da177e4 638
318893e1
AR		 639 /*
640 * If the device fixup already set the dma_mask to some non-standard
641 * value, don't extend it here. This happens on STA2X11, for example.
642 */
643 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
644 return 0;
645
1da177e4 646 if (using_dac &&
6a35528a
YH		 647 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 649 if (rc) {
284901a9 650 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 651 if (rc) {
a44fec1f
JP		 652 dev_err(&pdev->dev,
653 "64-bit DMA enable failed\n");
1da177e4
LT		 654 return rc;
655 }
656 }
1da177e4 657 } else {
284901a9 658 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 659 if (rc) {
a44fec1f 660 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 661 return rc;
662 }
284901a9 663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 664 if (rc) {
a44fec1f
JP		 665 dev_err(&pdev->dev,
666 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 667 return rc;
668 }
669 }
1da177e4
LT		 670 return 0;
671}
672
439fcaec
AV		 673static void ahci_pci_print_info(struct ata_host *host)
674{
675 struct pci_dev *pdev = to_pci_dev(host->dev);
676 u16 cc;
677 const char *scc_s;
678
679 pci_read_config_word(pdev, 0x0a, &cc);
680 if (cc == PCI_CLASS_STORAGE_IDE)
681 scc_s = "IDE";
682 else if (cc == PCI_CLASS_STORAGE_SATA)
683 scc_s = "SATA";
684 else if (cc == PCI_CLASS_STORAGE_RAID)
685 scc_s = "RAID";
686 else
687 scc_s = "unknown";
688
689 ahci_print_info(host, scc_s);
690}
691
edc93052
TH		 692/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
693 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
694 * support PMP and the 4726 either directly exports the device
695 * attached to the first downstream port or acts as a hardware storage
696 * controller and emulate a single ATA device (can be RAID 0/1 or some
697 * other configuration).
698 *
699 * When there's no device attached to the first downstream port of the
700 * 4726, "Config Disk" appears, which is a pseudo ATA device to
701 * configure the 4726. However, ATA emulation of the device is very
702 * lame. It doesn't send signature D2H Reg FIS after the initial
703 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
704 *
705 * The following function works around the problem by always using
706 * hardreset on the port and not depending on receiving signature FIS
707 * afterward. If signature FIS isn't received soon, ATA class is
708 * assumed without follow-up softreset.
709 */
710static void ahci_p5wdh_workaround(struct ata_host *host)
711{
712 static struct dmi_system_id sysids[] = {
713 {
714 .ident = "P5W DH Deluxe",
715 .matches = {
716 DMI_MATCH(DMI_SYS_VENDOR,
717 "ASUSTEK COMPUTER INC"),
718 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
719 },
720 },
721 { }
722 };
723 struct pci_dev *pdev = to_pci_dev(host->dev);
724
725 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
726 dmi_check_system(sysids)) {
727 struct ata_port *ap = host->ports[1];
728
a44fec1f
JP		 729 dev_info(&pdev->dev,
730 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 731
732 ap->ops = &ahci_p5wdh_ops;
733 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
734 }
735}
736
2fcad9d2
TH		 737/* only some SB600 ahci controllers can do 64bit DMA */
738static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 739{
740 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 741 /*
742 * The oldest version known to be broken is 0901 and
743 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 744 * Enable 64bit DMA on 1501 and anything newer.
745 *
03d783bf
TH		 746 * Please read bko#9412 for more info.
747 */
58a09b38
SH		 748 {
749 .ident = "ASUS M2A-VM",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR,
752 "ASUSTeK Computer INC."),
753 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
754 },
03d783bf 755 .driver_data = "20071026", /* yyyymmdd */
58a09b38 756 },
e65cc194
MN		 757 /*
758 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
759 * support 64bit DMA.
760 *
761 * BIOS versions earlier than 1.5 had the Manufacturer DMI
762 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
763 * This spelling mistake was fixed in BIOS version 1.5, so
764 * 1.5 and later have the Manufacturer as
765 * "MICRO-STAR INTERNATIONAL CO.,LTD".
766 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
767 *
768 * BIOS versions earlier than 1.9 had a Board Product Name
769 * DMI field of "MS-7376". This was changed to be
770 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
771 * match on DMI_BOARD_NAME of "MS-7376".
772 */
773 {
774 .ident = "MSI K9A2 Platinum",
775 .matches = {
776 DMI_MATCH(DMI_BOARD_VENDOR,
777 "MICRO-STAR INTER"),
778 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
779 },
780 },
ff0173c1
MN		 781 /*
782 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
783 * 64bit DMA.
784 *
785 * This board also had the typo mentioned above in the
786 * Manufacturer DMI field (fixed in BIOS version 1.5), so
787 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
788 */
789 {
790 .ident = "MSI K9AGM2",
791 .matches = {
792 DMI_MATCH(DMI_BOARD_VENDOR,
793 "MICRO-STAR INTER"),
794 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
795 },
796 },
3c4aa91f
MN		 797 /*
798 * All BIOS versions for the Asus M3A support 64bit DMA.
799 * (all release versions from 0301 to 1206 were tested)
800 */
801 {
802 .ident = "ASUS M3A",
803 .matches = {
804 DMI_MATCH(DMI_BOARD_VENDOR,
805 "ASUSTeK Computer INC."),
806 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
807 },
808 },
58a09b38
SH		 809 { }
810 };
03d783bf 811 const struct dmi_system_id *match;
2fcad9d2
TH		 812 int year, month, date;
813 char buf[9];
58a09b38 814
03d783bf 815 match = dmi_first_match(sysids);
58a09b38 816 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 817 !match)
58a09b38
SH		 818 return false;
819
e65cc194
MN		 820 if (!match->driver_data)
821 goto enable_64bit;
822
2fcad9d2
TH		 823 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
824 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 825
e65cc194
MN		 826 if (strcmp(buf, match->driver_data) >= 0)
827 goto enable_64bit;
828 else {
a44fec1f
JP		 829 dev_warn(&pdev->dev,
830 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
831 match->ident);
2fcad9d2
TH		 832 return false;
833 }
e65cc194
MN		 834
835enable_64bit:
a44fec1f 836 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 837 return true;
58a09b38
SH		 838}
839
1fd68434
RW		 840static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
841{
842 static const struct dmi_system_id broken_systems[] = {
843 {
844 .ident = "HP Compaq nx6310",
845 .matches = {
846 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
848 },
849 /* PCI slot number of the controller */
850 .driver_data = (void *)0x1FUL,
851 },
d2f9c061
MR		 852 {
853 .ident = "HP Compaq 6720s",
854 .matches = {
855 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
856 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
857 },
858 /* PCI slot number of the controller */
859 .driver_data = (void *)0x1FUL,
860 },
1fd68434
RW		 861
862 { } /* terminate list */
863 };
864 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
865
866 if (dmi) {
867 unsigned long slot = (unsigned long)dmi->driver_data;
868 /* apply the quirk only to on-board controllers */
869 return slot == PCI_SLOT(pdev->devfn);
870 }
871
872 return false;
873}
874
9b10ae86
TH		 875static bool ahci_broken_suspend(struct pci_dev *pdev)
876{
877 static const struct dmi_system_id sysids[] = {
878 /*
879 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
880 * to the harddisk doesn't become online after
881 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 882 *
883 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
884 *
885 * Use dates instead of versions to match as HP is
886 * apparently recycling both product and version
887 * strings.
888 *
889 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 890 */
891 {
892 .ident = "dv4",
893 .matches = {
894 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
895 DMI_MATCH(DMI_PRODUCT_NAME,
896 "HP Pavilion dv4 Notebook PC"),
897 },
9deb3431 898 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 899 },
900 {
901 .ident = "dv5",
902 .matches = {
903 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
904 DMI_MATCH(DMI_PRODUCT_NAME,
905 "HP Pavilion dv5 Notebook PC"),
906 },
9deb3431 907 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 908 },
909 {
910 .ident = "dv6",
911 .matches = {
912 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
913 DMI_MATCH(DMI_PRODUCT_NAME,
914 "HP Pavilion dv6 Notebook PC"),
915 },
9deb3431 916 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 917 },
918 {
919 .ident = "HDX18",
920 .matches = {
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME,
923 "HP HDX18 Notebook PC"),
924 },
9deb3431 925 .driver_data = "20090430", /* F.23 */
9b10ae86 926 },
cedc9bf9
TH		 927 /*
928 * Acer eMachines G725 has the same problem. BIOS
929 * V1.03 is known to be broken. V3.04 is known to
25985edc 930 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 931 * that we don't have much idea about. For now,
932 * blacklist anything older than V3.04.
9deb3431
TH		 933 *
934 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 935 */
936 {
937 .ident = "G725",
938 .matches = {
939 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
940 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
941 },
9deb3431 942 .driver_data = "20091216", /* V3.04 */
cedc9bf9 943 },
9b10ae86
TH		 944 { } /* terminate list */
945 };
946 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 947 int year, month, date;
948 char buf[9];
9b10ae86
TH		 949
950 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
951 return false;
952
9deb3431
TH		 953 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
954 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 955
9deb3431 956 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 957}
958
5594639a
TH		 959static bool ahci_broken_online(struct pci_dev *pdev)
960{
961#define ENCODE_BUSDEVFN(bus, slot, func) \
962 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
963 static const struct dmi_system_id sysids[] = {
964 /*
965 * There are several gigabyte boards which use
966 * SIMG5723s configured as hardware RAID. Certain
967 * 5723 firmware revisions shipped there keep the link
968 * online but fail to answer properly to SRST or
969 * IDENTIFY when no device is attached downstream
970 * causing libata to retry quite a few times leading
971 * to excessive detection delay.
972 *
973 * As these firmwares respond to the second reset try
974 * with invalid device signature, considering unknown
975 * sig as offline works around the problem acceptably.
976 */
977 {
978 .ident = "EP45-DQ6",
979 .matches = {
980 DMI_MATCH(DMI_BOARD_VENDOR,
981 "Gigabyte Technology Co., Ltd."),
982 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
983 },
984 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
985 },
986 {
987 .ident = "EP45-DS5",
988 .matches = {
989 DMI_MATCH(DMI_BOARD_VENDOR,
990 "Gigabyte Technology Co., Ltd."),
991 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
992 },
993 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
994 },
995 { } /* terminate list */
996 };
997#undef ENCODE_BUSDEVFN
998 const struct dmi_system_id *dmi = dmi_first_match(sysids);
999 unsigned int val;
1000
1001 if (!dmi)
1002 return false;
1003
1004 val = (unsigned long)dmi->driver_data;
1005
1006 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1007}
1008
8e513217 1009#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1010static void ahci_gtf_filter_workaround(struct ata_host *host)
1011{
1012 static const struct dmi_system_id sysids[] = {
1013 /*
1014 * Aspire 3810T issues a bunch of SATA enable commands
1015 * via _GTF including an invalid one and one which is
1016 * rejected by the device. Among the successful ones
1017 * is FPDMA non-zero offset enable which when enabled
1018 * only on the drive side leads to NCQ command
1019 * failures. Filter it out.
1020 */
1021 {
1022 .ident = "Aspire 3810T",
1023 .matches = {
1024 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1025 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1026 },
1027 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1028 },
1029 { }
1030 };
1031 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1032 unsigned int filter;
1033 int i;
1034
1035 if (!dmi)
1036 return;
1037
1038 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1039 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1040 filter, dmi->ident);
f80ae7e4
TH		 1041
1042 for (i = 0; i < host->n_ports; i++) {
1043 struct ata_port *ap = host->ports[i];
1044 struct ata_link *link;
1045 struct ata_device *dev;
1046
1047 ata_for_each_link(link, ap, EDGE)
1048 ata_for_each_dev(dev, link, ALL)
1049 dev->gtf_filter |= filter;
1050 }
1051}
8e513217
MT		 1052#else
1053static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1054{}
1055#endif
f80ae7e4 1056
24dc5f33 1057static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1058{
e297d99e
TH		 1059 unsigned int board_id = ent->driver_data;
1060 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1061 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1062 struct device *dev = &pdev->dev;
1da177e4 1063 struct ahci_host_priv *hpriv;
4447d351 1064 struct ata_host *host;
837f5f8f 1065 int n_ports, i, rc;
318893e1 1066 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1067
1068 VPRINTK("ENTER\n");
1069
b429dd59 1070 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1071
06296a1e 1072 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1073
5b66c829
AC		 1074 /* The AHCI driver can only drive the SATA ports, the PATA driver
1075 can drive them all so if both drivers are selected make sure
1076 AHCI stays out of the way */
1077 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1078 return -ENODEV;
1079
c6353b45
TH		 1080 /*
1081 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1082 * ahci, use ata_generic instead.
1083 */
1084 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1085 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1086 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1087 pdev->subsystem_device == 0xcb89)
1088 return -ENODEV;
1089
7a02267e
MN		 1090 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1091 * At the moment, we can only use the AHCI mode. Let the users know
1092 * that for SAS drives they're out of luck.
1093 */
1094 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1095 dev_info(&pdev->dev,
1096 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1097
318893e1
AR		 1098 /* The Connext uses non-standard BAR */
1099 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1100 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1101
4447d351 1102 /* acquire resources */
24dc5f33 1103 rc = pcim_enable_device(pdev);
1da177e4
LT		 1104 if (rc)
1105 return rc;
1106
dea55137
TH		 1107 /* AHCI controllers often implement SFF compatible interface.
1108 * Grab all PCI BARs just in case.
1109 */
318893e1 1110 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1111 if (rc == -EBUSY)
24dc5f33 1112 pcim_pin_device(pdev);
0d5ff566 1113 if (rc)
24dc5f33 1114 return rc;
1da177e4 1115
c4f7792c
TH		 1116 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1117 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1118 u8 map;
1119
1120 /* ICH6s share the same PCI ID for both piix and ahci
1121 * modes. Enabling ahci mode while MAP indicates
1122 * combined mode is a bad idea. Yield to ata_piix.
1123 */
1124 pci_read_config_byte(pdev, ICH_MAP, &map);
1125 if (map & 0x3) {
a44fec1f
JP		 1126 dev_info(&pdev->dev,
1127 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1128 return -ENODEV;
1129 }
1130 }
1131
24dc5f33
TH		 1132 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1133 if (!hpriv)
1134 return -ENOMEM;
417a1a6d
TH		 1135 hpriv->flags |= (unsigned long)pi.private_data;
1136
e297d99e
TH		 1137 /* MCP65 revision A1 and A2 can't do MSI */
1138 if (board_id == board_ahci_mcp65 &&
1139 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1140 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1141
e427fe04
SH		 1142 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1143 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1144 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1145
2fcad9d2
TH		 1146 /* only some SB600s can do 64bit DMA */
1147 if (ahci_sb600_enable_64bit(pdev))
1148 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1149
31b239ad
TH		 1150 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1151 pci_intx(pdev, 1);
1da177e4 1152
318893e1 1153 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1154
4447d351 1155 /* save initial config */
394d6e53 1156 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1157
4447d351 1158 /* prepare host */
453d3131
RH		 1159 if (hpriv->cap & HOST_CAP_NCQ) {
1160 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1161 /*
1162 * Auto-activate optimization is supposed to be
1163 * supported on all AHCI controllers indicating NCQ
1164 * capability, but it seems to be broken on some
1165 * chipsets including NVIDIAs.
1166 */
1167 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1168 pi.flags |= ATA_FLAG_FPDMA_AA;
1169 }
1da177e4 1170
7d50b60b
TH		 1171 if (hpriv->cap & HOST_CAP_PMP)
1172 pi.flags |= ATA_FLAG_PMP;
1173
0cbb0e77 1174 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1175
1fd68434
RW		 1176 if (ahci_broken_system_poweroff(pdev)) {
1177 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1178 dev_info(&pdev->dev,
1179 "quirky BIOS, skipping spindown on poweroff\n");
1180 }
1181
9b10ae86
TH		 1182 if (ahci_broken_suspend(pdev)) {
1183 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1184 dev_warn(&pdev->dev,
1185 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1186 }
1187
5594639a
TH		 1188 if (ahci_broken_online(pdev)) {
1189 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1190 dev_info(&pdev->dev,
1191 "online status unreliable, applying workaround\n");
1192 }
1193
837f5f8f
TH		 1194 /* CAP.NP sometimes indicate the index of the last enabled
1195 * port, at other times, that of the last possible port, so
1196 * determining the maximum port number requires looking at
1197 * both CAP.NP and port_map.
1198 */
1199 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1200
1201 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1202 if (!host)
1203 return -ENOMEM;
4447d351
TH		 1204 host->private_data = hpriv;
1205
f3d7f23f 1206 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1207 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1208 else
1209 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1210
18f7ba4c
KCA		 1211 if (pi.flags & ATA_FLAG_EM)
1212 ahci_reset_em(host);
1213
4447d351 1214 for (i = 0; i < host->n_ports; i++) {
dab632e8 1215 struct ata_port *ap = host->ports[i];
4447d351 1216
318893e1
AR		 1217 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1218 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1219 0x100 + ap->port_no * 0x80, "port");
1220
18f7ba4c
KCA		 1221 /* set enclosure management message type */
1222 if (ap->flags & ATA_FLAG_EM)
008dbd61 1223 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1224
1225
dab632e8 1226 /* disabled/not-implemented port */
350756f6 1227 if (!(hpriv->port_map & (1 << i)))
dab632e8 1228 ap->ops = &ata_dummy_port_ops;
4447d351 1229 }
d447df14 1230
edc93052
TH		 1231 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1232 ahci_p5wdh_workaround(host);
1233
f80ae7e4
TH		 1234 /* apply gtf filter quirk */
1235 ahci_gtf_filter_workaround(host);
1236
4447d351
TH		 1237 /* initialize adapter */
1238 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1239 if (rc)
24dc5f33 1240 return rc;
1da177e4 1241
3303040d 1242 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1243 if (rc)
1244 return rc;
1da177e4 1245
781d6550 1246 ahci_pci_init_controller(host);
439fcaec 1247 ahci_pci_print_info(host);
1da177e4 1248
4447d351
TH		 1249 pci_set_master(pdev);
1250 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1251 &ahci_sht);
907f4678 1252}
1da177e4 1253
2fc75da0 1254module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1255
1256MODULE_AUTHOR("Jeff Garzik");
1257MODULE_DESCRIPTION("AHCI SATA low-level driver");
1258MODULE_LICENSE("GPL");
1259MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1260MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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