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ahci: move ahci_sb600_softreset to libahci.c and rename it
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 82static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
438ac6d5 86#ifdef CONFIG_PM
c1332875
TH		 87static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 89#endif
ad616ffb 90
fad16e7a
TH		 91static struct scsi_host_template ahci_sht = {
92 AHCI_SHT("ahci"),
93};
94
029cfd6b
TH		 95static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
a1efdaba 97 .hardreset = ahci_vt8251_hardreset,
029cfd6b 98};
edc93052 99
029cfd6b
TH		 100static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 103};
104
417a1a6d
TH		 105#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
4da646b7 109 [board_ahci] =
1da177e4 110 {
1188c0d8 111 .flags = AHCI_FLAG_COMMON,
14bdef98 112 .pio_mask = ATA_PIO4,
469248ab 113 .udma_mask = ATA_UDMA6,
1da177e4
LT		 114 .port_ops = &ahci_ops,
115 },
441577ef 116 [board_ahci_ign_iferr] =
bf2af2a2 117 {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
441577ef 124 [board_ahci_nosntf] =
41669553 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
41669553
TH		 130 .port_ops = &ahci_ops,
131 },
5f173107
TH		 132 [board_ahci_yes_fbs] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
441577ef
TH		 140 /* by chipsets */
141 [board_ahci_mcp65] =
55a61604 142 {
83f2b963
TH		 143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
144 AHCI_HFLAG_YES_NCQ),
ae01b249 145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_mcp77] =
151 {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp89] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 161 .flags = AHCI_FLAG_COMMON,
14bdef98 162 .pio_mask = ATA_PIO4,
469248ab 163 .udma_mask = ATA_UDMA6,
441577ef 164 .port_ops = &ahci_ops,
55a61604 165 },
4da646b7 166 [board_ahci_mv] =
cd70c266 167 {
417a1a6d 168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 171 .pio_mask = ATA_PIO4,
cd70c266
JG		 172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
441577ef 175 [board_ahci_sb600] =
e39fc8c9 176 {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
441577ef 185 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 186 {
441577ef 187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 192 },
441577ef 193 [board_ahci_vt8251] =
1b677afd 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_vt8251_ops,
1b677afd 200 },
1da177e4
LT		 201};
202
3b7d697d 203static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 204 /* Intel */
54bb3a94
JG		 205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
fe7fa31a 262
e34bb370
TH		 263 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
264 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
265 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 266
267 /* ATI */
c65ec1c2 268 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 269 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
270 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 275
e2dd90b1 276 /* AMD */
5deab536 277 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 278 /* AMD is using RAID class only for ahci controllers */
279 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
280 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
281
fe7fa31a 282 /* VIA */
54bb3a94 283 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 284 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 285
286 /* NVIDIA */
e297d99e
TH		 287 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 295 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 371
95916edd 372 /* SiS */
20e2de4a
TH		 373 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
374 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
375 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 376
cd70c266
JG		 377 /* Marvell */
378 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 379 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 380 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 381 .class = PCI_CLASS_STORAGE_SATA_AHCI,
382 .class_mask = 0xffffff,
5f173107 383 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 384 { PCI_DEVICE(0x1b4b, 0x9125),
385 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 386 { PCI_DEVICE(0x1b4b, 0x91a3),
387 .driver_data = board_ahci_yes_fbs },
cd70c266 388
c77a036b
MN		 389 /* Promise */
390 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
391
415ae2b5
JG		 392 /* Generic, PCI class code for AHCI */
393 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 394 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 395
1da177e4
LT		 396 { } /* terminate list */
397};
398
399
400static struct pci_driver ahci_pci_driver = {
401 .name = DRV_NAME,
402 .id_table = ahci_pci_tbl,
403 .probe = ahci_init_one,
24dc5f33 404 .remove = ata_pci_remove_one,
438ac6d5 405#ifdef CONFIG_PM
c1332875 406 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 407 .resume = ahci_pci_device_resume,
408#endif
409};
1da177e4 410
365cfa1e
AV		 411#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
412static int marvell_enable;
413#else
414static int marvell_enable = 1;
415#endif
416module_param(marvell_enable, int, 0644);
417MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 418
1da177e4 419
365cfa1e
AV		 420static void ahci_pci_save_initial_config(struct pci_dev *pdev,
421 struct ahci_host_priv *hpriv)
422{
423 unsigned int force_port_map = 0;
424 unsigned int mask_port_map = 0;
67846b30 425
365cfa1e
AV		 426 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
427 dev_info(&pdev->dev, "JMB361 has only one port\n");
428 force_port_map = 1;
1da177e4
LT		 429 }
430
365cfa1e
AV		 431 /*
432 * Temporary Marvell 6145 hack: PATA port presence
433 * is asserted through the standard AHCI port
434 * presence register, as bit 4 (counting from 0)
d28f87aa 435 */
365cfa1e
AV		 436 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
437 if (pdev->device == 0x6121)
438 mask_port_map = 0x3;
439 else
440 mask_port_map = 0xf;
441 dev_info(&pdev->dev,
442 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
443 }
1da177e4 444
365cfa1e
AV		 445 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
446 mask_port_map);
1da177e4
LT		 447}
448
365cfa1e 449static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 450{
365cfa1e 451 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 452
365cfa1e 453 ahci_reset_controller(host);
1da177e4 454
365cfa1e
AV		 455 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
456 struct ahci_host_priv *hpriv = host->private_data;
457 u16 tmp16;
d6ef3153 458
365cfa1e
AV		 459 /* configure PCS */
460 pci_read_config_word(pdev, 0x92, &tmp16);
461 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
462 tmp16 |= hpriv->port_map;
463 pci_write_config_word(pdev, 0x92, tmp16);
464 }
d6ef3153
SH		 465 }
466
1da177e4
LT		 467 return 0;
468}
469
365cfa1e 470static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 471{
365cfa1e
AV		 472 struct ahci_host_priv *hpriv = host->private_data;
473 struct pci_dev *pdev = to_pci_dev(host->dev);
474 void __iomem *port_mmio;
78cd52d0 475 u32 tmp;
365cfa1e 476 int mv;
78cd52d0 477
365cfa1e
AV		 478 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
479 if (pdev->device == 0x6121)
480 mv = 2;
481 else
482 mv = 4;
483 port_mmio = __ahci_port_base(host, mv);
78cd52d0 484
365cfa1e 485 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 486
365cfa1e
AV		 487 /* clear port IRQ */
488 tmp = readl(port_mmio + PORT_IRQ_STAT);
489 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
490 if (tmp)
491 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 492 }
493
365cfa1e 494 ahci_init_controller(host);
edc93052
TH		 495}
496
365cfa1e
AV		 497static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
498 unsigned long deadline)
d6ef3153 499{
365cfa1e
AV		 500 struct ata_port *ap = link->ap;
501 bool online;
d6ef3153
SH		 502 int rc;
503
365cfa1e 504 DPRINTK("ENTER\n");
d6ef3153 505
365cfa1e 506 ahci_stop_engine(ap);
d6ef3153 507
365cfa1e
AV		 508 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
509 deadline, &online, NULL);
d6ef3153
SH		 510
511 ahci_start_engine(ap);
d6ef3153 512
365cfa1e 513 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 514
365cfa1e
AV		 515 /* vt8251 doesn't clear BSY on signature FIS reception,
516 * request follow-up softreset.
517 */
518 return online ? -EAGAIN : rc;
7d50b60b
TH		 519}
520
365cfa1e
AV		 521static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
522 unsigned long deadline)
7d50b60b 523{
365cfa1e 524 struct ata_port *ap = link->ap;
1c954a4d 525 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 526 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
527 struct ata_taskfile tf;
528 bool online;
529 int rc;
7d50b60b 530
365cfa1e 531 ahci_stop_engine(ap);
028a2596 532
365cfa1e
AV		 533 /* clear D2H reception area to properly wait for D2H FIS */
534 ata_tf_init(link->device, &tf);
535 tf.command = 0x80;
536 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 537
365cfa1e
AV		 538 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
539 deadline, &online, NULL);
028a2596 540
365cfa1e 541 ahci_start_engine(ap);
c1332875 542
365cfa1e
AV		 543 /* The pseudo configuration device on SIMG4726 attached to
544 * ASUS P5W-DH Deluxe doesn't send signature FIS after
545 * hardreset if no device is attached to the first downstream
546 * port && the pseudo device locks up on SRST w/ PMP==0. To
547 * work around this, wait for !BSY only briefly. If BSY isn't
548 * cleared, perform CLO and proceed to IDENTIFY (achieved by
549 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
550 *
551 * Wait for two seconds. Devices attached to downstream port
552 * which can't process the following IDENTIFY after this will
553 * have to be reset again. For most cases, this should
554 * suffice while making probing snappish enough.
555 */
556 if (online) {
557 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
558 ahci_check_ready);
559 if (rc)
560 ahci_kick_engine(ap);
c1332875 561 }
c1332875
TH		 562 return rc;
563}
564
365cfa1e 565#ifdef CONFIG_PM
c1332875
TH		 566static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
567{
cca3974e 568 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 569 struct ahci_host_priv *hpriv = host->private_data;
d8993349 570 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 571 u32 ctl;
572
9b10ae86
TH		 573 if (mesg.event & PM_EVENT_SUSPEND &&
574 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 575 dev_err(&pdev->dev,
576 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 577 return -EIO;
578 }
579
3a2d5b70 580 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 581 /* AHCI spec rev1.1 section 8.3.3:
582 * Software must disable interrupts prior to requesting a
583 * transition of the HBA to D3 state.
584 */
585 ctl = readl(mmio + HOST_CTL);
586 ctl &= ~HOST_IRQ_EN;
587 writel(ctl, mmio + HOST_CTL);
588 readl(mmio + HOST_CTL); /* flush */
589 }
590
591 return ata_pci_device_suspend(pdev, mesg);
592}
593
594static int ahci_pci_device_resume(struct pci_dev *pdev)
595{
cca3974e 596 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 597 int rc;
598
553c4aa6
TH		 599 rc = ata_pci_device_do_resume(pdev);
600 if (rc)
601 return rc;
c1332875
TH		 602
603 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 604 rc = ahci_pci_reset_controller(host);
c1332875
TH		 605 if (rc)
606 return rc;
607
781d6550 608 ahci_pci_init_controller(host);
c1332875
TH		 609 }
610
cca3974e 611 ata_host_resume(host);
c1332875
TH		 612
613 return 0;
614}
438ac6d5 615#endif
c1332875 616
4447d351 617static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 618{
1da177e4 619 int rc;
1da177e4 620
1da177e4 621 if (using_dac &&
6a35528a
YH		 622 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
623 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 624 if (rc) {
284901a9 625 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 626 if (rc) {
a44fec1f
JP		 627 dev_err(&pdev->dev,
628 "64-bit DMA enable failed\n");
1da177e4
LT		 629 return rc;
630 }
631 }
1da177e4 632 } else {
284901a9 633 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 634 if (rc) {
a44fec1f 635 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 636 return rc;
637 }
284901a9 638 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 639 if (rc) {
a44fec1f
JP		 640 dev_err(&pdev->dev,
641 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 642 return rc;
643 }
644 }
1da177e4
LT		 645 return 0;
646}
647
439fcaec
AV		 648static void ahci_pci_print_info(struct ata_host *host)
649{
650 struct pci_dev *pdev = to_pci_dev(host->dev);
651 u16 cc;
652 const char *scc_s;
653
654 pci_read_config_word(pdev, 0x0a, &cc);
655 if (cc == PCI_CLASS_STORAGE_IDE)
656 scc_s = "IDE";
657 else if (cc == PCI_CLASS_STORAGE_SATA)
658 scc_s = "SATA";
659 else if (cc == PCI_CLASS_STORAGE_RAID)
660 scc_s = "RAID";
661 else
662 scc_s = "unknown";
663
664 ahci_print_info(host, scc_s);
665}
666
edc93052
TH		 667/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
668 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
669 * support PMP and the 4726 either directly exports the device
670 * attached to the first downstream port or acts as a hardware storage
671 * controller and emulate a single ATA device (can be RAID 0/1 or some
672 * other configuration).
673 *
674 * When there's no device attached to the first downstream port of the
675 * 4726, "Config Disk" appears, which is a pseudo ATA device to
676 * configure the 4726. However, ATA emulation of the device is very
677 * lame. It doesn't send signature D2H Reg FIS after the initial
678 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
679 *
680 * The following function works around the problem by always using
681 * hardreset on the port and not depending on receiving signature FIS
682 * afterward. If signature FIS isn't received soon, ATA class is
683 * assumed without follow-up softreset.
684 */
685static void ahci_p5wdh_workaround(struct ata_host *host)
686{
687 static struct dmi_system_id sysids[] = {
688 {
689 .ident = "P5W DH Deluxe",
690 .matches = {
691 DMI_MATCH(DMI_SYS_VENDOR,
692 "ASUSTEK COMPUTER INC"),
693 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
694 },
695 },
696 { }
697 };
698 struct pci_dev *pdev = to_pci_dev(host->dev);
699
700 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
701 dmi_check_system(sysids)) {
702 struct ata_port *ap = host->ports[1];
703
a44fec1f
JP		 704 dev_info(&pdev->dev,
705 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 706
707 ap->ops = &ahci_p5wdh_ops;
708 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
709 }
710}
711
2fcad9d2
TH		 712/* only some SB600 ahci controllers can do 64bit DMA */
713static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 714{
715 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 716 /*
717 * The oldest version known to be broken is 0901 and
718 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 719 * Enable 64bit DMA on 1501 and anything newer.
720 *
03d783bf
TH		 721 * Please read bko#9412 for more info.
722 */
58a09b38
SH		 723 {
724 .ident = "ASUS M2A-VM",
725 .matches = {
726 DMI_MATCH(DMI_BOARD_VENDOR,
727 "ASUSTeK Computer INC."),
728 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
729 },
03d783bf 730 .driver_data = "20071026", /* yyyymmdd */
58a09b38 731 },
e65cc194
MN		 732 /*
733 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
734 * support 64bit DMA.
735 *
736 * BIOS versions earlier than 1.5 had the Manufacturer DMI
737 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
738 * This spelling mistake was fixed in BIOS version 1.5, so
739 * 1.5 and later have the Manufacturer as
740 * "MICRO-STAR INTERNATIONAL CO.,LTD".
741 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
742 *
743 * BIOS versions earlier than 1.9 had a Board Product Name
744 * DMI field of "MS-7376". This was changed to be
745 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
746 * match on DMI_BOARD_NAME of "MS-7376".
747 */
748 {
749 .ident = "MSI K9A2 Platinum",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR,
752 "MICRO-STAR INTER"),
753 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
754 },
755 },
58a09b38
SH		 756 { }
757 };
03d783bf 758 const struct dmi_system_id *match;
2fcad9d2
TH		 759 int year, month, date;
760 char buf[9];
58a09b38 761
03d783bf 762 match = dmi_first_match(sysids);
58a09b38 763 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 764 !match)
58a09b38
SH		 765 return false;
766
e65cc194
MN		 767 if (!match->driver_data)
768 goto enable_64bit;
769
2fcad9d2
TH		 770 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
771 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 772
e65cc194
MN		 773 if (strcmp(buf, match->driver_data) >= 0)
774 goto enable_64bit;
775 else {
a44fec1f
JP		 776 dev_warn(&pdev->dev,
777 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
778 match->ident);
2fcad9d2
TH		 779 return false;
780 }
e65cc194
MN		 781
782enable_64bit:
a44fec1f 783 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 784 return true;
58a09b38
SH		 785}
786
1fd68434
RW		 787static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
788{
789 static const struct dmi_system_id broken_systems[] = {
790 {
791 .ident = "HP Compaq nx6310",
792 .matches = {
793 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
794 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
795 },
796 /* PCI slot number of the controller */
797 .driver_data = (void *)0x1FUL,
798 },
d2f9c061
MR		 799 {
800 .ident = "HP Compaq 6720s",
801 .matches = {
802 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
803 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
804 },
805 /* PCI slot number of the controller */
806 .driver_data = (void *)0x1FUL,
807 },
1fd68434
RW		 808
809 { } /* terminate list */
810 };
811 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
812
813 if (dmi) {
814 unsigned long slot = (unsigned long)dmi->driver_data;
815 /* apply the quirk only to on-board controllers */
816 return slot == PCI_SLOT(pdev->devfn);
817 }
818
819 return false;
820}
821
9b10ae86
TH		 822static bool ahci_broken_suspend(struct pci_dev *pdev)
823{
824 static const struct dmi_system_id sysids[] = {
825 /*
826 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
827 * to the harddisk doesn't become online after
828 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 829 *
830 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
831 *
832 * Use dates instead of versions to match as HP is
833 * apparently recycling both product and version
834 * strings.
835 *
836 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 837 */
838 {
839 .ident = "dv4",
840 .matches = {
841 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
842 DMI_MATCH(DMI_PRODUCT_NAME,
843 "HP Pavilion dv4 Notebook PC"),
844 },
9deb3431 845 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 846 },
847 {
848 .ident = "dv5",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
851 DMI_MATCH(DMI_PRODUCT_NAME,
852 "HP Pavilion dv5 Notebook PC"),
853 },
9deb3431 854 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 855 },
856 {
857 .ident = "dv6",
858 .matches = {
859 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
860 DMI_MATCH(DMI_PRODUCT_NAME,
861 "HP Pavilion dv6 Notebook PC"),
862 },
9deb3431 863 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 864 },
865 {
866 .ident = "HDX18",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
869 DMI_MATCH(DMI_PRODUCT_NAME,
870 "HP HDX18 Notebook PC"),
871 },
9deb3431 872 .driver_data = "20090430", /* F.23 */
9b10ae86 873 },
cedc9bf9
TH		 874 /*
875 * Acer eMachines G725 has the same problem. BIOS
876 * V1.03 is known to be broken. V3.04 is known to
25985edc 877 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 878 * that we don't have much idea about. For now,
879 * blacklist anything older than V3.04.
9deb3431
TH		 880 *
881 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 882 */
883 {
884 .ident = "G725",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
887 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
888 },
9deb3431 889 .driver_data = "20091216", /* V3.04 */
cedc9bf9 890 },
9b10ae86
TH		 891 { } /* terminate list */
892 };
893 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 894 int year, month, date;
895 char buf[9];
9b10ae86
TH		 896
897 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
898 return false;
899
9deb3431
TH		 900 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
901 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 902
9deb3431 903 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 904}
905
5594639a
TH		 906static bool ahci_broken_online(struct pci_dev *pdev)
907{
908#define ENCODE_BUSDEVFN(bus, slot, func) \
909 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
910 static const struct dmi_system_id sysids[] = {
911 /*
912 * There are several gigabyte boards which use
913 * SIMG5723s configured as hardware RAID. Certain
914 * 5723 firmware revisions shipped there keep the link
915 * online but fail to answer properly to SRST or
916 * IDENTIFY when no device is attached downstream
917 * causing libata to retry quite a few times leading
918 * to excessive detection delay.
919 *
920 * As these firmwares respond to the second reset try
921 * with invalid device signature, considering unknown
922 * sig as offline works around the problem acceptably.
923 */
924 {
925 .ident = "EP45-DQ6",
926 .matches = {
927 DMI_MATCH(DMI_BOARD_VENDOR,
928 "Gigabyte Technology Co., Ltd."),
929 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
930 },
931 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
932 },
933 {
934 .ident = "EP45-DS5",
935 .matches = {
936 DMI_MATCH(DMI_BOARD_VENDOR,
937 "Gigabyte Technology Co., Ltd."),
938 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
939 },
940 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
941 },
942 { } /* terminate list */
943 };
944#undef ENCODE_BUSDEVFN
945 const struct dmi_system_id *dmi = dmi_first_match(sysids);
946 unsigned int val;
947
948 if (!dmi)
949 return false;
950
951 val = (unsigned long)dmi->driver_data;
952
953 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
954}
955
8e513217 956#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 957static void ahci_gtf_filter_workaround(struct ata_host *host)
958{
959 static const struct dmi_system_id sysids[] = {
960 /*
961 * Aspire 3810T issues a bunch of SATA enable commands
962 * via _GTF including an invalid one and one which is
963 * rejected by the device. Among the successful ones
964 * is FPDMA non-zero offset enable which when enabled
965 * only on the drive side leads to NCQ command
966 * failures. Filter it out.
967 */
968 {
969 .ident = "Aspire 3810T",
970 .matches = {
971 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
972 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
973 },
974 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
975 },
976 { }
977 };
978 const struct dmi_system_id *dmi = dmi_first_match(sysids);
979 unsigned int filter;
980 int i;
981
982 if (!dmi)
983 return;
984
985 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 986 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
987 filter, dmi->ident);
f80ae7e4
TH		 988
989 for (i = 0; i < host->n_ports; i++) {
990 struct ata_port *ap = host->ports[i];
991 struct ata_link *link;
992 struct ata_device *dev;
993
994 ata_for_each_link(link, ap, EDGE)
995 ata_for_each_dev(dev, link, ALL)
996 dev->gtf_filter |= filter;
997 }
998}
8e513217
MT		 999#else
1000static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1001{}
1002#endif
f80ae7e4 1003
24dc5f33 1004static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1005{
e297d99e
TH		 1006 unsigned int board_id = ent->driver_data;
1007 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1008 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1009 struct device *dev = &pdev->dev;
1da177e4 1010 struct ahci_host_priv *hpriv;
4447d351 1011 struct ata_host *host;
837f5f8f 1012 int n_ports, i, rc;
1da177e4
LT		 1013
1014 VPRINTK("ENTER\n");
1015
b429dd59 1016 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1017
06296a1e 1018 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1019
5b66c829
AC		 1020 /* The AHCI driver can only drive the SATA ports, the PATA driver
1021 can drive them all so if both drivers are selected make sure
1022 AHCI stays out of the way */
1023 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1024 return -ENODEV;
1025
c6353b45
TH		 1026 /*
1027 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1028 * ahci, use ata_generic instead.
1029 */
1030 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1031 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1032 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1033 pdev->subsystem_device == 0xcb89)
1034 return -ENODEV;
1035
7a02267e
MN		 1036 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1037 * At the moment, we can only use the AHCI mode. Let the users know
1038 * that for SAS drives they're out of luck.
1039 */
1040 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1041 dev_info(&pdev->dev,
1042 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1043
4447d351 1044 /* acquire resources */
24dc5f33 1045 rc = pcim_enable_device(pdev);
1da177e4
LT		 1046 if (rc)
1047 return rc;
1048
dea55137
TH		 1049 /* AHCI controllers often implement SFF compatible interface.
1050 * Grab all PCI BARs just in case.
1051 */
1052 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1053 if (rc == -EBUSY)
24dc5f33 1054 pcim_pin_device(pdev);
0d5ff566 1055 if (rc)
24dc5f33 1056 return rc;
1da177e4 1057
c4f7792c
TH		 1058 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1059 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1060 u8 map;
1061
1062 /* ICH6s share the same PCI ID for both piix and ahci
1063 * modes. Enabling ahci mode while MAP indicates
1064 * combined mode is a bad idea. Yield to ata_piix.
1065 */
1066 pci_read_config_byte(pdev, ICH_MAP, &map);
1067 if (map & 0x3) {
a44fec1f
JP		 1068 dev_info(&pdev->dev,
1069 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1070 return -ENODEV;
1071 }
1072 }
1073
24dc5f33
TH		 1074 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1075 if (!hpriv)
1076 return -ENOMEM;
417a1a6d
TH		 1077 hpriv->flags |= (unsigned long)pi.private_data;
1078
e297d99e
TH		 1079 /* MCP65 revision A1 and A2 can't do MSI */
1080 if (board_id == board_ahci_mcp65 &&
1081 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1082 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1083
e427fe04
SH		 1084 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1085 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1086 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1087
2fcad9d2
TH		 1088 /* only some SB600s can do 64bit DMA */
1089 if (ahci_sb600_enable_64bit(pdev))
1090 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1091
31b239ad
TH		 1092 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1093 pci_intx(pdev, 1);
1da177e4 1094
d8993349
AV		 1095 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1096
4447d351 1097 /* save initial config */
394d6e53 1098 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1099
4447d351 1100 /* prepare host */
453d3131
RH		 1101 if (hpriv->cap & HOST_CAP_NCQ) {
1102 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1103 /*
1104 * Auto-activate optimization is supposed to be
1105 * supported on all AHCI controllers indicating NCQ
1106 * capability, but it seems to be broken on some
1107 * chipsets including NVIDIAs.
1108 */
1109 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1110 pi.flags |= ATA_FLAG_FPDMA_AA;
1111 }
1da177e4 1112
7d50b60b
TH		 1113 if (hpriv->cap & HOST_CAP_PMP)
1114 pi.flags |= ATA_FLAG_PMP;
1115
0cbb0e77 1116 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1117
1fd68434
RW		 1118 if (ahci_broken_system_poweroff(pdev)) {
1119 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1120 dev_info(&pdev->dev,
1121 "quirky BIOS, skipping spindown on poweroff\n");
1122 }
1123
9b10ae86
TH		 1124 if (ahci_broken_suspend(pdev)) {
1125 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1126 dev_warn(&pdev->dev,
1127 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1128 }
1129
5594639a
TH		 1130 if (ahci_broken_online(pdev)) {
1131 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1132 dev_info(&pdev->dev,
1133 "online status unreliable, applying workaround\n");
1134 }
1135
837f5f8f
TH		 1136 /* CAP.NP sometimes indicate the index of the last enabled
1137 * port, at other times, that of the last possible port, so
1138 * determining the maximum port number requires looking at
1139 * both CAP.NP and port_map.
1140 */
1141 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1142
1143 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1144 if (!host)
1145 return -ENOMEM;
4447d351
TH		 1146 host->private_data = hpriv;
1147
f3d7f23f 1148 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1149 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1150 else
1151 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1152
18f7ba4c
KCA		 1153 if (pi.flags & ATA_FLAG_EM)
1154 ahci_reset_em(host);
1155
4447d351 1156 for (i = 0; i < host->n_ports; i++) {
dab632e8 1157 struct ata_port *ap = host->ports[i];
4447d351 1158
cbcdd875
TH		 1159 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1160 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1161 0x100 + ap->port_no * 0x80, "port");
1162
18f7ba4c
KCA		 1163 /* set enclosure management message type */
1164 if (ap->flags & ATA_FLAG_EM)
008dbd61 1165 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1166
1167
dab632e8 1168 /* disabled/not-implemented port */
350756f6 1169 if (!(hpriv->port_map & (1 << i)))
dab632e8 1170 ap->ops = &ata_dummy_port_ops;
4447d351 1171 }
d447df14 1172
edc93052
TH		 1173 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1174 ahci_p5wdh_workaround(host);
1175
f80ae7e4
TH		 1176 /* apply gtf filter quirk */
1177 ahci_gtf_filter_workaround(host);
1178
4447d351
TH		 1179 /* initialize adapter */
1180 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1181 if (rc)
24dc5f33 1182 return rc;
1da177e4 1183
3303040d 1184 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1185 if (rc)
1186 return rc;
1da177e4 1187
781d6550 1188 ahci_pci_init_controller(host);
439fcaec 1189 ahci_pci_print_info(host);
1da177e4 1190
4447d351
TH		 1191 pci_set_master(pdev);
1192 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1193 &ahci_sht);
907f4678 1194}
1da177e4
LT		 1195
1196static int __init ahci_init(void)
1197{
b7887196 1198 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1199}
1200
1da177e4
LT		 1201static void __exit ahci_exit(void)
1202{
1203 pci_unregister_driver(&ahci_pci_driver);
1204}
1205
1206
1207MODULE_AUTHOR("Jeff Garzik");
1208MODULE_DESCRIPTION("AHCI SATA low-level driver");
1209MODULE_LICENSE("GPL");
1210MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1211MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1212
1213module_init(ahci_init);
1214module_exit(ahci_exit);
Linux kernel - Deliverables
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