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ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
66a7cbc3 63 board_ahci_nomsi,
67809f85 64 board_ahci_noncq,
441577ef 65 board_ahci_nosntf,
5f173107 66 board_ahci_yes_fbs,
1da177e4 67
441577ef
TH		 68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
83f2b963
TH		 70 board_ahci_mcp77,
71 board_ahci_mcp89,
441577ef
TH		 72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 81 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 82};
83
2dcb407e 84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 85static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
cb85696d
JL		 87static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 89static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
438ac6d5 91#ifdef CONFIG_PM
c1332875
TH		 92static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 94#endif
ad616ffb 95
fad16e7a
TH		 96static struct scsi_host_template ahci_sht = {
97 AHCI_SHT("ahci"),
98};
99
029cfd6b
TH		 100static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_vt8251_hardreset,
029cfd6b 103};
edc93052 104
029cfd6b
TH		 105static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
a1efdaba 107 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 108};
109
98ac62de 110static const struct ata_port_info ahci_port_info[] = {
441577ef 111 /* by features */
facb8fa6 112 [board_ahci] = {
1188c0d8 113 .flags = AHCI_FLAG_COMMON,
14bdef98 114 .pio_mask = ATA_PIO4,
469248ab 115 .udma_mask = ATA_UDMA6,
1da177e4
LT		 116 .port_ops = &ahci_ops,
117 },
facb8fa6 118 [board_ahci_ign_iferr] = {
441577ef 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 120 .flags = AHCI_FLAG_COMMON,
14bdef98 121 .pio_mask = ATA_PIO4,
469248ab 122 .udma_mask = ATA_UDMA6,
441577ef 123 .port_ops = &ahci_ops,
bf2af2a2 124 },
66a7cbc3
TH		 125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
67809f85
LK		 132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
facb8fa6 139 [board_ahci_nosntf] = {
441577ef 140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 141 .flags = AHCI_FLAG_COMMON,
14bdef98 142 .pio_mask = ATA_PIO4,
469248ab 143 .udma_mask = ATA_UDMA6,
41669553
TH		 144 .port_ops = &ahci_ops,
145 },
facb8fa6 146 [board_ahci_yes_fbs] = {
5f173107
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
441577ef 153 /* by chipsets */
facb8fa6 154 [board_ahci_mcp65] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ),
ae01b249 157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
facb8fa6 162 [board_ahci_mcp77] = {
83f2b963
TH		 163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
facb8fa6 169 [board_ahci_mcp89] = {
83f2b963 170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
469248ab 173 .udma_mask = ATA_UDMA6,
441577ef 174 .port_ops = &ahci_ops,
55a61604 175 },
facb8fa6 176 [board_ahci_mv] = {
417a1a6d 177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 180 .pio_mask = ATA_PIO4,
cd70c266
JG		 181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
facb8fa6 184 [board_ahci_sb600] = {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 192 },
facb8fa6 193 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
345347c5 198 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 199 },
facb8fa6 200 [board_ahci_vt8251] = {
441577ef 201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
441577ef 205 .port_ops = &ahci_vt8251_ops,
1b677afd 206 },
1da177e4
LT		 207};
208
3b7d697d 209static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 210 /* Intel */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
fe7fa31a 324
e34bb370
TH		 325 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
326 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
327 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 328 /* JMicron 362B and 362C have an AHCI function with IDE class code */
329 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
330 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 331
332 /* ATI */
c65ec1c2 333 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 334 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
335 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
336 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
337 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
338 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
339 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 340
e2dd90b1 341 /* AMD */
5deab536 342 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 343 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 344 /* AMD is using RAID class only for ahci controllers */
345 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
346 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
347
fe7fa31a 348 /* VIA */
54bb3a94 349 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 350 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 351
352 /* NVIDIA */
e297d99e
TH		 353 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
354 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
355 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
356 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
357 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
358 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
360 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 361 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
366 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
367 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
393 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
394 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
395 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
396 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
405 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
406 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
407 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
417 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
418 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
419 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
420 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
428 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
429 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
430 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
431 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
432 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 437
95916edd 438 /* SiS */
20e2de4a
TH		 439 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
440 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
441 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 442
318893e1
AR		 443 /* ST Microelectronics */
444 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
445
cd70c266
JG		 446 /* Marvell */
447 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 448 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 450 .class = PCI_CLASS_STORAGE_SATA_AHCI,
451 .class_mask = 0xffffff,
5f173107 452 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 454 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 455 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
456 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
457 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 459 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 461 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
462 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 463 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 464 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 465 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 466 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
467 .driver_data = board_ahci_yes_fbs },
69fd3157 468 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 469 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
471 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 472 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
473 .driver_data = board_ahci_yes_fbs },
cd70c266 474
c77a036b
MN		 475 /* Promise */
476 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 477 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 478
c9703765 479 /* Asmedia */
7b4f6eca
AC		 480 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
481 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
482 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
483 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 484
67809f85 485 /*
66a7cbc3
TH		 486 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
487 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 488 */
66a7cbc3 489 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
67809f85 490
7f9c9f8e
HD		 491 /* Enmotus */
492 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
493
415ae2b5
JG		 494 /* Generic, PCI class code for AHCI */
495 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 496 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 497
1da177e4
LT		 498 { } /* terminate list */
499};
500
501
502static struct pci_driver ahci_pci_driver = {
503 .name = DRV_NAME,
504 .id_table = ahci_pci_tbl,
505 .probe = ahci_init_one,
24dc5f33 506 .remove = ata_pci_remove_one,
438ac6d5 507#ifdef CONFIG_PM
c1332875 508 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 509 .resume = ahci_pci_device_resume,
510#endif
511};
1da177e4 512
365cfa1e
AV		 513#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
514static int marvell_enable;
515#else
516static int marvell_enable = 1;
517#endif
518module_param(marvell_enable, int, 0644);
519MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 520
1da177e4 521
365cfa1e
AV		 522static void ahci_pci_save_initial_config(struct pci_dev *pdev,
523 struct ahci_host_priv *hpriv)
524{
525 unsigned int force_port_map = 0;
526 unsigned int mask_port_map = 0;
67846b30 527
365cfa1e
AV		 528 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
529 dev_info(&pdev->dev, "JMB361 has only one port\n");
530 force_port_map = 1;
1da177e4
LT		 531 }
532
365cfa1e
AV		 533 /*
534 * Temporary Marvell 6145 hack: PATA port presence
535 * is asserted through the standard AHCI port
536 * presence register, as bit 4 (counting from 0)
d28f87aa 537 */
365cfa1e
AV		 538 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
539 if (pdev->device == 0x6121)
540 mask_port_map = 0x3;
541 else
542 mask_port_map = 0xf;
543 dev_info(&pdev->dev,
544 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
545 }
1da177e4 546
725c7b57 547 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 548}
549
365cfa1e 550static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 551{
365cfa1e 552 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 553
365cfa1e 554 ahci_reset_controller(host);
1da177e4 555
365cfa1e
AV		 556 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
557 struct ahci_host_priv *hpriv = host->private_data;
558 u16 tmp16;
d6ef3153 559
365cfa1e
AV		 560 /* configure PCS */
561 pci_read_config_word(pdev, 0x92, &tmp16);
562 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
563 tmp16 |= hpriv->port_map;
564 pci_write_config_word(pdev, 0x92, tmp16);
565 }
d6ef3153
SH		 566 }
567
1da177e4
LT		 568 return 0;
569}
570
365cfa1e 571static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 572{
365cfa1e
AV		 573 struct ahci_host_priv *hpriv = host->private_data;
574 struct pci_dev *pdev = to_pci_dev(host->dev);
575 void __iomem *port_mmio;
78cd52d0 576 u32 tmp;
365cfa1e 577 int mv;
78cd52d0 578
365cfa1e
AV		 579 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
580 if (pdev->device == 0x6121)
581 mv = 2;
582 else
583 mv = 4;
584 port_mmio = __ahci_port_base(host, mv);
78cd52d0 585
365cfa1e 586 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 587
365cfa1e
AV		 588 /* clear port IRQ */
589 tmp = readl(port_mmio + PORT_IRQ_STAT);
590 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
591 if (tmp)
592 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 593 }
594
365cfa1e 595 ahci_init_controller(host);
edc93052
TH		 596}
597
365cfa1e
AV		 598static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
599 unsigned long deadline)
d6ef3153 600{
365cfa1e 601 struct ata_port *ap = link->ap;
039ece38 602 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 603 bool online;
d6ef3153
SH		 604 int rc;
605
365cfa1e 606 DPRINTK("ENTER\n");
d6ef3153 607
365cfa1e 608 ahci_stop_engine(ap);
d6ef3153 609
365cfa1e
AV		 610 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
611 deadline, &online, NULL);
d6ef3153 612
039ece38 613 hpriv->start_engine(ap);
d6ef3153 614
365cfa1e 615 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 616
365cfa1e
AV		 617 /* vt8251 doesn't clear BSY on signature FIS reception,
618 * request follow-up softreset.
619 */
620 return online ? -EAGAIN : rc;
7d50b60b
TH		 621}
622
365cfa1e
AV		 623static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
624 unsigned long deadline)
7d50b60b 625{
365cfa1e 626 struct ata_port *ap = link->ap;
1c954a4d 627 struct ahci_port_priv *pp = ap->private_data;
039ece38 628 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 629 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
630 struct ata_taskfile tf;
631 bool online;
632 int rc;
7d50b60b 633
365cfa1e 634 ahci_stop_engine(ap);
028a2596 635
365cfa1e
AV		 636 /* clear D2H reception area to properly wait for D2H FIS */
637 ata_tf_init(link->device, &tf);
9bbb1b0e 638 tf.command = ATA_BUSY;
365cfa1e 639 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 640
365cfa1e
AV		 641 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
642 deadline, &online, NULL);
028a2596 643
039ece38 644 hpriv->start_engine(ap);
c1332875 645
365cfa1e
AV		 646 /* The pseudo configuration device on SIMG4726 attached to
647 * ASUS P5W-DH Deluxe doesn't send signature FIS after
648 * hardreset if no device is attached to the first downstream
649 * port && the pseudo device locks up on SRST w/ PMP==0. To
650 * work around this, wait for !BSY only briefly. If BSY isn't
651 * cleared, perform CLO and proceed to IDENTIFY (achieved by
652 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
653 *
654 * Wait for two seconds. Devices attached to downstream port
655 * which can't process the following IDENTIFY after this will
656 * have to be reset again. For most cases, this should
657 * suffice while making probing snappish enough.
658 */
659 if (online) {
660 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
661 ahci_check_ready);
662 if (rc)
663 ahci_kick_engine(ap);
c1332875 664 }
c1332875
TH		 665 return rc;
666}
667
365cfa1e 668#ifdef CONFIG_PM
c1332875
TH		 669static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
670{
0a86e1c8 671 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 672 struct ahci_host_priv *hpriv = host->private_data;
d8993349 673 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 674 u32 ctl;
675
9b10ae86
TH		 676 if (mesg.event & PM_EVENT_SUSPEND &&
677 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 678 dev_err(&pdev->dev,
679 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 680 return -EIO;
681 }
682
3a2d5b70 683 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 684 /* AHCI spec rev1.1 section 8.3.3:
685 * Software must disable interrupts prior to requesting a
686 * transition of the HBA to D3 state.
687 */
688 ctl = readl(mmio + HOST_CTL);
689 ctl &= ~HOST_IRQ_EN;
690 writel(ctl, mmio + HOST_CTL);
691 readl(mmio + HOST_CTL); /* flush */
692 }
693
694 return ata_pci_device_suspend(pdev, mesg);
695}
696
697static int ahci_pci_device_resume(struct pci_dev *pdev)
698{
0a86e1c8 699 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 700 int rc;
701
553c4aa6
TH		 702 rc = ata_pci_device_do_resume(pdev);
703 if (rc)
704 return rc;
c1332875 705
cb85696d
JL		 706 /* Apple BIOS helpfully mangles the registers on resume */
707 if (is_mcp89_apple(pdev))
708 ahci_mcp89_apple_enable(pdev);
709
c1332875 710 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 711 rc = ahci_pci_reset_controller(host);
c1332875
TH		 712 if (rc)
713 return rc;
714
781d6550 715 ahci_pci_init_controller(host);
c1332875
TH		 716 }
717
cca3974e 718 ata_host_resume(host);
c1332875
TH		 719
720 return 0;
721}
438ac6d5 722#endif
c1332875 723
4447d351 724static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 725{
1da177e4 726 int rc;
1da177e4 727
318893e1
AR		 728 /*
729 * If the device fixup already set the dma_mask to some non-standard
730 * value, don't extend it here. This happens on STA2X11, for example.
731 */
732 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
733 return 0;
734
1da177e4 735 if (using_dac &&
6a35528a
YH		 736 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
737 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 738 if (rc) {
284901a9 739 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 740 if (rc) {
a44fec1f
JP		 741 dev_err(&pdev->dev,
742 "64-bit DMA enable failed\n");
1da177e4
LT		 743 return rc;
744 }
745 }
1da177e4 746 } else {
284901a9 747 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 748 if (rc) {
a44fec1f 749 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 750 return rc;
751 }
284901a9 752 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 753 if (rc) {
a44fec1f
JP		 754 dev_err(&pdev->dev,
755 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 756 return rc;
757 }
758 }
1da177e4
LT		 759 return 0;
760}
761
439fcaec
AV		 762static void ahci_pci_print_info(struct ata_host *host)
763{
764 struct pci_dev *pdev = to_pci_dev(host->dev);
765 u16 cc;
766 const char *scc_s;
767
768 pci_read_config_word(pdev, 0x0a, &cc);
769 if (cc == PCI_CLASS_STORAGE_IDE)
770 scc_s = "IDE";
771 else if (cc == PCI_CLASS_STORAGE_SATA)
772 scc_s = "SATA";
773 else if (cc == PCI_CLASS_STORAGE_RAID)
774 scc_s = "RAID";
775 else
776 scc_s = "unknown";
777
778 ahci_print_info(host, scc_s);
779}
780
edc93052
TH		 781/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
782 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
783 * support PMP and the 4726 either directly exports the device
784 * attached to the first downstream port or acts as a hardware storage
785 * controller and emulate a single ATA device (can be RAID 0/1 or some
786 * other configuration).
787 *
788 * When there's no device attached to the first downstream port of the
789 * 4726, "Config Disk" appears, which is a pseudo ATA device to
790 * configure the 4726. However, ATA emulation of the device is very
791 * lame. It doesn't send signature D2H Reg FIS after the initial
792 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
793 *
794 * The following function works around the problem by always using
795 * hardreset on the port and not depending on receiving signature FIS
796 * afterward. If signature FIS isn't received soon, ATA class is
797 * assumed without follow-up softreset.
798 */
799static void ahci_p5wdh_workaround(struct ata_host *host)
800{
1bd06867 801 static const struct dmi_system_id sysids[] = {
edc93052
TH		 802 {
803 .ident = "P5W DH Deluxe",
804 .matches = {
805 DMI_MATCH(DMI_SYS_VENDOR,
806 "ASUSTEK COMPUTER INC"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
808 },
809 },
810 { }
811 };
812 struct pci_dev *pdev = to_pci_dev(host->dev);
813
814 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
815 dmi_check_system(sysids)) {
816 struct ata_port *ap = host->ports[1];
817
a44fec1f
JP		 818 dev_info(&pdev->dev,
819 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 820
821 ap->ops = &ahci_p5wdh_ops;
822 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
823 }
824}
825
cb85696d
JL		 826/*
827 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
828 * booting in BIOS compatibility mode. We restore the registers but not ID.
829 */
830static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
831{
832 u32 val;
833
834 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
835
836 pci_read_config_dword(pdev, 0xf8, &val);
837 val |= 1 << 0x1b;
838 /* the following changes the device ID, but appears not to affect function */
839 /* val = (val & ~0xf0000000) | 0x80000000; */
840 pci_write_config_dword(pdev, 0xf8, val);
841
842 pci_read_config_dword(pdev, 0x54c, &val);
843 val |= 1 << 0xc;
844 pci_write_config_dword(pdev, 0x54c, val);
845
846 pci_read_config_dword(pdev, 0x4a4, &val);
847 val &= 0xff;
848 val |= 0x01060100;
849 pci_write_config_dword(pdev, 0x4a4, val);
850
851 pci_read_config_dword(pdev, 0x54c, &val);
852 val &= ~(1 << 0xc);
853 pci_write_config_dword(pdev, 0x54c, val);
854
855 pci_read_config_dword(pdev, 0xf8, &val);
856 val &= ~(1 << 0x1b);
857 pci_write_config_dword(pdev, 0xf8, val);
858}
859
860static bool is_mcp89_apple(struct pci_dev *pdev)
861{
862 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
863 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
864 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
865 pdev->subsystem_device == 0xcb89;
866}
867
2fcad9d2
TH		 868/* only some SB600 ahci controllers can do 64bit DMA */
869static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 870{
871 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 872 /*
873 * The oldest version known to be broken is 0901 and
874 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 875 * Enable 64bit DMA on 1501 and anything newer.
876 *
03d783bf
TH		 877 * Please read bko#9412 for more info.
878 */
58a09b38
SH		 879 {
880 .ident = "ASUS M2A-VM",
881 .matches = {
882 DMI_MATCH(DMI_BOARD_VENDOR,
883 "ASUSTeK Computer INC."),
884 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
885 },
03d783bf 886 .driver_data = "20071026", /* yyyymmdd */
58a09b38 887 },
e65cc194
MN		 888 /*
889 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
890 * support 64bit DMA.
891 *
892 * BIOS versions earlier than 1.5 had the Manufacturer DMI
893 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
894 * This spelling mistake was fixed in BIOS version 1.5, so
895 * 1.5 and later have the Manufacturer as
896 * "MICRO-STAR INTERNATIONAL CO.,LTD".
897 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
898 *
899 * BIOS versions earlier than 1.9 had a Board Product Name
900 * DMI field of "MS-7376". This was changed to be
901 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
902 * match on DMI_BOARD_NAME of "MS-7376".
903 */
904 {
905 .ident = "MSI K9A2 Platinum",
906 .matches = {
907 DMI_MATCH(DMI_BOARD_VENDOR,
908 "MICRO-STAR INTER"),
909 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
910 },
911 },
ff0173c1
MN		 912 /*
913 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
914 * 64bit DMA.
915 *
916 * This board also had the typo mentioned above in the
917 * Manufacturer DMI field (fixed in BIOS version 1.5), so
918 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
919 */
920 {
921 .ident = "MSI K9AGM2",
922 .matches = {
923 DMI_MATCH(DMI_BOARD_VENDOR,
924 "MICRO-STAR INTER"),
925 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
926 },
927 },
3c4aa91f
MN		 928 /*
929 * All BIOS versions for the Asus M3A support 64bit DMA.
930 * (all release versions from 0301 to 1206 were tested)
931 */
932 {
933 .ident = "ASUS M3A",
934 .matches = {
935 DMI_MATCH(DMI_BOARD_VENDOR,
936 "ASUSTeK Computer INC."),
937 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
938 },
939 },
58a09b38
SH		 940 { }
941 };
03d783bf 942 const struct dmi_system_id *match;
2fcad9d2
TH		 943 int year, month, date;
944 char buf[9];
58a09b38 945
03d783bf 946 match = dmi_first_match(sysids);
58a09b38 947 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 948 !match)
58a09b38
SH		 949 return false;
950
e65cc194
MN		 951 if (!match->driver_data)
952 goto enable_64bit;
953
2fcad9d2
TH		 954 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
955 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 956
e65cc194
MN		 957 if (strcmp(buf, match->driver_data) >= 0)
958 goto enable_64bit;
959 else {
a44fec1f
JP		 960 dev_warn(&pdev->dev,
961 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
962 match->ident);
2fcad9d2
TH		 963 return false;
964 }
e65cc194
MN		 965
966enable_64bit:
a44fec1f 967 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 968 return true;
58a09b38
SH		 969}
970
1fd68434
RW		 971static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
972{
973 static const struct dmi_system_id broken_systems[] = {
974 {
975 .ident = "HP Compaq nx6310",
976 .matches = {
977 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
978 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
979 },
980 /* PCI slot number of the controller */
981 .driver_data = (void *)0x1FUL,
982 },
d2f9c061
MR		 983 {
984 .ident = "HP Compaq 6720s",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
988 },
989 /* PCI slot number of the controller */
990 .driver_data = (void *)0x1FUL,
991 },
1fd68434
RW		 992
993 { } /* terminate list */
994 };
995 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
996
997 if (dmi) {
998 unsigned long slot = (unsigned long)dmi->driver_data;
999 /* apply the quirk only to on-board controllers */
1000 return slot == PCI_SLOT(pdev->devfn);
1001 }
1002
1003 return false;
1004}
1005
9b10ae86
TH		 1006static bool ahci_broken_suspend(struct pci_dev *pdev)
1007{
1008 static const struct dmi_system_id sysids[] = {
1009 /*
1010 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1011 * to the harddisk doesn't become online after
1012 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1013 *
1014 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1015 *
1016 * Use dates instead of versions to match as HP is
1017 * apparently recycling both product and version
1018 * strings.
1019 *
1020 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1021 */
1022 {
1023 .ident = "dv4",
1024 .matches = {
1025 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1026 DMI_MATCH(DMI_PRODUCT_NAME,
1027 "HP Pavilion dv4 Notebook PC"),
1028 },
9deb3431 1029 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1030 },
1031 {
1032 .ident = "dv5",
1033 .matches = {
1034 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1035 DMI_MATCH(DMI_PRODUCT_NAME,
1036 "HP Pavilion dv5 Notebook PC"),
1037 },
9deb3431 1038 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1039 },
1040 {
1041 .ident = "dv6",
1042 .matches = {
1043 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1044 DMI_MATCH(DMI_PRODUCT_NAME,
1045 "HP Pavilion dv6 Notebook PC"),
1046 },
9deb3431 1047 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1048 },
1049 {
1050 .ident = "HDX18",
1051 .matches = {
1052 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1053 DMI_MATCH(DMI_PRODUCT_NAME,
1054 "HP HDX18 Notebook PC"),
1055 },
9deb3431 1056 .driver_data = "20090430", /* F.23 */
9b10ae86 1057 },
cedc9bf9
TH		 1058 /*
1059 * Acer eMachines G725 has the same problem. BIOS
1060 * V1.03 is known to be broken. V3.04 is known to
25985edc 1061 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1062 * that we don't have much idea about. For now,
1063 * blacklist anything older than V3.04.
9deb3431
TH		 1064 *
1065 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1066 */
1067 {
1068 .ident = "G725",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1072 },
9deb3431 1073 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1074 },
9b10ae86
TH		 1075 { } /* terminate list */
1076 };
1077 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1078 int year, month, date;
1079 char buf[9];
9b10ae86
TH		 1080
1081 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1082 return false;
1083
9deb3431
TH		 1084 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1085 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1086
9deb3431 1087 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1088}
1089
5594639a
TH		 1090static bool ahci_broken_online(struct pci_dev *pdev)
1091{
1092#define ENCODE_BUSDEVFN(bus, slot, func) \
1093 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1094 static const struct dmi_system_id sysids[] = {
1095 /*
1096 * There are several gigabyte boards which use
1097 * SIMG5723s configured as hardware RAID. Certain
1098 * 5723 firmware revisions shipped there keep the link
1099 * online but fail to answer properly to SRST or
1100 * IDENTIFY when no device is attached downstream
1101 * causing libata to retry quite a few times leading
1102 * to excessive detection delay.
1103 *
1104 * As these firmwares respond to the second reset try
1105 * with invalid device signature, considering unknown
1106 * sig as offline works around the problem acceptably.
1107 */
1108 {
1109 .ident = "EP45-DQ6",
1110 .matches = {
1111 DMI_MATCH(DMI_BOARD_VENDOR,
1112 "Gigabyte Technology Co., Ltd."),
1113 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1114 },
1115 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1116 },
1117 {
1118 .ident = "EP45-DS5",
1119 .matches = {
1120 DMI_MATCH(DMI_BOARD_VENDOR,
1121 "Gigabyte Technology Co., Ltd."),
1122 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1123 },
1124 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1125 },
1126 { } /* terminate list */
1127 };
1128#undef ENCODE_BUSDEVFN
1129 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1130 unsigned int val;
1131
1132 if (!dmi)
1133 return false;
1134
1135 val = (unsigned long)dmi->driver_data;
1136
1137 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1138}
1139
0cf4a7d6
JP		 1140static bool ahci_broken_devslp(struct pci_dev *pdev)
1141{
1142 /* device with broken DEVSLP but still showing SDS capability */
1143 static const struct pci_device_id ids[] = {
1144 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1145 {}
1146 };
1147
1148 return pci_match_id(ids, pdev);
1149}
1150
8e513217 1151#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1152static void ahci_gtf_filter_workaround(struct ata_host *host)
1153{
1154 static const struct dmi_system_id sysids[] = {
1155 /*
1156 * Aspire 3810T issues a bunch of SATA enable commands
1157 * via _GTF including an invalid one and one which is
1158 * rejected by the device. Among the successful ones
1159 * is FPDMA non-zero offset enable which when enabled
1160 * only on the drive side leads to NCQ command
1161 * failures. Filter it out.
1162 */
1163 {
1164 .ident = "Aspire 3810T",
1165 .matches = {
1166 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1167 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1168 },
1169 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1170 },
1171 { }
1172 };
1173 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1174 unsigned int filter;
1175 int i;
1176
1177 if (!dmi)
1178 return;
1179
1180 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1181 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1182 filter, dmi->ident);
f80ae7e4
TH		 1183
1184 for (i = 0; i < host->n_ports; i++) {
1185 struct ata_port *ap = host->ports[i];
1186 struct ata_link *link;
1187 struct ata_device *dev;
1188
1189 ata_for_each_link(link, ap, EDGE)
1190 ata_for_each_dev(dev, link, ALL)
1191 dev->gtf_filter |= filter;
1192 }
1193}
8e513217
MT		 1194#else
1195static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1196{}
1197#endif
f80ae7e4 1198
e1ba8459 1199static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1200 struct ahci_host_priv *hpriv)
5ca72c4f 1201{
ccf8f53c 1202 int rc, nvec;
5ca72c4f 1203
7b92b4f6
AG		 1204 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1205 goto intx;
1206
fc061d96
AG		 1207 nvec = pci_msi_vec_count(pdev);
1208 if (nvec < 0)
7b92b4f6
AG		 1209 goto intx;
1210
1211 /*
1212 * If number of MSIs is less than number of ports then Sharing Last
1213 * Message mode could be enforced. In this case assume that advantage
1214 * of multipe MSIs is negated and use single MSI mode instead.
1215 */
fc061d96 1216 if (nvec < n_ports)
7b92b4f6
AG		 1217 goto single_msi;
1218
ccf8f53c
AG		 1219 rc = pci_enable_msi_exact(pdev, nvec);
1220 if (rc == -ENOSPC)
fc40363b 1221 goto single_msi;
ccf8f53c 1222 else if (rc < 0)
fc061d96 1223 goto intx;
5ca72c4f 1224
ab0f9e78
AG		 1225 /* fallback to single MSI mode if the controller enforced MRSM mode */
1226 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1227 pci_disable_msi(pdev);
1228 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1229 goto single_msi;
1230 }
1231
c3ebd6a9
AG		 1232 if (nvec > 1)
1233 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1234
7b92b4f6
AG		 1235 return nvec;
1236
1237single_msi:
fc061d96 1238 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1239 goto intx;
1240 return 1;
1241
1242intx:
5ca72c4f
AG		 1243 pci_intx(pdev, 1);
1244 return 0;
1245}
1246
24dc5f33 1247static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1248{
e297d99e
TH		 1249 unsigned int board_id = ent->driver_data;
1250 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1251 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1252 struct device *dev = &pdev->dev;
1da177e4 1253 struct ahci_host_priv *hpriv;
4447d351 1254 struct ata_host *host;
c3ebd6a9 1255 int n_ports, i, rc;
318893e1 1256 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1257
1258 VPRINTK("ENTER\n");
1259
b429dd59 1260 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1261
06296a1e 1262 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1263
5b66c829
AC		 1264 /* The AHCI driver can only drive the SATA ports, the PATA driver
1265 can drive them all so if both drivers are selected make sure
1266 AHCI stays out of the way */
1267 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1268 return -ENODEV;
1269
cb85696d
JL		 1270 /* Apple BIOS on MCP89 prevents us using AHCI */
1271 if (is_mcp89_apple(pdev))
1272 ahci_mcp89_apple_enable(pdev);
c6353b45 1273
7a02267e
MN		 1274 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1275 * At the moment, we can only use the AHCI mode. Let the users know
1276 * that for SAS drives they're out of luck.
1277 */
1278 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1279 dev_info(&pdev->dev,
1280 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1281
7f9c9f8e 1282 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1283 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1284 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1285 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1286 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1287
e6b7e41c
CL		 1288 /*
1289 * The JMicron chip 361/363 contains one SATA controller and one
1290 * PATA controller,for powering on these both controllers, we must
1291 * follow the sequence one by one, otherwise one of them can not be
1292 * powered on successfully, so here we disable the async suspend
1293 * method for these chips.
1294 */
1295 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1296 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1297 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1298 device_disable_async_suspend(&pdev->dev);
1299
4447d351 1300 /* acquire resources */
24dc5f33 1301 rc = pcim_enable_device(pdev);
1da177e4
LT		 1302 if (rc)
1303 return rc;
1304
c4f7792c
TH		 1305 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1306 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1307 u8 map;
1308
1309 /* ICH6s share the same PCI ID for both piix and ahci
1310 * modes. Enabling ahci mode while MAP indicates
1311 * combined mode is a bad idea. Yield to ata_piix.
1312 */
1313 pci_read_config_byte(pdev, ICH_MAP, &map);
1314 if (map & 0x3) {
a44fec1f
JP		 1315 dev_info(&pdev->dev,
1316 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1317 return -ENODEV;
1318 }
1319 }
1320
6fec8871
PB		 1321 /* AHCI controllers often implement SFF compatible interface.
1322 * Grab all PCI BARs just in case.
1323 */
1324 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1325 if (rc == -EBUSY)
1326 pcim_pin_device(pdev);
1327 if (rc)
1328 return rc;
1329
24dc5f33
TH		 1330 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1331 if (!hpriv)
1332 return -ENOMEM;
417a1a6d
TH		 1333 hpriv->flags |= (unsigned long)pi.private_data;
1334
e297d99e
TH		 1335 /* MCP65 revision A1 and A2 can't do MSI */
1336 if (board_id == board_ahci_mcp65 &&
1337 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1338 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1339
e427fe04
SH		 1340 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1341 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1342 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1343
2fcad9d2
TH		 1344 /* only some SB600s can do 64bit DMA */
1345 if (ahci_sb600_enable_64bit(pdev))
1346 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1347
318893e1 1348 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1349
0cf4a7d6
JP		 1350 /* must set flag prior to save config in order to take effect */
1351 if (ahci_broken_devslp(pdev))
1352 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1353
4447d351 1354 /* save initial config */
394d6e53 1355 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1356
4447d351 1357 /* prepare host */
453d3131
RH		 1358 if (hpriv->cap & HOST_CAP_NCQ) {
1359 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1360 /*
1361 * Auto-activate optimization is supposed to be
1362 * supported on all AHCI controllers indicating NCQ
1363 * capability, but it seems to be broken on some
1364 * chipsets including NVIDIAs.
1365 */
1366 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1367 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1368
1369 /*
1370 * All AHCI controllers should be forward-compatible
1371 * with the new auxiliary field. This code should be
1372 * conditionalized if any buggy AHCI controllers are
1373 * encountered.
1374 */
1375 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1376 }
1da177e4 1377
7d50b60b
TH		 1378 if (hpriv->cap & HOST_CAP_PMP)
1379 pi.flags |= ATA_FLAG_PMP;
1380
0cbb0e77 1381 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1382
1fd68434
RW		 1383 if (ahci_broken_system_poweroff(pdev)) {
1384 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1385 dev_info(&pdev->dev,
1386 "quirky BIOS, skipping spindown on poweroff\n");
1387 }
1388
9b10ae86
TH		 1389 if (ahci_broken_suspend(pdev)) {
1390 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1391 dev_warn(&pdev->dev,
1392 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1393 }
1394
5594639a
TH		 1395 if (ahci_broken_online(pdev)) {
1396 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1397 dev_info(&pdev->dev,
1398 "online status unreliable, applying workaround\n");
1399 }
1400
837f5f8f
TH		 1401 /* CAP.NP sometimes indicate the index of the last enabled
1402 * port, at other times, that of the last possible port, so
1403 * determining the maximum port number requires looking at
1404 * both CAP.NP and port_map.
1405 */
1406 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1407
c3ebd6a9 1408 ahci_init_interrupts(pdev, n_ports, hpriv);
7b92b4f6 1409
837f5f8f 1410 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1411 if (!host)
1412 return -ENOMEM;
4447d351
TH		 1413 host->private_data = hpriv;
1414
f3d7f23f 1415 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1416 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1417 else
d2782d96 1418 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1419
18f7ba4c
KCA		 1420 if (pi.flags & ATA_FLAG_EM)
1421 ahci_reset_em(host);
1422
4447d351 1423 for (i = 0; i < host->n_ports; i++) {
dab632e8 1424 struct ata_port *ap = host->ports[i];
4447d351 1425
318893e1
AR		 1426 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1427 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1428 0x100 + ap->port_no * 0x80, "port");
1429
18f7ba4c
KCA		 1430 /* set enclosure management message type */
1431 if (ap->flags & ATA_FLAG_EM)
008dbd61 1432 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1433
1434
dab632e8 1435 /* disabled/not-implemented port */
350756f6 1436 if (!(hpriv->port_map & (1 << i)))
dab632e8 1437 ap->ops = &ata_dummy_port_ops;
4447d351 1438 }
d447df14 1439
edc93052
TH		 1440 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1441 ahci_p5wdh_workaround(host);
1442
f80ae7e4
TH		 1443 /* apply gtf filter quirk */
1444 ahci_gtf_filter_workaround(host);
1445
4447d351
TH		 1446 /* initialize adapter */
1447 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1448 if (rc)
24dc5f33 1449 return rc;
1da177e4 1450
3303040d 1451 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1452 if (rc)
1453 return rc;
1da177e4 1454
781d6550 1455 ahci_pci_init_controller(host);
439fcaec 1456 ahci_pci_print_info(host);
1da177e4 1457
4447d351 1458 pci_set_master(pdev);
5ca72c4f 1459
d1028e2f 1460 return ahci_host_activate(host, pdev->irq, &ahci_sht);
907f4678 1461}
1da177e4 1462
2fc75da0 1463module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1464
1465MODULE_AUTHOR("Jeff Garzik");
1466MODULE_DESCRIPTION("AHCI SATA low-level driver");
1467MODULE_LICENSE("GPL");
1468MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1469MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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