projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libata-pmp-prep: implement sata_async_notification()
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
1da177e4 44#include <scsi/scsi_host.h>
193515d5 45#include <scsi/scsi_cmnd.h>
1da177e4 46#include <linux/libata.h>
1da177e4
LT		 47
48#define DRV_NAME "ahci"
cd70c266 49#define DRV_VERSION "2.3"
1da177e4
LT		 50
51
52enum {
53 AHCI_PCI_BAR = 5,
648a88be 54 AHCI_MAX_PORTS = 32,
1da177e4
LT		 55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 57 AHCI_USE_CLUSTERING = 1,
12fad3f9 58 AHCI_MAX_CMDS = 32,
dd410ff1 59 AHCI_CMD_SZ = 32,
12fad3f9 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 61 AHCI_RX_FIS_SZ = 256,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
4b10e559 71 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
7a234aff
TH		 80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82 board_ahci_sb600 = 3,
83 board_ahci_mv = 4,
1da177e4
LT		 84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
0be0aa98 98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 101 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 102 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 103 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 104
105 /* registers for each SATA port */
106 PORT_LST_ADDR = 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT = 0x10, /* interrupt status */
111 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
112 PORT_CMD = 0x18, /* port command */
113 PORT_TFDATA = 0x20, /* taskfile data */
114 PORT_SIG = 0x24, /* device TF signature */
115 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 120 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 121
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
131
132 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
141
78cd52d0
TH		 142 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
143 PORT_IRQ_IF_ERR |
144 PORT_IRQ_CONNECT |
4296971d 145 PORT_IRQ_PHYRDY |
78cd52d0
TH		 146 PORT_IRQ_UNK_FIS,
147 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
148 PORT_IRQ_TF_ERR |
149 PORT_IRQ_HBUS_DATA_ERR,
150 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
151 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
152 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 153
154 /* PORT_CMD bits */
02eaa666 155 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 156 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 159 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 160 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
162 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
163
0be0aa98 164 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 165 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 168
bf2af2a2 169 /* ap->flags bits */
4aeb0e32
TH		 170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
55a61604 172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
c7a42156 173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
cd70c266
JG		 174 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
175 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
a7384925 176 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
1188c0d8
TH		 177
178 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2 180 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
0c88758b 181 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
1da177e4
LT		 182};
183
184struct ahci_cmd_hdr {
185 u32 opts;
186 u32 status;
187 u32 tbl_addr;
188 u32 tbl_addr_hi;
189 u32 reserved[4];
190};
191
192struct ahci_sg {
193 u32 addr;
194 u32 addr_hi;
195 u32 reserved;
196 u32 flags_size;
197};
198
199struct ahci_host_priv {
d447df14
TH		 200 u32 cap; /* cap to use */
201 u32 port_map; /* port map to use */
202 u32 saved_cap; /* saved initial cap */
203 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 204};
205
206struct ahci_port_priv {
207 struct ahci_cmd_hdr *cmd_slot;
208 dma_addr_t cmd_slot_dma;
209 void *cmd_tbl;
210 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 211 void *rx_fis;
212 dma_addr_t rx_fis_dma;
0291f95f 213 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 214 unsigned int ncq_saw_d2h:1;
215 unsigned int ncq_saw_dmas:1;
afb2d552 216 unsigned int ncq_saw_sdb:1;
a7384925 217 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 218};
219
da3dbb17
TH		 220static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
221static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4 222static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 223static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 224static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 225static int ahci_port_start(struct ata_port *ap);
226static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 227static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
228static void ahci_qc_prep(struct ata_queued_cmd *qc);
229static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 230static void ahci_freeze(struct ata_port *ap);
231static void ahci_thaw(struct ata_port *ap);
232static void ahci_error_handler(struct ata_port *ap);
ad616ffb 233static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 234static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 235static int ahci_port_resume(struct ata_port *ap);
dab632e8
JG		 236static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
237static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
238 u32 opts);
438ac6d5 239#ifdef CONFIG_PM
c1332875 240static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 241static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
242static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 243#endif
1da177e4 244
193515d5 245static struct scsi_host_template ahci_sht = {
1da177e4
LT		 246 .module = THIS_MODULE,
247 .name = DRV_NAME,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 250 .change_queue_depth = ata_scsi_change_queue_depth,
251 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 252 .this_id = ATA_SHT_THIS_ID,
253 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = AHCI_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = AHCI_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
ccf68c34 260 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 261 .bios_param = ata_std_bios_param,
1da177e4
LT		 262};
263
057ace5e 264static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 265 .check_status = ahci_check_status,
266 .check_altstatus = ahci_check_status,
1da177e4
LT		 267 .dev_select = ata_noop_dev_select,
268
269 .tf_read = ahci_tf_read,
270
31cc23b3 271 .qc_defer = ata_std_qc_defer,
1da177e4
LT		 272 .qc_prep = ahci_qc_prep,
273 .qc_issue = ahci_qc_issue,
274
1da177e4
LT		 275 .irq_clear = ahci_irq_clear,
276
277 .scr_read = ahci_scr_read,
278 .scr_write = ahci_scr_write,
279
78cd52d0
TH		 280 .freeze = ahci_freeze,
281 .thaw = ahci_thaw,
282
283 .error_handler = ahci_error_handler,
284 .post_internal_cmd = ahci_post_internal_cmd,
285
438ac6d5 286#ifdef CONFIG_PM
c1332875
TH		 287 .port_suspend = ahci_port_suspend,
288 .port_resume = ahci_port_resume,
438ac6d5 289#endif
c1332875 290
1da177e4
LT		 291 .port_start = ahci_port_start,
292 .port_stop = ahci_port_stop,
1da177e4
LT		 293};
294
ad616ffb 295static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 296 .check_status = ahci_check_status,
297 .check_altstatus = ahci_check_status,
298 .dev_select = ata_noop_dev_select,
299
300 .tf_read = ahci_tf_read,
301
31cc23b3 302 .qc_defer = ata_std_qc_defer,
ad616ffb
TH		 303 .qc_prep = ahci_qc_prep,
304 .qc_issue = ahci_qc_issue,
305
ad616ffb
TH		 306 .irq_clear = ahci_irq_clear,
307
308 .scr_read = ahci_scr_read,
309 .scr_write = ahci_scr_write,
310
311 .freeze = ahci_freeze,
312 .thaw = ahci_thaw,
313
314 .error_handler = ahci_vt8251_error_handler,
315 .post_internal_cmd = ahci_post_internal_cmd,
316
438ac6d5 317#ifdef CONFIG_PM
ad616ffb
TH		 318 .port_suspend = ahci_port_suspend,
319 .port_resume = ahci_port_resume,
438ac6d5 320#endif
ad616ffb
TH		 321
322 .port_start = ahci_port_start,
323 .port_stop = ahci_port_stop,
324};
325
98ac62de 326static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 327 /* board_ahci */
328 {
1188c0d8 329 .flags = AHCI_FLAG_COMMON,
0c88758b 330 .link_flags = AHCI_LFLAG_COMMON,
7da79312 331 .pio_mask = 0x1f, /* pio0-4 */
469248ab 332 .udma_mask = ATA_UDMA6,
1da177e4
LT		 333 .port_ops = &ahci_ops,
334 },
bf2af2a2
BJ		 335 /* board_ahci_vt8251 */
336 {
0c88758b
TH		 337 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
338 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
bf2af2a2 339 .pio_mask = 0x1f, /* pio0-4 */
469248ab 340 .udma_mask = ATA_UDMA6,
ad616ffb 341 .port_ops = &ahci_vt8251_ops,
bf2af2a2 342 },
41669553
TH		 343 /* board_ahci_ign_iferr */
344 {
1188c0d8 345 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
0c88758b 346 .link_flags = AHCI_LFLAG_COMMON,
41669553 347 .pio_mask = 0x1f, /* pio0-4 */
469248ab 348 .udma_mask = ATA_UDMA6,
41669553
TH		 349 .port_ops = &ahci_ops,
350 },
55a61604
CH		 351 /* board_ahci_sb600 */
352 {
1188c0d8 353 .flags = AHCI_FLAG_COMMON |
c7a42156
TH		 354 AHCI_FLAG_IGN_SERR_INTERNAL |
355 AHCI_FLAG_32BIT_ONLY,
0c88758b 356 .link_flags = AHCI_LFLAG_COMMON,
55a61604 357 .pio_mask = 0x1f, /* pio0-4 */
469248ab 358 .udma_mask = ATA_UDMA6,
55a61604
CH		 359 .port_ops = &ahci_ops,
360 },
cd70c266
JG		 361 /* board_ahci_mv */
362 {
363 .sht = &ahci_sht,
364 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
365 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
7a234aff
TH		 366 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
367 AHCI_FLAG_MV_PATA,
0c88758b 368 .link_flags = AHCI_LFLAG_COMMON,
cd70c266
JG		 369 .pio_mask = 0x1f, /* pio0-4 */
370 .udma_mask = ATA_UDMA6,
371 .port_ops = &ahci_ops,
372 },
1da177e4
LT		 373};
374
3b7d697d 375static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 376 /* Intel */
54bb3a94
JG		 377 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
378 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
379 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
380 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
381 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 382 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 383 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
384 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
385 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
386 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 387 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
388 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
389 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
390 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
391 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
392 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
393 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
395 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
396 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
397 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
398 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
399 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
400 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
401 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
402 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 404 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
405 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
fe7fa31a 406
e34bb370
TH		 407 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
408 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
409 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 410
411 /* ATI */
c65ec1c2 412 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
c69c0892 413 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
418 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
fe7fa31a
JG		 419
420 /* VIA */
54bb3a94 421 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 422 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 423
424 /* NVIDIA */
54bb3a94
JG		 425 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 429 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 437 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 445 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
447 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
fe7fa31a 469
95916edd 470 /* SiS */
54bb3a94
JG		 471 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
472 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
473 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 474
cd70c266
JG		 475 /* Marvell */
476 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
477
415ae2b5
JG		 478 /* Generic, PCI class code for AHCI */
479 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 480 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 481
1da177e4
LT		 482 { } /* terminate list */
483};
484
485
486static struct pci_driver ahci_pci_driver = {
487 .name = DRV_NAME,
488 .id_table = ahci_pci_tbl,
489 .probe = ahci_init_one,
24dc5f33 490 .remove = ata_pci_remove_one,
438ac6d5 491#ifdef CONFIG_PM
c1332875
TH		 492 .suspend = ahci_pci_device_suspend,
493 .resume = ahci_pci_device_resume,
438ac6d5 494#endif
1da177e4
LT		 495};
496
497
98fa4b60
TH		 498static inline int ahci_nr_ports(u32 cap)
499{
500 return (cap & 0x1f) + 1;
501}
502
dab632e8
JG		 503static inline void __iomem *__ahci_port_base(struct ata_host *host,
504 unsigned int port_no)
1da177e4 505{
dab632e8 506 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 507
dab632e8
JG		 508 return mmio + 0x100 + (port_no * 0x80);
509}
510
511static inline void __iomem *ahci_port_base(struct ata_port *ap)
512{
513 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 514}
515
d447df14
TH		 516/**
517 * ahci_save_initial_config - Save and fixup initial config values
4447d351
TH		 518 * @pdev: target PCI device
519 * @pi: associated ATA port info
520 * @hpriv: host private area to store config values
d447df14
TH		 521 *
522 * Some registers containing configuration info might be setup by
523 * BIOS and might be cleared on reset. This function saves the
524 * initial values of those registers into @hpriv such that they
525 * can be restored after controller reset.
526 *
527 * If inconsistent, config values are fixed up by this function.
528 *
529 * LOCKING:
530 * None.
531 */
4447d351
TH		 532static void ahci_save_initial_config(struct pci_dev *pdev,
533 const struct ata_port_info *pi,
534 struct ahci_host_priv *hpriv)
d447df14 535{
4447d351 536 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 537 u32 cap, port_map;
17199b18 538 int i;
d447df14
TH		 539
540 /* Values prefixed with saved_ are written back to host after
541 * reset. Values without are used for driver operation.
542 */
543 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
544 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
545
274c1fde 546 /* some chips have errata preventing 64bit use */
c7a42156
TH		 547 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
548 dev_printk(KERN_INFO, &pdev->dev,
549 "controller can't do 64bit DMA, forcing 32bit\n");
550 cap &= ~HOST_CAP_64;
551 }
552
274c1fde
TH		 553 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
554 dev_printk(KERN_INFO, &pdev->dev,
555 "controller can't do NCQ, turning off CAP_NCQ\n");
556 cap &= ~HOST_CAP_NCQ;
557 }
558
cd70c266
JG		 559 /*
560 * Temporary Marvell 6145 hack: PATA port presence
561 * is asserted through the standard AHCI port
562 * presence register, as bit 4 (counting from 0)
563 */
564 if (pi->flags & AHCI_FLAG_MV_PATA) {
565 dev_printk(KERN_ERR, &pdev->dev,
566 "MV_AHCI HACK: port_map %x -> %x\n",
567 hpriv->port_map,
568 hpriv->port_map & 0xf);
569
570 port_map &= 0xf;
571 }
572
17199b18 573 /* cross check port_map and cap.n_ports */
7a234aff 574 if (port_map) {
17199b18
TH		 575 u32 tmp_port_map = port_map;
576 int n_ports = ahci_nr_ports(cap);
577
578 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
579 if (tmp_port_map & (1 << i)) {
580 n_ports--;
581 tmp_port_map &= ~(1 << i);
582 }
583 }
584
7a234aff
TH		 585 /* If n_ports and port_map are inconsistent, whine and
586 * clear port_map and let it be generated from n_ports.
17199b18 587 */
7a234aff 588 if (n_ports || tmp_port_map) {
4447d351 589 dev_printk(KERN_WARNING, &pdev->dev,
17199b18 590 "nr_ports (%u) and implemented port map "
7a234aff 591 "(0x%x) don't match, using nr_ports\n",
17199b18 592 ahci_nr_ports(cap), port_map);
7a234aff
TH		 593 port_map = 0;
594 }
595 }
596
597 /* fabricate port_map from cap.nr_ports */
598 if (!port_map) {
17199b18 599 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 600 dev_printk(KERN_WARNING, &pdev->dev,
601 "forcing PORTS_IMPL to 0x%x\n", port_map);
602
603 /* write the fixed up value to the PI register */
604 hpriv->saved_port_map = port_map;
17199b18
TH		 605 }
606
d447df14
TH		 607 /* record values to use during operation */
608 hpriv->cap = cap;
609 hpriv->port_map = port_map;
610}
611
612/**
613 * ahci_restore_initial_config - Restore initial config
4447d351 614 * @host: target ATA host
d447df14
TH		 615 *
616 * Restore initial config stored by ahci_save_initial_config().
617 *
618 * LOCKING:
619 * None.
620 */
4447d351 621static void ahci_restore_initial_config(struct ata_host *host)
d447df14 622{
4447d351
TH		 623 struct ahci_host_priv *hpriv = host->private_data;
624 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
625
d447df14
TH		 626 writel(hpriv->saved_cap, mmio + HOST_CAP);
627 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
628 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
629}
630
203ef6c4 631static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 632{
203ef6c4
TH		 633 static const int offset[] = {
634 [SCR_STATUS] = PORT_SCR_STAT,
635 [SCR_CONTROL] = PORT_SCR_CTL,
636 [SCR_ERROR] = PORT_SCR_ERR,
637 [SCR_ACTIVE] = PORT_SCR_ACT,
638 [SCR_NOTIFICATION] = PORT_SCR_NTF,
639 };
640 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 641
203ef6c4
TH		 642 if (sc_reg < ARRAY_SIZE(offset) &&
643 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
644 return offset[sc_reg];
da3dbb17 645 return 0;
1da177e4
LT		 646}
647
203ef6c4 648static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 649{
203ef6c4
TH		 650 void __iomem *port_mmio = ahci_port_base(ap);
651 int offset = ahci_scr_offset(ap, sc_reg);
652
653 if (offset) {
654 *val = readl(port_mmio + offset);
655 return 0;
1da177e4 656 }
203ef6c4
TH		 657 return -EINVAL;
658}
1da177e4 659
203ef6c4
TH		 660static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
661{
662 void __iomem *port_mmio = ahci_port_base(ap);
663 int offset = ahci_scr_offset(ap, sc_reg);
664
665 if (offset) {
666 writel(val, port_mmio + offset);
667 return 0;
668 }
669 return -EINVAL;
1da177e4
LT		 670}
671
4447d351 672static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 673{
4447d351 674 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 675 u32 tmp;
676
d8fcd116 677 /* start DMA */
9f592056 678 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 679 tmp |= PORT_CMD_START;
680 writel(tmp, port_mmio + PORT_CMD);
681 readl(port_mmio + PORT_CMD); /* flush */
682}
683
4447d351 684static int ahci_stop_engine(struct ata_port *ap)
254950cd 685{
4447d351 686 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 687 u32 tmp;
688
689 tmp = readl(port_mmio + PORT_CMD);
690
d8fcd116 691 /* check if the HBA is idle */
254950cd
TH		 692 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
693 return 0;
694
d8fcd116 695 /* setting HBA to idle */
254950cd
TH		 696 tmp &= ~PORT_CMD_START;
697 writel(tmp, port_mmio + PORT_CMD);
698
d8fcd116 699 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 700 tmp = ata_wait_register(port_mmio + PORT_CMD,
701 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 702 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 703 return -EIO;
704
705 return 0;
706}
707
4447d351 708static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 709{
4447d351
TH		 710 void __iomem *port_mmio = ahci_port_base(ap);
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 713 u32 tmp;
714
715 /* set FIS registers */
4447d351
TH		 716 if (hpriv->cap & HOST_CAP_64)
717 writel((pp->cmd_slot_dma >> 16) >> 16,
718 port_mmio + PORT_LST_ADDR_HI);
719 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 720
4447d351
TH		 721 if (hpriv->cap & HOST_CAP_64)
722 writel((pp->rx_fis_dma >> 16) >> 16,
723 port_mmio + PORT_FIS_ADDR_HI);
724 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 725
726 /* enable FIS reception */
727 tmp = readl(port_mmio + PORT_CMD);
728 tmp |= PORT_CMD_FIS_RX;
729 writel(tmp, port_mmio + PORT_CMD);
730
731 /* flush */
732 readl(port_mmio + PORT_CMD);
733}
734
4447d351 735static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 736{
4447d351 737 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 738 u32 tmp;
739
740 /* disable FIS reception */
741 tmp = readl(port_mmio + PORT_CMD);
742 tmp &= ~PORT_CMD_FIS_RX;
743 writel(tmp, port_mmio + PORT_CMD);
744
745 /* wait for completion, spec says 500ms, give it 1000 */
746 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
747 PORT_CMD_FIS_ON, 10, 1000);
748 if (tmp & PORT_CMD_FIS_ON)
749 return -EBUSY;
750
751 return 0;
752}
753
4447d351 754static void ahci_power_up(struct ata_port *ap)
0be0aa98 755{
4447d351
TH		 756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 758 u32 cmd;
759
760 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
761
762 /* spin up device */
4447d351 763 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 764 cmd |= PORT_CMD_SPIN_UP;
765 writel(cmd, port_mmio + PORT_CMD);
766 }
767
768 /* wake up link */
769 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
770}
771
438ac6d5 772#ifdef CONFIG_PM
4447d351 773static void ahci_power_down(struct ata_port *ap)
0be0aa98 774{
4447d351
TH		 775 struct ahci_host_priv *hpriv = ap->host->private_data;
776 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 777 u32 cmd, scontrol;
778
4447d351 779 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 780 return;
0be0aa98 781
07c53dac
TH		 782 /* put device into listen mode, first set PxSCTL.DET to 0 */
783 scontrol = readl(port_mmio + PORT_SCR_CTL);
784 scontrol &= ~0xf;
785 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 786
07c53dac
TH		 787 /* then set PxCMD.SUD to 0 */
788 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
789 cmd &= ~PORT_CMD_SPIN_UP;
790 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 791}
438ac6d5 792#endif
0be0aa98 793
df69c9c5 794static void ahci_start_port(struct ata_port *ap)
0be0aa98 795{
0be0aa98 796 /* enable FIS reception */
4447d351 797 ahci_start_fis_rx(ap);
0be0aa98
TH		 798
799 /* enable DMA */
4447d351 800 ahci_start_engine(ap);
0be0aa98
TH		 801}
802
4447d351 803static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 804{
805 int rc;
806
807 /* disable DMA */
4447d351 808 rc = ahci_stop_engine(ap);
0be0aa98
TH		 809 if (rc) {
810 *emsg = "failed to stop engine";
811 return rc;
812 }
813
814 /* disable FIS reception */
4447d351 815 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 816 if (rc) {
817 *emsg = "failed stop FIS RX";
818 return rc;
819 }
820
0be0aa98
TH		 821 return 0;
822}
823
4447d351 824static int ahci_reset_controller(struct ata_host *host)
d91542c1 825{
4447d351
TH		 826 struct pci_dev *pdev = to_pci_dev(host->dev);
827 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 828 u32 tmp;
d91542c1
TH		 829
830 /* global controller reset */
831 tmp = readl(mmio + HOST_CTL);
832 if ((tmp & HOST_RESET) == 0) {
833 writel(tmp | HOST_RESET, mmio + HOST_CTL);
834 readl(mmio + HOST_CTL); /* flush */
835 }
836
837 /* reset must complete within 1 second, or
838 * the hardware should be considered fried.
839 */
840 ssleep(1);
841
842 tmp = readl(mmio + HOST_CTL);
843 if (tmp & HOST_RESET) {
4447d351 844 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 845 "controller reset failed (0x%x)\n", tmp);
846 return -EIO;
847 }
848
98fa4b60 849 /* turn on AHCI mode */
d91542c1
TH		 850 writel(HOST_AHCI_EN, mmio + HOST_CTL);
851 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60 852
d447df14 853 /* some registers might be cleared on reset. restore initial values */
4447d351 854 ahci_restore_initial_config(host);
d91542c1
TH		 855
856 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
857 u16 tmp16;
858
859 /* configure PCS */
860 pci_read_config_word(pdev, 0x92, &tmp16);
861 tmp16 |= 0xf;
862 pci_write_config_word(pdev, 0x92, tmp16);
863 }
864
865 return 0;
866}
867
2bcd866b
JG		 868static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
869 int port_no, void __iomem *mmio,
870 void __iomem *port_mmio)
871{
872 const char *emsg = NULL;
873 int rc;
874 u32 tmp;
875
876 /* make sure port is not active */
877 rc = ahci_deinit_port(ap, &emsg);
878 if (rc)
879 dev_printk(KERN_WARNING, &pdev->dev,
880 "%s (%d)\n", emsg, rc);
881
882 /* clear SError */
883 tmp = readl(port_mmio + PORT_SCR_ERR);
884 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
885 writel(tmp, port_mmio + PORT_SCR_ERR);
886
887 /* clear port IRQ */
888 tmp = readl(port_mmio + PORT_IRQ_STAT);
889 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
890 if (tmp)
891 writel(tmp, port_mmio + PORT_IRQ_STAT);
892
893 writel(1 << port_no, mmio + HOST_IRQ_STAT);
894}
895
4447d351 896static void ahci_init_controller(struct ata_host *host)
d91542c1 897{
4447d351
TH		 898 struct pci_dev *pdev = to_pci_dev(host->dev);
899 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 900 int i;
cd70c266 901 void __iomem *port_mmio;
d91542c1
TH		 902 u32 tmp;
903
cd70c266
JG		 904 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
905 port_mmio = __ahci_port_base(host, 4);
906
907 writel(0, port_mmio + PORT_IRQ_MASK);
908
909 /* clear port IRQ */
910 tmp = readl(port_mmio + PORT_IRQ_STAT);
911 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
912 if (tmp)
913 writel(tmp, port_mmio + PORT_IRQ_STAT);
914 }
915
4447d351
TH		 916 for (i = 0; i < host->n_ports; i++) {
917 struct ata_port *ap = host->ports[i];
d91542c1 918
cd70c266 919 port_mmio = ahci_port_base(ap);
4447d351 920 if (ata_port_is_dummy(ap))
d91542c1 921 continue;
d91542c1 922
2bcd866b 923 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 924 }
925
926 tmp = readl(mmio + HOST_CTL);
927 VPRINTK("HOST_CTL 0x%x\n", tmp);
928 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
929 tmp = readl(mmio + HOST_CTL);
930 VPRINTK("HOST_CTL 0x%x\n", tmp);
931}
932
422b7595 933static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 934{
4447d351 935 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 936 struct ata_taskfile tf;
422b7595
TH		 937 u32 tmp;
938
939 tmp = readl(port_mmio + PORT_SIG);
940 tf.lbah = (tmp >> 24) & 0xff;
941 tf.lbam = (tmp >> 16) & 0xff;
942 tf.lbal = (tmp >> 8) & 0xff;
943 tf.nsect = (tmp) & 0xff;
944
945 return ata_dev_classify(&tf);
946}
947
12fad3f9
TH		 948static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
949 u32 opts)
cc9278ed 950{
12fad3f9
TH		 951 dma_addr_t cmd_tbl_dma;
952
953 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
954
955 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
956 pp->cmd_slot[tag].status = 0;
957 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
958 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 959}
960
d2e75dff 961static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 962{
0d5ff566 963 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 964 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 965 u32 tmp;
d2e75dff 966 int busy, rc;
bf2af2a2 967
d2e75dff
TH		 968 /* do we need to kick the port? */
969 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
970 if (!busy && !force_restart)
971 return 0;
972
973 /* stop engine */
974 rc = ahci_stop_engine(ap);
975 if (rc)
976 goto out_restart;
977
978 /* need to do CLO? */
979 if (!busy) {
980 rc = 0;
981 goto out_restart;
982 }
983
984 if (!(hpriv->cap & HOST_CAP_CLO)) {
985 rc = -EOPNOTSUPP;
986 goto out_restart;
987 }
bf2af2a2 988
d2e75dff 989 /* perform CLO */
bf2af2a2
BJ		 990 tmp = readl(port_mmio + PORT_CMD);
991 tmp |= PORT_CMD_CLO;
992 writel(tmp, port_mmio + PORT_CMD);
993
d2e75dff 994 rc = 0;
bf2af2a2
BJ		 995 tmp = ata_wait_register(port_mmio + PORT_CMD,
996 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
997 if (tmp & PORT_CMD_CLO)
d2e75dff 998 rc = -EIO;
bf2af2a2 999
d2e75dff
TH		 1000 /* restart engine */
1001 out_restart:
1002 ahci_start_engine(ap);
1003 return rc;
bf2af2a2
BJ		 1004}
1005
91c4a2e0
TH		 1006static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1007 struct ata_taskfile *tf, int is_cmd, u16 flags,
1008 unsigned long timeout_msec)
bf2af2a2 1009{
91c4a2e0 1010 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1011 struct ahci_port_priv *pp = ap->private_data;
4447d351 1012 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1013 u8 *fis = pp->cmd_tbl;
1014 u32 tmp;
1015
1016 /* prep the command */
1017 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1018 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1019
1020 /* issue & wait */
1021 writel(1, port_mmio + PORT_CMD_ISSUE);
1022
1023 if (timeout_msec) {
1024 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1025 1, timeout_msec);
1026 if (tmp & 0x1) {
1027 ahci_kick_engine(ap, 1);
1028 return -EBUSY;
1029 }
1030 } else
1031 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1032
1033 return 0;
1034}
1035
cc0680a5 1036static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1037 int pmp, unsigned long deadline)
91c4a2e0 1038{
cc0680a5 1039 struct ata_port *ap = link->ap;
4658f79b 1040 const char *reason = NULL;
2cbb79eb 1041 unsigned long now, msecs;
4658f79b 1042 struct ata_taskfile tf;
4658f79b
TH		 1043 int rc;
1044
1045 DPRINTK("ENTER\n");
1046
cc0680a5 1047 if (ata_link_offline(link)) {
c2a65852
TH		 1048 DPRINTK("PHY reports no device\n");
1049 *class = ATA_DEV_NONE;
1050 return 0;
1051 }
1052
4658f79b 1053 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff
TH		 1054 rc = ahci_kick_engine(ap, 1);
1055 if (rc)
cc0680a5 1056 ata_link_printk(link, KERN_WARNING,
d2e75dff 1057 "failed to reset engine (errno=%d)", rc);
4658f79b 1058
cc0680a5 1059 ata_tf_init(link->device, &tf);
4658f79b
TH		 1060
1061 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1062 msecs = 0;
1063 now = jiffies;
1064 if (time_after(now, deadline))
1065 msecs = jiffies_to_msecs(deadline - now);
1066
4658f79b 1067 tf.ctl |= ATA_SRST;
a9cf5e85 1068 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1069 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1070 rc = -EIO;
1071 reason = "1st FIS failed";
1072 goto fail;
1073 }
1074
1075 /* spec says at least 5us, but be generous and sleep for 1ms */
1076 msleep(1);
1077
1078 /* issue the second D2H Register FIS */
4658f79b 1079 tf.ctl &= ~ATA_SRST;
a9cf5e85 1080 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b
TH		 1081
1082 /* spec mandates ">= 2ms" before checking status.
1083 * We wait 150ms, because that was the magic delay used for
1084 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1085 * between when the ATA command register is written, and then
1086 * status is checked. Because waiting for "a while" before
1087 * checking status is fine, post SRST, we perform this magic
1088 * delay here as well.
1089 */
1090 msleep(150);
1091
9b89391c
TH		 1092 rc = ata_wait_ready(ap, deadline);
1093 /* link occupied, -ENODEV too is an error */
1094 if (rc) {
1095 reason = "device not ready";
1096 goto fail;
4658f79b 1097 }
9b89391c 1098 *class = ahci_dev_classify(ap);
4658f79b
TH		 1099
1100 DPRINTK("EXIT, class=%u\n", *class);
1101 return 0;
1102
4658f79b 1103 fail:
cc0680a5 1104 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1105 return rc;
1106}
1107
cc0680a5 1108static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1109 unsigned long deadline)
1110{
cc0680a5 1111 return ahci_do_softreset(link, class, 0, deadline);
a9cf5e85
TH		 1112}
1113
cc0680a5 1114static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1115 unsigned long deadline)
422b7595 1116{
cc0680a5 1117 struct ata_port *ap = link->ap;
4296971d
TH		 1118 struct ahci_port_priv *pp = ap->private_data;
1119 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1120 struct ata_taskfile tf;
4bd00f6a
TH		 1121 int rc;
1122
1123 DPRINTK("ENTER\n");
1da177e4 1124
4447d351 1125 ahci_stop_engine(ap);
4296971d
TH		 1126
1127 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1128 ata_tf_init(link->device, &tf);
dfd7a3db 1129 tf.command = 0x80;
9977126c 1130 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1131
cc0680a5 1132 rc = sata_std_hardreset(link, class, deadline);
4296971d 1133
4447d351 1134 ahci_start_engine(ap);
1da177e4 1135
cc0680a5 1136 if (rc == 0 && ata_link_online(link))
4bd00f6a
TH		 1137 *class = ahci_dev_classify(ap);
1138 if (*class == ATA_DEV_UNKNOWN)
1139 *class = ATA_DEV_NONE;
1da177e4 1140
4bd00f6a
TH		 1141 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1142 return rc;
1143}
1144
cc0680a5 1145static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1146 unsigned long deadline)
ad616ffb 1147{
cc0680a5 1148 struct ata_port *ap = link->ap;
da3dbb17 1149 u32 serror;
ad616ffb
TH		 1150 int rc;
1151
1152 DPRINTK("ENTER\n");
1153
4447d351 1154 ahci_stop_engine(ap);
ad616ffb 1155
cc0680a5 1156 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1157 deadline);
ad616ffb
TH		 1158
1159 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1160 ahci_scr_read(ap, SCR_ERROR, &serror);
1161 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1162
4447d351 1163 ahci_start_engine(ap);
ad616ffb
TH		 1164
1165 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1166
1167 /* vt8251 doesn't clear BSY on signature FIS reception,
1168 * request follow-up softreset.
1169 */
1170 return rc ?: -EAGAIN;
1171}
1172
cc0680a5 1173static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1174{
cc0680a5 1175 struct ata_port *ap = link->ap;
4447d351 1176 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1177 u32 new_tmp, tmp;
1178
cc0680a5 1179 ata_std_postreset(link, class);
02eaa666
JG		 1180
1181 /* Make sure port's ATAPI bit is set appropriately */
1182 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1183 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1184 new_tmp |= PORT_CMD_ATAPI;
1185 else
1186 new_tmp &= ~PORT_CMD_ATAPI;
1187 if (new_tmp != tmp) {
1188 writel(new_tmp, port_mmio + PORT_CMD);
1189 readl(port_mmio + PORT_CMD); /* flush */
1190 }
1da177e4
LT		 1191}
1192
1193static u8 ahci_check_status(struct ata_port *ap)
1194{
0d5ff566 1195 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1196
1197 return readl(mmio + PORT_TFDATA) & 0xFF;
1198}
1199
1da177e4
LT		 1200static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1201{
1202 struct ahci_port_priv *pp = ap->private_data;
1203 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1204
1205 ata_tf_from_fis(d2h_fis, tf);
1206}
1207
12fad3f9 1208static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1209{
cedc9a47
JG		 1210 struct scatterlist *sg;
1211 struct ahci_sg *ahci_sg;
828d09de 1212 unsigned int n_sg = 0;
1da177e4
LT		 1213
1214 VPRINTK("ENTER\n");
1215
1216 /*
1217 * Next, the S/G list.
1218 */
12fad3f9 1219 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1220 ata_for_each_sg(sg, qc) {
1221 dma_addr_t addr = sg_dma_address(sg);
1222 u32 sg_len = sg_dma_len(sg);
1223
1224 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1225 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1226 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1227
cedc9a47 1228 ahci_sg++;
828d09de 1229 n_sg++;
1da177e4 1230 }
828d09de
JG		 1231
1232 return n_sg;
1da177e4
LT		 1233}
1234
1235static void ahci_qc_prep(struct ata_queued_cmd *qc)
1236{
a0ea7328
JG		 1237 struct ata_port *ap = qc->ap;
1238 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1239 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1240 void *cmd_tbl;
1da177e4
LT		 1241 u32 opts;
1242 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1243 unsigned int n_elem;
1da177e4 1244
1da177e4
LT		 1245 /*
1246 * Fill in command table information. First, the header,
1247 * a SATA Register - Host to Device command FIS.
1248 */
12fad3f9
TH		 1249 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1250
9977126c 1251 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
cc9278ed 1252 if (is_atapi) {
12fad3f9
TH		 1253 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1254 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1255 }
1da177e4 1256
cc9278ed
TH		 1257 n_elem = 0;
1258 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1259 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1260
cc9278ed
TH		 1261 /*
1262 * Fill in command slot information.
1263 */
1264 opts = cmd_fis_len | n_elem << 16;
1265 if (qc->tf.flags & ATA_TFLAG_WRITE)
1266 opts |= AHCI_CMD_WRITE;
1267 if (is_atapi)
4b10e559 1268 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1269
12fad3f9 1270 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1271}
1272
78cd52d0 1273static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1274{
78cd52d0 1275 struct ahci_port_priv *pp = ap->private_data;
9af5c9c9 1276 struct ata_eh_info *ehi = &ap->link.eh_info;
78cd52d0
TH		 1277 unsigned int err_mask = 0, action = 0;
1278 struct ata_queued_cmd *qc;
1279 u32 serror;
1da177e4 1280
78cd52d0 1281 ata_ehi_clear_desc(ehi);
1da177e4 1282
78cd52d0 1283 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1284 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1285 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1286
78cd52d0
TH		 1287 /* analyze @irq_stat */
1288 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1289
41669553
TH		 1290 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1291 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1292 irq_stat &= ~PORT_IRQ_IF_ERR;
1293
55a61604 1294 if (irq_stat & PORT_IRQ_TF_ERR) {
78cd52d0 1295 err_mask |= AC_ERR_DEV;
55a61604
CH		 1296 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1297 serror &= ~SERR_INTERNAL;
1298 }
78cd52d0
TH		 1299
1300 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1301 err_mask |= AC_ERR_HOST_BUS;
1302 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1303 }
1304
78cd52d0
TH		 1305 if (irq_stat & PORT_IRQ_IF_ERR) {
1306 err_mask |= AC_ERR_ATA_BUS;
1307 action |= ATA_EH_SOFTRESET;
b64bbc39 1308 ata_ehi_push_desc(ehi, "interface fatal error");
78cd52d0 1309 }
1da177e4 1310
78cd52d0 1311 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1312 ata_ehi_hotplugged(ehi);
b64bbc39 1313 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1314 "connection status changed" : "PHY RDY changed");
1315 }
1316
1317 if (irq_stat & PORT_IRQ_UNK_FIS) {
1318 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1319
78cd52d0
TH		 1320 err_mask |= AC_ERR_HSM;
1321 action |= ATA_EH_SOFTRESET;
b64bbc39 1322 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
78cd52d0
TH		 1323 unk[0], unk[1], unk[2], unk[3]);
1324 }
1da177e4 1325
78cd52d0
TH		 1326 /* okay, let's hand over to EH */
1327 ehi->serror |= serror;
1328 ehi->action |= action;
b8f6153e 1329
9af5c9c9 1330 qc = ata_qc_from_tag(ap, ap->link.active_tag);
78cd52d0
TH		 1331 if (qc)
1332 qc->err_mask |= err_mask;
1333 else
1334 ehi->err_mask |= err_mask;
a72ec4ce 1335
78cd52d0
TH		 1336 if (irq_stat & PORT_IRQ_FREEZE)
1337 ata_port_freeze(ap);
1338 else
1339 ata_port_abort(ap);
1da177e4
LT		 1340}
1341
df69c9c5 1342static void ahci_port_intr(struct ata_port *ap)
1da177e4 1343{
4447d351 1344 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1345 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1346 struct ahci_port_priv *pp = ap->private_data;
12fad3f9 1347 u32 status, qc_active;
0291f95f 1348 int rc, known_irq = 0;
1da177e4
LT		 1349
1350 status = readl(port_mmio + PORT_IRQ_STAT);
1351 writel(status, port_mmio + PORT_IRQ_STAT);
1352
78cd52d0
TH		 1353 if (unlikely(status & PORT_IRQ_ERROR)) {
1354 ahci_error_intr(ap, status);
1355 return;
1da177e4
LT		 1356 }
1357
2f294968 1358 if (status & PORT_IRQ_SDB_FIS) {
7d77b247
TH		 1359 /* If the 'N' bit in word 0 of the FIS is set, we just
1360 * received asynchronous notification. Tell libata
1361 * about it. Note that as the SDB FIS itself is
1362 * accessible, SNotification can be emulated by the
1363 * driver but don't bother for the time being.
2f294968
KCA		 1364 */
1365 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1366 u32 f0 = le32_to_cpu(f[0]);
1367
7d77b247
TH		 1368 if (f0 & (1 << 15))
1369 sata_async_notification(ap);
2f294968
KCA		 1370 }
1371
9af5c9c9 1372 if (ap->link.sactive)
12fad3f9
TH		 1373 qc_active = readl(port_mmio + PORT_SCR_ACT);
1374 else
1375 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1376
1377 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1378 if (rc > 0)
1379 return;
1380 if (rc < 0) {
1381 ehi->err_mask |= AC_ERR_HSM;
1382 ehi->action |= ATA_EH_SOFTRESET;
1383 ata_port_freeze(ap);
1384 return;
1da177e4
LT		 1385 }
1386
2a3917a8
TH		 1387 /* hmmm... a spurious interupt */
1388
0291f95f
TH		 1389 /* if !NCQ, ignore. No modern ATA device has broken HSM
1390 * implementation for non-NCQ commands.
1391 */
9af5c9c9 1392 if (!ap->link.sactive)
12fad3f9
TH		 1393 return;
1394
0291f95f
TH		 1395 if (status & PORT_IRQ_D2H_REG_FIS) {
1396 if (!pp->ncq_saw_d2h)
1397 ata_port_printk(ap, KERN_INFO,
1398 "D2H reg with I during NCQ, "
1399 "this message won't be printed again\n");
1400 pp->ncq_saw_d2h = 1;
1401 known_irq = 1;
1402 }
1403
1404 if (status & PORT_IRQ_DMAS_FIS) {
1405 if (!pp->ncq_saw_dmas)
1406 ata_port_printk(ap, KERN_INFO,
1407 "DMAS FIS during NCQ, "
1408 "this message won't be printed again\n");
1409 pp->ncq_saw_dmas = 1;
1410 known_irq = 1;
1411 }
1412
a2bbd0c9 1413 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1414 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1415
afb2d552
TH		 1416 if (le32_to_cpu(f[1])) {
1417 /* SDB FIS containing spurious completions
1418 * might be dangerous, whine and fail commands
1419 * with HSM violation. EH will turn off NCQ
1420 * after several such failures.
1421 */
1422 ata_ehi_push_desc(ehi,
1423 "spurious completions during NCQ "
1424 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1425 readl(port_mmio + PORT_CMD_ISSUE),
1426 readl(port_mmio + PORT_SCR_ACT),
1427 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1428 ehi->err_mask |= AC_ERR_HSM;
1429 ehi->action |= ATA_EH_SOFTRESET;
1430 ata_port_freeze(ap);
1431 } else {
1432 if (!pp->ncq_saw_sdb)
1433 ata_port_printk(ap, KERN_INFO,
1434 "spurious SDB FIS %08x:%08x during NCQ, "
1435 "this message won't be printed again\n",
1436 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1437 pp->ncq_saw_sdb = 1;
1438 }
0291f95f
TH		 1439 known_irq = 1;
1440 }
2a3917a8 1441
0291f95f 1442 if (!known_irq)
78cd52d0 1443 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1444 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
9af5c9c9 1445 status, ap->link.active_tag, ap->link.sactive);
1da177e4
LT		 1446}
1447
1448static void ahci_irq_clear(struct ata_port *ap)
1449{
1450 /* TODO */
1451}
1452
7d12e780 1453static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1454{
cca3974e 1455 struct ata_host *host = dev_instance;
1da177e4
LT		 1456 struct ahci_host_priv *hpriv;
1457 unsigned int i, handled = 0;
ea6ba10b 1458 void __iomem *mmio;
1da177e4
LT		 1459 u32 irq_stat, irq_ack = 0;
1460
1461 VPRINTK("ENTER\n");
1462
cca3974e 1463 hpriv = host->private_data;
0d5ff566 1464 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1465
1466 /* sigh. 0xffffffff is a valid return from h/w */
1467 irq_stat = readl(mmio + HOST_IRQ_STAT);
1468 irq_stat &= hpriv->port_map;
1469 if (!irq_stat)
1470 return IRQ_NONE;
1471
cca3974e 1472 spin_lock(&host->lock);
1da177e4 1473
cca3974e 1474 for (i = 0; i < host->n_ports; i++) {
1da177e4 1475 struct ata_port *ap;
1da177e4 1476
67846b30
JG		 1477 if (!(irq_stat & (1 << i)))
1478 continue;
1479
cca3974e 1480 ap = host->ports[i];
67846b30 1481 if (ap) {
df69c9c5 1482 ahci_port_intr(ap);
67846b30
JG		 1483 VPRINTK("port %u\n", i);
1484 } else {
1485 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1486 if (ata_ratelimit())
cca3974e 1487 dev_printk(KERN_WARNING, host->dev,
a9524a76 1488 "interrupt on disabled port %u\n", i);
1da177e4 1489 }
67846b30
JG		 1490
1491 irq_ack |= (1 << i);
1da177e4
LT		 1492 }
1493
1494 if (irq_ack) {
1495 writel(irq_ack, mmio + HOST_IRQ_STAT);
1496 handled = 1;
1497 }
1498
cca3974e 1499 spin_unlock(&host->lock);
1da177e4
LT		 1500
1501 VPRINTK("EXIT\n");
1502
1503 return IRQ_RETVAL(handled);
1504}
1505
9a3d9eb0 1506static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1507{
1508 struct ata_port *ap = qc->ap;
4447d351 1509 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1510
12fad3f9
TH		 1511 if (qc->tf.protocol == ATA_PROT_NCQ)
1512 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1513 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1514 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1515
1516 return 0;
1517}
1518
78cd52d0
TH		 1519static void ahci_freeze(struct ata_port *ap)
1520{
4447d351 1521 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1522
1523 /* turn IRQ off */
1524 writel(0, port_mmio + PORT_IRQ_MASK);
1525}
1526
1527static void ahci_thaw(struct ata_port *ap)
1528{
0d5ff566 1529 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1530 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1531 u32 tmp;
a7384925 1532 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1533
1534 /* clear IRQ */
1535 tmp = readl(port_mmio + PORT_IRQ_STAT);
1536 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1537 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0
TH		 1538
1539 /* turn IRQ back on */
a7384925 1540 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1541}
1542
1543static void ahci_error_handler(struct ata_port *ap)
1544{
b51e9e5d 1545 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1546 /* restart engine */
4447d351
TH		 1547 ahci_stop_engine(ap);
1548 ahci_start_engine(ap);
78cd52d0
TH		 1549 }
1550
1551 /* perform recovery */
4aeb0e32 1552 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1553 ahci_postreset);
78cd52d0
TH		 1554}
1555
ad616ffb
TH		 1556static void ahci_vt8251_error_handler(struct ata_port *ap)
1557{
ad616ffb
TH		 1558 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1559 /* restart engine */
4447d351
TH		 1560 ahci_stop_engine(ap);
1561 ahci_start_engine(ap);
ad616ffb
TH		 1562 }
1563
1564 /* perform recovery */
1565 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1566 ahci_postreset);
1567}
1568
78cd52d0
TH		 1569static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1570{
1571 struct ata_port *ap = qc->ap;
1572
d2e75dff
TH		 1573 /* make DMA engine forget about the failed command */
1574 if (qc->flags & ATA_QCFLAG_FAILED)
1575 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1576}
1577
028a2596
AD		 1578static int ahci_port_resume(struct ata_port *ap)
1579{
1580 ahci_power_up(ap);
1581 ahci_start_port(ap);
1582
1583 return 0;
1584}
1585
438ac6d5 1586#ifdef CONFIG_PM
c1332875
TH		 1587static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1588{
c1332875
TH		 1589 const char *emsg = NULL;
1590 int rc;
1591
4447d351 1592 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1593 if (rc == 0)
4447d351 1594 ahci_power_down(ap);
8e16f941 1595 else {
c1332875 1596 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1597 ahci_start_port(ap);
c1332875
TH		 1598 }
1599
1600 return rc;
1601}
1602
c1332875
TH		 1603static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1604{
cca3974e 1605 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1606 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1607 u32 ctl;
1608
1609 if (mesg.event == PM_EVENT_SUSPEND) {
1610 /* AHCI spec rev1.1 section 8.3.3:
1611 * Software must disable interrupts prior to requesting a
1612 * transition of the HBA to D3 state.
1613 */
1614 ctl = readl(mmio + HOST_CTL);
1615 ctl &= ~HOST_IRQ_EN;
1616 writel(ctl, mmio + HOST_CTL);
1617 readl(mmio + HOST_CTL); /* flush */
1618 }
1619
1620 return ata_pci_device_suspend(pdev, mesg);
1621}
1622
1623static int ahci_pci_device_resume(struct pci_dev *pdev)
1624{
cca3974e 1625 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1626 int rc;
1627
553c4aa6
TH		 1628 rc = ata_pci_device_do_resume(pdev);
1629 if (rc)
1630 return rc;
c1332875
TH		 1631
1632 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 1633 rc = ahci_reset_controller(host);
c1332875
TH		 1634 if (rc)
1635 return rc;
1636
4447d351 1637 ahci_init_controller(host);
c1332875
TH		 1638 }
1639
cca3974e 1640 ata_host_resume(host);
c1332875
TH		 1641
1642 return 0;
1643}
438ac6d5 1644#endif
c1332875 1645
254950cd
TH		 1646static int ahci_port_start(struct ata_port *ap)
1647{
cca3974e 1648 struct device *dev = ap->host->dev;
254950cd 1649 struct ahci_port_priv *pp;
254950cd
TH		 1650 void *mem;
1651 dma_addr_t mem_dma;
1652 int rc;
1653
24dc5f33 1654 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1655 if (!pp)
1656 return -ENOMEM;
254950cd
TH		 1657
1658 rc = ata_pad_alloc(ap, dev);
24dc5f33 1659 if (rc)
254950cd 1660 return rc;
254950cd 1661
24dc5f33
TH		 1662 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1663 GFP_KERNEL);
1664 if (!mem)
254950cd 1665 return -ENOMEM;
254950cd
TH		 1666 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1667
1668 /*
1669 * First item in chunk of DMA memory: 32-slot command table,
1670 * 32 bytes each in size
1671 */
1672 pp->cmd_slot = mem;
1673 pp->cmd_slot_dma = mem_dma;
1674
1675 mem += AHCI_CMD_SLOT_SZ;
1676 mem_dma += AHCI_CMD_SLOT_SZ;
1677
1678 /*
1679 * Second item: Received-FIS area
1680 */
1681 pp->rx_fis = mem;
1682 pp->rx_fis_dma = mem_dma;
1683
1684 mem += AHCI_RX_FIS_SZ;
1685 mem_dma += AHCI_RX_FIS_SZ;
1686
1687 /*
1688 * Third item: data area for storing a single command
1689 * and its scatter-gather table
1690 */
1691 pp->cmd_tbl = mem;
1692 pp->cmd_tbl_dma = mem_dma;
1693
a7384925
KCA		 1694 /*
1695 * Save off initial list of interrupts to be enabled.
1696 * This could be changed later
1697 */
1698 pp->intr_mask = DEF_PORT_IRQ;
1699
254950cd
TH		 1700 ap->private_data = pp;
1701
df69c9c5
JG		 1702 /* engage engines, captain */
1703 return ahci_port_resume(ap);
254950cd
TH		 1704}
1705
1706static void ahci_port_stop(struct ata_port *ap)
1707{
0be0aa98
TH		 1708 const char *emsg = NULL;
1709 int rc;
254950cd 1710
0be0aa98 1711 /* de-initialize port */
4447d351 1712 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 1713 if (rc)
1714 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1715}
1716
4447d351 1717static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 1718{
1da177e4 1719 int rc;
1da177e4 1720
1da177e4
LT		 1721 if (using_dac &&
1722 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1723 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1724 if (rc) {
1725 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1726 if (rc) {
a9524a76
JG		 1727 dev_printk(KERN_ERR, &pdev->dev,
1728 "64-bit DMA enable failed\n");
1da177e4
LT		 1729 return rc;
1730 }
1731 }
1da177e4
LT		 1732 } else {
1733 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1734 if (rc) {
a9524a76
JG		 1735 dev_printk(KERN_ERR, &pdev->dev,
1736 "32-bit DMA enable failed\n");
1da177e4
LT		 1737 return rc;
1738 }
1739 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1740 if (rc) {
a9524a76
JG		 1741 dev_printk(KERN_ERR, &pdev->dev,
1742 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1743 return rc;
1744 }
1745 }
1da177e4
LT		 1746 return 0;
1747}
1748
4447d351 1749static void ahci_print_info(struct ata_host *host)
1da177e4 1750{
4447d351
TH		 1751 struct ahci_host_priv *hpriv = host->private_data;
1752 struct pci_dev *pdev = to_pci_dev(host->dev);
1753 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1754 u32 vers, cap, impl, speed;
1755 const char *speed_s;
1756 u16 cc;
1757 const char *scc_s;
1758
1759 vers = readl(mmio + HOST_VERSION);
1760 cap = hpriv->cap;
1761 impl = hpriv->port_map;
1762
1763 speed = (cap >> 20) & 0xf;
1764 if (speed == 1)
1765 speed_s = "1.5";
1766 else if (speed == 2)
1767 speed_s = "3";
1768 else
1769 speed_s = "?";
1770
1771 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 1772 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 1773 scc_s = "IDE";
c9f89475 1774 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 1775 scc_s = "SATA";
c9f89475 1776 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 1777 scc_s = "RAID";
1778 else
1779 scc_s = "unknown";
1780
a9524a76
JG		 1781 dev_printk(KERN_INFO, &pdev->dev,
1782 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1783 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1784 ,
1da177e4
LT		 1785
1786 (vers >> 24) & 0xff,
1787 (vers >> 16) & 0xff,
1788 (vers >> 8) & 0xff,
1789 vers & 0xff,
1790
1791 ((cap >> 8) & 0x1f) + 1,
1792 (cap & 0x1f) + 1,
1793 speed_s,
1794 impl,
1795 scc_s);
1796
a9524a76
JG		 1797 dev_printk(KERN_INFO, &pdev->dev,
1798 "flags: "
203ef6c4
TH		 1799 "%s%s%s%s%s%s%s"
1800 "%s%s%s%s%s%s%s\n"
1da177e4 1801 ,
1da177e4
LT		 1802
1803 cap & (1 << 31) ? "64bit " : "",
1804 cap & (1 << 30) ? "ncq " : "",
203ef6c4 1805 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 1806 cap & (1 << 28) ? "ilck " : "",
1807 cap & (1 << 27) ? "stag " : "",
1808 cap & (1 << 26) ? "pm " : "",
1809 cap & (1 << 25) ? "led " : "",
1810
1811 cap & (1 << 24) ? "clo " : "",
1812 cap & (1 << 19) ? "nz " : "",
1813 cap & (1 << 18) ? "only " : "",
1814 cap & (1 << 17) ? "pmp " : "",
1815 cap & (1 << 15) ? "pio " : "",
1816 cap & (1 << 14) ? "slum " : "",
1817 cap & (1 << 13) ? "part " : ""
1818 );
1819}
1820
24dc5f33 1821static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1822{
1823 static int printed_version;
4447d351
TH		 1824 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1825 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1826 struct device *dev = &pdev->dev;
1da177e4 1827 struct ahci_host_priv *hpriv;
4447d351
TH		 1828 struct ata_host *host;
1829 int i, rc;
1da177e4
LT		 1830
1831 VPRINTK("ENTER\n");
1832
12fad3f9
TH		 1833 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1834
1da177e4 1835 if (!printed_version++)
a9524a76 1836 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1837
4447d351 1838 /* acquire resources */
24dc5f33 1839 rc = pcim_enable_device(pdev);
1da177e4
LT		 1840 if (rc)
1841 return rc;
1842
0d5ff566
TH		 1843 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1844 if (rc == -EBUSY)
24dc5f33 1845 pcim_pin_device(pdev);
0d5ff566 1846 if (rc)
24dc5f33 1847 return rc;
1da177e4 1848
cd70c266 1849 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
907f4678 1850 pci_intx(pdev, 1);
1da177e4 1851
24dc5f33
TH		 1852 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1853 if (!hpriv)
1854 return -ENOMEM;
1da177e4 1855
4447d351
TH		 1856 /* save initial config */
1857 ahci_save_initial_config(pdev, &pi, hpriv);
1da177e4 1858
4447d351 1859 /* prepare host */
274c1fde 1860 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 1861 pi.flags |= ATA_FLAG_NCQ;
1da177e4 1862
4447d351
TH		 1863 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1864 if (!host)
1865 return -ENOMEM;
1866 host->iomap = pcim_iomap_table(pdev);
1867 host->private_data = hpriv;
1868
1869 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 1870 struct ata_port *ap = host->ports[i];
1871 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 1872
cbcdd875
TH		 1873 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1874 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1875 0x100 + ap->port_no * 0x80, "port");
1876
dab632e8 1877 /* standard SATA port setup */
203ef6c4 1878 if (hpriv->port_map & (1 << i))
4447d351 1879 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 1880
1881 /* disabled/not-implemented port */
1882 else
1883 ap->ops = &ata_dummy_port_ops;
4447d351 1884 }
d447df14 1885
4447d351
TH		 1886 /* initialize adapter */
1887 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1888 if (rc)
24dc5f33 1889 return rc;
1da177e4 1890
4447d351
TH		 1891 rc = ahci_reset_controller(host);
1892 if (rc)
1893 return rc;
1da177e4 1894
4447d351
TH		 1895 ahci_init_controller(host);
1896 ahci_print_info(host);
1da177e4 1897
4447d351
TH		 1898 pci_set_master(pdev);
1899 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1900 &ahci_sht);
907f4678 1901}
1da177e4
LT		 1902
1903static int __init ahci_init(void)
1904{
b7887196 1905 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1906}
1907
1da177e4
LT		 1908static void __exit ahci_exit(void)
1909{
1910 pci_unregister_driver(&ahci_pci_driver);
1911}
1912
1913
1914MODULE_AUTHOR("Jeff Garzik");
1915MODULE_DESCRIPTION("AHCI SATA low-level driver");
1916MODULE_LICENSE("GPL");
1917MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1918MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1919
1920module_init(ahci_init);
1921module_exit(ahci_exit);
Linux kernel - Deliverables
This page took 0.370072 seconds and 5 git commands to generate.