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pata_bf54x: fix BMIDE status register emulation
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 82static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
438ac6d5 86#ifdef CONFIG_PM
c1332875
TH		 87static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 89#endif
ad616ffb 90
fad16e7a
TH		 91static struct scsi_host_template ahci_sht = {
92 AHCI_SHT("ahci"),
93};
94
029cfd6b
TH		 95static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
a1efdaba 97 .hardreset = ahci_vt8251_hardreset,
029cfd6b 98};
edc93052 99
029cfd6b
TH		 100static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 103};
104
417a1a6d
TH		 105#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
4da646b7 109 [board_ahci] =
1da177e4 110 {
1188c0d8 111 .flags = AHCI_FLAG_COMMON,
14bdef98 112 .pio_mask = ATA_PIO4,
469248ab 113 .udma_mask = ATA_UDMA6,
1da177e4
LT		 114 .port_ops = &ahci_ops,
115 },
441577ef 116 [board_ahci_ign_iferr] =
bf2af2a2 117 {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
441577ef 124 [board_ahci_nosntf] =
41669553 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
41669553
TH		 130 .port_ops = &ahci_ops,
131 },
5f173107
TH		 132 [board_ahci_yes_fbs] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
441577ef
TH		 140 /* by chipsets */
141 [board_ahci_mcp65] =
55a61604 142 {
83f2b963
TH		 143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
144 AHCI_HFLAG_YES_NCQ),
ae01b249 145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_mcp77] =
151 {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp89] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 161 .flags = AHCI_FLAG_COMMON,
14bdef98 162 .pio_mask = ATA_PIO4,
469248ab 163 .udma_mask = ATA_UDMA6,
441577ef 164 .port_ops = &ahci_ops,
55a61604 165 },
4da646b7 166 [board_ahci_mv] =
cd70c266 167 {
417a1a6d 168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 171 .pio_mask = ATA_PIO4,
cd70c266
JG		 172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
441577ef 175 [board_ahci_sb600] =
e39fc8c9 176 {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
441577ef 185 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 186 {
441577ef 187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 192 },
441577ef 193 [board_ahci_vt8251] =
1b677afd 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_vt8251_ops,
1b677afd 200 },
1da177e4
LT		 201};
202
3b7d697d 203static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 204 /* Intel */
54bb3a94
JG		 205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 262 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
fe7fa31a 263
e34bb370
TH		 264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 267
268 /* ATI */
c65ec1c2 269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 276
e2dd90b1 277 /* AMD */
5deab536 278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
fe7fa31a 283 /* VIA */
54bb3a94 284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 286
287 /* NVIDIA */
e297d99e
TH		 288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 372
95916edd 373 /* SiS */
20e2de4a
TH		 374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 377
cd70c266
JG		 378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 381 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
5f173107 384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 385 { PCI_DEVICE(0x1b4b, 0x9125),
386 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 387 { PCI_DEVICE(0x1b4b, 0x91a3),
388 .driver_data = board_ahci_yes_fbs },
cd70c266 389
c77a036b
MN		 390 /* Promise */
391 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392
c9703765
KYL		 393 /* Asmedia */
394 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
395
415ae2b5
JG		 396 /* Generic, PCI class code for AHCI */
397 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 399
1da177e4
LT		 400 { } /* terminate list */
401};
402
403
404static struct pci_driver ahci_pci_driver = {
405 .name = DRV_NAME,
406 .id_table = ahci_pci_tbl,
407 .probe = ahci_init_one,
24dc5f33 408 .remove = ata_pci_remove_one,
438ac6d5 409#ifdef CONFIG_PM
c1332875 410 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 411 .resume = ahci_pci_device_resume,
412#endif
413};
1da177e4 414
365cfa1e
AV		 415#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
416static int marvell_enable;
417#else
418static int marvell_enable = 1;
419#endif
420module_param(marvell_enable, int, 0644);
421MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 422
1da177e4 423
365cfa1e
AV		 424static void ahci_pci_save_initial_config(struct pci_dev *pdev,
425 struct ahci_host_priv *hpriv)
426{
427 unsigned int force_port_map = 0;
428 unsigned int mask_port_map = 0;
67846b30 429
365cfa1e
AV		 430 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
431 dev_info(&pdev->dev, "JMB361 has only one port\n");
432 force_port_map = 1;
1da177e4
LT		 433 }
434
365cfa1e
AV		 435 /*
436 * Temporary Marvell 6145 hack: PATA port presence
437 * is asserted through the standard AHCI port
438 * presence register, as bit 4 (counting from 0)
d28f87aa 439 */
365cfa1e
AV		 440 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
441 if (pdev->device == 0x6121)
442 mask_port_map = 0x3;
443 else
444 mask_port_map = 0xf;
445 dev_info(&pdev->dev,
446 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
447 }
1da177e4 448
365cfa1e
AV		 449 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
450 mask_port_map);
1da177e4
LT		 451}
452
365cfa1e 453static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 454{
365cfa1e 455 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 456
365cfa1e 457 ahci_reset_controller(host);
1da177e4 458
365cfa1e
AV		 459 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
460 struct ahci_host_priv *hpriv = host->private_data;
461 u16 tmp16;
d6ef3153 462
365cfa1e
AV		 463 /* configure PCS */
464 pci_read_config_word(pdev, 0x92, &tmp16);
465 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
466 tmp16 |= hpriv->port_map;
467 pci_write_config_word(pdev, 0x92, tmp16);
468 }
d6ef3153
SH		 469 }
470
1da177e4
LT		 471 return 0;
472}
473
365cfa1e 474static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 475{
365cfa1e
AV		 476 struct ahci_host_priv *hpriv = host->private_data;
477 struct pci_dev *pdev = to_pci_dev(host->dev);
478 void __iomem *port_mmio;
78cd52d0 479 u32 tmp;
365cfa1e 480 int mv;
78cd52d0 481
365cfa1e
AV		 482 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
483 if (pdev->device == 0x6121)
484 mv = 2;
485 else
486 mv = 4;
487 port_mmio = __ahci_port_base(host, mv);
78cd52d0 488
365cfa1e 489 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 490
365cfa1e
AV		 491 /* clear port IRQ */
492 tmp = readl(port_mmio + PORT_IRQ_STAT);
493 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
494 if (tmp)
495 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 496 }
497
365cfa1e 498 ahci_init_controller(host);
edc93052
TH		 499}
500
365cfa1e
AV		 501static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
502 unsigned long deadline)
d6ef3153 503{
365cfa1e
AV		 504 struct ata_port *ap = link->ap;
505 bool online;
d6ef3153
SH		 506 int rc;
507
365cfa1e 508 DPRINTK("ENTER\n");
d6ef3153 509
365cfa1e 510 ahci_stop_engine(ap);
d6ef3153 511
365cfa1e
AV		 512 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
513 deadline, &online, NULL);
d6ef3153
SH		 514
515 ahci_start_engine(ap);
d6ef3153 516
365cfa1e 517 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 518
365cfa1e
AV		 519 /* vt8251 doesn't clear BSY on signature FIS reception,
520 * request follow-up softreset.
521 */
522 return online ? -EAGAIN : rc;
7d50b60b
TH		 523}
524
365cfa1e
AV		 525static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
526 unsigned long deadline)
7d50b60b 527{
365cfa1e 528 struct ata_port *ap = link->ap;
1c954a4d 529 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 530 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
531 struct ata_taskfile tf;
532 bool online;
533 int rc;
7d50b60b 534
365cfa1e 535 ahci_stop_engine(ap);
028a2596 536
365cfa1e
AV		 537 /* clear D2H reception area to properly wait for D2H FIS */
538 ata_tf_init(link->device, &tf);
539 tf.command = 0x80;
540 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 541
365cfa1e
AV		 542 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
543 deadline, &online, NULL);
028a2596 544
365cfa1e 545 ahci_start_engine(ap);
c1332875 546
365cfa1e
AV		 547 /* The pseudo configuration device on SIMG4726 attached to
548 * ASUS P5W-DH Deluxe doesn't send signature FIS after
549 * hardreset if no device is attached to the first downstream
550 * port && the pseudo device locks up on SRST w/ PMP==0. To
551 * work around this, wait for !BSY only briefly. If BSY isn't
552 * cleared, perform CLO and proceed to IDENTIFY (achieved by
553 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
554 *
555 * Wait for two seconds. Devices attached to downstream port
556 * which can't process the following IDENTIFY after this will
557 * have to be reset again. For most cases, this should
558 * suffice while making probing snappish enough.
559 */
560 if (online) {
561 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
562 ahci_check_ready);
563 if (rc)
564 ahci_kick_engine(ap);
c1332875 565 }
c1332875
TH		 566 return rc;
567}
568
365cfa1e 569#ifdef CONFIG_PM
c1332875
TH		 570static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
571{
cca3974e 572 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 573 struct ahci_host_priv *hpriv = host->private_data;
d8993349 574 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 575 u32 ctl;
576
9b10ae86
TH		 577 if (mesg.event & PM_EVENT_SUSPEND &&
578 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 579 dev_err(&pdev->dev,
580 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 581 return -EIO;
582 }
583
3a2d5b70 584 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 585 /* AHCI spec rev1.1 section 8.3.3:
586 * Software must disable interrupts prior to requesting a
587 * transition of the HBA to D3 state.
588 */
589 ctl = readl(mmio + HOST_CTL);
590 ctl &= ~HOST_IRQ_EN;
591 writel(ctl, mmio + HOST_CTL);
592 readl(mmio + HOST_CTL); /* flush */
593 }
594
595 return ata_pci_device_suspend(pdev, mesg);
596}
597
598static int ahci_pci_device_resume(struct pci_dev *pdev)
599{
cca3974e 600 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 601 int rc;
602
553c4aa6
TH		 603 rc = ata_pci_device_do_resume(pdev);
604 if (rc)
605 return rc;
c1332875
TH		 606
607 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 608 rc = ahci_pci_reset_controller(host);
c1332875
TH		 609 if (rc)
610 return rc;
611
781d6550 612 ahci_pci_init_controller(host);
c1332875
TH		 613 }
614
cca3974e 615 ata_host_resume(host);
c1332875
TH		 616
617 return 0;
618}
438ac6d5 619#endif
c1332875 620
4447d351 621static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 622{
1da177e4 623 int rc;
1da177e4 624
1da177e4 625 if (using_dac &&
6a35528a
YH		 626 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
627 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 628 if (rc) {
284901a9 629 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 630 if (rc) {
a44fec1f
JP		 631 dev_err(&pdev->dev,
632 "64-bit DMA enable failed\n");
1da177e4
LT		 633 return rc;
634 }
635 }
1da177e4 636 } else {
284901a9 637 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 638 if (rc) {
a44fec1f 639 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 640 return rc;
641 }
284901a9 642 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 643 if (rc) {
a44fec1f
JP		 644 dev_err(&pdev->dev,
645 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 646 return rc;
647 }
648 }
1da177e4
LT		 649 return 0;
650}
651
439fcaec
AV		 652static void ahci_pci_print_info(struct ata_host *host)
653{
654 struct pci_dev *pdev = to_pci_dev(host->dev);
655 u16 cc;
656 const char *scc_s;
657
658 pci_read_config_word(pdev, 0x0a, &cc);
659 if (cc == PCI_CLASS_STORAGE_IDE)
660 scc_s = "IDE";
661 else if (cc == PCI_CLASS_STORAGE_SATA)
662 scc_s = "SATA";
663 else if (cc == PCI_CLASS_STORAGE_RAID)
664 scc_s = "RAID";
665 else
666 scc_s = "unknown";
667
668 ahci_print_info(host, scc_s);
669}
670
edc93052
TH		 671/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
672 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
673 * support PMP and the 4726 either directly exports the device
674 * attached to the first downstream port or acts as a hardware storage
675 * controller and emulate a single ATA device (can be RAID 0/1 or some
676 * other configuration).
677 *
678 * When there's no device attached to the first downstream port of the
679 * 4726, "Config Disk" appears, which is a pseudo ATA device to
680 * configure the 4726. However, ATA emulation of the device is very
681 * lame. It doesn't send signature D2H Reg FIS after the initial
682 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
683 *
684 * The following function works around the problem by always using
685 * hardreset on the port and not depending on receiving signature FIS
686 * afterward. If signature FIS isn't received soon, ATA class is
687 * assumed without follow-up softreset.
688 */
689static void ahci_p5wdh_workaround(struct ata_host *host)
690{
691 static struct dmi_system_id sysids[] = {
692 {
693 .ident = "P5W DH Deluxe",
694 .matches = {
695 DMI_MATCH(DMI_SYS_VENDOR,
696 "ASUSTEK COMPUTER INC"),
697 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
698 },
699 },
700 { }
701 };
702 struct pci_dev *pdev = to_pci_dev(host->dev);
703
704 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
705 dmi_check_system(sysids)) {
706 struct ata_port *ap = host->ports[1];
707
a44fec1f
JP		 708 dev_info(&pdev->dev,
709 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 710
711 ap->ops = &ahci_p5wdh_ops;
712 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
713 }
714}
715
2fcad9d2
TH		 716/* only some SB600 ahci controllers can do 64bit DMA */
717static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 718{
719 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 720 /*
721 * The oldest version known to be broken is 0901 and
722 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 723 * Enable 64bit DMA on 1501 and anything newer.
724 *
03d783bf
TH		 725 * Please read bko#9412 for more info.
726 */
58a09b38
SH		 727 {
728 .ident = "ASUS M2A-VM",
729 .matches = {
730 DMI_MATCH(DMI_BOARD_VENDOR,
731 "ASUSTeK Computer INC."),
732 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
733 },
03d783bf 734 .driver_data = "20071026", /* yyyymmdd */
58a09b38 735 },
e65cc194
MN		 736 /*
737 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
738 * support 64bit DMA.
739 *
740 * BIOS versions earlier than 1.5 had the Manufacturer DMI
741 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
742 * This spelling mistake was fixed in BIOS version 1.5, so
743 * 1.5 and later have the Manufacturer as
744 * "MICRO-STAR INTERNATIONAL CO.,LTD".
745 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
746 *
747 * BIOS versions earlier than 1.9 had a Board Product Name
748 * DMI field of "MS-7376". This was changed to be
749 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
750 * match on DMI_BOARD_NAME of "MS-7376".
751 */
752 {
753 .ident = "MSI K9A2 Platinum",
754 .matches = {
755 DMI_MATCH(DMI_BOARD_VENDOR,
756 "MICRO-STAR INTER"),
757 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
758 },
759 },
3c4aa91f
MN		 760 /*
761 * All BIOS versions for the Asus M3A support 64bit DMA.
762 * (all release versions from 0301 to 1206 were tested)
763 */
764 {
765 .ident = "ASUS M3A",
766 .matches = {
767 DMI_MATCH(DMI_BOARD_VENDOR,
768 "ASUSTeK Computer INC."),
769 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
770 },
771 },
58a09b38
SH		 772 { }
773 };
03d783bf 774 const struct dmi_system_id *match;
2fcad9d2
TH		 775 int year, month, date;
776 char buf[9];
58a09b38 777
03d783bf 778 match = dmi_first_match(sysids);
58a09b38 779 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 780 !match)
58a09b38
SH		 781 return false;
782
e65cc194
MN		 783 if (!match->driver_data)
784 goto enable_64bit;
785
2fcad9d2
TH		 786 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
787 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 788
e65cc194
MN		 789 if (strcmp(buf, match->driver_data) >= 0)
790 goto enable_64bit;
791 else {
a44fec1f
JP		 792 dev_warn(&pdev->dev,
793 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
794 match->ident);
2fcad9d2
TH		 795 return false;
796 }
e65cc194
MN		 797
798enable_64bit:
a44fec1f 799 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 800 return true;
58a09b38
SH		 801}
802
1fd68434
RW		 803static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
804{
805 static const struct dmi_system_id broken_systems[] = {
806 {
807 .ident = "HP Compaq nx6310",
808 .matches = {
809 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
810 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
811 },
812 /* PCI slot number of the controller */
813 .driver_data = (void *)0x1FUL,
814 },
d2f9c061
MR		 815 {
816 .ident = "HP Compaq 6720s",
817 .matches = {
818 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
819 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
820 },
821 /* PCI slot number of the controller */
822 .driver_data = (void *)0x1FUL,
823 },
1fd68434
RW		 824
825 { } /* terminate list */
826 };
827 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
828
829 if (dmi) {
830 unsigned long slot = (unsigned long)dmi->driver_data;
831 /* apply the quirk only to on-board controllers */
832 return slot == PCI_SLOT(pdev->devfn);
833 }
834
835 return false;
836}
837
9b10ae86
TH		 838static bool ahci_broken_suspend(struct pci_dev *pdev)
839{
840 static const struct dmi_system_id sysids[] = {
841 /*
842 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
843 * to the harddisk doesn't become online after
844 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 845 *
846 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
847 *
848 * Use dates instead of versions to match as HP is
849 * apparently recycling both product and version
850 * strings.
851 *
852 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 853 */
854 {
855 .ident = "dv4",
856 .matches = {
857 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
858 DMI_MATCH(DMI_PRODUCT_NAME,
859 "HP Pavilion dv4 Notebook PC"),
860 },
9deb3431 861 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 862 },
863 {
864 .ident = "dv5",
865 .matches = {
866 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
867 DMI_MATCH(DMI_PRODUCT_NAME,
868 "HP Pavilion dv5 Notebook PC"),
869 },
9deb3431 870 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 871 },
872 {
873 .ident = "dv6",
874 .matches = {
875 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
876 DMI_MATCH(DMI_PRODUCT_NAME,
877 "HP Pavilion dv6 Notebook PC"),
878 },
9deb3431 879 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 880 },
881 {
882 .ident = "HDX18",
883 .matches = {
884 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
885 DMI_MATCH(DMI_PRODUCT_NAME,
886 "HP HDX18 Notebook PC"),
887 },
9deb3431 888 .driver_data = "20090430", /* F.23 */
9b10ae86 889 },
cedc9bf9
TH		 890 /*
891 * Acer eMachines G725 has the same problem. BIOS
892 * V1.03 is known to be broken. V3.04 is known to
25985edc 893 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 894 * that we don't have much idea about. For now,
895 * blacklist anything older than V3.04.
9deb3431
TH		 896 *
897 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 898 */
899 {
900 .ident = "G725",
901 .matches = {
902 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
903 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
904 },
9deb3431 905 .driver_data = "20091216", /* V3.04 */
cedc9bf9 906 },
9b10ae86
TH		 907 { } /* terminate list */
908 };
909 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 910 int year, month, date;
911 char buf[9];
9b10ae86
TH		 912
913 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
914 return false;
915
9deb3431
TH		 916 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
917 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 918
9deb3431 919 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 920}
921
5594639a
TH		 922static bool ahci_broken_online(struct pci_dev *pdev)
923{
924#define ENCODE_BUSDEVFN(bus, slot, func) \
925 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
926 static const struct dmi_system_id sysids[] = {
927 /*
928 * There are several gigabyte boards which use
929 * SIMG5723s configured as hardware RAID. Certain
930 * 5723 firmware revisions shipped there keep the link
931 * online but fail to answer properly to SRST or
932 * IDENTIFY when no device is attached downstream
933 * causing libata to retry quite a few times leading
934 * to excessive detection delay.
935 *
936 * As these firmwares respond to the second reset try
937 * with invalid device signature, considering unknown
938 * sig as offline works around the problem acceptably.
939 */
940 {
941 .ident = "EP45-DQ6",
942 .matches = {
943 DMI_MATCH(DMI_BOARD_VENDOR,
944 "Gigabyte Technology Co., Ltd."),
945 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
946 },
947 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
948 },
949 {
950 .ident = "EP45-DS5",
951 .matches = {
952 DMI_MATCH(DMI_BOARD_VENDOR,
953 "Gigabyte Technology Co., Ltd."),
954 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
955 },
956 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
957 },
958 { } /* terminate list */
959 };
960#undef ENCODE_BUSDEVFN
961 const struct dmi_system_id *dmi = dmi_first_match(sysids);
962 unsigned int val;
963
964 if (!dmi)
965 return false;
966
967 val = (unsigned long)dmi->driver_data;
968
969 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
970}
971
8e513217 972#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 973static void ahci_gtf_filter_workaround(struct ata_host *host)
974{
975 static const struct dmi_system_id sysids[] = {
976 /*
977 * Aspire 3810T issues a bunch of SATA enable commands
978 * via _GTF including an invalid one and one which is
979 * rejected by the device. Among the successful ones
980 * is FPDMA non-zero offset enable which when enabled
981 * only on the drive side leads to NCQ command
982 * failures. Filter it out.
983 */
984 {
985 .ident = "Aspire 3810T",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
988 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
989 },
990 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
991 },
992 { }
993 };
994 const struct dmi_system_id *dmi = dmi_first_match(sysids);
995 unsigned int filter;
996 int i;
997
998 if (!dmi)
999 return;
1000
1001 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1002 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1003 filter, dmi->ident);
f80ae7e4
TH		 1004
1005 for (i = 0; i < host->n_ports; i++) {
1006 struct ata_port *ap = host->ports[i];
1007 struct ata_link *link;
1008 struct ata_device *dev;
1009
1010 ata_for_each_link(link, ap, EDGE)
1011 ata_for_each_dev(dev, link, ALL)
1012 dev->gtf_filter |= filter;
1013 }
1014}
8e513217
MT		 1015#else
1016static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1017{}
1018#endif
f80ae7e4 1019
24dc5f33 1020static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1021{
e297d99e
TH		 1022 unsigned int board_id = ent->driver_data;
1023 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1024 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1025 struct device *dev = &pdev->dev;
1da177e4 1026 struct ahci_host_priv *hpriv;
4447d351 1027 struct ata_host *host;
837f5f8f 1028 int n_ports, i, rc;
1da177e4
LT		 1029
1030 VPRINTK("ENTER\n");
1031
b429dd59 1032 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1033
06296a1e 1034 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1035
5b66c829
AC		 1036 /* The AHCI driver can only drive the SATA ports, the PATA driver
1037 can drive them all so if both drivers are selected make sure
1038 AHCI stays out of the way */
1039 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1040 return -ENODEV;
1041
c6353b45
TH		 1042 /*
1043 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1044 * ahci, use ata_generic instead.
1045 */
1046 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1047 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1048 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1049 pdev->subsystem_device == 0xcb89)
1050 return -ENODEV;
1051
7a02267e
MN		 1052 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1053 * At the moment, we can only use the AHCI mode. Let the users know
1054 * that for SAS drives they're out of luck.
1055 */
1056 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1057 dev_info(&pdev->dev,
1058 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1059
4447d351 1060 /* acquire resources */
24dc5f33 1061 rc = pcim_enable_device(pdev);
1da177e4
LT		 1062 if (rc)
1063 return rc;
1064
dea55137
TH		 1065 /* AHCI controllers often implement SFF compatible interface.
1066 * Grab all PCI BARs just in case.
1067 */
1068 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1069 if (rc == -EBUSY)
24dc5f33 1070 pcim_pin_device(pdev);
0d5ff566 1071 if (rc)
24dc5f33 1072 return rc;
1da177e4 1073
c4f7792c
TH		 1074 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1075 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1076 u8 map;
1077
1078 /* ICH6s share the same PCI ID for both piix and ahci
1079 * modes. Enabling ahci mode while MAP indicates
1080 * combined mode is a bad idea. Yield to ata_piix.
1081 */
1082 pci_read_config_byte(pdev, ICH_MAP, &map);
1083 if (map & 0x3) {
a44fec1f
JP		 1084 dev_info(&pdev->dev,
1085 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1086 return -ENODEV;
1087 }
1088 }
1089
24dc5f33
TH		 1090 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1091 if (!hpriv)
1092 return -ENOMEM;
417a1a6d
TH		 1093 hpriv->flags |= (unsigned long)pi.private_data;
1094
e297d99e
TH		 1095 /* MCP65 revision A1 and A2 can't do MSI */
1096 if (board_id == board_ahci_mcp65 &&
1097 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1098 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1099
e427fe04
SH		 1100 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1101 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1102 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1103
2fcad9d2
TH		 1104 /* only some SB600s can do 64bit DMA */
1105 if (ahci_sb600_enable_64bit(pdev))
1106 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1107
31b239ad
TH		 1108 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1109 pci_intx(pdev, 1);
1da177e4 1110
d8993349
AV		 1111 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1112
4447d351 1113 /* save initial config */
394d6e53 1114 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1115
4447d351 1116 /* prepare host */
453d3131
RH		 1117 if (hpriv->cap & HOST_CAP_NCQ) {
1118 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1119 /*
1120 * Auto-activate optimization is supposed to be
1121 * supported on all AHCI controllers indicating NCQ
1122 * capability, but it seems to be broken on some
1123 * chipsets including NVIDIAs.
1124 */
1125 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1126 pi.flags |= ATA_FLAG_FPDMA_AA;
1127 }
1da177e4 1128
7d50b60b
TH		 1129 if (hpriv->cap & HOST_CAP_PMP)
1130 pi.flags |= ATA_FLAG_PMP;
1131
0cbb0e77 1132 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1133
1fd68434
RW		 1134 if (ahci_broken_system_poweroff(pdev)) {
1135 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1136 dev_info(&pdev->dev,
1137 "quirky BIOS, skipping spindown on poweroff\n");
1138 }
1139
9b10ae86
TH		 1140 if (ahci_broken_suspend(pdev)) {
1141 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1142 dev_warn(&pdev->dev,
1143 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1144 }
1145
5594639a
TH		 1146 if (ahci_broken_online(pdev)) {
1147 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1148 dev_info(&pdev->dev,
1149 "online status unreliable, applying workaround\n");
1150 }
1151
837f5f8f
TH		 1152 /* CAP.NP sometimes indicate the index of the last enabled
1153 * port, at other times, that of the last possible port, so
1154 * determining the maximum port number requires looking at
1155 * both CAP.NP and port_map.
1156 */
1157 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1158
1159 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1160 if (!host)
1161 return -ENOMEM;
4447d351
TH		 1162 host->private_data = hpriv;
1163
f3d7f23f 1164 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1165 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1166 else
1167 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1168
18f7ba4c
KCA		 1169 if (pi.flags & ATA_FLAG_EM)
1170 ahci_reset_em(host);
1171
4447d351 1172 for (i = 0; i < host->n_ports; i++) {
dab632e8 1173 struct ata_port *ap = host->ports[i];
4447d351 1174
cbcdd875
TH		 1175 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1176 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1177 0x100 + ap->port_no * 0x80, "port");
1178
18f7ba4c
KCA		 1179 /* set enclosure management message type */
1180 if (ap->flags & ATA_FLAG_EM)
008dbd61 1181 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1182
1183
dab632e8 1184 /* disabled/not-implemented port */
350756f6 1185 if (!(hpriv->port_map & (1 << i)))
dab632e8 1186 ap->ops = &ata_dummy_port_ops;
4447d351 1187 }
d447df14 1188
edc93052
TH		 1189 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1190 ahci_p5wdh_workaround(host);
1191
f80ae7e4
TH		 1192 /* apply gtf filter quirk */
1193 ahci_gtf_filter_workaround(host);
1194
4447d351
TH		 1195 /* initialize adapter */
1196 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1197 if (rc)
24dc5f33 1198 return rc;
1da177e4 1199
3303040d 1200 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1201 if (rc)
1202 return rc;
1da177e4 1203
781d6550 1204 ahci_pci_init_controller(host);
439fcaec 1205 ahci_pci_print_info(host);
1da177e4 1206
4447d351
TH		 1207 pci_set_master(pdev);
1208 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1209 &ahci_sht);
907f4678 1210}
1da177e4
LT		 1211
1212static int __init ahci_init(void)
1213{
b7887196 1214 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1215}
1216
1da177e4
LT		 1217static void __exit ahci_exit(void)
1218{
1219 pci_unregister_driver(&ahci_pci_driver);
1220}
1221
1222
1223MODULE_AUTHOR("Jeff Garzik");
1224MODULE_DESCRIPTION("AHCI SATA low-level driver");
1225MODULE_LICENSE("GPL");
1226MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1227MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1228
1229module_init(ahci_init);
1230module_exit(ahci_exit);
Linux kernel - Deliverables
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