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ahci: fix AHCI parameters not taken into account
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
66a7cbc3 63 board_ahci_nomsi,
67809f85 64 board_ahci_noncq,
441577ef 65 board_ahci_nosntf,
5f173107 66 board_ahci_yes_fbs,
1da177e4 67
441577ef
TH		 68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
83f2b963
TH		 70 board_ahci_mcp77,
71 board_ahci_mcp89,
441577ef
TH		 72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 81 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 82};
83
2dcb407e 84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 85static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
cb85696d
JL		 87static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 89static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
438ac6d5 91#ifdef CONFIG_PM
c1332875
TH		 92static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 94#endif
ad616ffb 95
fad16e7a
TH		 96static struct scsi_host_template ahci_sht = {
97 AHCI_SHT("ahci"),
98};
99
029cfd6b
TH		 100static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_vt8251_hardreset,
029cfd6b 103};
edc93052 104
029cfd6b
TH		 105static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
a1efdaba 107 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 108};
109
98ac62de 110static const struct ata_port_info ahci_port_info[] = {
441577ef 111 /* by features */
facb8fa6 112 [board_ahci] = {
1188c0d8 113 .flags = AHCI_FLAG_COMMON,
14bdef98 114 .pio_mask = ATA_PIO4,
469248ab 115 .udma_mask = ATA_UDMA6,
1da177e4
LT		 116 .port_ops = &ahci_ops,
117 },
facb8fa6 118 [board_ahci_ign_iferr] = {
441577ef 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 120 .flags = AHCI_FLAG_COMMON,
14bdef98 121 .pio_mask = ATA_PIO4,
469248ab 122 .udma_mask = ATA_UDMA6,
441577ef 123 .port_ops = &ahci_ops,
bf2af2a2 124 },
66a7cbc3
TH		 125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
67809f85
LK		 132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
facb8fa6 139 [board_ahci_nosntf] = {
441577ef 140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 141 .flags = AHCI_FLAG_COMMON,
14bdef98 142 .pio_mask = ATA_PIO4,
469248ab 143 .udma_mask = ATA_UDMA6,
41669553
TH		 144 .port_ops = &ahci_ops,
145 },
facb8fa6 146 [board_ahci_yes_fbs] = {
5f173107
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
441577ef 153 /* by chipsets */
facb8fa6 154 [board_ahci_mcp65] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ),
ae01b249 157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
facb8fa6 162 [board_ahci_mcp77] = {
83f2b963
TH		 163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
facb8fa6 169 [board_ahci_mcp89] = {
83f2b963 170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
469248ab 173 .udma_mask = ATA_UDMA6,
441577ef 174 .port_ops = &ahci_ops,
55a61604 175 },
facb8fa6 176 [board_ahci_mv] = {
417a1a6d 177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 180 .pio_mask = ATA_PIO4,
cd70c266
JG		 181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
facb8fa6 184 [board_ahci_sb600] = {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 192 },
facb8fa6 193 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
345347c5 198 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 199 },
facb8fa6 200 [board_ahci_vt8251] = {
441577ef 201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
441577ef 205 .port_ops = &ahci_vt8251_ops,
1b677afd 206 },
1da177e4
LT		 207};
208
3b7d697d 209static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 210 /* Intel */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
690000b9
JR		 324 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
325 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
326 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
327 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
328 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
fe7fa31a 329
e34bb370
TH		 330 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
331 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
332 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 333 /* JMicron 362B and 362C have an AHCI function with IDE class code */
334 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
335 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 336
337 /* ATI */
c65ec1c2 338 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 339 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
340 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
341 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 345
e2dd90b1 346 /* AMD */
5deab536 347 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 348 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 349 /* AMD is using RAID class only for ahci controllers */
350 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
351 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
352
fe7fa31a 353 /* VIA */
54bb3a94 354 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 355 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 356
357 /* NVIDIA */
e297d99e
TH		 358 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
360 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 366 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
367 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
395 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
396 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
407 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
419 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
431 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
432 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 442
95916edd 443 /* SiS */
20e2de4a
TH		 444 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
445 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
446 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 447
318893e1
AR		 448 /* ST Microelectronics */
449 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
450
cd70c266
JG		 451 /* Marvell */
452 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 453 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 454 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 455 .class = PCI_CLASS_STORAGE_SATA_AHCI,
456 .class_mask = 0xffffff,
5f173107 457 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 459 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 460 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
461 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
462 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 463 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 464 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 466 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 468 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
472 .driver_data = board_ahci_yes_fbs },
69fd3157 473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 474 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
476 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 477 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
478 .driver_data = board_ahci_yes_fbs },
cd70c266 479
c77a036b
MN		 480 /* Promise */
481 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 482 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 483
c9703765 484 /* Asmedia */
7b4f6eca
AC		 485 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
486 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
487 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
488 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 489
67809f85 490 /*
66a7cbc3
TH		 491 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
492 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 493 */
66a7cbc3 494 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
67809f85 495
7f9c9f8e
HD		 496 /* Enmotus */
497 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
498
415ae2b5
JG		 499 /* Generic, PCI class code for AHCI */
500 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 501 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 502
1da177e4
LT		 503 { } /* terminate list */
504};
505
506
507static struct pci_driver ahci_pci_driver = {
508 .name = DRV_NAME,
509 .id_table = ahci_pci_tbl,
510 .probe = ahci_init_one,
24dc5f33 511 .remove = ata_pci_remove_one,
438ac6d5 512#ifdef CONFIG_PM
c1332875 513 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 514 .resume = ahci_pci_device_resume,
515#endif
516};
1da177e4 517
365cfa1e
AV		 518#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
519static int marvell_enable;
520#else
521static int marvell_enable = 1;
522#endif
523module_param(marvell_enable, int, 0644);
524MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 525
1da177e4 526
365cfa1e
AV		 527static void ahci_pci_save_initial_config(struct pci_dev *pdev,
528 struct ahci_host_priv *hpriv)
529{
365cfa1e
AV		 530 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
531 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 532 hpriv->force_port_map = 1;
1da177e4
LT		 533 }
534
365cfa1e
AV		 535 /*
536 * Temporary Marvell 6145 hack: PATA port presence
537 * is asserted through the standard AHCI port
538 * presence register, as bit 4 (counting from 0)
d28f87aa 539 */
365cfa1e
AV		 540 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
541 if (pdev->device == 0x6121)
9a23c1d6 542 hpriv->mask_port_map = 0x3;
365cfa1e 543 else
9a23c1d6 544 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 545 dev_info(&pdev->dev,
546 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
547 }
1da177e4 548
725c7b57 549 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 550}
551
365cfa1e 552static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 553{
365cfa1e 554 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 555
365cfa1e 556 ahci_reset_controller(host);
1da177e4 557
365cfa1e
AV		 558 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
559 struct ahci_host_priv *hpriv = host->private_data;
560 u16 tmp16;
d6ef3153 561
365cfa1e
AV		 562 /* configure PCS */
563 pci_read_config_word(pdev, 0x92, &tmp16);
564 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
565 tmp16 |= hpriv->port_map;
566 pci_write_config_word(pdev, 0x92, tmp16);
567 }
d6ef3153
SH		 568 }
569
1da177e4
LT		 570 return 0;
571}
572
365cfa1e 573static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 574{
365cfa1e
AV		 575 struct ahci_host_priv *hpriv = host->private_data;
576 struct pci_dev *pdev = to_pci_dev(host->dev);
577 void __iomem *port_mmio;
78cd52d0 578 u32 tmp;
365cfa1e 579 int mv;
78cd52d0 580
365cfa1e
AV		 581 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
582 if (pdev->device == 0x6121)
583 mv = 2;
584 else
585 mv = 4;
586 port_mmio = __ahci_port_base(host, mv);
78cd52d0 587
365cfa1e 588 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 589
365cfa1e
AV		 590 /* clear port IRQ */
591 tmp = readl(port_mmio + PORT_IRQ_STAT);
592 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
593 if (tmp)
594 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 595 }
596
365cfa1e 597 ahci_init_controller(host);
edc93052
TH		 598}
599
365cfa1e
AV		 600static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
601 unsigned long deadline)
d6ef3153 602{
365cfa1e 603 struct ata_port *ap = link->ap;
039ece38 604 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 605 bool online;
d6ef3153
SH		 606 int rc;
607
365cfa1e 608 DPRINTK("ENTER\n");
d6ef3153 609
365cfa1e 610 ahci_stop_engine(ap);
d6ef3153 611
365cfa1e
AV		 612 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
613 deadline, &online, NULL);
d6ef3153 614
039ece38 615 hpriv->start_engine(ap);
d6ef3153 616
365cfa1e 617 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 618
365cfa1e
AV		 619 /* vt8251 doesn't clear BSY on signature FIS reception,
620 * request follow-up softreset.
621 */
622 return online ? -EAGAIN : rc;
7d50b60b
TH		 623}
624
365cfa1e
AV		 625static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
626 unsigned long deadline)
7d50b60b 627{
365cfa1e 628 struct ata_port *ap = link->ap;
1c954a4d 629 struct ahci_port_priv *pp = ap->private_data;
039ece38 630 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 631 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
632 struct ata_taskfile tf;
633 bool online;
634 int rc;
7d50b60b 635
365cfa1e 636 ahci_stop_engine(ap);
028a2596 637
365cfa1e
AV		 638 /* clear D2H reception area to properly wait for D2H FIS */
639 ata_tf_init(link->device, &tf);
9bbb1b0e 640 tf.command = ATA_BUSY;
365cfa1e 641 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 642
365cfa1e
AV		 643 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
644 deadline, &online, NULL);
028a2596 645
039ece38 646 hpriv->start_engine(ap);
c1332875 647
365cfa1e
AV		 648 /* The pseudo configuration device on SIMG4726 attached to
649 * ASUS P5W-DH Deluxe doesn't send signature FIS after
650 * hardreset if no device is attached to the first downstream
651 * port && the pseudo device locks up on SRST w/ PMP==0. To
652 * work around this, wait for !BSY only briefly. If BSY isn't
653 * cleared, perform CLO and proceed to IDENTIFY (achieved by
654 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
655 *
656 * Wait for two seconds. Devices attached to downstream port
657 * which can't process the following IDENTIFY after this will
658 * have to be reset again. For most cases, this should
659 * suffice while making probing snappish enough.
660 */
661 if (online) {
662 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
663 ahci_check_ready);
664 if (rc)
665 ahci_kick_engine(ap);
c1332875 666 }
c1332875
TH		 667 return rc;
668}
669
365cfa1e 670#ifdef CONFIG_PM
c1332875
TH		 671static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
672{
0a86e1c8 673 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 674 struct ahci_host_priv *hpriv = host->private_data;
d8993349 675 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 676 u32 ctl;
677
9b10ae86
TH		 678 if (mesg.event & PM_EVENT_SUSPEND &&
679 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 680 dev_err(&pdev->dev,
681 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 682 return -EIO;
683 }
684
3a2d5b70 685 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 686 /* AHCI spec rev1.1 section 8.3.3:
687 * Software must disable interrupts prior to requesting a
688 * transition of the HBA to D3 state.
689 */
690 ctl = readl(mmio + HOST_CTL);
691 ctl &= ~HOST_IRQ_EN;
692 writel(ctl, mmio + HOST_CTL);
693 readl(mmio + HOST_CTL); /* flush */
694 }
695
696 return ata_pci_device_suspend(pdev, mesg);
697}
698
699static int ahci_pci_device_resume(struct pci_dev *pdev)
700{
0a86e1c8 701 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 702 int rc;
703
553c4aa6
TH		 704 rc = ata_pci_device_do_resume(pdev);
705 if (rc)
706 return rc;
c1332875 707
cb85696d
JL		 708 /* Apple BIOS helpfully mangles the registers on resume */
709 if (is_mcp89_apple(pdev))
710 ahci_mcp89_apple_enable(pdev);
711
c1332875 712 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 713 rc = ahci_pci_reset_controller(host);
c1332875
TH		 714 if (rc)
715 return rc;
716
781d6550 717 ahci_pci_init_controller(host);
c1332875
TH		 718 }
719
cca3974e 720 ata_host_resume(host);
c1332875
TH		 721
722 return 0;
723}
438ac6d5 724#endif
c1332875 725
4447d351 726static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 727{
1da177e4 728 int rc;
1da177e4 729
318893e1
AR		 730 /*
731 * If the device fixup already set the dma_mask to some non-standard
732 * value, don't extend it here. This happens on STA2X11, for example.
733 */
734 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
735 return 0;
736
1da177e4 737 if (using_dac &&
6a35528a
YH		 738 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
739 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 740 if (rc) {
284901a9 741 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 742 if (rc) {
a44fec1f
JP		 743 dev_err(&pdev->dev,
744 "64-bit DMA enable failed\n");
1da177e4
LT		 745 return rc;
746 }
747 }
1da177e4 748 } else {
284901a9 749 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 750 if (rc) {
a44fec1f 751 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 752 return rc;
753 }
284901a9 754 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 755 if (rc) {
a44fec1f
JP		 756 dev_err(&pdev->dev,
757 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 758 return rc;
759 }
760 }
1da177e4
LT		 761 return 0;
762}
763
439fcaec
AV		 764static void ahci_pci_print_info(struct ata_host *host)
765{
766 struct pci_dev *pdev = to_pci_dev(host->dev);
767 u16 cc;
768 const char *scc_s;
769
770 pci_read_config_word(pdev, 0x0a, &cc);
771 if (cc == PCI_CLASS_STORAGE_IDE)
772 scc_s = "IDE";
773 else if (cc == PCI_CLASS_STORAGE_SATA)
774 scc_s = "SATA";
775 else if (cc == PCI_CLASS_STORAGE_RAID)
776 scc_s = "RAID";
777 else
778 scc_s = "unknown";
779
780 ahci_print_info(host, scc_s);
781}
782
edc93052
TH		 783/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
784 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
785 * support PMP and the 4726 either directly exports the device
786 * attached to the first downstream port or acts as a hardware storage
787 * controller and emulate a single ATA device (can be RAID 0/1 or some
788 * other configuration).
789 *
790 * When there's no device attached to the first downstream port of the
791 * 4726, "Config Disk" appears, which is a pseudo ATA device to
792 * configure the 4726. However, ATA emulation of the device is very
793 * lame. It doesn't send signature D2H Reg FIS after the initial
794 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
795 *
796 * The following function works around the problem by always using
797 * hardreset on the port and not depending on receiving signature FIS
798 * afterward. If signature FIS isn't received soon, ATA class is
799 * assumed without follow-up softreset.
800 */
801static void ahci_p5wdh_workaround(struct ata_host *host)
802{
1bd06867 803 static const struct dmi_system_id sysids[] = {
edc93052
TH		 804 {
805 .ident = "P5W DH Deluxe",
806 .matches = {
807 DMI_MATCH(DMI_SYS_VENDOR,
808 "ASUSTEK COMPUTER INC"),
809 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
810 },
811 },
812 { }
813 };
814 struct pci_dev *pdev = to_pci_dev(host->dev);
815
816 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
817 dmi_check_system(sysids)) {
818 struct ata_port *ap = host->ports[1];
819
a44fec1f
JP		 820 dev_info(&pdev->dev,
821 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 822
823 ap->ops = &ahci_p5wdh_ops;
824 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
825 }
826}
827
cb85696d
JL		 828/*
829 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
830 * booting in BIOS compatibility mode. We restore the registers but not ID.
831 */
832static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
833{
834 u32 val;
835
836 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
837
838 pci_read_config_dword(pdev, 0xf8, &val);
839 val |= 1 << 0x1b;
840 /* the following changes the device ID, but appears not to affect function */
841 /* val = (val & ~0xf0000000) | 0x80000000; */
842 pci_write_config_dword(pdev, 0xf8, val);
843
844 pci_read_config_dword(pdev, 0x54c, &val);
845 val |= 1 << 0xc;
846 pci_write_config_dword(pdev, 0x54c, val);
847
848 pci_read_config_dword(pdev, 0x4a4, &val);
849 val &= 0xff;
850 val |= 0x01060100;
851 pci_write_config_dword(pdev, 0x4a4, val);
852
853 pci_read_config_dword(pdev, 0x54c, &val);
854 val &= ~(1 << 0xc);
855 pci_write_config_dword(pdev, 0x54c, val);
856
857 pci_read_config_dword(pdev, 0xf8, &val);
858 val &= ~(1 << 0x1b);
859 pci_write_config_dword(pdev, 0xf8, val);
860}
861
862static bool is_mcp89_apple(struct pci_dev *pdev)
863{
864 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
865 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
866 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
867 pdev->subsystem_device == 0xcb89;
868}
869
2fcad9d2
TH		 870/* only some SB600 ahci controllers can do 64bit DMA */
871static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 872{
873 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 874 /*
875 * The oldest version known to be broken is 0901 and
876 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 877 * Enable 64bit DMA on 1501 and anything newer.
878 *
03d783bf
TH		 879 * Please read bko#9412 for more info.
880 */
58a09b38
SH		 881 {
882 .ident = "ASUS M2A-VM",
883 .matches = {
884 DMI_MATCH(DMI_BOARD_VENDOR,
885 "ASUSTeK Computer INC."),
886 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
887 },
03d783bf 888 .driver_data = "20071026", /* yyyymmdd */
58a09b38 889 },
e65cc194
MN		 890 /*
891 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
892 * support 64bit DMA.
893 *
894 * BIOS versions earlier than 1.5 had the Manufacturer DMI
895 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
896 * This spelling mistake was fixed in BIOS version 1.5, so
897 * 1.5 and later have the Manufacturer as
898 * "MICRO-STAR INTERNATIONAL CO.,LTD".
899 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
900 *
901 * BIOS versions earlier than 1.9 had a Board Product Name
902 * DMI field of "MS-7376". This was changed to be
903 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
904 * match on DMI_BOARD_NAME of "MS-7376".
905 */
906 {
907 .ident = "MSI K9A2 Platinum",
908 .matches = {
909 DMI_MATCH(DMI_BOARD_VENDOR,
910 "MICRO-STAR INTER"),
911 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
912 },
913 },
ff0173c1
MN		 914 /*
915 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
916 * 64bit DMA.
917 *
918 * This board also had the typo mentioned above in the
919 * Manufacturer DMI field (fixed in BIOS version 1.5), so
920 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
921 */
922 {
923 .ident = "MSI K9AGM2",
924 .matches = {
925 DMI_MATCH(DMI_BOARD_VENDOR,
926 "MICRO-STAR INTER"),
927 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
928 },
929 },
3c4aa91f
MN		 930 /*
931 * All BIOS versions for the Asus M3A support 64bit DMA.
932 * (all release versions from 0301 to 1206 were tested)
933 */
934 {
935 .ident = "ASUS M3A",
936 .matches = {
937 DMI_MATCH(DMI_BOARD_VENDOR,
938 "ASUSTeK Computer INC."),
939 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
940 },
941 },
58a09b38
SH		 942 { }
943 };
03d783bf 944 const struct dmi_system_id *match;
2fcad9d2
TH		 945 int year, month, date;
946 char buf[9];
58a09b38 947
03d783bf 948 match = dmi_first_match(sysids);
58a09b38 949 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 950 !match)
58a09b38
SH		 951 return false;
952
e65cc194
MN		 953 if (!match->driver_data)
954 goto enable_64bit;
955
2fcad9d2
TH		 956 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
957 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 958
e65cc194
MN		 959 if (strcmp(buf, match->driver_data) >= 0)
960 goto enable_64bit;
961 else {
a44fec1f
JP		 962 dev_warn(&pdev->dev,
963 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
964 match->ident);
2fcad9d2
TH		 965 return false;
966 }
e65cc194
MN		 967
968enable_64bit:
a44fec1f 969 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 970 return true;
58a09b38
SH		 971}
972
1fd68434
RW		 973static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
974{
975 static const struct dmi_system_id broken_systems[] = {
976 {
977 .ident = "HP Compaq nx6310",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
981 },
982 /* PCI slot number of the controller */
983 .driver_data = (void *)0x1FUL,
984 },
d2f9c061
MR		 985 {
986 .ident = "HP Compaq 6720s",
987 .matches = {
988 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
989 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
990 },
991 /* PCI slot number of the controller */
992 .driver_data = (void *)0x1FUL,
993 },
1fd68434
RW		 994
995 { } /* terminate list */
996 };
997 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
998
999 if (dmi) {
1000 unsigned long slot = (unsigned long)dmi->driver_data;
1001 /* apply the quirk only to on-board controllers */
1002 return slot == PCI_SLOT(pdev->devfn);
1003 }
1004
1005 return false;
1006}
1007
9b10ae86
TH		 1008static bool ahci_broken_suspend(struct pci_dev *pdev)
1009{
1010 static const struct dmi_system_id sysids[] = {
1011 /*
1012 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1013 * to the harddisk doesn't become online after
1014 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1015 *
1016 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1017 *
1018 * Use dates instead of versions to match as HP is
1019 * apparently recycling both product and version
1020 * strings.
1021 *
1022 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1023 */
1024 {
1025 .ident = "dv4",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1028 DMI_MATCH(DMI_PRODUCT_NAME,
1029 "HP Pavilion dv4 Notebook PC"),
1030 },
9deb3431 1031 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1032 },
1033 {
1034 .ident = "dv5",
1035 .matches = {
1036 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1037 DMI_MATCH(DMI_PRODUCT_NAME,
1038 "HP Pavilion dv5 Notebook PC"),
1039 },
9deb3431 1040 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1041 },
1042 {
1043 .ident = "dv6",
1044 .matches = {
1045 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1046 DMI_MATCH(DMI_PRODUCT_NAME,
1047 "HP Pavilion dv6 Notebook PC"),
1048 },
9deb3431 1049 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1050 },
1051 {
1052 .ident = "HDX18",
1053 .matches = {
1054 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1055 DMI_MATCH(DMI_PRODUCT_NAME,
1056 "HP HDX18 Notebook PC"),
1057 },
9deb3431 1058 .driver_data = "20090430", /* F.23 */
9b10ae86 1059 },
cedc9bf9
TH		 1060 /*
1061 * Acer eMachines G725 has the same problem. BIOS
1062 * V1.03 is known to be broken. V3.04 is known to
25985edc 1063 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1064 * that we don't have much idea about. For now,
1065 * blacklist anything older than V3.04.
9deb3431
TH		 1066 *
1067 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1068 */
1069 {
1070 .ident = "G725",
1071 .matches = {
1072 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1073 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1074 },
9deb3431 1075 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1076 },
9b10ae86
TH		 1077 { } /* terminate list */
1078 };
1079 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1080 int year, month, date;
1081 char buf[9];
9b10ae86
TH		 1082
1083 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1084 return false;
1085
9deb3431
TH		 1086 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1087 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1088
9deb3431 1089 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1090}
1091
5594639a
TH		 1092static bool ahci_broken_online(struct pci_dev *pdev)
1093{
1094#define ENCODE_BUSDEVFN(bus, slot, func) \
1095 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1096 static const struct dmi_system_id sysids[] = {
1097 /*
1098 * There are several gigabyte boards which use
1099 * SIMG5723s configured as hardware RAID. Certain
1100 * 5723 firmware revisions shipped there keep the link
1101 * online but fail to answer properly to SRST or
1102 * IDENTIFY when no device is attached downstream
1103 * causing libata to retry quite a few times leading
1104 * to excessive detection delay.
1105 *
1106 * As these firmwares respond to the second reset try
1107 * with invalid device signature, considering unknown
1108 * sig as offline works around the problem acceptably.
1109 */
1110 {
1111 .ident = "EP45-DQ6",
1112 .matches = {
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "Gigabyte Technology Co., Ltd."),
1115 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1116 },
1117 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1118 },
1119 {
1120 .ident = "EP45-DS5",
1121 .matches = {
1122 DMI_MATCH(DMI_BOARD_VENDOR,
1123 "Gigabyte Technology Co., Ltd."),
1124 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1125 },
1126 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1127 },
1128 { } /* terminate list */
1129 };
1130#undef ENCODE_BUSDEVFN
1131 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1132 unsigned int val;
1133
1134 if (!dmi)
1135 return false;
1136
1137 val = (unsigned long)dmi->driver_data;
1138
1139 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1140}
1141
0cf4a7d6
JP		 1142static bool ahci_broken_devslp(struct pci_dev *pdev)
1143{
1144 /* device with broken DEVSLP but still showing SDS capability */
1145 static const struct pci_device_id ids[] = {
1146 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1147 {}
1148 };
1149
1150 return pci_match_id(ids, pdev);
1151}
1152
8e513217 1153#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1154static void ahci_gtf_filter_workaround(struct ata_host *host)
1155{
1156 static const struct dmi_system_id sysids[] = {
1157 /*
1158 * Aspire 3810T issues a bunch of SATA enable commands
1159 * via _GTF including an invalid one and one which is
1160 * rejected by the device. Among the successful ones
1161 * is FPDMA non-zero offset enable which when enabled
1162 * only on the drive side leads to NCQ command
1163 * failures. Filter it out.
1164 */
1165 {
1166 .ident = "Aspire 3810T",
1167 .matches = {
1168 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1169 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1170 },
1171 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1172 },
1173 { }
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1176 unsigned int filter;
1177 int i;
1178
1179 if (!dmi)
1180 return;
1181
1182 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1183 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1184 filter, dmi->ident);
f80ae7e4
TH		 1185
1186 for (i = 0; i < host->n_ports; i++) {
1187 struct ata_port *ap = host->ports[i];
1188 struct ata_link *link;
1189 struct ata_device *dev;
1190
1191 ata_for_each_link(link, ap, EDGE)
1192 ata_for_each_dev(dev, link, ALL)
1193 dev->gtf_filter |= filter;
1194 }
1195}
8e513217
MT		 1196#else
1197static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1198{}
1199#endif
f80ae7e4 1200
e1ba8459 1201static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1202 struct ahci_host_priv *hpriv)
5ca72c4f 1203{
ccf8f53c 1204 int rc, nvec;
5ca72c4f 1205
7b92b4f6
AG		 1206 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1207 goto intx;
1208
fc061d96
AG		 1209 nvec = pci_msi_vec_count(pdev);
1210 if (nvec < 0)
7b92b4f6
AG		 1211 goto intx;
1212
1213 /*
1214 * If number of MSIs is less than number of ports then Sharing Last
1215 * Message mode could be enforced. In this case assume that advantage
1216 * of multipe MSIs is negated and use single MSI mode instead.
1217 */
fc061d96 1218 if (nvec < n_ports)
7b92b4f6
AG		 1219 goto single_msi;
1220
ccf8f53c
AG		 1221 rc = pci_enable_msi_exact(pdev, nvec);
1222 if (rc == -ENOSPC)
fc40363b 1223 goto single_msi;
ccf8f53c 1224 else if (rc < 0)
fc061d96 1225 goto intx;
5ca72c4f 1226
ab0f9e78
AG		 1227 /* fallback to single MSI mode if the controller enforced MRSM mode */
1228 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1229 pci_disable_msi(pdev);
1230 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1231 goto single_msi;
1232 }
1233
c3ebd6a9
AG		 1234 if (nvec > 1)
1235 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1236
7b92b4f6
AG		 1237 return nvec;
1238
1239single_msi:
fc061d96 1240 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1241 goto intx;
1242 return 1;
1243
1244intx:
5ca72c4f
AG		 1245 pci_intx(pdev, 1);
1246 return 0;
1247}
1248
24dc5f33 1249static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1250{
e297d99e
TH		 1251 unsigned int board_id = ent->driver_data;
1252 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1253 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1254 struct device *dev = &pdev->dev;
1da177e4 1255 struct ahci_host_priv *hpriv;
4447d351 1256 struct ata_host *host;
c3ebd6a9 1257 int n_ports, i, rc;
318893e1 1258 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1259
1260 VPRINTK("ENTER\n");
1261
b429dd59 1262 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1263
06296a1e 1264 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1265
5b66c829
AC		 1266 /* The AHCI driver can only drive the SATA ports, the PATA driver
1267 can drive them all so if both drivers are selected make sure
1268 AHCI stays out of the way */
1269 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1270 return -ENODEV;
1271
cb85696d
JL		 1272 /* Apple BIOS on MCP89 prevents us using AHCI */
1273 if (is_mcp89_apple(pdev))
1274 ahci_mcp89_apple_enable(pdev);
c6353b45 1275
7a02267e
MN		 1276 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1277 * At the moment, we can only use the AHCI mode. Let the users know
1278 * that for SAS drives they're out of luck.
1279 */
1280 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1281 dev_info(&pdev->dev,
1282 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1283
7f9c9f8e 1284 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1285 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1286 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1287 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1288 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1289
e6b7e41c
CL		 1290 /*
1291 * The JMicron chip 361/363 contains one SATA controller and one
1292 * PATA controller,for powering on these both controllers, we must
1293 * follow the sequence one by one, otherwise one of them can not be
1294 * powered on successfully, so here we disable the async suspend
1295 * method for these chips.
1296 */
1297 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1298 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1299 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1300 device_disable_async_suspend(&pdev->dev);
1301
4447d351 1302 /* acquire resources */
24dc5f33 1303 rc = pcim_enable_device(pdev);
1da177e4
LT		 1304 if (rc)
1305 return rc;
1306
c4f7792c
TH		 1307 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1308 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1309 u8 map;
1310
1311 /* ICH6s share the same PCI ID for both piix and ahci
1312 * modes. Enabling ahci mode while MAP indicates
1313 * combined mode is a bad idea. Yield to ata_piix.
1314 */
1315 pci_read_config_byte(pdev, ICH_MAP, &map);
1316 if (map & 0x3) {
a44fec1f
JP		 1317 dev_info(&pdev->dev,
1318 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1319 return -ENODEV;
1320 }
1321 }
1322
6fec8871
PB		 1323 /* AHCI controllers often implement SFF compatible interface.
1324 * Grab all PCI BARs just in case.
1325 */
1326 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1327 if (rc == -EBUSY)
1328 pcim_pin_device(pdev);
1329 if (rc)
1330 return rc;
1331
24dc5f33
TH		 1332 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1333 if (!hpriv)
1334 return -ENOMEM;
417a1a6d
TH		 1335 hpriv->flags |= (unsigned long)pi.private_data;
1336
e297d99e
TH		 1337 /* MCP65 revision A1 and A2 can't do MSI */
1338 if (board_id == board_ahci_mcp65 &&
1339 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1340 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1341
e427fe04
SH		 1342 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1343 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1344 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1345
2fcad9d2
TH		 1346 /* only some SB600s can do 64bit DMA */
1347 if (ahci_sb600_enable_64bit(pdev))
1348 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1349
318893e1 1350 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1351
0cf4a7d6
JP		 1352 /* must set flag prior to save config in order to take effect */
1353 if (ahci_broken_devslp(pdev))
1354 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1355
4447d351 1356 /* save initial config */
394d6e53 1357 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1358
4447d351 1359 /* prepare host */
453d3131
RH		 1360 if (hpriv->cap & HOST_CAP_NCQ) {
1361 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1362 /*
1363 * Auto-activate optimization is supposed to be
1364 * supported on all AHCI controllers indicating NCQ
1365 * capability, but it seems to be broken on some
1366 * chipsets including NVIDIAs.
1367 */
1368 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1369 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1370
1371 /*
1372 * All AHCI controllers should be forward-compatible
1373 * with the new auxiliary field. This code should be
1374 * conditionalized if any buggy AHCI controllers are
1375 * encountered.
1376 */
1377 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1378 }
1da177e4 1379
7d50b60b
TH		 1380 if (hpriv->cap & HOST_CAP_PMP)
1381 pi.flags |= ATA_FLAG_PMP;
1382
0cbb0e77 1383 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1384
1fd68434
RW		 1385 if (ahci_broken_system_poweroff(pdev)) {
1386 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1387 dev_info(&pdev->dev,
1388 "quirky BIOS, skipping spindown on poweroff\n");
1389 }
1390
9b10ae86
TH		 1391 if (ahci_broken_suspend(pdev)) {
1392 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1393 dev_warn(&pdev->dev,
1394 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1395 }
1396
5594639a
TH		 1397 if (ahci_broken_online(pdev)) {
1398 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1399 dev_info(&pdev->dev,
1400 "online status unreliable, applying workaround\n");
1401 }
1402
837f5f8f
TH		 1403 /* CAP.NP sometimes indicate the index of the last enabled
1404 * port, at other times, that of the last possible port, so
1405 * determining the maximum port number requires looking at
1406 * both CAP.NP and port_map.
1407 */
1408 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1409
c3ebd6a9 1410 ahci_init_interrupts(pdev, n_ports, hpriv);
7b92b4f6 1411
837f5f8f 1412 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1413 if (!host)
1414 return -ENOMEM;
4447d351
TH		 1415 host->private_data = hpriv;
1416
f3d7f23f 1417 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1418 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1419 else
d2782d96 1420 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1421
18f7ba4c
KCA		 1422 if (pi.flags & ATA_FLAG_EM)
1423 ahci_reset_em(host);
1424
4447d351 1425 for (i = 0; i < host->n_ports; i++) {
dab632e8 1426 struct ata_port *ap = host->ports[i];
4447d351 1427
318893e1
AR		 1428 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1429 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1430 0x100 + ap->port_no * 0x80, "port");
1431
18f7ba4c
KCA		 1432 /* set enclosure management message type */
1433 if (ap->flags & ATA_FLAG_EM)
008dbd61 1434 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1435
1436
dab632e8 1437 /* disabled/not-implemented port */
350756f6 1438 if (!(hpriv->port_map & (1 << i)))
dab632e8 1439 ap->ops = &ata_dummy_port_ops;
4447d351 1440 }
d447df14 1441
edc93052
TH		 1442 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1443 ahci_p5wdh_workaround(host);
1444
f80ae7e4
TH		 1445 /* apply gtf filter quirk */
1446 ahci_gtf_filter_workaround(host);
1447
4447d351
TH		 1448 /* initialize adapter */
1449 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1450 if (rc)
24dc5f33 1451 return rc;
1da177e4 1452
3303040d 1453 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1454 if (rc)
1455 return rc;
1da177e4 1456
781d6550 1457 ahci_pci_init_controller(host);
439fcaec 1458 ahci_pci_print_info(host);
1da177e4 1459
4447d351 1460 pci_set_master(pdev);
5ca72c4f 1461
d1028e2f 1462 return ahci_host_activate(host, pdev->irq, &ahci_sht);
907f4678 1463}
1da177e4 1464
2fc75da0 1465module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1466
1467MODULE_AUTHOR("Jeff Garzik");
1468MODULE_DESCRIPTION("AHCI SATA low-level driver");
1469MODULE_LICENSE("GPL");
1470MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1471MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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