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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "ahci" | |
cb48cab7 | 49 | #define DRV_VERSION "2.1" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | AHCI_PCI_BAR = 5, | |
648a88be | 54 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
56 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
57 | AHCI_USE_CLUSTERING = 0, | |
12fad3f9 | 58 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 59 | AHCI_CMD_SZ = 32, |
12fad3f9 | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 61 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
67 | AHCI_RX_FIS_SZ, |
68 | AHCI_IRQ_ON_SG = (1 << 31), | |
69 | AHCI_CMD_ATAPI = (1 << 5), | |
70 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
72 | AHCI_CMD_RESET = (1 << 8), |
73 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
74 | |
75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
648a88be TH |
80 | board_ahci_pi = 1, |
81 | board_ahci_vt8251 = 2, | |
82 | board_ahci_ign_iferr = 3, | |
55a61604 | 83 | board_ahci_sb600 = 4, |
1da177e4 LT |
84 | |
85 | /* global controller registers */ | |
86 | HOST_CAP = 0x00, /* host capabilities */ | |
87 | HOST_CTL = 0x04, /* global host control */ | |
88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
91 | ||
92 | /* HOST_CTL bits */ | |
93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
96 | ||
97 | /* HOST_CAP bits */ | |
0be0aa98 | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 99 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 100 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
979db803 | 101 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 102 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
103 | |
104 | /* registers for each SATA port */ | |
105 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
106 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
107 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
108 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
109 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
110 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
111 | PORT_CMD = 0x18, /* port command */ | |
112 | PORT_TFDATA = 0x20, /* taskfile data */ | |
113 | PORT_SIG = 0x24, /* device TF signature */ | |
114 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
115 | PORT_SCR = 0x28, /* SATA phy register block */ | |
116 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
117 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
118 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
119 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
120 | ||
121 | /* PORT_IRQ_{STAT,MASK} bits */ | |
122 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
123 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
124 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
125 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
126 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
127 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
128 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
129 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
130 | ||
131 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
132 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
133 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
134 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
135 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
136 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
137 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
138 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
139 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
140 | ||
78cd52d0 TH |
141 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
142 | PORT_IRQ_IF_ERR | | |
143 | PORT_IRQ_CONNECT | | |
4296971d | 144 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
145 | PORT_IRQ_UNK_FIS, |
146 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
147 | PORT_IRQ_TF_ERR | | |
148 | PORT_IRQ_HBUS_DATA_ERR, | |
149 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
150 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
151 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
152 | |
153 | /* PORT_CMD bits */ | |
02eaa666 | 154 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
155 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
156 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
157 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 158 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
159 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
160 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
161 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
162 | ||
0be0aa98 | 163 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
164 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
165 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
166 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 167 | |
bf2af2a2 | 168 | /* ap->flags bits */ |
4aeb0e32 TH |
169 | AHCI_FLAG_NO_NCQ = (1 << 24), |
170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | |
648a88be | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
55a61604 | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
1da177e4 LT |
173 | }; |
174 | ||
175 | struct ahci_cmd_hdr { | |
176 | u32 opts; | |
177 | u32 status; | |
178 | u32 tbl_addr; | |
179 | u32 tbl_addr_hi; | |
180 | u32 reserved[4]; | |
181 | }; | |
182 | ||
183 | struct ahci_sg { | |
184 | u32 addr; | |
185 | u32 addr_hi; | |
186 | u32 reserved; | |
187 | u32 flags_size; | |
188 | }; | |
189 | ||
190 | struct ahci_host_priv { | |
d447df14 TH |
191 | u32 cap; /* cap to use */ |
192 | u32 port_map; /* port map to use */ | |
193 | u32 saved_cap; /* saved initial cap */ | |
194 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
195 | }; |
196 | ||
197 | struct ahci_port_priv { | |
198 | struct ahci_cmd_hdr *cmd_slot; | |
199 | dma_addr_t cmd_slot_dma; | |
200 | void *cmd_tbl; | |
201 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
202 | void *rx_fis; |
203 | dma_addr_t rx_fis_dma; | |
0291f95f | 204 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
205 | unsigned int ncq_saw_d2h:1; |
206 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 207 | unsigned int ncq_saw_sdb:1; |
1da177e4 LT |
208 | }; |
209 | ||
210 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
211 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
212 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 213 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
7d12e780 | 214 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance); |
1da177e4 | 215 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
216 | static int ahci_port_start(struct ata_port *ap); |
217 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
218 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
219 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
220 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
221 | static void ahci_freeze(struct ata_port *ap); |
222 | static void ahci_thaw(struct ata_port *ap); | |
223 | static void ahci_error_handler(struct ata_port *ap); | |
ad616ffb | 224 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 225 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
438ac6d5 | 226 | #ifdef CONFIG_PM |
c1332875 TH |
227 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
228 | static int ahci_port_resume(struct ata_port *ap); | |
229 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
230 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 231 | #endif |
1da177e4 | 232 | |
193515d5 | 233 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
234 | .module = THIS_MODULE, |
235 | .name = DRV_NAME, | |
236 | .ioctl = ata_scsi_ioctl, | |
237 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
238 | .change_queue_depth = ata_scsi_change_queue_depth, |
239 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
240 | .this_id = ATA_SHT_THIS_ID, |
241 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
242 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
243 | .emulated = ATA_SHT_EMULATED, | |
244 | .use_clustering = AHCI_USE_CLUSTERING, | |
245 | .proc_name = DRV_NAME, | |
246 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
247 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 248 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 249 | .bios_param = ata_std_bios_param, |
438ac6d5 | 250 | #ifdef CONFIG_PM |
c1332875 TH |
251 | .suspend = ata_scsi_device_suspend, |
252 | .resume = ata_scsi_device_resume, | |
438ac6d5 | 253 | #endif |
1da177e4 LT |
254 | }; |
255 | ||
057ace5e | 256 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
257 | .port_disable = ata_port_disable, |
258 | ||
259 | .check_status = ahci_check_status, | |
260 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
261 | .dev_select = ata_noop_dev_select, |
262 | ||
263 | .tf_read = ahci_tf_read, | |
264 | ||
1da177e4 LT |
265 | .qc_prep = ahci_qc_prep, |
266 | .qc_issue = ahci_qc_issue, | |
267 | ||
1da177e4 LT |
268 | .irq_handler = ahci_interrupt, |
269 | .irq_clear = ahci_irq_clear, | |
246ce3b6 AI |
270 | .irq_on = ata_dummy_irq_on, |
271 | .irq_ack = ata_dummy_irq_ack, | |
1da177e4 LT |
272 | |
273 | .scr_read = ahci_scr_read, | |
274 | .scr_write = ahci_scr_write, | |
275 | ||
78cd52d0 TH |
276 | .freeze = ahci_freeze, |
277 | .thaw = ahci_thaw, | |
278 | ||
279 | .error_handler = ahci_error_handler, | |
280 | .post_internal_cmd = ahci_post_internal_cmd, | |
281 | ||
438ac6d5 | 282 | #ifdef CONFIG_PM |
c1332875 TH |
283 | .port_suspend = ahci_port_suspend, |
284 | .port_resume = ahci_port_resume, | |
438ac6d5 | 285 | #endif |
c1332875 | 286 | |
1da177e4 LT |
287 | .port_start = ahci_port_start, |
288 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
289 | }; |
290 | ||
ad616ffb TH |
291 | static const struct ata_port_operations ahci_vt8251_ops = { |
292 | .port_disable = ata_port_disable, | |
293 | ||
294 | .check_status = ahci_check_status, | |
295 | .check_altstatus = ahci_check_status, | |
296 | .dev_select = ata_noop_dev_select, | |
297 | ||
298 | .tf_read = ahci_tf_read, | |
299 | ||
300 | .qc_prep = ahci_qc_prep, | |
301 | .qc_issue = ahci_qc_issue, | |
302 | ||
303 | .irq_handler = ahci_interrupt, | |
304 | .irq_clear = ahci_irq_clear, | |
246ce3b6 AI |
305 | .irq_on = ata_dummy_irq_on, |
306 | .irq_ack = ata_dummy_irq_ack, | |
ad616ffb TH |
307 | |
308 | .scr_read = ahci_scr_read, | |
309 | .scr_write = ahci_scr_write, | |
310 | ||
311 | .freeze = ahci_freeze, | |
312 | .thaw = ahci_thaw, | |
313 | ||
314 | .error_handler = ahci_vt8251_error_handler, | |
315 | .post_internal_cmd = ahci_post_internal_cmd, | |
316 | ||
438ac6d5 | 317 | #ifdef CONFIG_PM |
ad616ffb TH |
318 | .port_suspend = ahci_port_suspend, |
319 | .port_resume = ahci_port_resume, | |
438ac6d5 | 320 | #endif |
ad616ffb TH |
321 | |
322 | .port_start = ahci_port_start, | |
323 | .port_stop = ahci_port_stop, | |
324 | }; | |
325 | ||
98ac62de | 326 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
327 | /* board_ahci */ |
328 | { | |
329 | .sht = &ahci_sht, | |
cca3974e | 330 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
4296971d TH |
331 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
332 | ATA_FLAG_SKIP_D2H_BSY, | |
7da79312 | 333 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
334 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
335 | .port_ops = &ahci_ops, | |
336 | }, | |
648a88be TH |
337 | /* board_ahci_pi */ |
338 | { | |
339 | .sht = &ahci_sht, | |
340 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
341 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
342 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, | |
343 | .pio_mask = 0x1f, /* pio0-4 */ | |
344 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
345 | .port_ops = &ahci_ops, | |
346 | }, | |
bf2af2a2 BJ |
347 | /* board_ahci_vt8251 */ |
348 | { | |
349 | .sht = &ahci_sht, | |
cca3974e | 350 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
bf2af2a2 | 351 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
ad616ffb TH |
352 | ATA_FLAG_SKIP_D2H_BSY | |
353 | ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ, | |
bf2af2a2 BJ |
354 | .pio_mask = 0x1f, /* pio0-4 */ |
355 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
ad616ffb | 356 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 357 | }, |
41669553 TH |
358 | /* board_ahci_ign_iferr */ |
359 | { | |
360 | .sht = &ahci_sht, | |
361 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
362 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
363 | ATA_FLAG_SKIP_D2H_BSY | | |
364 | AHCI_FLAG_IGN_IRQ_IF_ERR, | |
365 | .pio_mask = 0x1f, /* pio0-4 */ | |
366 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
367 | .port_ops = &ahci_ops, | |
368 | }, | |
55a61604 CH |
369 | /* board_ahci_sb600 */ |
370 | { | |
371 | .sht = &ahci_sht, | |
372 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
373 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
374 | ATA_FLAG_SKIP_D2H_BSY | | |
375 | AHCI_FLAG_IGN_SERR_INTERNAL, | |
376 | .pio_mask = 0x1f, /* pio0-4 */ | |
377 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
378 | .port_ops = &ahci_ops, | |
379 | }, | |
380 | ||
1da177e4 LT |
381 | }; |
382 | ||
3b7d697d | 383 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 384 | /* Intel */ |
54bb3a94 JG |
385 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
386 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
387 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
388 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
389 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 390 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
391 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
392 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
393 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
394 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
648a88be TH |
395 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
396 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ | |
397 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ | |
398 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ | |
399 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ | |
400 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ | |
401 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ | |
402 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ | |
403 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ | |
404 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ | |
405 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ | |
406 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ | |
407 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ | |
8af12cdb | 408 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
648a88be TH |
409 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
410 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ | |
411 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ | |
fe7fa31a | 412 | |
e34bb370 TH |
413 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
414 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
415 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
416 | |
417 | /* ATI */ | |
c65ec1c2 | 418 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
fe7fa31a JG |
419 | |
420 | /* VIA */ | |
54bb3a94 | 421 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 422 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
423 | |
424 | /* NVIDIA */ | |
54bb3a94 JG |
425 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
426 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
427 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
428 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
429 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
430 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
431 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
432 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
433 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
435 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
437 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
438 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
443 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
fe7fa31a | 445 | |
95916edd | 446 | /* SiS */ |
54bb3a94 JG |
447 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
448 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
449 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 450 | |
415ae2b5 JG |
451 | /* Generic, PCI class code for AHCI */ |
452 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 453 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 454 | |
1da177e4 LT |
455 | { } /* terminate list */ |
456 | }; | |
457 | ||
458 | ||
459 | static struct pci_driver ahci_pci_driver = { | |
460 | .name = DRV_NAME, | |
461 | .id_table = ahci_pci_tbl, | |
462 | .probe = ahci_init_one, | |
24dc5f33 | 463 | .remove = ata_pci_remove_one, |
438ac6d5 | 464 | #ifdef CONFIG_PM |
c1332875 TH |
465 | .suspend = ahci_pci_device_suspend, |
466 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 467 | #endif |
1da177e4 LT |
468 | }; |
469 | ||
470 | ||
98fa4b60 TH |
471 | static inline int ahci_nr_ports(u32 cap) |
472 | { | |
473 | return (cap & 0x1f) + 1; | |
474 | } | |
475 | ||
0d5ff566 TH |
476 | static inline void __iomem *ahci_port_base(void __iomem *base, |
477 | unsigned int port) | |
1da177e4 LT |
478 | { |
479 | return base + 0x100 + (port * 0x80); | |
480 | } | |
481 | ||
d447df14 TH |
482 | /** |
483 | * ahci_save_initial_config - Save and fixup initial config values | |
484 | * @probe_ent: probe_ent of target device | |
485 | * | |
486 | * Some registers containing configuration info might be setup by | |
487 | * BIOS and might be cleared on reset. This function saves the | |
488 | * initial values of those registers into @hpriv such that they | |
489 | * can be restored after controller reset. | |
490 | * | |
491 | * If inconsistent, config values are fixed up by this function. | |
492 | * | |
493 | * LOCKING: | |
494 | * None. | |
495 | */ | |
496 | static void ahci_save_initial_config(struct ata_probe_ent *probe_ent) | |
497 | { | |
498 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
499 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; | |
500 | u32 cap, port_map; | |
17199b18 | 501 | int i; |
d447df14 TH |
502 | |
503 | /* Values prefixed with saved_ are written back to host after | |
504 | * reset. Values without are used for driver operation. | |
505 | */ | |
506 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
507 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
508 | ||
509 | /* fixup zero port_map */ | |
510 | if (!port_map) { | |
511 | port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1; | |
512 | dev_printk(KERN_WARNING, probe_ent->dev, | |
513 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); | |
514 | ||
515 | /* write the fixed up value to the PI register */ | |
516 | hpriv->saved_port_map = port_map; | |
517 | } | |
518 | ||
17199b18 TH |
519 | /* cross check port_map and cap.n_ports */ |
520 | if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { | |
521 | u32 tmp_port_map = port_map; | |
522 | int n_ports = ahci_nr_ports(cap); | |
523 | ||
524 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
525 | if (tmp_port_map & (1 << i)) { | |
526 | n_ports--; | |
527 | tmp_port_map &= ~(1 << i); | |
528 | } | |
529 | } | |
530 | ||
531 | /* Whine if inconsistent. No need to update cap. | |
532 | * port_map is used to determine number of ports. | |
533 | */ | |
534 | if (n_ports || tmp_port_map) | |
535 | dev_printk(KERN_WARNING, probe_ent->dev, | |
536 | "nr_ports (%u) and implemented port map " | |
537 | "(0x%x) don't match\n", | |
538 | ahci_nr_ports(cap), port_map); | |
539 | } else { | |
540 | /* fabricate port_map from cap.nr_ports */ | |
541 | port_map = (1 << ahci_nr_ports(cap)) - 1; | |
542 | } | |
543 | ||
d447df14 TH |
544 | /* record values to use during operation */ |
545 | hpriv->cap = cap; | |
546 | hpriv->port_map = port_map; | |
547 | } | |
548 | ||
549 | /** | |
550 | * ahci_restore_initial_config - Restore initial config | |
551 | * @mmio: MMIO base for the host | |
552 | * @hpriv: host private data | |
553 | * | |
554 | * Restore initial config stored by ahci_save_initial_config(). | |
555 | * | |
556 | * LOCKING: | |
557 | * None. | |
558 | */ | |
559 | static void ahci_restore_initial_config(void __iomem *mmio, | |
560 | struct ahci_host_priv *hpriv) | |
561 | { | |
562 | writel(hpriv->saved_cap, mmio + HOST_CAP); | |
563 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
564 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
565 | } | |
566 | ||
1da177e4 LT |
567 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
568 | { | |
569 | unsigned int sc_reg; | |
570 | ||
571 | switch (sc_reg_in) { | |
572 | case SCR_STATUS: sc_reg = 0; break; | |
573 | case SCR_CONTROL: sc_reg = 1; break; | |
574 | case SCR_ERROR: sc_reg = 2; break; | |
575 | case SCR_ACTIVE: sc_reg = 3; break; | |
576 | default: | |
577 | return 0xffffffffU; | |
578 | } | |
579 | ||
0d5ff566 | 580 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
581 | } |
582 | ||
583 | ||
584 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
585 | u32 val) | |
586 | { | |
587 | unsigned int sc_reg; | |
588 | ||
589 | switch (sc_reg_in) { | |
590 | case SCR_STATUS: sc_reg = 0; break; | |
591 | case SCR_CONTROL: sc_reg = 1; break; | |
592 | case SCR_ERROR: sc_reg = 2; break; | |
593 | case SCR_ACTIVE: sc_reg = 3; break; | |
594 | default: | |
595 | return; | |
596 | } | |
597 | ||
0d5ff566 | 598 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
599 | } |
600 | ||
9f592056 | 601 | static void ahci_start_engine(void __iomem *port_mmio) |
7c76d1e8 | 602 | { |
7c76d1e8 TH |
603 | u32 tmp; |
604 | ||
d8fcd116 | 605 | /* start DMA */ |
9f592056 | 606 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
607 | tmp |= PORT_CMD_START; |
608 | writel(tmp, port_mmio + PORT_CMD); | |
609 | readl(port_mmio + PORT_CMD); /* flush */ | |
610 | } | |
611 | ||
254950cd TH |
612 | static int ahci_stop_engine(void __iomem *port_mmio) |
613 | { | |
614 | u32 tmp; | |
615 | ||
616 | tmp = readl(port_mmio + PORT_CMD); | |
617 | ||
d8fcd116 | 618 | /* check if the HBA is idle */ |
254950cd TH |
619 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
620 | return 0; | |
621 | ||
d8fcd116 | 622 | /* setting HBA to idle */ |
254950cd TH |
623 | tmp &= ~PORT_CMD_START; |
624 | writel(tmp, port_mmio + PORT_CMD); | |
625 | ||
d8fcd116 | 626 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
627 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
628 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 629 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
630 | return -EIO; |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
0be0aa98 TH |
635 | static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, |
636 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
637 | { | |
638 | u32 tmp; | |
639 | ||
640 | /* set FIS registers */ | |
641 | if (cap & HOST_CAP_64) | |
642 | writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
643 | writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
644 | ||
645 | if (cap & HOST_CAP_64) | |
646 | writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
647 | writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
648 | ||
649 | /* enable FIS reception */ | |
650 | tmp = readl(port_mmio + PORT_CMD); | |
651 | tmp |= PORT_CMD_FIS_RX; | |
652 | writel(tmp, port_mmio + PORT_CMD); | |
653 | ||
654 | /* flush */ | |
655 | readl(port_mmio + PORT_CMD); | |
656 | } | |
657 | ||
658 | static int ahci_stop_fis_rx(void __iomem *port_mmio) | |
659 | { | |
660 | u32 tmp; | |
661 | ||
662 | /* disable FIS reception */ | |
663 | tmp = readl(port_mmio + PORT_CMD); | |
664 | tmp &= ~PORT_CMD_FIS_RX; | |
665 | writel(tmp, port_mmio + PORT_CMD); | |
666 | ||
667 | /* wait for completion, spec says 500ms, give it 1000 */ | |
668 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
669 | PORT_CMD_FIS_ON, 10, 1000); | |
670 | if (tmp & PORT_CMD_FIS_ON) | |
671 | return -EBUSY; | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | static void ahci_power_up(void __iomem *port_mmio, u32 cap) | |
677 | { | |
678 | u32 cmd; | |
679 | ||
680 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
681 | ||
682 | /* spin up device */ | |
683 | if (cap & HOST_CAP_SSS) { | |
684 | cmd |= PORT_CMD_SPIN_UP; | |
685 | writel(cmd, port_mmio + PORT_CMD); | |
686 | } | |
687 | ||
688 | /* wake up link */ | |
689 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
690 | } | |
691 | ||
438ac6d5 | 692 | #ifdef CONFIG_PM |
0be0aa98 TH |
693 | static void ahci_power_down(void __iomem *port_mmio, u32 cap) |
694 | { | |
695 | u32 cmd, scontrol; | |
696 | ||
07c53dac TH |
697 | if (!(cap & HOST_CAP_SSS)) |
698 | return; | |
0be0aa98 | 699 | |
07c53dac TH |
700 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
701 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
702 | scontrol &= ~0xf; | |
703 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 704 | |
07c53dac TH |
705 | /* then set PxCMD.SUD to 0 */ |
706 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
707 | cmd &= ~PORT_CMD_SPIN_UP; | |
708 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 709 | } |
438ac6d5 | 710 | #endif |
0be0aa98 TH |
711 | |
712 | static void ahci_init_port(void __iomem *port_mmio, u32 cap, | |
713 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
714 | { | |
0be0aa98 TH |
715 | /* enable FIS reception */ |
716 | ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); | |
717 | ||
718 | /* enable DMA */ | |
719 | ahci_start_engine(port_mmio); | |
720 | } | |
721 | ||
722 | static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | |
723 | { | |
724 | int rc; | |
725 | ||
726 | /* disable DMA */ | |
727 | rc = ahci_stop_engine(port_mmio); | |
728 | if (rc) { | |
729 | *emsg = "failed to stop engine"; | |
730 | return rc; | |
731 | } | |
732 | ||
733 | /* disable FIS reception */ | |
734 | rc = ahci_stop_fis_rx(port_mmio); | |
735 | if (rc) { | |
736 | *emsg = "failed stop FIS RX"; | |
737 | return rc; | |
738 | } | |
739 | ||
0be0aa98 TH |
740 | return 0; |
741 | } | |
742 | ||
d447df14 TH |
743 | static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev, |
744 | struct ahci_host_priv *hpriv) | |
d91542c1 | 745 | { |
d447df14 | 746 | u32 tmp; |
d91542c1 TH |
747 | |
748 | /* global controller reset */ | |
749 | tmp = readl(mmio + HOST_CTL); | |
750 | if ((tmp & HOST_RESET) == 0) { | |
751 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
752 | readl(mmio + HOST_CTL); /* flush */ | |
753 | } | |
754 | ||
755 | /* reset must complete within 1 second, or | |
756 | * the hardware should be considered fried. | |
757 | */ | |
758 | ssleep(1); | |
759 | ||
760 | tmp = readl(mmio + HOST_CTL); | |
761 | if (tmp & HOST_RESET) { | |
762 | dev_printk(KERN_ERR, &pdev->dev, | |
763 | "controller reset failed (0x%x)\n", tmp); | |
764 | return -EIO; | |
765 | } | |
766 | ||
98fa4b60 | 767 | /* turn on AHCI mode */ |
d91542c1 TH |
768 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
769 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 | 770 | |
d447df14 TH |
771 | /* some registers might be cleared on reset. restore initial values */ |
772 | ahci_restore_initial_config(mmio, hpriv); | |
d91542c1 TH |
773 | |
774 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
775 | u16 tmp16; | |
776 | ||
777 | /* configure PCS */ | |
778 | pci_read_config_word(pdev, 0x92, &tmp16); | |
779 | tmp16 |= 0xf; | |
780 | pci_write_config_word(pdev, 0x92, tmp16); | |
781 | } | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |
648a88be TH |
787 | int n_ports, unsigned int port_flags, |
788 | struct ahci_host_priv *hpriv) | |
d91542c1 TH |
789 | { |
790 | int i, rc; | |
791 | u32 tmp; | |
792 | ||
793 | for (i = 0; i < n_ports; i++) { | |
794 | void __iomem *port_mmio = ahci_port_base(mmio, i); | |
795 | const char *emsg = NULL; | |
796 | ||
648a88be TH |
797 | if ((port_flags & AHCI_FLAG_HONOR_PI) && |
798 | !(hpriv->port_map & (1 << i))) | |
d91542c1 | 799 | continue; |
d91542c1 TH |
800 | |
801 | /* make sure port is not active */ | |
648a88be | 802 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); |
d91542c1 TH |
803 | if (rc) |
804 | dev_printk(KERN_WARNING, &pdev->dev, | |
805 | "%s (%d)\n", emsg, rc); | |
806 | ||
807 | /* clear SError */ | |
808 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
809 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
810 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
811 | ||
f4b5cc87 | 812 | /* clear port IRQ */ |
d91542c1 TH |
813 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
814 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
815 | if (tmp) | |
816 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
817 | ||
818 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
d91542c1 TH |
819 | } |
820 | ||
821 | tmp = readl(mmio + HOST_CTL); | |
822 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
823 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
824 | tmp = readl(mmio + HOST_CTL); | |
825 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
826 | } | |
827 | ||
422b7595 | 828 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 829 | { |
0d5ff566 | 830 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 831 | struct ata_taskfile tf; |
422b7595 TH |
832 | u32 tmp; |
833 | ||
834 | tmp = readl(port_mmio + PORT_SIG); | |
835 | tf.lbah = (tmp >> 24) & 0xff; | |
836 | tf.lbam = (tmp >> 16) & 0xff; | |
837 | tf.lbal = (tmp >> 8) & 0xff; | |
838 | tf.nsect = (tmp) & 0xff; | |
839 | ||
840 | return ata_dev_classify(&tf); | |
841 | } | |
842 | ||
12fad3f9 TH |
843 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
844 | u32 opts) | |
cc9278ed | 845 | { |
12fad3f9 TH |
846 | dma_addr_t cmd_tbl_dma; |
847 | ||
848 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
849 | ||
850 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
851 | pp->cmd_slot[tag].status = 0; | |
852 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
853 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
854 | } |
855 | ||
bf2af2a2 | 856 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 857 | { |
0d5ff566 | 858 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 859 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 BJ |
860 | u32 tmp; |
861 | ||
862 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
863 | return -EOPNOTSUPP; | |
864 | ||
865 | tmp = readl(port_mmio + PORT_CMD); | |
866 | tmp |= PORT_CMD_CLO; | |
867 | writel(tmp, port_mmio + PORT_CMD); | |
868 | ||
869 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
870 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
871 | if (tmp & PORT_CMD_CLO) | |
872 | return -EIO; | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |
878 | { | |
4658f79b | 879 | struct ahci_port_priv *pp = ap->private_data; |
0d5ff566 | 880 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4658f79b TH |
881 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
882 | const u32 cmd_fis_len = 5; /* five dwords */ | |
883 | const char *reason = NULL; | |
884 | struct ata_taskfile tf; | |
75fe1806 | 885 | u32 tmp; |
4658f79b TH |
886 | u8 *fis; |
887 | int rc; | |
888 | ||
889 | DPRINTK("ENTER\n"); | |
890 | ||
81952c54 | 891 | if (ata_port_offline(ap)) { |
c2a65852 TH |
892 | DPRINTK("PHY reports no device\n"); |
893 | *class = ATA_DEV_NONE; | |
894 | return 0; | |
895 | } | |
896 | ||
4658f79b | 897 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
5457f219 | 898 | rc = ahci_stop_engine(port_mmio); |
4658f79b TH |
899 | if (rc) { |
900 | reason = "failed to stop engine"; | |
901 | goto fail_restart; | |
902 | } | |
903 | ||
904 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
1244a19c | 905 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
bf2af2a2 | 906 | rc = ahci_clo(ap); |
4658f79b | 907 | |
bf2af2a2 BJ |
908 | if (rc == -EOPNOTSUPP) { |
909 | reason = "port busy but CLO unavailable"; | |
910 | goto fail_restart; | |
911 | } else if (rc) { | |
912 | reason = "port busy but CLO failed"; | |
4658f79b TH |
913 | goto fail_restart; |
914 | } | |
915 | } | |
916 | ||
917 | /* restart engine */ | |
5457f219 | 918 | ahci_start_engine(port_mmio); |
4658f79b | 919 | |
3373efd8 | 920 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
921 | fis = pp->cmd_tbl; |
922 | ||
923 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
924 | ahci_fill_cmd_slot(pp, 0, |
925 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
926 | |
927 | tf.ctl |= ATA_SRST; | |
928 | ata_tf_to_fis(&tf, fis, 0); | |
929 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
930 | ||
931 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 932 | |
75fe1806 TH |
933 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
934 | if (tmp & 0x1) { | |
4658f79b TH |
935 | rc = -EIO; |
936 | reason = "1st FIS failed"; | |
937 | goto fail; | |
938 | } | |
939 | ||
940 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
941 | msleep(1); | |
942 | ||
943 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 944 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
945 | |
946 | tf.ctl &= ~ATA_SRST; | |
947 | ata_tf_to_fis(&tf, fis, 0); | |
948 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
949 | ||
950 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
951 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
952 | ||
953 | /* spec mandates ">= 2ms" before checking status. | |
954 | * We wait 150ms, because that was the magic delay used for | |
955 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
956 | * between when the ATA command register is written, and then | |
957 | * status is checked. Because waiting for "a while" before | |
958 | * checking status is fine, post SRST, we perform this magic | |
959 | * delay here as well. | |
960 | */ | |
961 | msleep(150); | |
962 | ||
963 | *class = ATA_DEV_NONE; | |
81952c54 | 964 | if (ata_port_online(ap)) { |
4658f79b TH |
965 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
966 | rc = -EIO; | |
967 | reason = "device not ready"; | |
968 | goto fail; | |
969 | } | |
970 | *class = ahci_dev_classify(ap); | |
971 | } | |
972 | ||
973 | DPRINTK("EXIT, class=%u\n", *class); | |
974 | return 0; | |
975 | ||
976 | fail_restart: | |
5457f219 | 977 | ahci_start_engine(port_mmio); |
4658f79b | 978 | fail: |
f15a1daf | 979 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
980 | return rc; |
981 | } | |
982 | ||
2bf2cb26 | 983 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
422b7595 | 984 | { |
4296971d TH |
985 | struct ahci_port_priv *pp = ap->private_data; |
986 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
987 | struct ata_taskfile tf; | |
0d5ff566 | 988 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 989 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
4bd00f6a TH |
990 | int rc; |
991 | ||
992 | DPRINTK("ENTER\n"); | |
1da177e4 | 993 | |
5457f219 | 994 | ahci_stop_engine(port_mmio); |
4296971d TH |
995 | |
996 | /* clear D2H reception area to properly wait for D2H FIS */ | |
997 | ata_tf_init(ap->device, &tf); | |
dfd7a3db | 998 | tf.command = 0x80; |
4296971d TH |
999 | ata_tf_to_fis(&tf, d2h_fis, 0); |
1000 | ||
2bf2cb26 | 1001 | rc = sata_std_hardreset(ap, class); |
4296971d | 1002 | |
5457f219 | 1003 | ahci_start_engine(port_mmio); |
1da177e4 | 1004 | |
81952c54 | 1005 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
1006 | *class = ahci_dev_classify(ap); |
1007 | if (*class == ATA_DEV_UNKNOWN) | |
1008 | *class = ATA_DEV_NONE; | |
1da177e4 | 1009 | |
4bd00f6a TH |
1010 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1011 | return rc; | |
1012 | } | |
1013 | ||
ad616ffb TH |
1014 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) |
1015 | { | |
0d5ff566 | 1016 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ad616ffb TH |
1017 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1018 | int rc; | |
1019 | ||
1020 | DPRINTK("ENTER\n"); | |
1021 | ||
1022 | ahci_stop_engine(port_mmio); | |
1023 | ||
1024 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); | |
1025 | ||
1026 | /* vt8251 needs SError cleared for the port to operate */ | |
1027 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); | |
1028 | ||
1029 | ahci_start_engine(port_mmio); | |
1030 | ||
1031 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1032 | ||
1033 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1034 | * request follow-up softreset. | |
1035 | */ | |
1036 | return rc ?: -EAGAIN; | |
1037 | } | |
1038 | ||
4bd00f6a TH |
1039 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
1040 | { | |
0d5ff566 | 1041 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
4bd00f6a TH |
1042 | u32 new_tmp, tmp; |
1043 | ||
1044 | ata_std_postreset(ap, class); | |
02eaa666 JG |
1045 | |
1046 | /* Make sure port's ATAPI bit is set appropriately */ | |
1047 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1048 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1049 | new_tmp |= PORT_CMD_ATAPI; |
1050 | else | |
1051 | new_tmp &= ~PORT_CMD_ATAPI; | |
1052 | if (new_tmp != tmp) { | |
1053 | writel(new_tmp, port_mmio + PORT_CMD); | |
1054 | readl(port_mmio + PORT_CMD); /* flush */ | |
1055 | } | |
1da177e4 LT |
1056 | } |
1057 | ||
1058 | static u8 ahci_check_status(struct ata_port *ap) | |
1059 | { | |
0d5ff566 | 1060 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1061 | |
1062 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1063 | } | |
1064 | ||
1da177e4 LT |
1065 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1066 | { | |
1067 | struct ahci_port_priv *pp = ap->private_data; | |
1068 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1069 | ||
1070 | ata_tf_from_fis(d2h_fis, tf); | |
1071 | } | |
1072 | ||
12fad3f9 | 1073 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1074 | { |
cedc9a47 JG |
1075 | struct scatterlist *sg; |
1076 | struct ahci_sg *ahci_sg; | |
828d09de | 1077 | unsigned int n_sg = 0; |
1da177e4 LT |
1078 | |
1079 | VPRINTK("ENTER\n"); | |
1080 | ||
1081 | /* | |
1082 | * Next, the S/G list. | |
1083 | */ | |
12fad3f9 | 1084 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1085 | ata_for_each_sg(sg, qc) { |
1086 | dma_addr_t addr = sg_dma_address(sg); | |
1087 | u32 sg_len = sg_dma_len(sg); | |
1088 | ||
1089 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1090 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1091 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1092 | |
cedc9a47 | 1093 | ahci_sg++; |
828d09de | 1094 | n_sg++; |
1da177e4 | 1095 | } |
828d09de JG |
1096 | |
1097 | return n_sg; | |
1da177e4 LT |
1098 | } |
1099 | ||
1100 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1101 | { | |
a0ea7328 JG |
1102 | struct ata_port *ap = qc->ap; |
1103 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1104 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1105 | void *cmd_tbl; |
1da177e4 LT |
1106 | u32 opts; |
1107 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1108 | unsigned int n_elem; |
1da177e4 | 1109 | |
1da177e4 LT |
1110 | /* |
1111 | * Fill in command table information. First, the header, | |
1112 | * a SATA Register - Host to Device command FIS. | |
1113 | */ | |
12fad3f9 TH |
1114 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1115 | ||
1116 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 1117 | if (is_atapi) { |
12fad3f9 TH |
1118 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1119 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1120 | } |
1da177e4 | 1121 | |
cc9278ed TH |
1122 | n_elem = 0; |
1123 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1124 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1125 | |
cc9278ed TH |
1126 | /* |
1127 | * Fill in command slot information. | |
1128 | */ | |
1129 | opts = cmd_fis_len | n_elem << 16; | |
1130 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1131 | opts |= AHCI_CMD_WRITE; | |
1132 | if (is_atapi) | |
4b10e559 | 1133 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1134 | |
12fad3f9 | 1135 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1136 | } |
1137 | ||
78cd52d0 | 1138 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1139 | { |
78cd52d0 TH |
1140 | struct ahci_port_priv *pp = ap->private_data; |
1141 | struct ata_eh_info *ehi = &ap->eh_info; | |
1142 | unsigned int err_mask = 0, action = 0; | |
1143 | struct ata_queued_cmd *qc; | |
1144 | u32 serror; | |
1da177e4 | 1145 | |
78cd52d0 | 1146 | ata_ehi_clear_desc(ehi); |
1da177e4 | 1147 | |
78cd52d0 TH |
1148 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
1149 | serror = ahci_scr_read(ap, SCR_ERROR); | |
1150 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 1151 | |
78cd52d0 TH |
1152 | /* analyze @irq_stat */ |
1153 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
1154 | ||
41669553 TH |
1155 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
1156 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) | |
1157 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1158 | ||
55a61604 | 1159 | if (irq_stat & PORT_IRQ_TF_ERR) { |
78cd52d0 | 1160 | err_mask |= AC_ERR_DEV; |
55a61604 CH |
1161 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
1162 | serror &= ~SERR_INTERNAL; | |
1163 | } | |
78cd52d0 TH |
1164 | |
1165 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1166 | err_mask |= AC_ERR_HOST_BUS; | |
1167 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
1168 | } |
1169 | ||
78cd52d0 TH |
1170 | if (irq_stat & PORT_IRQ_IF_ERR) { |
1171 | err_mask |= AC_ERR_ATA_BUS; | |
1172 | action |= ATA_EH_SOFTRESET; | |
1173 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
1174 | } | |
1da177e4 | 1175 | |
78cd52d0 | 1176 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 1177 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
1178 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
1179 | "connection status changed" : "PHY RDY changed"); | |
1180 | } | |
1181 | ||
1182 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1183 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 1184 | |
78cd52d0 TH |
1185 | err_mask |= AC_ERR_HSM; |
1186 | action |= ATA_EH_SOFTRESET; | |
1187 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
1188 | unk[0], unk[1], unk[2], unk[3]); | |
1189 | } | |
1da177e4 | 1190 | |
78cd52d0 TH |
1191 | /* okay, let's hand over to EH */ |
1192 | ehi->serror |= serror; | |
1193 | ehi->action |= action; | |
b8f6153e | 1194 | |
1da177e4 | 1195 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1196 | if (qc) |
1197 | qc->err_mask |= err_mask; | |
1198 | else | |
1199 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1200 | |
78cd52d0 TH |
1201 | if (irq_stat & PORT_IRQ_FREEZE) |
1202 | ata_port_freeze(ap); | |
1203 | else | |
1204 | ata_port_abort(ap); | |
1da177e4 LT |
1205 | } |
1206 | ||
78cd52d0 | 1207 | static void ahci_host_intr(struct ata_port *ap) |
1da177e4 | 1208 | { |
0d5ff566 | 1209 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ea6ba10b | 1210 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
12fad3f9 | 1211 | struct ata_eh_info *ehi = &ap->eh_info; |
0291f95f | 1212 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1213 | u32 status, qc_active; |
0291f95f | 1214 | int rc, known_irq = 0; |
1da177e4 LT |
1215 | |
1216 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1217 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1218 | ||
78cd52d0 TH |
1219 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1220 | ahci_error_intr(ap, status); | |
1221 | return; | |
1da177e4 LT |
1222 | } |
1223 | ||
12fad3f9 TH |
1224 | if (ap->sactive) |
1225 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1226 | else | |
1227 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1228 | ||
1229 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1230 | if (rc > 0) | |
1231 | return; | |
1232 | if (rc < 0) { | |
1233 | ehi->err_mask |= AC_ERR_HSM; | |
1234 | ehi->action |= ATA_EH_SOFTRESET; | |
1235 | ata_port_freeze(ap); | |
1236 | return; | |
1da177e4 LT |
1237 | } |
1238 | ||
2a3917a8 TH |
1239 | /* hmmm... a spurious interupt */ |
1240 | ||
0291f95f TH |
1241 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1242 | * implementation for non-NCQ commands. | |
1243 | */ | |
1244 | if (!ap->sactive) | |
12fad3f9 TH |
1245 | return; |
1246 | ||
0291f95f TH |
1247 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1248 | if (!pp->ncq_saw_d2h) | |
1249 | ata_port_printk(ap, KERN_INFO, | |
1250 | "D2H reg with I during NCQ, " | |
1251 | "this message won't be printed again\n"); | |
1252 | pp->ncq_saw_d2h = 1; | |
1253 | known_irq = 1; | |
1254 | } | |
1255 | ||
1256 | if (status & PORT_IRQ_DMAS_FIS) { | |
1257 | if (!pp->ncq_saw_dmas) | |
1258 | ata_port_printk(ap, KERN_INFO, | |
1259 | "DMAS FIS during NCQ, " | |
1260 | "this message won't be printed again\n"); | |
1261 | pp->ncq_saw_dmas = 1; | |
1262 | known_irq = 1; | |
1263 | } | |
1264 | ||
a2bbd0c9 | 1265 | if (status & PORT_IRQ_SDB_FIS) { |
04d4f7a1 | 1266 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
0291f95f | 1267 | |
afb2d552 TH |
1268 | if (le32_to_cpu(f[1])) { |
1269 | /* SDB FIS containing spurious completions | |
1270 | * might be dangerous, whine and fail commands | |
1271 | * with HSM violation. EH will turn off NCQ | |
1272 | * after several such failures. | |
1273 | */ | |
1274 | ata_ehi_push_desc(ehi, | |
1275 | "spurious completions during NCQ " | |
1276 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", | |
1277 | readl(port_mmio + PORT_CMD_ISSUE), | |
1278 | readl(port_mmio + PORT_SCR_ACT), | |
1279 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1280 | ehi->err_mask |= AC_ERR_HSM; | |
1281 | ehi->action |= ATA_EH_SOFTRESET; | |
1282 | ata_port_freeze(ap); | |
1283 | } else { | |
1284 | if (!pp->ncq_saw_sdb) | |
1285 | ata_port_printk(ap, KERN_INFO, | |
1286 | "spurious SDB FIS %08x:%08x during NCQ, " | |
1287 | "this message won't be printed again\n", | |
1288 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1289 | pp->ncq_saw_sdb = 1; | |
1290 | } | |
0291f95f TH |
1291 | known_irq = 1; |
1292 | } | |
2a3917a8 | 1293 | |
0291f95f | 1294 | if (!known_irq) |
78cd52d0 | 1295 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1296 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
12fad3f9 | 1297 | status, ap->active_tag, ap->sactive); |
1da177e4 LT |
1298 | } |
1299 | ||
1300 | static void ahci_irq_clear(struct ata_port *ap) | |
1301 | { | |
1302 | /* TODO */ | |
1303 | } | |
1304 | ||
7d12e780 | 1305 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1306 | { |
cca3974e | 1307 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1308 | struct ahci_host_priv *hpriv; |
1309 | unsigned int i, handled = 0; | |
ea6ba10b | 1310 | void __iomem *mmio; |
1da177e4 LT |
1311 | u32 irq_stat, irq_ack = 0; |
1312 | ||
1313 | VPRINTK("ENTER\n"); | |
1314 | ||
cca3974e | 1315 | hpriv = host->private_data; |
0d5ff566 | 1316 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1317 | |
1318 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1319 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1320 | irq_stat &= hpriv->port_map; | |
1321 | if (!irq_stat) | |
1322 | return IRQ_NONE; | |
1323 | ||
cca3974e | 1324 | spin_lock(&host->lock); |
1da177e4 | 1325 | |
cca3974e | 1326 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1327 | struct ata_port *ap; |
1da177e4 | 1328 | |
67846b30 JG |
1329 | if (!(irq_stat & (1 << i))) |
1330 | continue; | |
1331 | ||
cca3974e | 1332 | ap = host->ports[i]; |
67846b30 | 1333 | if (ap) { |
78cd52d0 | 1334 | ahci_host_intr(ap); |
67846b30 JG |
1335 | VPRINTK("port %u\n", i); |
1336 | } else { | |
1337 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1338 | if (ata_ratelimit()) |
cca3974e | 1339 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1340 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1341 | } |
67846b30 JG |
1342 | |
1343 | irq_ack |= (1 << i); | |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | if (irq_ack) { | |
1347 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1348 | handled = 1; | |
1349 | } | |
1350 | ||
cca3974e | 1351 | spin_unlock(&host->lock); |
1da177e4 LT |
1352 | |
1353 | VPRINTK("EXIT\n"); | |
1354 | ||
1355 | return IRQ_RETVAL(handled); | |
1356 | } | |
1357 | ||
9a3d9eb0 | 1358 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1359 | { |
1360 | struct ata_port *ap = qc->ap; | |
0d5ff566 | 1361 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
1da177e4 | 1362 | |
12fad3f9 TH |
1363 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1364 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1365 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1366 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
78cd52d0 TH |
1371 | static void ahci_freeze(struct ata_port *ap) |
1372 | { | |
0d5ff566 | 1373 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
78cd52d0 TH |
1374 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1375 | ||
1376 | /* turn IRQ off */ | |
1377 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1378 | } | |
1379 | ||
1380 | static void ahci_thaw(struct ata_port *ap) | |
1381 | { | |
0d5ff566 | 1382 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
78cd52d0 TH |
1383 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1384 | u32 tmp; | |
1385 | ||
1386 | /* clear IRQ */ | |
1387 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1388 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1389 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 TH |
1390 | |
1391 | /* turn IRQ back on */ | |
1392 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1393 | } | |
1394 | ||
1395 | static void ahci_error_handler(struct ata_port *ap) | |
1396 | { | |
0d5ff566 | 1397 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 1398 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1399 | ||
b51e9e5d | 1400 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1401 | /* restart engine */ |
5457f219 | 1402 | ahci_stop_engine(port_mmio); |
1403 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1404 | } |
1405 | ||
1406 | /* perform recovery */ | |
4aeb0e32 | 1407 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1408 | ahci_postreset); |
78cd52d0 TH |
1409 | } |
1410 | ||
ad616ffb TH |
1411 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1412 | { | |
0d5ff566 | 1413 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
ad616ffb TH |
1414 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1415 | ||
1416 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | |
1417 | /* restart engine */ | |
1418 | ahci_stop_engine(port_mmio); | |
1419 | ahci_start_engine(port_mmio); | |
1420 | } | |
1421 | ||
1422 | /* perform recovery */ | |
1423 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1424 | ahci_postreset); | |
1425 | } | |
1426 | ||
78cd52d0 TH |
1427 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1428 | { | |
1429 | struct ata_port *ap = qc->ap; | |
0d5ff566 | 1430 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
5457f219 | 1431 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
78cd52d0 | 1432 | |
a51d644a | 1433 | if (qc->flags & ATA_QCFLAG_FAILED) { |
78cd52d0 | 1434 | /* make DMA engine forget about the failed command */ |
5457f219 | 1435 | ahci_stop_engine(port_mmio); |
1436 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1437 | } |
1438 | } | |
1439 | ||
438ac6d5 | 1440 | #ifdef CONFIG_PM |
c1332875 TH |
1441 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1442 | { | |
cca3974e | 1443 | struct ahci_host_priv *hpriv = ap->host->private_data; |
c1332875 | 1444 | struct ahci_port_priv *pp = ap->private_data; |
0d5ff566 | 1445 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1446 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1447 | const char *emsg = NULL; | |
1448 | int rc; | |
1449 | ||
1450 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
8e16f941 TH |
1451 | if (rc == 0) |
1452 | ahci_power_down(port_mmio, hpriv->cap); | |
1453 | else { | |
c1332875 TH |
1454 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
1455 | ahci_init_port(port_mmio, hpriv->cap, | |
1456 | pp->cmd_slot_dma, pp->rx_fis_dma); | |
1457 | } | |
1458 | ||
1459 | return rc; | |
1460 | } | |
1461 | ||
1462 | static int ahci_port_resume(struct ata_port *ap) | |
1463 | { | |
1464 | struct ahci_port_priv *pp = ap->private_data; | |
cca3974e | 1465 | struct ahci_host_priv *hpriv = ap->host->private_data; |
0d5ff566 | 1466 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1467 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1468 | ||
8e16f941 | 1469 | ahci_power_up(port_mmio, hpriv->cap); |
c1332875 TH |
1470 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1476 | { | |
cca3974e | 1477 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1478 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1479 | u32 ctl; |
1480 | ||
1481 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1482 | /* AHCI spec rev1.1 section 8.3.3: | |
1483 | * Software must disable interrupts prior to requesting a | |
1484 | * transition of the HBA to D3 state. | |
1485 | */ | |
1486 | ctl = readl(mmio + HOST_CTL); | |
1487 | ctl &= ~HOST_IRQ_EN; | |
1488 | writel(ctl, mmio + HOST_CTL); | |
1489 | readl(mmio + HOST_CTL); /* flush */ | |
1490 | } | |
1491 | ||
1492 | return ata_pci_device_suspend(pdev, mesg); | |
1493 | } | |
1494 | ||
1495 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1496 | { | |
cca3974e JG |
1497 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1498 | struct ahci_host_priv *hpriv = host->private_data; | |
0d5ff566 | 1499 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1500 | int rc; |
1501 | ||
553c4aa6 TH |
1502 | rc = ata_pci_device_do_resume(pdev); |
1503 | if (rc) | |
1504 | return rc; | |
c1332875 TH |
1505 | |
1506 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
d447df14 | 1507 | rc = ahci_reset_controller(mmio, pdev, hpriv); |
c1332875 TH |
1508 | if (rc) |
1509 | return rc; | |
1510 | ||
648a88be TH |
1511 | ahci_init_controller(mmio, pdev, host->n_ports, |
1512 | host->ports[0]->flags, hpriv); | |
c1332875 TH |
1513 | } |
1514 | ||
cca3974e | 1515 | ata_host_resume(host); |
c1332875 TH |
1516 | |
1517 | return 0; | |
1518 | } | |
438ac6d5 | 1519 | #endif |
c1332875 | 1520 | |
254950cd TH |
1521 | static int ahci_port_start(struct ata_port *ap) |
1522 | { | |
cca3974e JG |
1523 | struct device *dev = ap->host->dev; |
1524 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
254950cd | 1525 | struct ahci_port_priv *pp; |
0d5ff566 | 1526 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
254950cd TH |
1527 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1528 | void *mem; | |
1529 | dma_addr_t mem_dma; | |
1530 | int rc; | |
1531 | ||
24dc5f33 | 1532 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1533 | if (!pp) |
1534 | return -ENOMEM; | |
254950cd TH |
1535 | |
1536 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1537 | if (rc) |
254950cd | 1538 | return rc; |
254950cd | 1539 | |
24dc5f33 TH |
1540 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1541 | GFP_KERNEL); | |
1542 | if (!mem) | |
254950cd | 1543 | return -ENOMEM; |
254950cd TH |
1544 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1545 | ||
1546 | /* | |
1547 | * First item in chunk of DMA memory: 32-slot command table, | |
1548 | * 32 bytes each in size | |
1549 | */ | |
1550 | pp->cmd_slot = mem; | |
1551 | pp->cmd_slot_dma = mem_dma; | |
1552 | ||
1553 | mem += AHCI_CMD_SLOT_SZ; | |
1554 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1555 | ||
1556 | /* | |
1557 | * Second item: Received-FIS area | |
1558 | */ | |
1559 | pp->rx_fis = mem; | |
1560 | pp->rx_fis_dma = mem_dma; | |
1561 | ||
1562 | mem += AHCI_RX_FIS_SZ; | |
1563 | mem_dma += AHCI_RX_FIS_SZ; | |
1564 | ||
1565 | /* | |
1566 | * Third item: data area for storing a single command | |
1567 | * and its scatter-gather table | |
1568 | */ | |
1569 | pp->cmd_tbl = mem; | |
1570 | pp->cmd_tbl_dma = mem_dma; | |
1571 | ||
1572 | ap->private_data = pp; | |
1573 | ||
8e16f941 TH |
1574 | /* power up port */ |
1575 | ahci_power_up(port_mmio, hpriv->cap); | |
1576 | ||
0be0aa98 TH |
1577 | /* initialize port */ |
1578 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | |
254950cd TH |
1579 | |
1580 | return 0; | |
1581 | } | |
1582 | ||
1583 | static void ahci_port_stop(struct ata_port *ap) | |
1584 | { | |
cca3974e | 1585 | struct ahci_host_priv *hpriv = ap->host->private_data; |
0d5ff566 | 1586 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
254950cd | 1587 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
0be0aa98 TH |
1588 | const char *emsg = NULL; |
1589 | int rc; | |
254950cd | 1590 | |
0be0aa98 TH |
1591 | /* de-initialize port */ |
1592 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
1593 | if (rc) | |
1594 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1595 | } |
1596 | ||
0d5ff566 | 1597 | static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, |
1da177e4 LT |
1598 | unsigned int port_idx) |
1599 | { | |
1600 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
0d5ff566 | 1601 | base = ahci_port_base(base, port_idx); |
1da177e4 LT |
1602 | VPRINTK("base now==0x%lx\n", base); |
1603 | ||
1604 | port->cmd_addr = base; | |
1605 | port->scr_addr = base + PORT_SCR; | |
1606 | ||
1607 | VPRINTK("EXIT\n"); | |
1608 | } | |
1609 | ||
1610 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
1611 | { | |
1612 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1613 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
0d5ff566 | 1614 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
17199b18 | 1615 | unsigned int i, using_dac; |
1da177e4 | 1616 | int rc; |
1da177e4 | 1617 | |
d447df14 | 1618 | rc = ahci_reset_controller(mmio, pdev, hpriv); |
d91542c1 TH |
1619 | if (rc) |
1620 | return rc; | |
1da177e4 | 1621 | |
17199b18 TH |
1622 | probe_ent->n_ports = fls(hpriv->port_map); |
1623 | probe_ent->dummy_port_mask = ~hpriv->port_map; | |
1da177e4 LT |
1624 | |
1625 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
17199b18 | 1626 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); |
1da177e4 LT |
1627 | |
1628 | using_dac = hpriv->cap & HOST_CAP_64; | |
1629 | if (using_dac && | |
1630 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1631 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1632 | if (rc) { | |
1633 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1634 | if (rc) { | |
a9524a76 JG |
1635 | dev_printk(KERN_ERR, &pdev->dev, |
1636 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1637 | return rc; |
1638 | } | |
1639 | } | |
1da177e4 LT |
1640 | } else { |
1641 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1642 | if (rc) { | |
a9524a76 JG |
1643 | dev_printk(KERN_ERR, &pdev->dev, |
1644 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1645 | return rc; |
1646 | } | |
1647 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1648 | if (rc) { | |
a9524a76 JG |
1649 | dev_printk(KERN_ERR, &pdev->dev, |
1650 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1651 | return rc; |
1652 | } | |
1653 | } | |
1654 | ||
d91542c1 | 1655 | for (i = 0; i < probe_ent->n_ports; i++) |
0d5ff566 | 1656 | ahci_setup_port(&probe_ent->port[i], mmio, i); |
1da177e4 | 1657 | |
648a88be TH |
1658 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, |
1659 | probe_ent->port_flags, hpriv); | |
1da177e4 LT |
1660 | |
1661 | pci_set_master(pdev); | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1da177e4 LT |
1666 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
1667 | { | |
1668 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1669 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
0d5ff566 | 1670 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1671 | u32 vers, cap, impl, speed; |
1672 | const char *speed_s; | |
1673 | u16 cc; | |
1674 | const char *scc_s; | |
1675 | ||
1676 | vers = readl(mmio + HOST_VERSION); | |
1677 | cap = hpriv->cap; | |
1678 | impl = hpriv->port_map; | |
1679 | ||
1680 | speed = (cap >> 20) & 0xf; | |
1681 | if (speed == 1) | |
1682 | speed_s = "1.5"; | |
1683 | else if (speed == 2) | |
1684 | speed_s = "3"; | |
1685 | else | |
1686 | speed_s = "?"; | |
1687 | ||
1688 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 1689 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 1690 | scc_s = "IDE"; |
c9f89475 | 1691 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 1692 | scc_s = "SATA"; |
c9f89475 | 1693 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
1694 | scc_s = "RAID"; |
1695 | else | |
1696 | scc_s = "unknown"; | |
1697 | ||
a9524a76 JG |
1698 | dev_printk(KERN_INFO, &pdev->dev, |
1699 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1700 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1701 | , | |
1da177e4 LT |
1702 | |
1703 | (vers >> 24) & 0xff, | |
1704 | (vers >> 16) & 0xff, | |
1705 | (vers >> 8) & 0xff, | |
1706 | vers & 0xff, | |
1707 | ||
1708 | ((cap >> 8) & 0x1f) + 1, | |
1709 | (cap & 0x1f) + 1, | |
1710 | speed_s, | |
1711 | impl, | |
1712 | scc_s); | |
1713 | ||
a9524a76 JG |
1714 | dev_printk(KERN_INFO, &pdev->dev, |
1715 | "flags: " | |
1da177e4 LT |
1716 | "%s%s%s%s%s%s" |
1717 | "%s%s%s%s%s%s%s\n" | |
1718 | , | |
1da177e4 LT |
1719 | |
1720 | cap & (1 << 31) ? "64bit " : "", | |
1721 | cap & (1 << 30) ? "ncq " : "", | |
1722 | cap & (1 << 28) ? "ilck " : "", | |
1723 | cap & (1 << 27) ? "stag " : "", | |
1724 | cap & (1 << 26) ? "pm " : "", | |
1725 | cap & (1 << 25) ? "led " : "", | |
1726 | ||
1727 | cap & (1 << 24) ? "clo " : "", | |
1728 | cap & (1 << 19) ? "nz " : "", | |
1729 | cap & (1 << 18) ? "only " : "", | |
1730 | cap & (1 << 17) ? "pmp " : "", | |
1731 | cap & (1 << 15) ? "pio " : "", | |
1732 | cap & (1 << 14) ? "slum " : "", | |
1733 | cap & (1 << 13) ? "part " : "" | |
1734 | ); | |
1735 | } | |
1736 | ||
24dc5f33 | 1737 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1738 | { |
1739 | static int printed_version; | |
24dc5f33 TH |
1740 | unsigned int board_idx = (unsigned int) ent->driver_data; |
1741 | struct device *dev = &pdev->dev; | |
1742 | struct ata_probe_ent *probe_ent; | |
1da177e4 | 1743 | struct ahci_host_priv *hpriv; |
1da177e4 LT |
1744 | int rc; |
1745 | ||
1746 | VPRINTK("ENTER\n"); | |
1747 | ||
12fad3f9 TH |
1748 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1749 | ||
1da177e4 | 1750 | if (!printed_version++) |
a9524a76 | 1751 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1752 | |
24dc5f33 | 1753 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1754 | if (rc) |
1755 | return rc; | |
1756 | ||
0d5ff566 TH |
1757 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1758 | if (rc == -EBUSY) | |
24dc5f33 | 1759 | pcim_pin_device(pdev); |
0d5ff566 | 1760 | if (rc) |
24dc5f33 | 1761 | return rc; |
1da177e4 | 1762 | |
24dc5f33 | 1763 | if (pci_enable_msi(pdev)) |
907f4678 | 1764 | pci_intx(pdev, 1); |
1da177e4 | 1765 | |
24dc5f33 TH |
1766 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
1767 | if (probe_ent == NULL) | |
1768 | return -ENOMEM; | |
1da177e4 | 1769 | |
1da177e4 LT |
1770 | probe_ent->dev = pci_dev_to_dev(pdev); |
1771 | INIT_LIST_HEAD(&probe_ent->node); | |
1772 | ||
24dc5f33 TH |
1773 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1774 | if (!hpriv) | |
1775 | return -ENOMEM; | |
1da177e4 LT |
1776 | |
1777 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
cca3974e | 1778 | probe_ent->port_flags = ahci_port_info[board_idx].flags; |
1da177e4 LT |
1779 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; |
1780 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1781 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1782 | ||
1783 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1784 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 | 1785 | probe_ent->iomap = pcim_iomap_table(pdev); |
1da177e4 LT |
1786 | probe_ent->private_data = hpriv; |
1787 | ||
1788 | /* initialize adapter */ | |
d447df14 TH |
1789 | ahci_save_initial_config(probe_ent); |
1790 | ||
1da177e4 LT |
1791 | rc = ahci_host_init(probe_ent); |
1792 | if (rc) | |
24dc5f33 | 1793 | return rc; |
1da177e4 | 1794 | |
cca3974e | 1795 | if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && |
71f0737b | 1796 | (hpriv->cap & HOST_CAP_NCQ)) |
cca3974e | 1797 | probe_ent->port_flags |= ATA_FLAG_NCQ; |
12fad3f9 | 1798 | |
1da177e4 LT |
1799 | ahci_print_info(probe_ent); |
1800 | ||
24dc5f33 TH |
1801 | if (!ata_device_add(probe_ent)) |
1802 | return -ENODEV; | |
1da177e4 | 1803 | |
24dc5f33 | 1804 | devm_kfree(dev, probe_ent); |
1da177e4 | 1805 | return 0; |
907f4678 | 1806 | } |
1da177e4 LT |
1807 | |
1808 | static int __init ahci_init(void) | |
1809 | { | |
b7887196 | 1810 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
1811 | } |
1812 | ||
1da177e4 LT |
1813 | static void __exit ahci_exit(void) |
1814 | { | |
1815 | pci_unregister_driver(&ahci_pci_driver); | |
1816 | } | |
1817 | ||
1818 | ||
1819 | MODULE_AUTHOR("Jeff Garzik"); | |
1820 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1821 | MODULE_LICENSE("GPL"); | |
1822 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1823 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1824 | |
1825 | module_init(ahci_init); | |
1826 | module_exit(ahci_exit); |