projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'x86/ras' into x86/core, to fix conflicts
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
66a7cbc3 63 board_ahci_nomsi,
67809f85 64 board_ahci_noncq,
441577ef 65 board_ahci_nosntf,
5f173107 66 board_ahci_yes_fbs,
1da177e4 67
441577ef 68 /* board IDs for specific chipsets in alphabetical order */
dbfe8ef5 69 board_ahci_avn,
441577ef 70 board_ahci_mcp65,
83f2b963
TH		 71 board_ahci_mcp77,
72 board_ahci_mcp89,
441577ef
TH		 73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 82 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 83};
84
2dcb407e 85static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
dbfe8ef5
DW		 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
cb85696d
JL		 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
438ac6d5 94#ifdef CONFIG_PM
c1332875
TH		 95static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
96static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 97#endif
ad616ffb 98
fad16e7a
TH		 99static struct scsi_host_template ahci_sht = {
100 AHCI_SHT("ahci"),
101};
102
029cfd6b
TH		 103static struct ata_port_operations ahci_vt8251_ops = {
104 .inherits = &ahci_ops,
a1efdaba 105 .hardreset = ahci_vt8251_hardreset,
029cfd6b 106};
edc93052 107
029cfd6b
TH		 108static struct ata_port_operations ahci_p5wdh_ops = {
109 .inherits = &ahci_ops,
a1efdaba 110 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 111};
112
dbfe8ef5
DW		 113static struct ata_port_operations ahci_avn_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_avn_hardreset,
116};
117
98ac62de 118static const struct ata_port_info ahci_port_info[] = {
441577ef 119 /* by features */
facb8fa6 120 [board_ahci] = {
1188c0d8 121 .flags = AHCI_FLAG_COMMON,
14bdef98 122 .pio_mask = ATA_PIO4,
469248ab 123 .udma_mask = ATA_UDMA6,
1da177e4
LT		 124 .port_ops = &ahci_ops,
125 },
facb8fa6 126 [board_ahci_ign_iferr] = {
441577ef 127 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 128 .flags = AHCI_FLAG_COMMON,
14bdef98 129 .pio_mask = ATA_PIO4,
469248ab 130 .udma_mask = ATA_UDMA6,
441577ef 131 .port_ops = &ahci_ops,
bf2af2a2 132 },
66a7cbc3
TH		 133 [board_ahci_nomsi] = {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
67809f85
LK		 140 [board_ahci_noncq] = {
141 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
facb8fa6 147 [board_ahci_nosntf] = {
441577ef 148 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 149 .flags = AHCI_FLAG_COMMON,
14bdef98 150 .pio_mask = ATA_PIO4,
469248ab 151 .udma_mask = ATA_UDMA6,
41669553
TH		 152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_yes_fbs] = {
5f173107
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
441577ef 161 /* by chipsets */
dbfe8ef5
DW		 162 [board_ahci_avn] = {
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_avn_ops,
167 },
facb8fa6 168 [board_ahci_mcp65] = {
83f2b963
TH		 169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
170 AHCI_HFLAG_YES_NCQ),
ae01b249 171 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
facb8fa6 176 [board_ahci_mcp77] = {
83f2b963
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
facb8fa6 183 [board_ahci_mcp89] = {
83f2b963 184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 185 .flags = AHCI_FLAG_COMMON,
14bdef98 186 .pio_mask = ATA_PIO4,
469248ab 187 .udma_mask = ATA_UDMA6,
441577ef 188 .port_ops = &ahci_ops,
55a61604 189 },
facb8fa6 190 [board_ahci_mv] = {
417a1a6d 191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 192 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 193 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 194 .pio_mask = ATA_PIO4,
cd70c266
JG		 195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
197 },
facb8fa6 198 [board_ahci_sb600] = {
441577ef
TH		 199 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
200 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
201 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 202 .flags = AHCI_FLAG_COMMON,
14bdef98 203 .pio_mask = ATA_PIO4,
e39fc8c9 204 .udma_mask = ATA_UDMA6,
345347c5 205 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 206 },
facb8fa6 207 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 209 .flags = AHCI_FLAG_COMMON,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
345347c5 212 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 213 },
facb8fa6 214 [board_ahci_vt8251] = {
441577ef 215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 216 .flags = AHCI_FLAG_COMMON,
217 .pio_mask = ATA_PIO4,
218 .udma_mask = ATA_UDMA6,
441577ef 219 .port_ops = &ahci_vt8251_ops,
1b677afd 220 },
1da177e4
LT		 221};
222
3b7d697d 223static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 224 /* Intel */
54bb3a94
JG		 225 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
226 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
227 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
228 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
229 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 230 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 231 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
232 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
233 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 235 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 236 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 237 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
239 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
240 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
242 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
246 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
247 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 252 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
253 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 254 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 255 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 256 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 257 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
258 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 259 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 260 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 261 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 262 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 263 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 264 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 265 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
266 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
267 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
268 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
269 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
270 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 271 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
272 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
273 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 274 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 275 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 276 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
277 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
278 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
279 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
280 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
281 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 282 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 283 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
284 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
285 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
286 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
287 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
289 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
290 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 291 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
292 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
293 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
294 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
295 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
296 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 299 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
300 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
301 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
303 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
306 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 307 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
308 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
309 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
310 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
311 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
313 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 315 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
316 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 317 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
318 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
319 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
320 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
322 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
323 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
324 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 325 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 326 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
327 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 330 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
331 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
332 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
333 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
334 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
335 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
336 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
337 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
249cd0a1
DR		 338 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
690000b9 341 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
690000b9
JR		 342 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
343 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
344 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
fe7fa31a 345
e34bb370
TH		 346 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
347 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
348 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 349 /* JMicron 362B and 362C have an AHCI function with IDE class code */
350 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
351 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 352
353 /* ATI */
c65ec1c2 354 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 355 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
356 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
357 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
358 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
359 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
360 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 361
e2dd90b1 362 /* AMD */
5deab536 363 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 364 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 365 /* AMD is using RAID class only for ahci controllers */
366 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
367 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
368
fe7fa31a 369 /* VIA */
54bb3a94 370 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 371 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 372
373 /* NVIDIA */
e297d99e
TH		 374 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
375 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
376 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
377 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
378 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
379 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
380 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
381 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 382 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
383 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
384 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
385 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
386 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
387 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
388 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
389 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
390 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
391 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
392 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
397 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
398 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
399 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
400 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
401 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
402 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
403 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
404 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
405 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
406 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
411 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
412 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
413 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
414 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
415 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
416 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
417 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
418 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
419 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
420 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
421 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
422 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
423 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
424 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
425 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
426 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
427 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
428 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
429 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
430 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
431 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
432 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
433 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
434 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
435 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
436 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
437 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
438 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
439 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
440 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
441 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
442 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
443 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
444 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
445 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
446 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
447 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
448 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
449 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
450 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
451 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
452 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
453 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
454 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
455 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
456 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
457 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 458
95916edd 459 /* SiS */
20e2de4a
TH		 460 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
461 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
462 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 463
318893e1
AR		 464 /* ST Microelectronics */
465 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
466
cd70c266
JG		 467 /* Marvell */
468 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 469 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 471 .class = PCI_CLASS_STORAGE_SATA_AHCI,
472 .class_mask = 0xffffff,
5f173107 473 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 474 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 475 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 476 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
477 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
478 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 479 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 480 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 481 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 482 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
483 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 484 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 485 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 486 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 487 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
488 .driver_data = board_ahci_yes_fbs },
69fd3157 489 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 490 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 491 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
492 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 493 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
494 .driver_data = board_ahci_yes_fbs },
cd70c266 495
c77a036b
MN		 496 /* Promise */
497 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 498 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 499
c9703765 500 /* Asmedia */
7b4f6eca
AC		 501 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
502 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
503 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
504 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 505
67809f85 506 /*
66a7cbc3
TH		 507 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
508 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 509 */
66a7cbc3 510 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 511 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 512
7f9c9f8e
HD		 513 /* Enmotus */
514 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
515
415ae2b5
JG		 516 /* Generic, PCI class code for AHCI */
517 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 518 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 519
1da177e4
LT		 520 { } /* terminate list */
521};
522
523
524static struct pci_driver ahci_pci_driver = {
525 .name = DRV_NAME,
526 .id_table = ahci_pci_tbl,
527 .probe = ahci_init_one,
24dc5f33 528 .remove = ata_pci_remove_one,
438ac6d5 529#ifdef CONFIG_PM
c1332875 530 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 531 .resume = ahci_pci_device_resume,
532#endif
533};
1da177e4 534
365cfa1e
AV		 535#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
536static int marvell_enable;
537#else
538static int marvell_enable = 1;
539#endif
540module_param(marvell_enable, int, 0644);
541MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 542
1da177e4 543
365cfa1e
AV		 544static void ahci_pci_save_initial_config(struct pci_dev *pdev,
545 struct ahci_host_priv *hpriv)
546{
365cfa1e
AV		 547 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
548 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 549 hpriv->force_port_map = 1;
1da177e4
LT		 550 }
551
365cfa1e
AV		 552 /*
553 * Temporary Marvell 6145 hack: PATA port presence
554 * is asserted through the standard AHCI port
555 * presence register, as bit 4 (counting from 0)
d28f87aa 556 */
365cfa1e
AV		 557 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
558 if (pdev->device == 0x6121)
9a23c1d6 559 hpriv->mask_port_map = 0x3;
365cfa1e 560 else
9a23c1d6 561 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 562 dev_info(&pdev->dev,
563 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
564 }
1da177e4 565
725c7b57 566 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 567}
568
365cfa1e 569static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 570{
365cfa1e 571 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 572
365cfa1e 573 ahci_reset_controller(host);
1da177e4 574
365cfa1e
AV		 575 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
576 struct ahci_host_priv *hpriv = host->private_data;
577 u16 tmp16;
d6ef3153 578
365cfa1e
AV		 579 /* configure PCS */
580 pci_read_config_word(pdev, 0x92, &tmp16);
581 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
582 tmp16 |= hpriv->port_map;
583 pci_write_config_word(pdev, 0x92, tmp16);
584 }
d6ef3153
SH		 585 }
586
1da177e4
LT		 587 return 0;
588}
589
365cfa1e 590static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 591{
365cfa1e
AV		 592 struct ahci_host_priv *hpriv = host->private_data;
593 struct pci_dev *pdev = to_pci_dev(host->dev);
594 void __iomem *port_mmio;
78cd52d0 595 u32 tmp;
365cfa1e 596 int mv;
78cd52d0 597
365cfa1e
AV		 598 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
599 if (pdev->device == 0x6121)
600 mv = 2;
601 else
602 mv = 4;
603 port_mmio = __ahci_port_base(host, mv);
78cd52d0 604
365cfa1e 605 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 606
365cfa1e
AV		 607 /* clear port IRQ */
608 tmp = readl(port_mmio + PORT_IRQ_STAT);
609 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
610 if (tmp)
611 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 612 }
613
365cfa1e 614 ahci_init_controller(host);
edc93052
TH		 615}
616
365cfa1e
AV		 617static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
618 unsigned long deadline)
d6ef3153 619{
365cfa1e 620 struct ata_port *ap = link->ap;
039ece38 621 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 622 bool online;
d6ef3153
SH		 623 int rc;
624
365cfa1e 625 DPRINTK("ENTER\n");
d6ef3153 626
365cfa1e 627 ahci_stop_engine(ap);
d6ef3153 628
365cfa1e
AV		 629 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
630 deadline, &online, NULL);
d6ef3153 631
039ece38 632 hpriv->start_engine(ap);
d6ef3153 633
365cfa1e 634 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 635
365cfa1e
AV		 636 /* vt8251 doesn't clear BSY on signature FIS reception,
637 * request follow-up softreset.
638 */
639 return online ? -EAGAIN : rc;
7d50b60b
TH		 640}
641
365cfa1e
AV		 642static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
643 unsigned long deadline)
7d50b60b 644{
365cfa1e 645 struct ata_port *ap = link->ap;
1c954a4d 646 struct ahci_port_priv *pp = ap->private_data;
039ece38 647 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 648 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
649 struct ata_taskfile tf;
650 bool online;
651 int rc;
7d50b60b 652
365cfa1e 653 ahci_stop_engine(ap);
028a2596 654
365cfa1e
AV		 655 /* clear D2H reception area to properly wait for D2H FIS */
656 ata_tf_init(link->device, &tf);
9bbb1b0e 657 tf.command = ATA_BUSY;
365cfa1e 658 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 659
365cfa1e
AV		 660 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
661 deadline, &online, NULL);
028a2596 662
039ece38 663 hpriv->start_engine(ap);
c1332875 664
365cfa1e
AV		 665 /* The pseudo configuration device on SIMG4726 attached to
666 * ASUS P5W-DH Deluxe doesn't send signature FIS after
667 * hardreset if no device is attached to the first downstream
668 * port && the pseudo device locks up on SRST w/ PMP==0. To
669 * work around this, wait for !BSY only briefly. If BSY isn't
670 * cleared, perform CLO and proceed to IDENTIFY (achieved by
671 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
672 *
673 * Wait for two seconds. Devices attached to downstream port
674 * which can't process the following IDENTIFY after this will
675 * have to be reset again. For most cases, this should
676 * suffice while making probing snappish enough.
677 */
678 if (online) {
679 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
680 ahci_check_ready);
681 if (rc)
682 ahci_kick_engine(ap);
c1332875 683 }
c1332875
TH		 684 return rc;
685}
686
dbfe8ef5
DW		 687/*
688 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
689 *
690 * It has been observed with some SSDs that the timing of events in the
691 * link synchronization phase can leave the port in a state that can not
692 * be recovered by a SATA-hard-reset alone. The failing signature is
693 * SStatus.DET stuck at 1 ("Device presence detected but Phy
694 * communication not established"). It was found that unloading and
695 * reloading the driver when this problem occurs allows the drive
696 * connection to be recovered (DET advanced to 0x3). The critical
697 * component of reloading the driver is that the port state machines are
698 * reset by bouncing "port enable" in the AHCI PCS configuration
699 * register. So, reproduce that effect by bouncing a port whenever we
700 * see DET==1 after a reset.
701 */
702static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
704{
705 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
706 struct ata_port *ap = link->ap;
707 struct ahci_port_priv *pp = ap->private_data;
708 struct ahci_host_priv *hpriv = ap->host->private_data;
709 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
710 unsigned long tmo = deadline - jiffies;
711 struct ata_taskfile tf;
712 bool online;
713 int rc, i;
714
715 DPRINTK("ENTER\n");
716
717 ahci_stop_engine(ap);
718
719 for (i = 0; i < 2; i++) {
720 u16 val;
721 u32 sstatus;
722 int port = ap->port_no;
723 struct ata_host *host = ap->host;
724 struct pci_dev *pdev = to_pci_dev(host->dev);
725
726 /* clear D2H reception area to properly wait for D2H FIS */
727 ata_tf_init(link->device, &tf);
728 tf.command = ATA_BUSY;
729 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
730
731 rc = sata_link_hardreset(link, timing, deadline, &online,
732 ahci_check_ready);
733
734 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
735 (sstatus & 0xf) != 1)
736 break;
737
738 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
739 port);
740
741 pci_read_config_word(pdev, 0x92, &val);
742 val &= ~(1 << port);
743 pci_write_config_word(pdev, 0x92, val);
744 ata_msleep(ap, 1000);
745 val |= 1 << port;
746 pci_write_config_word(pdev, 0x92, val);
747 deadline += tmo;
748 }
749
750 hpriv->start_engine(ap);
751
752 if (online)
753 *class = ahci_dev_classify(ap);
754
755 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
756 return rc;
757}
758
759
365cfa1e 760#ifdef CONFIG_PM
c1332875
TH		 761static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
762{
0a86e1c8 763 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 764 struct ahci_host_priv *hpriv = host->private_data;
d8993349 765 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 766 u32 ctl;
767
9b10ae86
TH		 768 if (mesg.event & PM_EVENT_SUSPEND &&
769 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 770 dev_err(&pdev->dev,
771 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 772 return -EIO;
773 }
774
3a2d5b70 775 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 776 /* AHCI spec rev1.1 section 8.3.3:
777 * Software must disable interrupts prior to requesting a
778 * transition of the HBA to D3 state.
779 */
780 ctl = readl(mmio + HOST_CTL);
781 ctl &= ~HOST_IRQ_EN;
782 writel(ctl, mmio + HOST_CTL);
783 readl(mmio + HOST_CTL); /* flush */
784 }
785
786 return ata_pci_device_suspend(pdev, mesg);
787}
788
789static int ahci_pci_device_resume(struct pci_dev *pdev)
790{
0a86e1c8 791 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 792 int rc;
793
553c4aa6
TH		 794 rc = ata_pci_device_do_resume(pdev);
795 if (rc)
796 return rc;
c1332875 797
cb85696d
JL		 798 /* Apple BIOS helpfully mangles the registers on resume */
799 if (is_mcp89_apple(pdev))
800 ahci_mcp89_apple_enable(pdev);
801
c1332875 802 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 803 rc = ahci_pci_reset_controller(host);
c1332875
TH		 804 if (rc)
805 return rc;
806
781d6550 807 ahci_pci_init_controller(host);
c1332875
TH		 808 }
809
cca3974e 810 ata_host_resume(host);
c1332875
TH		 811
812 return 0;
813}
438ac6d5 814#endif
c1332875 815
4447d351 816static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 817{
1da177e4 818 int rc;
1da177e4 819
318893e1
AR		 820 /*
821 * If the device fixup already set the dma_mask to some non-standard
822 * value, don't extend it here. This happens on STA2X11, for example.
823 */
824 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
825 return 0;
826
1da177e4 827 if (using_dac &&
c54c719b
QL		 828 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
829 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 830 if (rc) {
c54c719b 831 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 832 if (rc) {
a44fec1f
JP		 833 dev_err(&pdev->dev,
834 "64-bit DMA enable failed\n");
1da177e4
LT		 835 return rc;
836 }
837 }
1da177e4 838 } else {
c54c719b 839 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 840 if (rc) {
a44fec1f 841 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 842 return rc;
843 }
c54c719b 844 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 845 if (rc) {
a44fec1f
JP		 846 dev_err(&pdev->dev,
847 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 848 return rc;
849 }
850 }
1da177e4
LT		 851 return 0;
852}
853
439fcaec
AV		 854static void ahci_pci_print_info(struct ata_host *host)
855{
856 struct pci_dev *pdev = to_pci_dev(host->dev);
857 u16 cc;
858 const char *scc_s;
859
860 pci_read_config_word(pdev, 0x0a, &cc);
861 if (cc == PCI_CLASS_STORAGE_IDE)
862 scc_s = "IDE";
863 else if (cc == PCI_CLASS_STORAGE_SATA)
864 scc_s = "SATA";
865 else if (cc == PCI_CLASS_STORAGE_RAID)
866 scc_s = "RAID";
867 else
868 scc_s = "unknown";
869
870 ahci_print_info(host, scc_s);
871}
872
edc93052
TH		 873/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
874 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
875 * support PMP and the 4726 either directly exports the device
876 * attached to the first downstream port or acts as a hardware storage
877 * controller and emulate a single ATA device (can be RAID 0/1 or some
878 * other configuration).
879 *
880 * When there's no device attached to the first downstream port of the
881 * 4726, "Config Disk" appears, which is a pseudo ATA device to
882 * configure the 4726. However, ATA emulation of the device is very
883 * lame. It doesn't send signature D2H Reg FIS after the initial
884 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
885 *
886 * The following function works around the problem by always using
887 * hardreset on the port and not depending on receiving signature FIS
888 * afterward. If signature FIS isn't received soon, ATA class is
889 * assumed without follow-up softreset.
890 */
891static void ahci_p5wdh_workaround(struct ata_host *host)
892{
1bd06867 893 static const struct dmi_system_id sysids[] = {
edc93052
TH		 894 {
895 .ident = "P5W DH Deluxe",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR,
898 "ASUSTEK COMPUTER INC"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
900 },
901 },
902 { }
903 };
904 struct pci_dev *pdev = to_pci_dev(host->dev);
905
906 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
907 dmi_check_system(sysids)) {
908 struct ata_port *ap = host->ports[1];
909
a44fec1f
JP		 910 dev_info(&pdev->dev,
911 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 912
913 ap->ops = &ahci_p5wdh_ops;
914 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
915 }
916}
917
cb85696d
JL		 918/*
919 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
920 * booting in BIOS compatibility mode. We restore the registers but not ID.
921 */
922static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
923{
924 u32 val;
925
926 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
927
928 pci_read_config_dword(pdev, 0xf8, &val);
929 val |= 1 << 0x1b;
930 /* the following changes the device ID, but appears not to affect function */
931 /* val = (val & ~0xf0000000) | 0x80000000; */
932 pci_write_config_dword(pdev, 0xf8, val);
933
934 pci_read_config_dword(pdev, 0x54c, &val);
935 val |= 1 << 0xc;
936 pci_write_config_dword(pdev, 0x54c, val);
937
938 pci_read_config_dword(pdev, 0x4a4, &val);
939 val &= 0xff;
940 val |= 0x01060100;
941 pci_write_config_dword(pdev, 0x4a4, val);
942
943 pci_read_config_dword(pdev, 0x54c, &val);
944 val &= ~(1 << 0xc);
945 pci_write_config_dword(pdev, 0x54c, val);
946
947 pci_read_config_dword(pdev, 0xf8, &val);
948 val &= ~(1 << 0x1b);
949 pci_write_config_dword(pdev, 0xf8, val);
950}
951
952static bool is_mcp89_apple(struct pci_dev *pdev)
953{
954 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
955 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
956 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
957 pdev->subsystem_device == 0xcb89;
958}
959
2fcad9d2
TH		 960/* only some SB600 ahci controllers can do 64bit DMA */
961static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 962{
963 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 964 /*
965 * The oldest version known to be broken is 0901 and
966 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 967 * Enable 64bit DMA on 1501 and anything newer.
968 *
03d783bf
TH		 969 * Please read bko#9412 for more info.
970 */
58a09b38
SH		 971 {
972 .ident = "ASUS M2A-VM",
973 .matches = {
974 DMI_MATCH(DMI_BOARD_VENDOR,
975 "ASUSTeK Computer INC."),
976 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
977 },
03d783bf 978 .driver_data = "20071026", /* yyyymmdd */
58a09b38 979 },
e65cc194
MN		 980 /*
981 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
982 * support 64bit DMA.
983 *
984 * BIOS versions earlier than 1.5 had the Manufacturer DMI
985 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
986 * This spelling mistake was fixed in BIOS version 1.5, so
987 * 1.5 and later have the Manufacturer as
988 * "MICRO-STAR INTERNATIONAL CO.,LTD".
989 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
990 *
991 * BIOS versions earlier than 1.9 had a Board Product Name
992 * DMI field of "MS-7376". This was changed to be
993 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
994 * match on DMI_BOARD_NAME of "MS-7376".
995 */
996 {
997 .ident = "MSI K9A2 Platinum",
998 .matches = {
999 DMI_MATCH(DMI_BOARD_VENDOR,
1000 "MICRO-STAR INTER"),
1001 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1002 },
1003 },
ff0173c1
MN		 1004 /*
1005 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1006 * 64bit DMA.
1007 *
1008 * This board also had the typo mentioned above in the
1009 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1010 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1011 */
1012 {
1013 .ident = "MSI K9AGM2",
1014 .matches = {
1015 DMI_MATCH(DMI_BOARD_VENDOR,
1016 "MICRO-STAR INTER"),
1017 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1018 },
1019 },
3c4aa91f
MN		 1020 /*
1021 * All BIOS versions for the Asus M3A support 64bit DMA.
1022 * (all release versions from 0301 to 1206 were tested)
1023 */
1024 {
1025 .ident = "ASUS M3A",
1026 .matches = {
1027 DMI_MATCH(DMI_BOARD_VENDOR,
1028 "ASUSTeK Computer INC."),
1029 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1030 },
1031 },
58a09b38
SH		 1032 { }
1033 };
03d783bf 1034 const struct dmi_system_id *match;
2fcad9d2
TH		 1035 int year, month, date;
1036 char buf[9];
58a09b38 1037
03d783bf 1038 match = dmi_first_match(sysids);
58a09b38 1039 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1040 !match)
58a09b38
SH		 1041 return false;
1042
e65cc194
MN		 1043 if (!match->driver_data)
1044 goto enable_64bit;
1045
2fcad9d2
TH		 1046 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1047 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1048
e65cc194
MN		 1049 if (strcmp(buf, match->driver_data) >= 0)
1050 goto enable_64bit;
1051 else {
a44fec1f
JP		 1052 dev_warn(&pdev->dev,
1053 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1054 match->ident);
2fcad9d2
TH		 1055 return false;
1056 }
e65cc194
MN		 1057
1058enable_64bit:
a44fec1f 1059 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1060 return true;
58a09b38
SH		 1061}
1062
1fd68434
RW		 1063static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1064{
1065 static const struct dmi_system_id broken_systems[] = {
1066 {
1067 .ident = "HP Compaq nx6310",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1071 },
1072 /* PCI slot number of the controller */
1073 .driver_data = (void *)0x1FUL,
1074 },
d2f9c061
MR		 1075 {
1076 .ident = "HP Compaq 6720s",
1077 .matches = {
1078 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1079 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1080 },
1081 /* PCI slot number of the controller */
1082 .driver_data = (void *)0x1FUL,
1083 },
1fd68434
RW		 1084
1085 { } /* terminate list */
1086 };
1087 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1088
1089 if (dmi) {
1090 unsigned long slot = (unsigned long)dmi->driver_data;
1091 /* apply the quirk only to on-board controllers */
1092 return slot == PCI_SLOT(pdev->devfn);
1093 }
1094
1095 return false;
1096}
1097
9b10ae86
TH		 1098static bool ahci_broken_suspend(struct pci_dev *pdev)
1099{
1100 static const struct dmi_system_id sysids[] = {
1101 /*
1102 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1103 * to the harddisk doesn't become online after
1104 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1105 *
1106 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1107 *
1108 * Use dates instead of versions to match as HP is
1109 * apparently recycling both product and version
1110 * strings.
1111 *
1112 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1113 */
1114 {
1115 .ident = "dv4",
1116 .matches = {
1117 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1118 DMI_MATCH(DMI_PRODUCT_NAME,
1119 "HP Pavilion dv4 Notebook PC"),
1120 },
9deb3431 1121 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1122 },
1123 {
1124 .ident = "dv5",
1125 .matches = {
1126 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1127 DMI_MATCH(DMI_PRODUCT_NAME,
1128 "HP Pavilion dv5 Notebook PC"),
1129 },
9deb3431 1130 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1131 },
1132 {
1133 .ident = "dv6",
1134 .matches = {
1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1136 DMI_MATCH(DMI_PRODUCT_NAME,
1137 "HP Pavilion dv6 Notebook PC"),
1138 },
9deb3431 1139 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1140 },
1141 {
1142 .ident = "HDX18",
1143 .matches = {
1144 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1145 DMI_MATCH(DMI_PRODUCT_NAME,
1146 "HP HDX18 Notebook PC"),
1147 },
9deb3431 1148 .driver_data = "20090430", /* F.23 */
9b10ae86 1149 },
cedc9bf9
TH		 1150 /*
1151 * Acer eMachines G725 has the same problem. BIOS
1152 * V1.03 is known to be broken. V3.04 is known to
25985edc 1153 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1154 * that we don't have much idea about. For now,
1155 * blacklist anything older than V3.04.
9deb3431
TH		 1156 *
1157 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1158 */
1159 {
1160 .ident = "G725",
1161 .matches = {
1162 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1163 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1164 },
9deb3431 1165 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1166 },
9b10ae86
TH		 1167 { } /* terminate list */
1168 };
1169 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1170 int year, month, date;
1171 char buf[9];
9b10ae86
TH		 1172
1173 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1174 return false;
1175
9deb3431
TH		 1176 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1177 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1178
9deb3431 1179 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1180}
1181
5594639a
TH		 1182static bool ahci_broken_online(struct pci_dev *pdev)
1183{
1184#define ENCODE_BUSDEVFN(bus, slot, func) \
1185 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1186 static const struct dmi_system_id sysids[] = {
1187 /*
1188 * There are several gigabyte boards which use
1189 * SIMG5723s configured as hardware RAID. Certain
1190 * 5723 firmware revisions shipped there keep the link
1191 * online but fail to answer properly to SRST or
1192 * IDENTIFY when no device is attached downstream
1193 * causing libata to retry quite a few times leading
1194 * to excessive detection delay.
1195 *
1196 * As these firmwares respond to the second reset try
1197 * with invalid device signature, considering unknown
1198 * sig as offline works around the problem acceptably.
1199 */
1200 {
1201 .ident = "EP45-DQ6",
1202 .matches = {
1203 DMI_MATCH(DMI_BOARD_VENDOR,
1204 "Gigabyte Technology Co., Ltd."),
1205 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1206 },
1207 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1208 },
1209 {
1210 .ident = "EP45-DS5",
1211 .matches = {
1212 DMI_MATCH(DMI_BOARD_VENDOR,
1213 "Gigabyte Technology Co., Ltd."),
1214 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1215 },
1216 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1217 },
1218 { } /* terminate list */
1219 };
1220#undef ENCODE_BUSDEVFN
1221 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1222 unsigned int val;
1223
1224 if (!dmi)
1225 return false;
1226
1227 val = (unsigned long)dmi->driver_data;
1228
1229 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1230}
1231
0cf4a7d6
JP		 1232static bool ahci_broken_devslp(struct pci_dev *pdev)
1233{
1234 /* device with broken DEVSLP but still showing SDS capability */
1235 static const struct pci_device_id ids[] = {
1236 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1237 {}
1238 };
1239
1240 return pci_match_id(ids, pdev);
1241}
1242
8e513217 1243#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1244static void ahci_gtf_filter_workaround(struct ata_host *host)
1245{
1246 static const struct dmi_system_id sysids[] = {
1247 /*
1248 * Aspire 3810T issues a bunch of SATA enable commands
1249 * via _GTF including an invalid one and one which is
1250 * rejected by the device. Among the successful ones
1251 * is FPDMA non-zero offset enable which when enabled
1252 * only on the drive side leads to NCQ command
1253 * failures. Filter it out.
1254 */
1255 {
1256 .ident = "Aspire 3810T",
1257 .matches = {
1258 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1259 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1260 },
1261 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1262 },
1263 { }
1264 };
1265 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1266 unsigned int filter;
1267 int i;
1268
1269 if (!dmi)
1270 return;
1271
1272 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1273 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1274 filter, dmi->ident);
f80ae7e4
TH		 1275
1276 for (i = 0; i < host->n_ports; i++) {
1277 struct ata_port *ap = host->ports[i];
1278 struct ata_link *link;
1279 struct ata_device *dev;
1280
1281 ata_for_each_link(link, ap, EDGE)
1282 ata_for_each_dev(dev, link, ALL)
1283 dev->gtf_filter |= filter;
1284 }
1285}
8e513217
MT		 1286#else
1287static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1288{}
1289#endif
f80ae7e4 1290
e1ba8459 1291static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1292 struct ahci_host_priv *hpriv)
5ca72c4f 1293{
ccf8f53c 1294 int rc, nvec;
5ca72c4f 1295
7b92b4f6
AG		 1296 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1297 goto intx;
1298
fc061d96
AG		 1299 nvec = pci_msi_vec_count(pdev);
1300 if (nvec < 0)
7b92b4f6
AG		 1301 goto intx;
1302
1303 /*
1304 * If number of MSIs is less than number of ports then Sharing Last
1305 * Message mode could be enforced. In this case assume that advantage
1306 * of multipe MSIs is negated and use single MSI mode instead.
1307 */
fc061d96 1308 if (nvec < n_ports)
7b92b4f6
AG		 1309 goto single_msi;
1310
ccf8f53c
AG		 1311 rc = pci_enable_msi_exact(pdev, nvec);
1312 if (rc == -ENOSPC)
fc40363b 1313 goto single_msi;
ccf8f53c 1314 else if (rc < 0)
fc061d96 1315 goto intx;
5ca72c4f 1316
ab0f9e78
AG		 1317 /* fallback to single MSI mode if the controller enforced MRSM mode */
1318 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1319 pci_disable_msi(pdev);
1320 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1321 goto single_msi;
1322 }
1323
c3ebd6a9
AG		 1324 if (nvec > 1)
1325 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1326
7b92b4f6
AG		 1327 return nvec;
1328
1329single_msi:
fc061d96 1330 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1331 goto intx;
1332 return 1;
1333
1334intx:
5ca72c4f
AG		 1335 pci_intx(pdev, 1);
1336 return 0;
1337}
1338
24dc5f33 1339static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1340{
e297d99e
TH		 1341 unsigned int board_id = ent->driver_data;
1342 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1343 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1344 struct device *dev = &pdev->dev;
1da177e4 1345 struct ahci_host_priv *hpriv;
4447d351 1346 struct ata_host *host;
c3ebd6a9 1347 int n_ports, i, rc;
318893e1 1348 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1349
1350 VPRINTK("ENTER\n");
1351
b429dd59 1352 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1353
06296a1e 1354 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1355
5b66c829
AC		 1356 /* The AHCI driver can only drive the SATA ports, the PATA driver
1357 can drive them all so if both drivers are selected make sure
1358 AHCI stays out of the way */
1359 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1360 return -ENODEV;
1361
cb85696d
JL		 1362 /* Apple BIOS on MCP89 prevents us using AHCI */
1363 if (is_mcp89_apple(pdev))
1364 ahci_mcp89_apple_enable(pdev);
c6353b45 1365
7a02267e
MN		 1366 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1367 * At the moment, we can only use the AHCI mode. Let the users know
1368 * that for SAS drives they're out of luck.
1369 */
1370 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1371 dev_info(&pdev->dev,
1372 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1373
7f9c9f8e 1374 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1375 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1376 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1377 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1378 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1379
e6b7e41c
CL		 1380 /*
1381 * The JMicron chip 361/363 contains one SATA controller and one
1382 * PATA controller,for powering on these both controllers, we must
1383 * follow the sequence one by one, otherwise one of them can not be
1384 * powered on successfully, so here we disable the async suspend
1385 * method for these chips.
1386 */
1387 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1388 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1389 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1390 device_disable_async_suspend(&pdev->dev);
1391
4447d351 1392 /* acquire resources */
24dc5f33 1393 rc = pcim_enable_device(pdev);
1da177e4
LT		 1394 if (rc)
1395 return rc;
1396
c4f7792c
TH		 1397 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1398 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1399 u8 map;
1400
1401 /* ICH6s share the same PCI ID for both piix and ahci
1402 * modes. Enabling ahci mode while MAP indicates
1403 * combined mode is a bad idea. Yield to ata_piix.
1404 */
1405 pci_read_config_byte(pdev, ICH_MAP, &map);
1406 if (map & 0x3) {
a44fec1f
JP		 1407 dev_info(&pdev->dev,
1408 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1409 return -ENODEV;
1410 }
1411 }
1412
6fec8871
PB		 1413 /* AHCI controllers often implement SFF compatible interface.
1414 * Grab all PCI BARs just in case.
1415 */
1416 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1417 if (rc == -EBUSY)
1418 pcim_pin_device(pdev);
1419 if (rc)
1420 return rc;
1421
24dc5f33
TH		 1422 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1423 if (!hpriv)
1424 return -ENOMEM;
417a1a6d
TH		 1425 hpriv->flags |= (unsigned long)pi.private_data;
1426
e297d99e
TH		 1427 /* MCP65 revision A1 and A2 can't do MSI */
1428 if (board_id == board_ahci_mcp65 &&
1429 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1430 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1431
e427fe04
SH		 1432 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1433 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1434 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1435
2fcad9d2
TH		 1436 /* only some SB600s can do 64bit DMA */
1437 if (ahci_sb600_enable_64bit(pdev))
1438 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1439
318893e1 1440 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1441
0cf4a7d6
JP		 1442 /* must set flag prior to save config in order to take effect */
1443 if (ahci_broken_devslp(pdev))
1444 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1445
4447d351 1446 /* save initial config */
394d6e53 1447 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1448
4447d351 1449 /* prepare host */
453d3131
RH		 1450 if (hpriv->cap & HOST_CAP_NCQ) {
1451 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1452 /*
1453 * Auto-activate optimization is supposed to be
1454 * supported on all AHCI controllers indicating NCQ
1455 * capability, but it seems to be broken on some
1456 * chipsets including NVIDIAs.
1457 */
1458 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1459 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1460
1461 /*
1462 * All AHCI controllers should be forward-compatible
1463 * with the new auxiliary field. This code should be
1464 * conditionalized if any buggy AHCI controllers are
1465 * encountered.
1466 */
1467 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1468 }
1da177e4 1469
7d50b60b
TH		 1470 if (hpriv->cap & HOST_CAP_PMP)
1471 pi.flags |= ATA_FLAG_PMP;
1472
0cbb0e77 1473 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1474
1fd68434
RW		 1475 if (ahci_broken_system_poweroff(pdev)) {
1476 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1477 dev_info(&pdev->dev,
1478 "quirky BIOS, skipping spindown on poweroff\n");
1479 }
1480
9b10ae86
TH		 1481 if (ahci_broken_suspend(pdev)) {
1482 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1483 dev_warn(&pdev->dev,
1484 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1485 }
1486
5594639a
TH		 1487 if (ahci_broken_online(pdev)) {
1488 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1489 dev_info(&pdev->dev,
1490 "online status unreliable, applying workaround\n");
1491 }
1492
837f5f8f
TH		 1493 /* CAP.NP sometimes indicate the index of the last enabled
1494 * port, at other times, that of the last possible port, so
1495 * determining the maximum port number requires looking at
1496 * both CAP.NP and port_map.
1497 */
1498 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1499
c3ebd6a9 1500 ahci_init_interrupts(pdev, n_ports, hpriv);
7b92b4f6 1501
837f5f8f 1502 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1503 if (!host)
1504 return -ENOMEM;
4447d351
TH		 1505 host->private_data = hpriv;
1506
f3d7f23f 1507 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1508 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1509 else
d2782d96 1510 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1511
18f7ba4c
KCA		 1512 if (pi.flags & ATA_FLAG_EM)
1513 ahci_reset_em(host);
1514
4447d351 1515 for (i = 0; i < host->n_ports; i++) {
dab632e8 1516 struct ata_port *ap = host->ports[i];
4447d351 1517
318893e1
AR		 1518 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1519 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1520 0x100 + ap->port_no * 0x80, "port");
1521
18f7ba4c
KCA		 1522 /* set enclosure management message type */
1523 if (ap->flags & ATA_FLAG_EM)
008dbd61 1524 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1525
1526
dab632e8 1527 /* disabled/not-implemented port */
350756f6 1528 if (!(hpriv->port_map & (1 << i)))
dab632e8 1529 ap->ops = &ata_dummy_port_ops;
4447d351 1530 }
d447df14 1531
edc93052
TH		 1532 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1533 ahci_p5wdh_workaround(host);
1534
f80ae7e4
TH		 1535 /* apply gtf filter quirk */
1536 ahci_gtf_filter_workaround(host);
1537
4447d351
TH		 1538 /* initialize adapter */
1539 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1540 if (rc)
24dc5f33 1541 return rc;
1da177e4 1542
3303040d 1543 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1544 if (rc)
1545 return rc;
1da177e4 1546
781d6550 1547 ahci_pci_init_controller(host);
439fcaec 1548 ahci_pci_print_info(host);
1da177e4 1549
4447d351 1550 pci_set_master(pdev);
5ca72c4f 1551
d1028e2f 1552 return ahci_host_activate(host, pdev->irq, &ahci_sht);
907f4678 1553}
1da177e4 1554
2fc75da0 1555module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1556
1557MODULE_AUTHOR("Jeff Garzik");
1558MODULE_DESCRIPTION("AHCI SATA low-level driver");
1559MODULE_LICENSE("GPL");
1560MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1561MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
This page took 1.115011 seconds and 5 git commands to generate.