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sata_fsl: remove check for CONFIG_MPC8315_DS
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
67809f85 63 board_ahci_noncq,
441577ef 64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
cb85696d
JL		 86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
438ac6d5 90#ifdef CONFIG_PM
c1332875
TH		 91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 93#endif
ad616ffb 94
fad16e7a
TH		 95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
029cfd6b
TH		 99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
a1efdaba 101 .hardreset = ahci_vt8251_hardreset,
029cfd6b 102};
edc93052 103
029cfd6b
TH		 104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
a1efdaba 106 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 107};
108
98ac62de 109static const struct ata_port_info ahci_port_info[] = {
441577ef 110 /* by features */
facb8fa6 111 [board_ahci] = {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
facb8fa6 117 [board_ahci_ign_iferr] = {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
67809f85
LK		 124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
facb8fa6 131 [board_ahci_nosntf] = {
441577ef 132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 133 .flags = AHCI_FLAG_COMMON,
14bdef98 134 .pio_mask = ATA_PIO4,
469248ab 135 .udma_mask = ATA_UDMA6,
41669553
TH		 136 .port_ops = &ahci_ops,
137 },
facb8fa6 138 [board_ahci_yes_fbs] = {
5f173107
TH		 139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
441577ef 145 /* by chipsets */
facb8fa6 146 [board_ahci_mcp65] = {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
ae01b249 149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_mcp77] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
facb8fa6 161 [board_ahci_mcp89] = {
83f2b963 162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 163 .flags = AHCI_FLAG_COMMON,
14bdef98 164 .pio_mask = ATA_PIO4,
469248ab 165 .udma_mask = ATA_UDMA6,
441577ef 166 .port_ops = &ahci_ops,
55a61604 167 },
facb8fa6 168 [board_ahci_mv] = {
417a1a6d 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 172 .pio_mask = ATA_PIO4,
cd70c266
JG		 173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
facb8fa6 176 [board_ahci_sb600] = {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
facb8fa6 185 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
facb8fa6 192 [board_ahci_vt8251] = {
441577ef 193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_vt8251_ops,
1b677afd 198 },
1da177e4
LT		 199};
200
3b7d697d 201static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 202 /* Intel */
54bb3a94
JG		 203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
fe7fa31a 308
e34bb370
TH		 309 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
310 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
311 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 312 /* JMicron 362B and 362C have an AHCI function with IDE class code */
313 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
314 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 315
316 /* ATI */
c65ec1c2 317 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 318 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 324
e2dd90b1 325 /* AMD */
5deab536 326 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 327 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 328 /* AMD is using RAID class only for ahci controllers */
329 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
331
fe7fa31a 332 /* VIA */
54bb3a94 333 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 334 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 335
336 /* NVIDIA */
e297d99e
TH		 337 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 345 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 421
95916edd 422 /* SiS */
20e2de4a
TH		 423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 426
318893e1
AR		 427 /* ST Microelectronics */
428 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
429
cd70c266
JG		 430 /* Marvell */
431 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 432 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 434 .class = PCI_CLASS_STORAGE_SATA_AHCI,
435 .class_mask = 0xffffff,
5f173107 436 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 438 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 439 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
440 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 443 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 446 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 447 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
69fd3157 448 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 449 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
451 .driver_data = board_ahci_yes_fbs },
cd70c266 452
c77a036b
MN		 453 /* Promise */
454 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
455
c9703765 456 /* Asmedia */
7b4f6eca
AC		 457 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
458 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
459 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
460 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 461
67809f85
LK		 462 /*
463 * Samsung SSDs found on some macbooks. NCQ times out.
464 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
465 */
466 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
467
7f9c9f8e
HD		 468 /* Enmotus */
469 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
470
415ae2b5
JG		 471 /* Generic, PCI class code for AHCI */
472 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 473 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 474
1da177e4
LT		 475 { } /* terminate list */
476};
477
478
479static struct pci_driver ahci_pci_driver = {
480 .name = DRV_NAME,
481 .id_table = ahci_pci_tbl,
482 .probe = ahci_init_one,
24dc5f33 483 .remove = ata_pci_remove_one,
438ac6d5 484#ifdef CONFIG_PM
c1332875 485 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 486 .resume = ahci_pci_device_resume,
487#endif
488};
1da177e4 489
365cfa1e
AV		 490#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
491static int marvell_enable;
492#else
493static int marvell_enable = 1;
494#endif
495module_param(marvell_enable, int, 0644);
496MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 497
1da177e4 498
365cfa1e
AV		 499static void ahci_pci_save_initial_config(struct pci_dev *pdev,
500 struct ahci_host_priv *hpriv)
501{
502 unsigned int force_port_map = 0;
503 unsigned int mask_port_map = 0;
67846b30 504
365cfa1e
AV		 505 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
506 dev_info(&pdev->dev, "JMB361 has only one port\n");
507 force_port_map = 1;
1da177e4
LT		 508 }
509
365cfa1e
AV		 510 /*
511 * Temporary Marvell 6145 hack: PATA port presence
512 * is asserted through the standard AHCI port
513 * presence register, as bit 4 (counting from 0)
d28f87aa 514 */
365cfa1e
AV		 515 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
516 if (pdev->device == 0x6121)
517 mask_port_map = 0x3;
518 else
519 mask_port_map = 0xf;
520 dev_info(&pdev->dev,
521 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
522 }
1da177e4 523
365cfa1e
AV		 524 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
525 mask_port_map);
1da177e4
LT		 526}
527
365cfa1e 528static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 529{
365cfa1e 530 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 531
365cfa1e 532 ahci_reset_controller(host);
1da177e4 533
365cfa1e
AV		 534 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
535 struct ahci_host_priv *hpriv = host->private_data;
536 u16 tmp16;
d6ef3153 537
365cfa1e
AV		 538 /* configure PCS */
539 pci_read_config_word(pdev, 0x92, &tmp16);
540 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
541 tmp16 |= hpriv->port_map;
542 pci_write_config_word(pdev, 0x92, tmp16);
543 }
d6ef3153
SH		 544 }
545
1da177e4
LT		 546 return 0;
547}
548
365cfa1e 549static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 550{
365cfa1e
AV		 551 struct ahci_host_priv *hpriv = host->private_data;
552 struct pci_dev *pdev = to_pci_dev(host->dev);
553 void __iomem *port_mmio;
78cd52d0 554 u32 tmp;
365cfa1e 555 int mv;
78cd52d0 556
365cfa1e
AV		 557 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
558 if (pdev->device == 0x6121)
559 mv = 2;
560 else
561 mv = 4;
562 port_mmio = __ahci_port_base(host, mv);
78cd52d0 563
365cfa1e 564 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 565
365cfa1e
AV		 566 /* clear port IRQ */
567 tmp = readl(port_mmio + PORT_IRQ_STAT);
568 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
569 if (tmp)
570 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 571 }
572
365cfa1e 573 ahci_init_controller(host);
edc93052
TH		 574}
575
365cfa1e
AV		 576static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
577 unsigned long deadline)
d6ef3153 578{
365cfa1e 579 struct ata_port *ap = link->ap;
039ece38 580 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 581 bool online;
d6ef3153
SH		 582 int rc;
583
365cfa1e 584 DPRINTK("ENTER\n");
d6ef3153 585
365cfa1e 586 ahci_stop_engine(ap);
d6ef3153 587
365cfa1e
AV		 588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
589 deadline, &online, NULL);
d6ef3153 590
039ece38 591 hpriv->start_engine(ap);
d6ef3153 592
365cfa1e 593 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 594
365cfa1e
AV		 595 /* vt8251 doesn't clear BSY on signature FIS reception,
596 * request follow-up softreset.
597 */
598 return online ? -EAGAIN : rc;
7d50b60b
TH		 599}
600
365cfa1e
AV		 601static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
602 unsigned long deadline)
7d50b60b 603{
365cfa1e 604 struct ata_port *ap = link->ap;
1c954a4d 605 struct ahci_port_priv *pp = ap->private_data;
039ece38 606 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 607 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
608 struct ata_taskfile tf;
609 bool online;
610 int rc;
7d50b60b 611
365cfa1e 612 ahci_stop_engine(ap);
028a2596 613
365cfa1e
AV		 614 /* clear D2H reception area to properly wait for D2H FIS */
615 ata_tf_init(link->device, &tf);
9bbb1b0e 616 tf.command = ATA_BUSY;
365cfa1e 617 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 618
365cfa1e
AV		 619 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
620 deadline, &online, NULL);
028a2596 621
039ece38 622 hpriv->start_engine(ap);
c1332875 623
365cfa1e
AV		 624 /* The pseudo configuration device on SIMG4726 attached to
625 * ASUS P5W-DH Deluxe doesn't send signature FIS after
626 * hardreset if no device is attached to the first downstream
627 * port && the pseudo device locks up on SRST w/ PMP==0. To
628 * work around this, wait for !BSY only briefly. If BSY isn't
629 * cleared, perform CLO and proceed to IDENTIFY (achieved by
630 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
631 *
632 * Wait for two seconds. Devices attached to downstream port
633 * which can't process the following IDENTIFY after this will
634 * have to be reset again. For most cases, this should
635 * suffice while making probing snappish enough.
636 */
637 if (online) {
638 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
639 ahci_check_ready);
640 if (rc)
641 ahci_kick_engine(ap);
c1332875 642 }
c1332875
TH		 643 return rc;
644}
645
365cfa1e 646#ifdef CONFIG_PM
c1332875
TH		 647static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
648{
0a86e1c8 649 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 650 struct ahci_host_priv *hpriv = host->private_data;
d8993349 651 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 652 u32 ctl;
653
9b10ae86
TH		 654 if (mesg.event & PM_EVENT_SUSPEND &&
655 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 656 dev_err(&pdev->dev,
657 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 658 return -EIO;
659 }
660
3a2d5b70 661 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 662 /* AHCI spec rev1.1 section 8.3.3:
663 * Software must disable interrupts prior to requesting a
664 * transition of the HBA to D3 state.
665 */
666 ctl = readl(mmio + HOST_CTL);
667 ctl &= ~HOST_IRQ_EN;
668 writel(ctl, mmio + HOST_CTL);
669 readl(mmio + HOST_CTL); /* flush */
670 }
671
672 return ata_pci_device_suspend(pdev, mesg);
673}
674
675static int ahci_pci_device_resume(struct pci_dev *pdev)
676{
0a86e1c8 677 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 678 int rc;
679
553c4aa6
TH		 680 rc = ata_pci_device_do_resume(pdev);
681 if (rc)
682 return rc;
c1332875 683
cb85696d
JL		 684 /* Apple BIOS helpfully mangles the registers on resume */
685 if (is_mcp89_apple(pdev))
686 ahci_mcp89_apple_enable(pdev);
687
c1332875 688 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 689 rc = ahci_pci_reset_controller(host);
c1332875
TH		 690 if (rc)
691 return rc;
692
781d6550 693 ahci_pci_init_controller(host);
c1332875
TH		 694 }
695
cca3974e 696 ata_host_resume(host);
c1332875
TH		 697
698 return 0;
699}
438ac6d5 700#endif
c1332875 701
4447d351 702static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 703{
1da177e4 704 int rc;
1da177e4 705
318893e1
AR		 706 /*
707 * If the device fixup already set the dma_mask to some non-standard
708 * value, don't extend it here. This happens on STA2X11, for example.
709 */
710 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
711 return 0;
712
1da177e4 713 if (using_dac &&
6a35528a
YH		 714 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
715 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 716 if (rc) {
284901a9 717 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 718 if (rc) {
a44fec1f
JP		 719 dev_err(&pdev->dev,
720 "64-bit DMA enable failed\n");
1da177e4
LT		 721 return rc;
722 }
723 }
1da177e4 724 } else {
284901a9 725 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 726 if (rc) {
a44fec1f 727 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 728 return rc;
729 }
284901a9 730 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 731 if (rc) {
a44fec1f
JP		 732 dev_err(&pdev->dev,
733 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 734 return rc;
735 }
736 }
1da177e4
LT		 737 return 0;
738}
739
439fcaec
AV		 740static void ahci_pci_print_info(struct ata_host *host)
741{
742 struct pci_dev *pdev = to_pci_dev(host->dev);
743 u16 cc;
744 const char *scc_s;
745
746 pci_read_config_word(pdev, 0x0a, &cc);
747 if (cc == PCI_CLASS_STORAGE_IDE)
748 scc_s = "IDE";
749 else if (cc == PCI_CLASS_STORAGE_SATA)
750 scc_s = "SATA";
751 else if (cc == PCI_CLASS_STORAGE_RAID)
752 scc_s = "RAID";
753 else
754 scc_s = "unknown";
755
756 ahci_print_info(host, scc_s);
757}
758
edc93052
TH		 759/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
760 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
761 * support PMP and the 4726 either directly exports the device
762 * attached to the first downstream port or acts as a hardware storage
763 * controller and emulate a single ATA device (can be RAID 0/1 or some
764 * other configuration).
765 *
766 * When there's no device attached to the first downstream port of the
767 * 4726, "Config Disk" appears, which is a pseudo ATA device to
768 * configure the 4726. However, ATA emulation of the device is very
769 * lame. It doesn't send signature D2H Reg FIS after the initial
770 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
771 *
772 * The following function works around the problem by always using
773 * hardreset on the port and not depending on receiving signature FIS
774 * afterward. If signature FIS isn't received soon, ATA class is
775 * assumed without follow-up softreset.
776 */
777static void ahci_p5wdh_workaround(struct ata_host *host)
778{
779 static struct dmi_system_id sysids[] = {
780 {
781 .ident = "P5W DH Deluxe",
782 .matches = {
783 DMI_MATCH(DMI_SYS_VENDOR,
784 "ASUSTEK COMPUTER INC"),
785 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
786 },
787 },
788 { }
789 };
790 struct pci_dev *pdev = to_pci_dev(host->dev);
791
792 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
793 dmi_check_system(sysids)) {
794 struct ata_port *ap = host->ports[1];
795
a44fec1f
JP		 796 dev_info(&pdev->dev,
797 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 798
799 ap->ops = &ahci_p5wdh_ops;
800 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
801 }
802}
803
cb85696d
JL		 804/*
805 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
806 * booting in BIOS compatibility mode. We restore the registers but not ID.
807 */
808static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
809{
810 u32 val;
811
812 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
813
814 pci_read_config_dword(pdev, 0xf8, &val);
815 val |= 1 << 0x1b;
816 /* the following changes the device ID, but appears not to affect function */
817 /* val = (val & ~0xf0000000) | 0x80000000; */
818 pci_write_config_dword(pdev, 0xf8, val);
819
820 pci_read_config_dword(pdev, 0x54c, &val);
821 val |= 1 << 0xc;
822 pci_write_config_dword(pdev, 0x54c, val);
823
824 pci_read_config_dword(pdev, 0x4a4, &val);
825 val &= 0xff;
826 val |= 0x01060100;
827 pci_write_config_dword(pdev, 0x4a4, val);
828
829 pci_read_config_dword(pdev, 0x54c, &val);
830 val &= ~(1 << 0xc);
831 pci_write_config_dword(pdev, 0x54c, val);
832
833 pci_read_config_dword(pdev, 0xf8, &val);
834 val &= ~(1 << 0x1b);
835 pci_write_config_dword(pdev, 0xf8, val);
836}
837
838static bool is_mcp89_apple(struct pci_dev *pdev)
839{
840 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
841 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
842 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
843 pdev->subsystem_device == 0xcb89;
844}
845
2fcad9d2
TH		 846/* only some SB600 ahci controllers can do 64bit DMA */
847static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 848{
849 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 850 /*
851 * The oldest version known to be broken is 0901 and
852 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 853 * Enable 64bit DMA on 1501 and anything newer.
854 *
03d783bf
TH		 855 * Please read bko#9412 for more info.
856 */
58a09b38
SH		 857 {
858 .ident = "ASUS M2A-VM",
859 .matches = {
860 DMI_MATCH(DMI_BOARD_VENDOR,
861 "ASUSTeK Computer INC."),
862 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
863 },
03d783bf 864 .driver_data = "20071026", /* yyyymmdd */
58a09b38 865 },
e65cc194
MN		 866 /*
867 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
868 * support 64bit DMA.
869 *
870 * BIOS versions earlier than 1.5 had the Manufacturer DMI
871 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
872 * This spelling mistake was fixed in BIOS version 1.5, so
873 * 1.5 and later have the Manufacturer as
874 * "MICRO-STAR INTERNATIONAL CO.,LTD".
875 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
876 *
877 * BIOS versions earlier than 1.9 had a Board Product Name
878 * DMI field of "MS-7376". This was changed to be
879 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
880 * match on DMI_BOARD_NAME of "MS-7376".
881 */
882 {
883 .ident = "MSI K9A2 Platinum",
884 .matches = {
885 DMI_MATCH(DMI_BOARD_VENDOR,
886 "MICRO-STAR INTER"),
887 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
888 },
889 },
ff0173c1
MN		 890 /*
891 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
892 * 64bit DMA.
893 *
894 * This board also had the typo mentioned above in the
895 * Manufacturer DMI field (fixed in BIOS version 1.5), so
896 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
897 */
898 {
899 .ident = "MSI K9AGM2",
900 .matches = {
901 DMI_MATCH(DMI_BOARD_VENDOR,
902 "MICRO-STAR INTER"),
903 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
904 },
905 },
3c4aa91f
MN		 906 /*
907 * All BIOS versions for the Asus M3A support 64bit DMA.
908 * (all release versions from 0301 to 1206 were tested)
909 */
910 {
911 .ident = "ASUS M3A",
912 .matches = {
913 DMI_MATCH(DMI_BOARD_VENDOR,
914 "ASUSTeK Computer INC."),
915 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
916 },
917 },
58a09b38
SH		 918 { }
919 };
03d783bf 920 const struct dmi_system_id *match;
2fcad9d2
TH		 921 int year, month, date;
922 char buf[9];
58a09b38 923
03d783bf 924 match = dmi_first_match(sysids);
58a09b38 925 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 926 !match)
58a09b38
SH		 927 return false;
928
e65cc194
MN		 929 if (!match->driver_data)
930 goto enable_64bit;
931
2fcad9d2
TH		 932 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
933 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 934
e65cc194
MN		 935 if (strcmp(buf, match->driver_data) >= 0)
936 goto enable_64bit;
937 else {
a44fec1f
JP		 938 dev_warn(&pdev->dev,
939 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
940 match->ident);
2fcad9d2
TH		 941 return false;
942 }
e65cc194
MN		 943
944enable_64bit:
a44fec1f 945 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 946 return true;
58a09b38
SH		 947}
948
1fd68434
RW		 949static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
950{
951 static const struct dmi_system_id broken_systems[] = {
952 {
953 .ident = "HP Compaq nx6310",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
957 },
958 /* PCI slot number of the controller */
959 .driver_data = (void *)0x1FUL,
960 },
d2f9c061
MR		 961 {
962 .ident = "HP Compaq 6720s",
963 .matches = {
964 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
965 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
966 },
967 /* PCI slot number of the controller */
968 .driver_data = (void *)0x1FUL,
969 },
1fd68434
RW		 970
971 { } /* terminate list */
972 };
973 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
974
975 if (dmi) {
976 unsigned long slot = (unsigned long)dmi->driver_data;
977 /* apply the quirk only to on-board controllers */
978 return slot == PCI_SLOT(pdev->devfn);
979 }
980
981 return false;
982}
983
9b10ae86
TH		 984static bool ahci_broken_suspend(struct pci_dev *pdev)
985{
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
989 * to the harddisk doesn't become online after
990 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 991 *
992 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
993 *
994 * Use dates instead of versions to match as HP is
995 * apparently recycling both product and version
996 * strings.
997 *
998 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 999 */
1000 {
1001 .ident = "dv4",
1002 .matches = {
1003 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1004 DMI_MATCH(DMI_PRODUCT_NAME,
1005 "HP Pavilion dv4 Notebook PC"),
1006 },
9deb3431 1007 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1008 },
1009 {
1010 .ident = "dv5",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1013 DMI_MATCH(DMI_PRODUCT_NAME,
1014 "HP Pavilion dv5 Notebook PC"),
1015 },
9deb3431 1016 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1017 },
1018 {
1019 .ident = "dv6",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1022 DMI_MATCH(DMI_PRODUCT_NAME,
1023 "HP Pavilion dv6 Notebook PC"),
1024 },
9deb3431 1025 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1026 },
1027 {
1028 .ident = "HDX18",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031 DMI_MATCH(DMI_PRODUCT_NAME,
1032 "HP HDX18 Notebook PC"),
1033 },
9deb3431 1034 .driver_data = "20090430", /* F.23 */
9b10ae86 1035 },
cedc9bf9
TH		 1036 /*
1037 * Acer eMachines G725 has the same problem. BIOS
1038 * V1.03 is known to be broken. V3.04 is known to
25985edc 1039 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1040 * that we don't have much idea about. For now,
1041 * blacklist anything older than V3.04.
9deb3431
TH		 1042 *
1043 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1044 */
1045 {
1046 .ident = "G725",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1050 },
9deb3431 1051 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1052 },
9b10ae86
TH		 1053 { } /* terminate list */
1054 };
1055 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1056 int year, month, date;
1057 char buf[9];
9b10ae86
TH		 1058
1059 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1060 return false;
1061
9deb3431
TH		 1062 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1063 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1064
9deb3431 1065 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1066}
1067
5594639a
TH		 1068static bool ahci_broken_online(struct pci_dev *pdev)
1069{
1070#define ENCODE_BUSDEVFN(bus, slot, func) \
1071 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1072 static const struct dmi_system_id sysids[] = {
1073 /*
1074 * There are several gigabyte boards which use
1075 * SIMG5723s configured as hardware RAID. Certain
1076 * 5723 firmware revisions shipped there keep the link
1077 * online but fail to answer properly to SRST or
1078 * IDENTIFY when no device is attached downstream
1079 * causing libata to retry quite a few times leading
1080 * to excessive detection delay.
1081 *
1082 * As these firmwares respond to the second reset try
1083 * with invalid device signature, considering unknown
1084 * sig as offline works around the problem acceptably.
1085 */
1086 {
1087 .ident = "EP45-DQ6",
1088 .matches = {
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "Gigabyte Technology Co., Ltd."),
1091 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1092 },
1093 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1094 },
1095 {
1096 .ident = "EP45-DS5",
1097 .matches = {
1098 DMI_MATCH(DMI_BOARD_VENDOR,
1099 "Gigabyte Technology Co., Ltd."),
1100 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1101 },
1102 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1103 },
1104 { } /* terminate list */
1105 };
1106#undef ENCODE_BUSDEVFN
1107 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1108 unsigned int val;
1109
1110 if (!dmi)
1111 return false;
1112
1113 val = (unsigned long)dmi->driver_data;
1114
1115 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1116}
1117
8e513217 1118#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1119static void ahci_gtf_filter_workaround(struct ata_host *host)
1120{
1121 static const struct dmi_system_id sysids[] = {
1122 /*
1123 * Aspire 3810T issues a bunch of SATA enable commands
1124 * via _GTF including an invalid one and one which is
1125 * rejected by the device. Among the successful ones
1126 * is FPDMA non-zero offset enable which when enabled
1127 * only on the drive side leads to NCQ command
1128 * failures. Filter it out.
1129 */
1130 {
1131 .ident = "Aspire 3810T",
1132 .matches = {
1133 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1134 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1135 },
1136 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1137 },
1138 { }
1139 };
1140 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1141 unsigned int filter;
1142 int i;
1143
1144 if (!dmi)
1145 return;
1146
1147 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1148 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1149 filter, dmi->ident);
f80ae7e4
TH		 1150
1151 for (i = 0; i < host->n_ports; i++) {
1152 struct ata_port *ap = host->ports[i];
1153 struct ata_link *link;
1154 struct ata_device *dev;
1155
1156 ata_for_each_link(link, ap, EDGE)
1157 ata_for_each_dev(dev, link, ALL)
1158 dev->gtf_filter |= filter;
1159 }
1160}
8e513217
MT		 1161#else
1162static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1163{}
1164#endif
f80ae7e4 1165
e1ba8459 1166static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
7b92b4f6 1167 struct ahci_host_priv *hpriv)
5ca72c4f 1168{
fc061d96 1169 int nvec;
5ca72c4f 1170
7b92b4f6
AG		 1171 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1172 goto intx;
1173
fc061d96
AG		 1174 nvec = pci_msi_vec_count(pdev);
1175 if (nvec < 0)
7b92b4f6
AG		 1176 goto intx;
1177
1178 /*
1179 * If number of MSIs is less than number of ports then Sharing Last
1180 * Message mode could be enforced. In this case assume that advantage
1181 * of multipe MSIs is negated and use single MSI mode instead.
1182 */
fc061d96 1183 if (nvec < n_ports)
7b92b4f6
AG		 1184 goto single_msi;
1185
fc061d96
AG		 1186 nvec = pci_enable_msi_range(pdev, nvec, nvec);
1187 if (nvec == -ENOSPC)
fc40363b 1188 goto single_msi;
fc061d96
AG		 1189 else if (nvec < 0)
1190 goto intx;
5ca72c4f 1191
7b92b4f6
AG		 1192 return nvec;
1193
1194single_msi:
fc061d96 1195 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1196 goto intx;
1197 return 1;
1198
1199intx:
5ca72c4f
AG		 1200 pci_intx(pdev, 1);
1201 return 0;
1202}
1203
1204/**
1205 * ahci_host_activate - start AHCI host, request IRQs and register it
1206 * @host: target ATA host
1207 * @irq: base IRQ number to request
1208 * @n_msis: number of MSIs allocated for this host
1209 * @irq_handler: irq_handler used when requesting IRQs
1210 * @irq_flags: irq_flags used when requesting IRQs
1211 *
1212 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1213 * when multiple MSIs were allocated. That is one MSI per port, starting
1214 * from @irq.
1215 *
1216 * LOCKING:
1217 * Inherited from calling layer (may sleep).
1218 *
1219 * RETURNS:
1220 * 0 on success, -errno otherwise.
1221 */
1222int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1223{
1224 int i, rc;
1225
1226 /* Sharing Last Message among several ports is not supported */
1227 if (n_msis < host->n_ports)
1228 return -EINVAL;
1229
1230 rc = ata_host_start(host);
1231 if (rc)
1232 return rc;
1233
1234 for (i = 0; i < host->n_ports; i++) {
c91bc6cc 1235 const char* desc;
b29900e6
AG		 1236 struct ahci_port_priv *pp = host->ports[i]->private_data;
1237
c91bc6cc
XF		 1238 /* pp is NULL for dummy ports */
1239 if (pp)
1240 desc = pp->irq_desc;
1241 else
1242 desc = dev_driver_string(host->dev);
1243
5ca72c4f
AG		 1244 rc = devm_request_threaded_irq(host->dev,
1245 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
c91bc6cc 1246 desc, host->ports[i]);
5ca72c4f
AG		 1247 if (rc)
1248 goto out_free_irqs;
1249 }
1250
1251 for (i = 0; i < host->n_ports; i++)
1252 ata_port_desc(host->ports[i], "irq %d", irq + i);
1253
1254 rc = ata_host_register(host, &ahci_sht);
1255 if (rc)
1256 goto out_free_all_irqs;
1257
1258 return 0;
1259
1260out_free_all_irqs:
1261 i = host->n_ports;
1262out_free_irqs:
1263 for (i--; i >= 0; i--)
1264 devm_free_irq(host->dev, irq + i, host->ports[i]);
1265
1266 return rc;
1267}
1268
24dc5f33 1269static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1270{
e297d99e
TH		 1271 unsigned int board_id = ent->driver_data;
1272 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1273 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1274 struct device *dev = &pdev->dev;
1da177e4 1275 struct ahci_host_priv *hpriv;
4447d351 1276 struct ata_host *host;
5ca72c4f 1277 int n_ports, n_msis, i, rc;
318893e1 1278 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1279
1280 VPRINTK("ENTER\n");
1281
b429dd59 1282 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1283
06296a1e 1284 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1285
5b66c829
AC		 1286 /* The AHCI driver can only drive the SATA ports, the PATA driver
1287 can drive them all so if both drivers are selected make sure
1288 AHCI stays out of the way */
1289 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1290 return -ENODEV;
1291
cb85696d
JL		 1292 /* Apple BIOS on MCP89 prevents us using AHCI */
1293 if (is_mcp89_apple(pdev))
1294 ahci_mcp89_apple_enable(pdev);
c6353b45 1295
7a02267e
MN		 1296 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1297 * At the moment, we can only use the AHCI mode. Let the users know
1298 * that for SAS drives they're out of luck.
1299 */
1300 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1301 dev_info(&pdev->dev,
1302 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1303
7f9c9f8e 1304 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1305 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1306 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1307 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1308 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1309
4447d351 1310 /* acquire resources */
24dc5f33 1311 rc = pcim_enable_device(pdev);
1da177e4
LT		 1312 if (rc)
1313 return rc;
1314
c4f7792c
TH		 1315 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1316 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1317 u8 map;
1318
1319 /* ICH6s share the same PCI ID for both piix and ahci
1320 * modes. Enabling ahci mode while MAP indicates
1321 * combined mode is a bad idea. Yield to ata_piix.
1322 */
1323 pci_read_config_byte(pdev, ICH_MAP, &map);
1324 if (map & 0x3) {
a44fec1f
JP		 1325 dev_info(&pdev->dev,
1326 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1327 return -ENODEV;
1328 }
1329 }
1330
6fec8871
PB		 1331 /* AHCI controllers often implement SFF compatible interface.
1332 * Grab all PCI BARs just in case.
1333 */
1334 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1335 if (rc == -EBUSY)
1336 pcim_pin_device(pdev);
1337 if (rc)
1338 return rc;
1339
24dc5f33
TH		 1340 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1341 if (!hpriv)
1342 return -ENOMEM;
417a1a6d
TH		 1343 hpriv->flags |= (unsigned long)pi.private_data;
1344
e297d99e
TH		 1345 /* MCP65 revision A1 and A2 can't do MSI */
1346 if (board_id == board_ahci_mcp65 &&
1347 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1348 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1349
e427fe04
SH		 1350 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1351 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1352 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1353
2fcad9d2
TH		 1354 /* only some SB600s can do 64bit DMA */
1355 if (ahci_sb600_enable_64bit(pdev))
1356 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1357
318893e1 1358 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1359
4447d351 1360 /* save initial config */
394d6e53 1361 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1362
4447d351 1363 /* prepare host */
453d3131
RH		 1364 if (hpriv->cap & HOST_CAP_NCQ) {
1365 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1366 /*
1367 * Auto-activate optimization is supposed to be
1368 * supported on all AHCI controllers indicating NCQ
1369 * capability, but it seems to be broken on some
1370 * chipsets including NVIDIAs.
1371 */
1372 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1373 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1374
1375 /*
1376 * All AHCI controllers should be forward-compatible
1377 * with the new auxiliary field. This code should be
1378 * conditionalized if any buggy AHCI controllers are
1379 * encountered.
1380 */
1381 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1382 }
1da177e4 1383
7d50b60b
TH		 1384 if (hpriv->cap & HOST_CAP_PMP)
1385 pi.flags |= ATA_FLAG_PMP;
1386
0cbb0e77 1387 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1388
1fd68434
RW		 1389 if (ahci_broken_system_poweroff(pdev)) {
1390 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1391 dev_info(&pdev->dev,
1392 "quirky BIOS, skipping spindown on poweroff\n");
1393 }
1394
9b10ae86
TH		 1395 if (ahci_broken_suspend(pdev)) {
1396 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1397 dev_warn(&pdev->dev,
1398 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1399 }
1400
5594639a
TH		 1401 if (ahci_broken_online(pdev)) {
1402 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1403 dev_info(&pdev->dev,
1404 "online status unreliable, applying workaround\n");
1405 }
1406
837f5f8f
TH		 1407 /* CAP.NP sometimes indicate the index of the last enabled
1408 * port, at other times, that of the last possible port, so
1409 * determining the maximum port number requires looking at
1410 * both CAP.NP and port_map.
1411 */
1412 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1413
7b92b4f6
AG		 1414 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1415 if (n_msis > 1)
1416 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1417
837f5f8f 1418 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1419 if (!host)
1420 return -ENOMEM;
4447d351
TH		 1421 host->private_data = hpriv;
1422
f3d7f23f 1423 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1424 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1425 else
d2782d96 1426 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1427
18f7ba4c
KCA		 1428 if (pi.flags & ATA_FLAG_EM)
1429 ahci_reset_em(host);
1430
4447d351 1431 for (i = 0; i < host->n_ports; i++) {
dab632e8 1432 struct ata_port *ap = host->ports[i];
4447d351 1433
318893e1
AR		 1434 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1435 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1436 0x100 + ap->port_no * 0x80, "port");
1437
18f7ba4c
KCA		 1438 /* set enclosure management message type */
1439 if (ap->flags & ATA_FLAG_EM)
008dbd61 1440 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1441
1442
dab632e8 1443 /* disabled/not-implemented port */
350756f6 1444 if (!(hpriv->port_map & (1 << i)))
dab632e8 1445 ap->ops = &ata_dummy_port_ops;
4447d351 1446 }
d447df14 1447
edc93052
TH		 1448 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1449 ahci_p5wdh_workaround(host);
1450
f80ae7e4
TH		 1451 /* apply gtf filter quirk */
1452 ahci_gtf_filter_workaround(host);
1453
4447d351
TH		 1454 /* initialize adapter */
1455 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1456 if (rc)
24dc5f33 1457 return rc;
1da177e4 1458
3303040d 1459 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1460 if (rc)
1461 return rc;
1da177e4 1462
781d6550 1463 ahci_pci_init_controller(host);
439fcaec 1464 ahci_pci_print_info(host);
1da177e4 1465
4447d351 1466 pci_set_master(pdev);
5ca72c4f
AG		 1467
1468 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1469 return ahci_host_activate(host, pdev->irq, n_msis);
1470
4447d351
TH		 1471 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1472 &ahci_sht);
907f4678 1473}
1da177e4 1474
2fc75da0 1475module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1476
1477MODULE_AUTHOR("Jeff Garzik");
1478MODULE_DESCRIPTION("AHCI SATA low-level driver");
1479MODULE_LICENSE("GPL");
1480MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1481MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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