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ata_piix: add Toshiba Tecra M4 to broken suspend list
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
31556594
KCA		 52static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54static void ahci_disable_alpm(struct ata_port *ap);
1da177e4
LT		 55
56enum {
57 AHCI_PCI_BAR = 5,
648a88be 58 AHCI_MAX_PORTS = 32,
1da177e4
LT		 59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 61 AHCI_USE_CLUSTERING = 1,
12fad3f9 62 AHCI_MAX_CMDS = 32,
dd410ff1 63 AHCI_CMD_SZ = 32,
12fad3f9 64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 65 AHCI_RX_FIS_SZ = 256,
a0ea7328 66 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
4b10e559 75 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 82
83 board_ahci = 0,
7a234aff
TH		 84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
1da177e4
LT		 88
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
0be0aa98 102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
78cd52d0
TH		 148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
4296971d 151 PORT_IRQ_PHYRDY |
7d50b60b
TH		 152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 160
161 /* PORT_CMD bits */
31556594
KCA		 162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 169 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
0be0aa98 174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 178
417a1a6d
TH		 179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
417a1a6d 188
bf2af2a2 189 /* ap->flags bits */
1188c0d8
TH		 190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
0c88758b 195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
1da177e4
LT		 196};
197
198struct ahci_cmd_hdr {
199 u32 opts;
200 u32 status;
201 u32 tbl_addr;
202 u32 tbl_addr_hi;
203 u32 reserved[4];
204};
205
206struct ahci_sg {
207 u32 addr;
208 u32 addr_hi;
209 u32 reserved;
210 u32 flags_size;
211};
212
213struct ahci_host_priv {
417a1a6d 214 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 215 u32 cap; /* cap to use */
216 u32 port_map; /* port map to use */
217 u32 saved_cap; /* saved initial cap */
218 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 219};
220
221struct ahci_port_priv {
7d50b60b 222 struct ata_link *active_link;
1da177e4
LT		 223 struct ahci_cmd_hdr *cmd_slot;
224 dma_addr_t cmd_slot_dma;
225 void *cmd_tbl;
226 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 227 void *rx_fis;
228 dma_addr_t rx_fis_dma;
0291f95f 229 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 230 unsigned int ncq_saw_d2h:1;
231 unsigned int ncq_saw_dmas:1;
afb2d552 232 unsigned int ncq_saw_sdb:1;
a7384925 233 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 234};
235
da3dbb17
TH		 236static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
237static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 238static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 239static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 240static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 241static int ahci_port_start(struct ata_port *ap);
242static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 243static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
244static void ahci_qc_prep(struct ata_queued_cmd *qc);
245static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 246static void ahci_freeze(struct ata_port *ap);
247static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 248static void ahci_pmp_attach(struct ata_port *ap);
249static void ahci_pmp_detach(struct ata_port *ap);
78cd52d0 250static void ahci_error_handler(struct ata_port *ap);
ad616ffb 251static void ahci_vt8251_error_handler(struct ata_port *ap);
edc93052 252static void ahci_p5wdh_error_handler(struct ata_port *ap);
78cd52d0 253static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 254static int ahci_port_resume(struct ata_port *ap);
dab632e8
JG		 255static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
256static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
257 u32 opts);
438ac6d5 258#ifdef CONFIG_PM
c1332875 259static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 260static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
261static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 262#endif
1da177e4 263
31556594
KCA		 264static struct class_device_attribute *ahci_shost_attrs[] = {
265 &class_device_attr_link_power_management_policy,
266 NULL
267};
268
193515d5 269static struct scsi_host_template ahci_sht = {
1da177e4
LT		 270 .module = THIS_MODULE,
271 .name = DRV_NAME,
272 .ioctl = ata_scsi_ioctl,
273 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 274 .change_queue_depth = ata_scsi_change_queue_depth,
275 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 276 .this_id = ATA_SHT_THIS_ID,
277 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 278 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
279 .emulated = ATA_SHT_EMULATED,
280 .use_clustering = AHCI_USE_CLUSTERING,
281 .proc_name = DRV_NAME,
282 .dma_boundary = AHCI_DMA_BOUNDARY,
283 .slave_configure = ata_scsi_slave_config,
ccf68c34 284 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 285 .bios_param = ata_std_bios_param,
31556594 286 .shost_attrs = ahci_shost_attrs,
1da177e4
LT		 287};
288
057ace5e 289static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 290 .check_status = ahci_check_status,
291 .check_altstatus = ahci_check_status,
1da177e4
LT		 292 .dev_select = ata_noop_dev_select,
293
294 .tf_read = ahci_tf_read,
295
7d50b60b 296 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 297 .qc_prep = ahci_qc_prep,
298 .qc_issue = ahci_qc_issue,
299
1da177e4
LT		 300 .irq_clear = ahci_irq_clear,
301
302 .scr_read = ahci_scr_read,
303 .scr_write = ahci_scr_write,
304
78cd52d0
TH		 305 .freeze = ahci_freeze,
306 .thaw = ahci_thaw,
307
308 .error_handler = ahci_error_handler,
309 .post_internal_cmd = ahci_post_internal_cmd,
310
7d50b60b
TH		 311 .pmp_attach = ahci_pmp_attach,
312 .pmp_detach = ahci_pmp_detach,
7d50b60b 313
438ac6d5 314#ifdef CONFIG_PM
c1332875
TH		 315 .port_suspend = ahci_port_suspend,
316 .port_resume = ahci_port_resume,
438ac6d5 317#endif
31556594
KCA		 318 .enable_pm = ahci_enable_alpm,
319 .disable_pm = ahci_disable_alpm,
c1332875 320
1da177e4
LT		 321 .port_start = ahci_port_start,
322 .port_stop = ahci_port_stop,
1da177e4
LT		 323};
324
ad616ffb 325static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 326 .check_status = ahci_check_status,
327 .check_altstatus = ahci_check_status,
328 .dev_select = ata_noop_dev_select,
329
330 .tf_read = ahci_tf_read,
331
7d50b60b 332 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 333 .qc_prep = ahci_qc_prep,
334 .qc_issue = ahci_qc_issue,
335
ad616ffb
TH		 336 .irq_clear = ahci_irq_clear,
337
338 .scr_read = ahci_scr_read,
339 .scr_write = ahci_scr_write,
340
341 .freeze = ahci_freeze,
342 .thaw = ahci_thaw,
343
344 .error_handler = ahci_vt8251_error_handler,
345 .post_internal_cmd = ahci_post_internal_cmd,
346
7d50b60b
TH		 347 .pmp_attach = ahci_pmp_attach,
348 .pmp_detach = ahci_pmp_detach,
7d50b60b 349
438ac6d5 350#ifdef CONFIG_PM
ad616ffb
TH		 351 .port_suspend = ahci_port_suspend,
352 .port_resume = ahci_port_resume,
438ac6d5 353#endif
ad616ffb
TH		 354
355 .port_start = ahci_port_start,
356 .port_stop = ahci_port_stop,
357};
358
edc93052
TH		 359static const struct ata_port_operations ahci_p5wdh_ops = {
360 .check_status = ahci_check_status,
361 .check_altstatus = ahci_check_status,
362 .dev_select = ata_noop_dev_select,
363
364 .tf_read = ahci_tf_read,
365
366 .qc_defer = sata_pmp_qc_defer_cmd_switch,
367 .qc_prep = ahci_qc_prep,
368 .qc_issue = ahci_qc_issue,
369
370 .irq_clear = ahci_irq_clear,
371
372 .scr_read = ahci_scr_read,
373 .scr_write = ahci_scr_write,
374
375 .freeze = ahci_freeze,
376 .thaw = ahci_thaw,
377
378 .error_handler = ahci_p5wdh_error_handler,
379 .post_internal_cmd = ahci_post_internal_cmd,
380
381 .pmp_attach = ahci_pmp_attach,
382 .pmp_detach = ahci_pmp_detach,
383
384#ifdef CONFIG_PM
385 .port_suspend = ahci_port_suspend,
386 .port_resume = ahci_port_resume,
387#endif
388
389 .port_start = ahci_port_start,
390 .port_stop = ahci_port_stop,
391};
392
417a1a6d
TH		 393#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
394
98ac62de 395static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 396 /* board_ahci */
397 {
1188c0d8 398 .flags = AHCI_FLAG_COMMON,
0c88758b 399 .link_flags = AHCI_LFLAG_COMMON,
7da79312 400 .pio_mask = 0x1f, /* pio0-4 */
469248ab 401 .udma_mask = ATA_UDMA6,
1da177e4
LT		 402 .port_ops = &ahci_ops,
403 },
bf2af2a2
BJ		 404 /* board_ahci_vt8251 */
405 {
6949b914 406 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 407 .flags = AHCI_FLAG_COMMON,
0c88758b 408 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
bf2af2a2 409 .pio_mask = 0x1f, /* pio0-4 */
469248ab 410 .udma_mask = ATA_UDMA6,
ad616ffb 411 .port_ops = &ahci_vt8251_ops,
bf2af2a2 412 },
41669553
TH		 413 /* board_ahci_ign_iferr */
414 {
417a1a6d
TH		 415 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
416 .flags = AHCI_FLAG_COMMON,
0c88758b 417 .link_flags = AHCI_LFLAG_COMMON,
41669553 418 .pio_mask = 0x1f, /* pio0-4 */
469248ab 419 .udma_mask = ATA_UDMA6,
41669553
TH		 420 .port_ops = &ahci_ops,
421 },
55a61604
CH		 422 /* board_ahci_sb600 */
423 {
417a1a6d 424 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
6949b914 425 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
417a1a6d 426 .flags = AHCI_FLAG_COMMON,
0c88758b 427 .link_flags = AHCI_LFLAG_COMMON,
55a61604 428 .pio_mask = 0x1f, /* pio0-4 */
469248ab 429 .udma_mask = ATA_UDMA6,
55a61604
CH		 430 .port_ops = &ahci_ops,
431 },
cd70c266
JG		 432 /* board_ahci_mv */
433 {
417a1a6d
TH		 434 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
435 AHCI_HFLAG_MV_PATA),
cd70c266 436 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 437 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
0c88758b 438 .link_flags = AHCI_LFLAG_COMMON,
cd70c266
JG		 439 .pio_mask = 0x1f, /* pio0-4 */
440 .udma_mask = ATA_UDMA6,
441 .port_ops = &ahci_ops,
442 },
1da177e4
LT		 443};
444
3b7d697d 445static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 446 /* Intel */
54bb3a94
JG		 447 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
448 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
449 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
450 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
451 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 452 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 453 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
454 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
455 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 457 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
458 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
459 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
461 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
462 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
463 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
464 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
468 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
469 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
473 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 474 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
475 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
fe7fa31a 476
e34bb370
TH		 477 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
478 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 480
481 /* ATI */
c65ec1c2 482 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
c69c0892 483 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
484 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
485 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
486 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
487 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
fe7fa31a
JG		 489
490 /* VIA */
54bb3a94 491 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 492 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 493
494 /* NVIDIA */
54bb3a94
JG		 495 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
496 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
497 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
498 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 499 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
503 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
504 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
505 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
506 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 507 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
511 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 515 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 539 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 543 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
fe7fa31a 551
95916edd 552 /* SiS */
54bb3a94
JG		 553 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
554 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
555 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 556
cd70c266
JG		 557 /* Marvell */
558 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
559
415ae2b5
JG		 560 /* Generic, PCI class code for AHCI */
561 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 562 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 563
1da177e4
LT		 564 { } /* terminate list */
565};
566
567
568static struct pci_driver ahci_pci_driver = {
569 .name = DRV_NAME,
570 .id_table = ahci_pci_tbl,
571 .probe = ahci_init_one,
24dc5f33 572 .remove = ata_pci_remove_one,
438ac6d5 573#ifdef CONFIG_PM
c1332875
TH		 574 .suspend = ahci_pci_device_suspend,
575 .resume = ahci_pci_device_resume,
438ac6d5 576#endif
1da177e4
LT		 577};
578
579
98fa4b60
TH		 580static inline int ahci_nr_ports(u32 cap)
581{
582 return (cap & 0x1f) + 1;
583}
584
dab632e8
JG		 585static inline void __iomem *__ahci_port_base(struct ata_host *host,
586 unsigned int port_no)
1da177e4 587{
dab632e8 588 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 589
dab632e8
JG		 590 return mmio + 0x100 + (port_no * 0x80);
591}
592
593static inline void __iomem *ahci_port_base(struct ata_port *ap)
594{
595 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 596}
597
d447df14
TH		 598/**
599 * ahci_save_initial_config - Save and fixup initial config values
4447d351 600 * @pdev: target PCI device
4447d351 601 * @hpriv: host private area to store config values
d447df14
TH		 602 *
603 * Some registers containing configuration info might be setup by
604 * BIOS and might be cleared on reset. This function saves the
605 * initial values of those registers into @hpriv such that they
606 * can be restored after controller reset.
607 *
608 * If inconsistent, config values are fixed up by this function.
609 *
610 * LOCKING:
611 * None.
612 */
4447d351 613static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 614 struct ahci_host_priv *hpriv)
d447df14 615{
4447d351 616 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 617 u32 cap, port_map;
17199b18 618 int i;
d447df14
TH		 619
620 /* Values prefixed with saved_ are written back to host after
621 * reset. Values without are used for driver operation.
622 */
623 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
624 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
625
274c1fde 626 /* some chips have errata preventing 64bit use */
417a1a6d 627 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 628 dev_printk(KERN_INFO, &pdev->dev,
629 "controller can't do 64bit DMA, forcing 32bit\n");
630 cap &= ~HOST_CAP_64;
631 }
632
417a1a6d 633 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 634 dev_printk(KERN_INFO, &pdev->dev,
635 "controller can't do NCQ, turning off CAP_NCQ\n");
636 cap &= ~HOST_CAP_NCQ;
637 }
638
6949b914
TH		 639 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
640 dev_printk(KERN_INFO, &pdev->dev,
641 "controller can't do PMP, turning off CAP_PMP\n");
642 cap &= ~HOST_CAP_PMP;
643 }
644
cd70c266
JG		 645 /*
646 * Temporary Marvell 6145 hack: PATA port presence
647 * is asserted through the standard AHCI port
648 * presence register, as bit 4 (counting from 0)
649 */
417a1a6d 650 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 651 dev_printk(KERN_ERR, &pdev->dev,
652 "MV_AHCI HACK: port_map %x -> %x\n",
653 hpriv->port_map,
654 hpriv->port_map & 0xf);
655
656 port_map &= 0xf;
657 }
658
17199b18 659 /* cross check port_map and cap.n_ports */
7a234aff 660 if (port_map) {
17199b18
TH		 661 u32 tmp_port_map = port_map;
662 int n_ports = ahci_nr_ports(cap);
663
664 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
665 if (tmp_port_map & (1 << i)) {
666 n_ports--;
667 tmp_port_map &= ~(1 << i);
668 }
669 }
670
7a234aff
TH		 671 /* If n_ports and port_map are inconsistent, whine and
672 * clear port_map and let it be generated from n_ports.
17199b18 673 */
7a234aff 674 if (n_ports || tmp_port_map) {
4447d351 675 dev_printk(KERN_WARNING, &pdev->dev,
17199b18 676 "nr_ports (%u) and implemented port map "
7a234aff 677 "(0x%x) don't match, using nr_ports\n",
17199b18 678 ahci_nr_ports(cap), port_map);
7a234aff
TH		 679 port_map = 0;
680 }
681 }
682
683 /* fabricate port_map from cap.nr_ports */
684 if (!port_map) {
17199b18 685 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 686 dev_printk(KERN_WARNING, &pdev->dev,
687 "forcing PORTS_IMPL to 0x%x\n", port_map);
688
689 /* write the fixed up value to the PI register */
690 hpriv->saved_port_map = port_map;
17199b18
TH		 691 }
692
d447df14
TH		 693 /* record values to use during operation */
694 hpriv->cap = cap;
695 hpriv->port_map = port_map;
696}
697
698/**
699 * ahci_restore_initial_config - Restore initial config
4447d351 700 * @host: target ATA host
d447df14
TH		 701 *
702 * Restore initial config stored by ahci_save_initial_config().
703 *
704 * LOCKING:
705 * None.
706 */
4447d351 707static void ahci_restore_initial_config(struct ata_host *host)
d447df14 708{
4447d351
TH		 709 struct ahci_host_priv *hpriv = host->private_data;
710 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
711
d447df14
TH		 712 writel(hpriv->saved_cap, mmio + HOST_CAP);
713 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
714 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
715}
716
203ef6c4 717static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 718{
203ef6c4
TH		 719 static const int offset[] = {
720 [SCR_STATUS] = PORT_SCR_STAT,
721 [SCR_CONTROL] = PORT_SCR_CTL,
722 [SCR_ERROR] = PORT_SCR_ERR,
723 [SCR_ACTIVE] = PORT_SCR_ACT,
724 [SCR_NOTIFICATION] = PORT_SCR_NTF,
725 };
726 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 727
203ef6c4
TH		 728 if (sc_reg < ARRAY_SIZE(offset) &&
729 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
730 return offset[sc_reg];
da3dbb17 731 return 0;
1da177e4
LT		 732}
733
203ef6c4 734static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 735{
203ef6c4
TH		 736 void __iomem *port_mmio = ahci_port_base(ap);
737 int offset = ahci_scr_offset(ap, sc_reg);
738
739 if (offset) {
740 *val = readl(port_mmio + offset);
741 return 0;
1da177e4 742 }
203ef6c4
TH		 743 return -EINVAL;
744}
1da177e4 745
203ef6c4
TH		 746static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
747{
748 void __iomem *port_mmio = ahci_port_base(ap);
749 int offset = ahci_scr_offset(ap, sc_reg);
750
751 if (offset) {
752 writel(val, port_mmio + offset);
753 return 0;
754 }
755 return -EINVAL;
1da177e4
LT		 756}
757
4447d351 758static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 759{
4447d351 760 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 761 u32 tmp;
762
d8fcd116 763 /* start DMA */
9f592056 764 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 765 tmp |= PORT_CMD_START;
766 writel(tmp, port_mmio + PORT_CMD);
767 readl(port_mmio + PORT_CMD); /* flush */
768}
769
4447d351 770static int ahci_stop_engine(struct ata_port *ap)
254950cd 771{
4447d351 772 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 773 u32 tmp;
774
775 tmp = readl(port_mmio + PORT_CMD);
776
d8fcd116 777 /* check if the HBA is idle */
254950cd
TH		 778 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
779 return 0;
780
d8fcd116 781 /* setting HBA to idle */
254950cd
TH		 782 tmp &= ~PORT_CMD_START;
783 writel(tmp, port_mmio + PORT_CMD);
784
d8fcd116 785 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 786 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 787 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 788 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 789 return -EIO;
790
791 return 0;
792}
793
4447d351 794static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 795{
4447d351
TH		 796 void __iomem *port_mmio = ahci_port_base(ap);
797 struct ahci_host_priv *hpriv = ap->host->private_data;
798 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 799 u32 tmp;
800
801 /* set FIS registers */
4447d351
TH		 802 if (hpriv->cap & HOST_CAP_64)
803 writel((pp->cmd_slot_dma >> 16) >> 16,
804 port_mmio + PORT_LST_ADDR_HI);
805 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 806
4447d351
TH		 807 if (hpriv->cap & HOST_CAP_64)
808 writel((pp->rx_fis_dma >> 16) >> 16,
809 port_mmio + PORT_FIS_ADDR_HI);
810 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 811
812 /* enable FIS reception */
813 tmp = readl(port_mmio + PORT_CMD);
814 tmp |= PORT_CMD_FIS_RX;
815 writel(tmp, port_mmio + PORT_CMD);
816
817 /* flush */
818 readl(port_mmio + PORT_CMD);
819}
820
4447d351 821static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 822{
4447d351 823 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 824 u32 tmp;
825
826 /* disable FIS reception */
827 tmp = readl(port_mmio + PORT_CMD);
828 tmp &= ~PORT_CMD_FIS_RX;
829 writel(tmp, port_mmio + PORT_CMD);
830
831 /* wait for completion, spec says 500ms, give it 1000 */
832 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
833 PORT_CMD_FIS_ON, 10, 1000);
834 if (tmp & PORT_CMD_FIS_ON)
835 return -EBUSY;
836
837 return 0;
838}
839
4447d351 840static void ahci_power_up(struct ata_port *ap)
0be0aa98 841{
4447d351
TH		 842 struct ahci_host_priv *hpriv = ap->host->private_data;
843 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 844 u32 cmd;
845
846 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
847
848 /* spin up device */
4447d351 849 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 850 cmd |= PORT_CMD_SPIN_UP;
851 writel(cmd, port_mmio + PORT_CMD);
852 }
853
854 /* wake up link */
855 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
856}
857
31556594
KCA		 858static void ahci_disable_alpm(struct ata_port *ap)
859{
860 struct ahci_host_priv *hpriv = ap->host->private_data;
861 void __iomem *port_mmio = ahci_port_base(ap);
862 u32 cmd;
863 struct ahci_port_priv *pp = ap->private_data;
864
865 /* IPM bits should be disabled by libata-core */
866 /* get the existing command bits */
867 cmd = readl(port_mmio + PORT_CMD);
868
869 /* disable ALPM and ASP */
870 cmd &= ~PORT_CMD_ASP;
871 cmd &= ~PORT_CMD_ALPE;
872
873 /* force the interface back to active */
874 cmd |= PORT_CMD_ICC_ACTIVE;
875
876 /* write out new cmd value */
877 writel(cmd, port_mmio + PORT_CMD);
878 cmd = readl(port_mmio + PORT_CMD);
879
880 /* wait 10ms to be sure we've come out of any low power state */
881 msleep(10);
882
883 /* clear out any PhyRdy stuff from interrupt status */
884 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
885
886 /* go ahead and clean out PhyRdy Change from Serror too */
887 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
888
889 /*
890 * Clear flag to indicate that we should ignore all PhyRdy
891 * state changes
892 */
893 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
894
895 /*
896 * Enable interrupts on Phy Ready.
897 */
898 pp->intr_mask |= PORT_IRQ_PHYRDY;
899 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
900
901 /*
902 * don't change the link pm policy - we can be called
903 * just to turn of link pm temporarily
904 */
905}
906
907static int ahci_enable_alpm(struct ata_port *ap,
908 enum link_pm policy)
909{
910 struct ahci_host_priv *hpriv = ap->host->private_data;
911 void __iomem *port_mmio = ahci_port_base(ap);
912 u32 cmd;
913 struct ahci_port_priv *pp = ap->private_data;
914 u32 asp;
915
916 /* Make sure the host is capable of link power management */
917 if (!(hpriv->cap & HOST_CAP_ALPM))
918 return -EINVAL;
919
920 switch (policy) {
921 case MAX_PERFORMANCE:
922 case NOT_AVAILABLE:
923 /*
924 * if we came here with NOT_AVAILABLE,
925 * it just means this is the first time we
926 * have tried to enable - default to max performance,
927 * and let the user go to lower power modes on request.
928 */
929 ahci_disable_alpm(ap);
930 return 0;
931 case MIN_POWER:
932 /* configure HBA to enter SLUMBER */
933 asp = PORT_CMD_ASP;
934 break;
935 case MEDIUM_POWER:
936 /* configure HBA to enter PARTIAL */
937 asp = 0;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 /*
944 * Disable interrupts on Phy Ready. This keeps us from
945 * getting woken up due to spurious phy ready interrupts
946 * TBD - Hot plug should be done via polling now, is
947 * that even supported?
948 */
949 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
950 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
951
952 /*
953 * Set a flag to indicate that we should ignore all PhyRdy
954 * state changes since these can happen now whenever we
955 * change link state
956 */
957 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
958
959 /* get the existing command bits */
960 cmd = readl(port_mmio + PORT_CMD);
961
962 /*
963 * Set ASP based on Policy
964 */
965 cmd |= asp;
966
967 /*
968 * Setting this bit will instruct the HBA to aggressively
969 * enter a lower power link state when it's appropriate and
970 * based on the value set above for ASP
971 */
972 cmd |= PORT_CMD_ALPE;
973
974 /* write out new cmd value */
975 writel(cmd, port_mmio + PORT_CMD);
976 cmd = readl(port_mmio + PORT_CMD);
977
978 /* IPM bits should be set by libata-core */
979 return 0;
980}
981
438ac6d5 982#ifdef CONFIG_PM
4447d351 983static void ahci_power_down(struct ata_port *ap)
0be0aa98 984{
4447d351
TH		 985 struct ahci_host_priv *hpriv = ap->host->private_data;
986 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 987 u32 cmd, scontrol;
988
4447d351 989 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 990 return;
0be0aa98 991
07c53dac
TH		 992 /* put device into listen mode, first set PxSCTL.DET to 0 */
993 scontrol = readl(port_mmio + PORT_SCR_CTL);
994 scontrol &= ~0xf;
995 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 996
07c53dac
TH		 997 /* then set PxCMD.SUD to 0 */
998 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
999 cmd &= ~PORT_CMD_SPIN_UP;
1000 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1001}
438ac6d5 1002#endif
0be0aa98 1003
df69c9c5 1004static void ahci_start_port(struct ata_port *ap)
0be0aa98 1005{
0be0aa98 1006 /* enable FIS reception */
4447d351 1007 ahci_start_fis_rx(ap);
0be0aa98
TH		 1008
1009 /* enable DMA */
4447d351 1010 ahci_start_engine(ap);
0be0aa98
TH		 1011}
1012
4447d351 1013static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1014{
1015 int rc;
1016
1017 /* disable DMA */
4447d351 1018 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1019 if (rc) {
1020 *emsg = "failed to stop engine";
1021 return rc;
1022 }
1023
1024 /* disable FIS reception */
4447d351 1025 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1026 if (rc) {
1027 *emsg = "failed stop FIS RX";
1028 return rc;
1029 }
1030
0be0aa98
TH		 1031 return 0;
1032}
1033
4447d351 1034static int ahci_reset_controller(struct ata_host *host)
d91542c1 1035{
4447d351
TH		 1036 struct pci_dev *pdev = to_pci_dev(host->dev);
1037 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1038 u32 tmp;
d91542c1 1039
3cc3eb11
JG		 1040 /* we must be in AHCI mode, before using anything
1041 * AHCI-specific, such as HOST_RESET.
1042 */
d91542c1 1043 tmp = readl(mmio + HOST_CTL);
ab6fc95f
JG		 1044 if (!(tmp & HOST_AHCI_EN)) {
1045 tmp |= HOST_AHCI_EN;
1046 writel(tmp, mmio + HOST_CTL);
1047 }
3cc3eb11
JG		 1048
1049 /* global controller reset */
d91542c1
TH		 1050 if ((tmp & HOST_RESET) == 0) {
1051 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1052 readl(mmio + HOST_CTL); /* flush */
1053 }
1054
1055 /* reset must complete within 1 second, or
1056 * the hardware should be considered fried.
1057 */
1058 ssleep(1);
1059
1060 tmp = readl(mmio + HOST_CTL);
1061 if (tmp & HOST_RESET) {
4447d351 1062 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 1063 "controller reset failed (0x%x)\n", tmp);
1064 return -EIO;
1065 }
1066
98fa4b60 1067 /* turn on AHCI mode */
d91542c1
TH		 1068 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1069 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60 1070
d447df14 1071 /* some registers might be cleared on reset. restore initial values */
4447d351 1072 ahci_restore_initial_config(host);
d91542c1
TH		 1073
1074 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1075 u16 tmp16;
1076
1077 /* configure PCS */
1078 pci_read_config_word(pdev, 0x92, &tmp16);
1079 tmp16 |= 0xf;
1080 pci_write_config_word(pdev, 0x92, tmp16);
1081 }
1082
1083 return 0;
1084}
1085
2bcd866b
JG		 1086static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1087 int port_no, void __iomem *mmio,
1088 void __iomem *port_mmio)
1089{
1090 const char *emsg = NULL;
1091 int rc;
1092 u32 tmp;
1093
1094 /* make sure port is not active */
1095 rc = ahci_deinit_port(ap, &emsg);
1096 if (rc)
1097 dev_printk(KERN_WARNING, &pdev->dev,
1098 "%s (%d)\n", emsg, rc);
1099
1100 /* clear SError */
1101 tmp = readl(port_mmio + PORT_SCR_ERR);
1102 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1103 writel(tmp, port_mmio + PORT_SCR_ERR);
1104
1105 /* clear port IRQ */
1106 tmp = readl(port_mmio + PORT_IRQ_STAT);
1107 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1108 if (tmp)
1109 writel(tmp, port_mmio + PORT_IRQ_STAT);
1110
1111 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1112}
1113
4447d351 1114static void ahci_init_controller(struct ata_host *host)
d91542c1 1115{
417a1a6d 1116 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1117 struct pci_dev *pdev = to_pci_dev(host->dev);
1118 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1119 int i;
cd70c266 1120 void __iomem *port_mmio;
d91542c1
TH		 1121 u32 tmp;
1122
417a1a6d 1123 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 1124 port_mmio = __ahci_port_base(host, 4);
1125
1126 writel(0, port_mmio + PORT_IRQ_MASK);
1127
1128 /* clear port IRQ */
1129 tmp = readl(port_mmio + PORT_IRQ_STAT);
1130 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1131 if (tmp)
1132 writel(tmp, port_mmio + PORT_IRQ_STAT);
1133 }
1134
4447d351
TH		 1135 for (i = 0; i < host->n_ports; i++) {
1136 struct ata_port *ap = host->ports[i];
d91542c1 1137
cd70c266 1138 port_mmio = ahci_port_base(ap);
4447d351 1139 if (ata_port_is_dummy(ap))
d91542c1 1140 continue;
d91542c1 1141
2bcd866b 1142 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1143 }
1144
1145 tmp = readl(mmio + HOST_CTL);
1146 VPRINTK("HOST_CTL 0x%x\n", tmp);
1147 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1148 tmp = readl(mmio + HOST_CTL);
1149 VPRINTK("HOST_CTL 0x%x\n", tmp);
1150}
1151
422b7595 1152static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1153{
4447d351 1154 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1155 struct ata_taskfile tf;
422b7595
TH		 1156 u32 tmp;
1157
1158 tmp = readl(port_mmio + PORT_SIG);
1159 tf.lbah = (tmp >> 24) & 0xff;
1160 tf.lbam = (tmp >> 16) & 0xff;
1161 tf.lbal = (tmp >> 8) & 0xff;
1162 tf.nsect = (tmp) & 0xff;
1163
1164 return ata_dev_classify(&tf);
1165}
1166
12fad3f9
TH		 1167static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1168 u32 opts)
cc9278ed 1169{
12fad3f9
TH		 1170 dma_addr_t cmd_tbl_dma;
1171
1172 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1173
1174 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1175 pp->cmd_slot[tag].status = 0;
1176 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1177 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1178}
1179
d2e75dff 1180static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1181{
0d5ff566 1182 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 1183 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 1184 u32 tmp;
d2e75dff 1185 int busy, rc;
bf2af2a2 1186
d2e75dff
TH		 1187 /* do we need to kick the port? */
1188 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1189 if (!busy && !force_restart)
1190 return 0;
1191
1192 /* stop engine */
1193 rc = ahci_stop_engine(ap);
1194 if (rc)
1195 goto out_restart;
1196
1197 /* need to do CLO? */
1198 if (!busy) {
1199 rc = 0;
1200 goto out_restart;
1201 }
1202
1203 if (!(hpriv->cap & HOST_CAP_CLO)) {
1204 rc = -EOPNOTSUPP;
1205 goto out_restart;
1206 }
bf2af2a2 1207
d2e75dff 1208 /* perform CLO */
bf2af2a2
BJ		 1209 tmp = readl(port_mmio + PORT_CMD);
1210 tmp |= PORT_CMD_CLO;
1211 writel(tmp, port_mmio + PORT_CMD);
1212
d2e75dff 1213 rc = 0;
bf2af2a2
BJ		 1214 tmp = ata_wait_register(port_mmio + PORT_CMD,
1215 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1216 if (tmp & PORT_CMD_CLO)
d2e75dff 1217 rc = -EIO;
bf2af2a2 1218
d2e75dff
TH		 1219 /* restart engine */
1220 out_restart:
1221 ahci_start_engine(ap);
1222 return rc;
bf2af2a2
BJ		 1223}
1224
91c4a2e0
TH		 1225static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1226 struct ata_taskfile *tf, int is_cmd, u16 flags,
1227 unsigned long timeout_msec)
bf2af2a2 1228{
91c4a2e0 1229 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1230 struct ahci_port_priv *pp = ap->private_data;
4447d351 1231 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1232 u8 *fis = pp->cmd_tbl;
1233 u32 tmp;
1234
1235 /* prep the command */
1236 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1237 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1238
1239 /* issue & wait */
1240 writel(1, port_mmio + PORT_CMD_ISSUE);
1241
1242 if (timeout_msec) {
1243 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1244 1, timeout_msec);
1245 if (tmp & 0x1) {
1246 ahci_kick_engine(ap, 1);
1247 return -EBUSY;
1248 }
1249 } else
1250 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1251
1252 return 0;
1253}
1254
cc0680a5 1255static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1256 int pmp, unsigned long deadline)
91c4a2e0 1257{
cc0680a5 1258 struct ata_port *ap = link->ap;
4658f79b 1259 const char *reason = NULL;
2cbb79eb 1260 unsigned long now, msecs;
4658f79b 1261 struct ata_taskfile tf;
4658f79b
TH		 1262 int rc;
1263
1264 DPRINTK("ENTER\n");
1265
cc0680a5 1266 if (ata_link_offline(link)) {
c2a65852
TH		 1267 DPRINTK("PHY reports no device\n");
1268 *class = ATA_DEV_NONE;
1269 return 0;
1270 }
1271
4658f79b 1272 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1273 rc = ahci_kick_engine(ap, 1);
994056d7 1274 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1275 ata_link_printk(link, KERN_WARNING,
994056d7 1276 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1277
cc0680a5 1278 ata_tf_init(link->device, &tf);
4658f79b
TH		 1279
1280 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1281 msecs = 0;
1282 now = jiffies;
1283 if (time_after(now, deadline))
1284 msecs = jiffies_to_msecs(deadline - now);
1285
4658f79b 1286 tf.ctl |= ATA_SRST;
a9cf5e85 1287 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1288 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1289 rc = -EIO;
1290 reason = "1st FIS failed";
1291 goto fail;
1292 }
1293
1294 /* spec says at least 5us, but be generous and sleep for 1ms */
1295 msleep(1);
1296
1297 /* issue the second D2H Register FIS */
4658f79b 1298 tf.ctl &= ~ATA_SRST;
a9cf5e85 1299 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1300
88ff6eaf
TH		 1301 /* wait a while before checking status */
1302 ata_wait_after_reset(ap, deadline);
4658f79b 1303
9b89391c
TH		 1304 rc = ata_wait_ready(ap, deadline);
1305 /* link occupied, -ENODEV too is an error */
1306 if (rc) {
1307 reason = "device not ready";
1308 goto fail;
4658f79b 1309 }
9b89391c 1310 *class = ahci_dev_classify(ap);
4658f79b
TH		 1311
1312 DPRINTK("EXIT, class=%u\n", *class);
1313 return 0;
1314
4658f79b 1315 fail:
cc0680a5 1316 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1317 return rc;
1318}
1319
cc0680a5 1320static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1321 unsigned long deadline)
1322{
7d50b60b
TH		 1323 int pmp = 0;
1324
1325 if (link->ap->flags & ATA_FLAG_PMP)
1326 pmp = SATA_PMP_CTRL_PORT;
1327
1328 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1329}
1330
cc0680a5 1331static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1332 unsigned long deadline)
422b7595 1333{
cc0680a5 1334 struct ata_port *ap = link->ap;
4296971d
TH		 1335 struct ahci_port_priv *pp = ap->private_data;
1336 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1337 struct ata_taskfile tf;
4bd00f6a
TH		 1338 int rc;
1339
1340 DPRINTK("ENTER\n");
1da177e4 1341
4447d351 1342 ahci_stop_engine(ap);
4296971d
TH		 1343
1344 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1345 ata_tf_init(link->device, &tf);
dfd7a3db 1346 tf.command = 0x80;
9977126c 1347 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1348
cc0680a5 1349 rc = sata_std_hardreset(link, class, deadline);
4296971d 1350
4447d351 1351 ahci_start_engine(ap);
1da177e4 1352
cc0680a5 1353 if (rc == 0 && ata_link_online(link))
4bd00f6a 1354 *class = ahci_dev_classify(ap);
7d50b60b 1355 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1356 *class = ATA_DEV_NONE;
1da177e4 1357
4bd00f6a
TH		 1358 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1359 return rc;
1360}
1361
cc0680a5 1362static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1363 unsigned long deadline)
ad616ffb 1364{
cc0680a5 1365 struct ata_port *ap = link->ap;
da3dbb17 1366 u32 serror;
ad616ffb
TH		 1367 int rc;
1368
1369 DPRINTK("ENTER\n");
1370
4447d351 1371 ahci_stop_engine(ap);
ad616ffb 1372
cc0680a5 1373 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1374 deadline);
ad616ffb
TH		 1375
1376 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1377 ahci_scr_read(ap, SCR_ERROR, &serror);
1378 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1379
4447d351 1380 ahci_start_engine(ap);
ad616ffb
TH		 1381
1382 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1383
1384 /* vt8251 doesn't clear BSY on signature FIS reception,
1385 * request follow-up softreset.
1386 */
1387 return rc ?: -EAGAIN;
1388}
1389
edc93052
TH		 1390static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1391 unsigned long deadline)
1392{
1393 struct ata_port *ap = link->ap;
1394 struct ahci_port_priv *pp = ap->private_data;
1395 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1396 struct ata_taskfile tf;
1397 int rc;
1398
1399 ahci_stop_engine(ap);
1400
1401 /* clear D2H reception area to properly wait for D2H FIS */
1402 ata_tf_init(link->device, &tf);
1403 tf.command = 0x80;
1404 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1405
1406 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1407 deadline);
1408
1409 ahci_start_engine(ap);
1410
1411 if (rc || ata_link_offline(link))
1412 return rc;
1413
1414 /* spec mandates ">= 2ms" before checking status */
1415 msleep(150);
1416
1417 /* The pseudo configuration device on SIMG4726 attached to
1418 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1419 * hardreset if no device is attached to the first downstream
1420 * port && the pseudo device locks up on SRST w/ PMP==0. To
1421 * work around this, wait for !BSY only briefly. If BSY isn't
1422 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1423 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1424 *
1425 * Wait for two seconds. Devices attached to downstream port
1426 * which can't process the following IDENTIFY after this will
1427 * have to be reset again. For most cases, this should
1428 * suffice while making probing snappish enough.
1429 */
1430 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1431 if (rc)
1432 ahci_kick_engine(ap, 0);
1433
1434 return 0;
1435}
1436
cc0680a5 1437static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1438{
cc0680a5 1439 struct ata_port *ap = link->ap;
4447d351 1440 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1441 u32 new_tmp, tmp;
1442
cc0680a5 1443 ata_std_postreset(link, class);
02eaa666
JG		 1444
1445 /* Make sure port's ATAPI bit is set appropriately */
1446 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1447 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1448 new_tmp |= PORT_CMD_ATAPI;
1449 else
1450 new_tmp &= ~PORT_CMD_ATAPI;
1451 if (new_tmp != tmp) {
1452 writel(new_tmp, port_mmio + PORT_CMD);
1453 readl(port_mmio + PORT_CMD); /* flush */
1454 }
1da177e4
LT		 1455}
1456
7d50b60b
TH		 1457static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1458 unsigned long deadline)
1459{
1460 return ahci_do_softreset(link, class, link->pmp, deadline);
1461}
1462
1da177e4
LT		 1463static u8 ahci_check_status(struct ata_port *ap)
1464{
0d5ff566 1465 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1466
1467 return readl(mmio + PORT_TFDATA) & 0xFF;
1468}
1469
1da177e4
LT		 1470static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1471{
1472 struct ahci_port_priv *pp = ap->private_data;
1473 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1474
1475 ata_tf_from_fis(d2h_fis, tf);
1476}
1477
12fad3f9 1478static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1479{
cedc9a47
JG		 1480 struct scatterlist *sg;
1481 struct ahci_sg *ahci_sg;
828d09de 1482 unsigned int n_sg = 0;
1da177e4
LT		 1483
1484 VPRINTK("ENTER\n");
1485
1486 /*
1487 * Next, the S/G list.
1488 */
12fad3f9 1489 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1490 ata_for_each_sg(sg, qc) {
1491 dma_addr_t addr = sg_dma_address(sg);
1492 u32 sg_len = sg_dma_len(sg);
1493
1494 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1495 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1496 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1497
cedc9a47 1498 ahci_sg++;
828d09de 1499 n_sg++;
1da177e4 1500 }
828d09de
JG		 1501
1502 return n_sg;
1da177e4
LT		 1503}
1504
1505static void ahci_qc_prep(struct ata_queued_cmd *qc)
1506{
a0ea7328
JG		 1507 struct ata_port *ap = qc->ap;
1508 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1509 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1510 void *cmd_tbl;
1da177e4
LT		 1511 u32 opts;
1512 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1513 unsigned int n_elem;
1da177e4 1514
1da177e4
LT		 1515 /*
1516 * Fill in command table information. First, the header,
1517 * a SATA Register - Host to Device command FIS.
1518 */
12fad3f9
TH		 1519 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1520
7d50b60b 1521 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1522 if (is_atapi) {
12fad3f9
TH		 1523 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1524 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1525 }
1da177e4 1526
cc9278ed
TH		 1527 n_elem = 0;
1528 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1529 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1530
cc9278ed
TH		 1531 /*
1532 * Fill in command slot information.
1533 */
7d50b60b 1534 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1535 if (qc->tf.flags & ATA_TFLAG_WRITE)
1536 opts |= AHCI_CMD_WRITE;
1537 if (is_atapi)
4b10e559 1538 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1539
12fad3f9 1540 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1541}
1542
78cd52d0 1543static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1544{
417a1a6d 1545 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1546 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1547 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1548 struct ata_link *link = NULL;
1549 struct ata_queued_cmd *active_qc;
1550 struct ata_eh_info *active_ehi;
78cd52d0 1551 u32 serror;
1da177e4 1552
7d50b60b
TH		 1553 /* determine active link */
1554 ata_port_for_each_link(link, ap)
1555 if (ata_link_active(link))
1556 break;
1557 if (!link)
1558 link = &ap->link;
1559
1560 active_qc = ata_qc_from_tag(ap, link->active_tag);
1561 active_ehi = &link->eh_info;
1562
1563 /* record irq stat */
1564 ata_ehi_clear_desc(host_ehi);
1565 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1566
78cd52d0 1567 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1568 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1569 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1570 host_ehi->serror |= serror;
78cd52d0 1571
41669553 1572 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1573 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1574 irq_stat &= ~PORT_IRQ_IF_ERR;
1575
55a61604 1576 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1577 /* If qc is active, charge it; otherwise, the active
1578 * link. There's no active qc on NCQ errors. It will
1579 * be determined by EH by reading log page 10h.
1580 */
1581 if (active_qc)
1582 active_qc->err_mask |= AC_ERR_DEV;
1583 else
1584 active_ehi->err_mask |= AC_ERR_DEV;
1585
417a1a6d 1586 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1587 host_ehi->serror &= ~SERR_INTERNAL;
1588 }
1589
1590 if (irq_stat & PORT_IRQ_UNK_FIS) {
1591 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1592
1593 active_ehi->err_mask |= AC_ERR_HSM;
1594 active_ehi->action |= ATA_EH_SOFTRESET;
1595 ata_ehi_push_desc(active_ehi,
1596 "unknown FIS %08x %08x %08x %08x" ,
1597 unk[0], unk[1], unk[2], unk[3]);
1598 }
1599
1600 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1601 active_ehi->err_mask |= AC_ERR_HSM;
1602 active_ehi->action |= ATA_EH_SOFTRESET;
1603 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1604 }
78cd52d0
TH		 1605
1606 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b
TH		 1607 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1608 host_ehi->action |= ATA_EH_SOFTRESET;
1609 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1610 }
1611
78cd52d0 1612 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b
TH		 1613 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1614 host_ehi->action |= ATA_EH_SOFTRESET;
1615 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1616 }
1da177e4 1617
78cd52d0 1618 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1619 ata_ehi_hotplugged(host_ehi);
1620 ata_ehi_push_desc(host_ehi, "%s",
1621 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1622 "connection status changed" : "PHY RDY changed");
1623 }
1624
78cd52d0 1625 /* okay, let's hand over to EH */
a72ec4ce 1626
78cd52d0
TH		 1627 if (irq_stat & PORT_IRQ_FREEZE)
1628 ata_port_freeze(ap);
1629 else
1630 ata_port_abort(ap);
1da177e4
LT		 1631}
1632
df69c9c5 1633static void ahci_port_intr(struct ata_port *ap)
1da177e4 1634{
4447d351 1635 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1636 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1637 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1638 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1639 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1640 u32 status, qc_active;
0291f95f 1641 int rc, known_irq = 0;
1da177e4
LT		 1642
1643 status = readl(port_mmio + PORT_IRQ_STAT);
1644 writel(status, port_mmio + PORT_IRQ_STAT);
1645
b06ce3e5
TH		 1646 /* ignore BAD_PMP while resetting */
1647 if (unlikely(resetting))
1648 status &= ~PORT_IRQ_BAD_PMP;
1649
31556594
KCA		 1650 /* If we are getting PhyRdy, this is
1651 * just a power state change, we should
1652 * clear out this, plus the PhyRdy/Comm
1653 * Wake bits from Serror
1654 */
1655 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1656 (status & PORT_IRQ_PHYRDY)) {
1657 status &= ~PORT_IRQ_PHYRDY;
1658 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1659 }
1660
78cd52d0
TH		 1661 if (unlikely(status & PORT_IRQ_ERROR)) {
1662 ahci_error_intr(ap, status);
1663 return;
1da177e4
LT		 1664 }
1665
2f294968 1666 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 1667 /* If SNotification is available, leave notification
1668 * handling to sata_async_notification(). If not,
1669 * emulate it by snooping SDB FIS RX area.
1670 *
1671 * Snooping FIS RX area is probably cheaper than
1672 * poking SNotification but some constrollers which
1673 * implement SNotification, ICH9 for example, don't
1674 * store AN SDB FIS into receive area.
2f294968 1675 */
5f226c6b 1676 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 1677 sata_async_notification(ap);
5f226c6b
TH		 1678 else {
1679 /* If the 'N' bit in word 0 of the FIS is set,
1680 * we just received asynchronous notification.
1681 * Tell libata about it.
1682 */
1683 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1684 u32 f0 = le32_to_cpu(f[0]);
1685
1686 if (f0 & (1 << 15))
1687 sata_async_notification(ap);
1688 }
2f294968
KCA		 1689 }
1690
7d50b60b
TH		 1691 /* pp->active_link is valid iff any command is in flight */
1692 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1693 qc_active = readl(port_mmio + PORT_SCR_ACT);
1694 else
1695 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1696
1697 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
b06ce3e5
TH		 1698
1699 /* If resetting, spurious or invalid completions are expected,
1700 * return unconditionally.
1701 */
1702 if (resetting)
1703 return;
1704
12fad3f9
TH		 1705 if (rc > 0)
1706 return;
1707 if (rc < 0) {
1708 ehi->err_mask |= AC_ERR_HSM;
1709 ehi->action |= ATA_EH_SOFTRESET;
1710 ata_port_freeze(ap);
1711 return;
1da177e4
LT		 1712 }
1713
3a4fa0a2 1714 /* hmmm... a spurious interrupt */
2a3917a8 1715
0291f95f
TH		 1716 /* if !NCQ, ignore. No modern ATA device has broken HSM
1717 * implementation for non-NCQ commands.
1718 */
9af5c9c9 1719 if (!ap->link.sactive)
12fad3f9
TH		 1720 return;
1721
0291f95f
TH		 1722 if (status & PORT_IRQ_D2H_REG_FIS) {
1723 if (!pp->ncq_saw_d2h)
1724 ata_port_printk(ap, KERN_INFO,
1725 "D2H reg with I during NCQ, "
1726 "this message won't be printed again\n");
1727 pp->ncq_saw_d2h = 1;
1728 known_irq = 1;
1729 }
1730
1731 if (status & PORT_IRQ_DMAS_FIS) {
1732 if (!pp->ncq_saw_dmas)
1733 ata_port_printk(ap, KERN_INFO,
1734 "DMAS FIS during NCQ, "
1735 "this message won't be printed again\n");
1736 pp->ncq_saw_dmas = 1;
1737 known_irq = 1;
1738 }
1739
a2bbd0c9 1740 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1741 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1742
afb2d552
TH		 1743 if (le32_to_cpu(f[1])) {
1744 /* SDB FIS containing spurious completions
1745 * might be dangerous, whine and fail commands
1746 * with HSM violation. EH will turn off NCQ
1747 * after several such failures.
1748 */
1749 ata_ehi_push_desc(ehi,
1750 "spurious completions during NCQ "
1751 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1752 readl(port_mmio + PORT_CMD_ISSUE),
1753 readl(port_mmio + PORT_SCR_ACT),
1754 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1755 ehi->err_mask |= AC_ERR_HSM;
1756 ehi->action |= ATA_EH_SOFTRESET;
1757 ata_port_freeze(ap);
1758 } else {
1759 if (!pp->ncq_saw_sdb)
1760 ata_port_printk(ap, KERN_INFO,
1761 "spurious SDB FIS %08x:%08x during NCQ, "
1762 "this message won't be printed again\n",
1763 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1764 pp->ncq_saw_sdb = 1;
1765 }
0291f95f
TH		 1766 known_irq = 1;
1767 }
2a3917a8 1768
0291f95f 1769 if (!known_irq)
78cd52d0 1770 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1771 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
9af5c9c9 1772 status, ap->link.active_tag, ap->link.sactive);
1da177e4
LT		 1773}
1774
1775static void ahci_irq_clear(struct ata_port *ap)
1776{
1777 /* TODO */
1778}
1779
7d12e780 1780static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1781{
cca3974e 1782 struct ata_host *host = dev_instance;
1da177e4
LT		 1783 struct ahci_host_priv *hpriv;
1784 unsigned int i, handled = 0;
ea6ba10b 1785 void __iomem *mmio;
1da177e4
LT		 1786 u32 irq_stat, irq_ack = 0;
1787
1788 VPRINTK("ENTER\n");
1789
cca3974e 1790 hpriv = host->private_data;
0d5ff566 1791 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1792
1793 /* sigh. 0xffffffff is a valid return from h/w */
1794 irq_stat = readl(mmio + HOST_IRQ_STAT);
1795 irq_stat &= hpriv->port_map;
1796 if (!irq_stat)
1797 return IRQ_NONE;
1798
2dcb407e 1799 spin_lock(&host->lock);
1da177e4 1800
2dcb407e 1801 for (i = 0; i < host->n_ports; i++) {
1da177e4 1802 struct ata_port *ap;
1da177e4 1803
67846b30
JG		 1804 if (!(irq_stat & (1 << i)))
1805 continue;
1806
cca3974e 1807 ap = host->ports[i];
67846b30 1808 if (ap) {
df69c9c5 1809 ahci_port_intr(ap);
67846b30
JG		 1810 VPRINTK("port %u\n", i);
1811 } else {
1812 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1813 if (ata_ratelimit())
cca3974e 1814 dev_printk(KERN_WARNING, host->dev,
a9524a76 1815 "interrupt on disabled port %u\n", i);
1da177e4 1816 }
67846b30
JG		 1817
1818 irq_ack |= (1 << i);
1da177e4
LT		 1819 }
1820
1821 if (irq_ack) {
1822 writel(irq_ack, mmio + HOST_IRQ_STAT);
1823 handled = 1;
1824 }
1825
cca3974e 1826 spin_unlock(&host->lock);
1da177e4
LT		 1827
1828 VPRINTK("EXIT\n");
1829
1830 return IRQ_RETVAL(handled);
1831}
1832
9a3d9eb0 1833static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1834{
1835 struct ata_port *ap = qc->ap;
4447d351 1836 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1837 struct ahci_port_priv *pp = ap->private_data;
1838
1839 /* Keep track of the currently active link. It will be used
1840 * in completion path to determine whether NCQ phase is in
1841 * progress.
1842 */
1843 pp->active_link = qc->dev->link;
1da177e4 1844
12fad3f9
TH		 1845 if (qc->tf.protocol == ATA_PROT_NCQ)
1846 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1847 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1848 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1849
1850 return 0;
1851}
1852
78cd52d0
TH		 1853static void ahci_freeze(struct ata_port *ap)
1854{
4447d351 1855 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1856
1857 /* turn IRQ off */
1858 writel(0, port_mmio + PORT_IRQ_MASK);
1859}
1860
1861static void ahci_thaw(struct ata_port *ap)
1862{
0d5ff566 1863 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1864 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1865 u32 tmp;
a7384925 1866 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1867
1868 /* clear IRQ */
1869 tmp = readl(port_mmio + PORT_IRQ_STAT);
1870 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1871 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1872
1c954a4d
TH		 1873 /* turn IRQ back on */
1874 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1875}
1876
1877static void ahci_error_handler(struct ata_port *ap)
1878{
b51e9e5d 1879 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1880 /* restart engine */
4447d351
TH		 1881 ahci_stop_engine(ap);
1882 ahci_start_engine(ap);
78cd52d0
TH		 1883 }
1884
1885 /* perform recovery */
7d50b60b
TH		 1886 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1887 ahci_hardreset, ahci_postreset,
1888 sata_pmp_std_prereset, ahci_pmp_softreset,
1889 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1890}
1891
ad616ffb
TH		 1892static void ahci_vt8251_error_handler(struct ata_port *ap)
1893{
ad616ffb
TH		 1894 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1895 /* restart engine */
4447d351
TH		 1896 ahci_stop_engine(ap);
1897 ahci_start_engine(ap);
ad616ffb
TH		 1898 }
1899
1900 /* perform recovery */
1901 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1902 ahci_postreset);
1903}
1904
edc93052
TH		 1905static void ahci_p5wdh_error_handler(struct ata_port *ap)
1906{
1907 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1908 /* restart engine */
1909 ahci_stop_engine(ap);
1910 ahci_start_engine(ap);
1911 }
1912
1913 /* perform recovery */
1914 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1915 ahci_postreset);
1916}
1917
78cd52d0
TH		 1918static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1919{
1920 struct ata_port *ap = qc->ap;
1921
d2e75dff
TH		 1922 /* make DMA engine forget about the failed command */
1923 if (qc->flags & ATA_QCFLAG_FAILED)
1924 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1925}
1926
7d50b60b
TH		 1927static void ahci_pmp_attach(struct ata_port *ap)
1928{
1929 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1930 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1931 u32 cmd;
1932
1933 cmd = readl(port_mmio + PORT_CMD);
1934 cmd |= PORT_CMD_PMP;
1935 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1936
1937 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1938 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1939}
1940
1941static void ahci_pmp_detach(struct ata_port *ap)
1942{
1943 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1944 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1945 u32 cmd;
1946
1947 cmd = readl(port_mmio + PORT_CMD);
1948 cmd &= ~PORT_CMD_PMP;
1949 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1950
1951 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1952 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1953}
1954
028a2596
AD		 1955static int ahci_port_resume(struct ata_port *ap)
1956{
1957 ahci_power_up(ap);
1958 ahci_start_port(ap);
1959
7d50b60b
TH		 1960 if (ap->nr_pmp_links)
1961 ahci_pmp_attach(ap);
1962 else
1963 ahci_pmp_detach(ap);
1964
028a2596
AD		 1965 return 0;
1966}
1967
438ac6d5 1968#ifdef CONFIG_PM
c1332875
TH		 1969static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1970{
c1332875
TH		 1971 const char *emsg = NULL;
1972 int rc;
1973
4447d351 1974 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1975 if (rc == 0)
4447d351 1976 ahci_power_down(ap);
8e16f941 1977 else {
c1332875 1978 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1979 ahci_start_port(ap);
c1332875
TH		 1980 }
1981
1982 return rc;
1983}
1984
c1332875
TH		 1985static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1986{
cca3974e 1987 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1988 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1989 u32 ctl;
1990
1991 if (mesg.event == PM_EVENT_SUSPEND) {
1992 /* AHCI spec rev1.1 section 8.3.3:
1993 * Software must disable interrupts prior to requesting a
1994 * transition of the HBA to D3 state.
1995 */
1996 ctl = readl(mmio + HOST_CTL);
1997 ctl &= ~HOST_IRQ_EN;
1998 writel(ctl, mmio + HOST_CTL);
1999 readl(mmio + HOST_CTL); /* flush */
2000 }
2001
2002 return ata_pci_device_suspend(pdev, mesg);
2003}
2004
2005static int ahci_pci_device_resume(struct pci_dev *pdev)
2006{
cca3974e 2007 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2008 int rc;
2009
553c4aa6
TH		 2010 rc = ata_pci_device_do_resume(pdev);
2011 if (rc)
2012 return rc;
c1332875
TH		 2013
2014 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2015 rc = ahci_reset_controller(host);
c1332875
TH		 2016 if (rc)
2017 return rc;
2018
4447d351 2019 ahci_init_controller(host);
c1332875
TH		 2020 }
2021
cca3974e 2022 ata_host_resume(host);
c1332875
TH		 2023
2024 return 0;
2025}
438ac6d5 2026#endif
c1332875 2027
254950cd
TH		 2028static int ahci_port_start(struct ata_port *ap)
2029{
cca3974e 2030 struct device *dev = ap->host->dev;
254950cd 2031 struct ahci_port_priv *pp;
254950cd
TH		 2032 void *mem;
2033 dma_addr_t mem_dma;
2034 int rc;
2035
24dc5f33 2036 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2037 if (!pp)
2038 return -ENOMEM;
254950cd
TH		 2039
2040 rc = ata_pad_alloc(ap, dev);
24dc5f33 2041 if (rc)
254950cd 2042 return rc;
254950cd 2043
24dc5f33
TH		 2044 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2045 GFP_KERNEL);
2046 if (!mem)
254950cd 2047 return -ENOMEM;
254950cd
TH		 2048 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2049
2050 /*
2051 * First item in chunk of DMA memory: 32-slot command table,
2052 * 32 bytes each in size
2053 */
2054 pp->cmd_slot = mem;
2055 pp->cmd_slot_dma = mem_dma;
2056
2057 mem += AHCI_CMD_SLOT_SZ;
2058 mem_dma += AHCI_CMD_SLOT_SZ;
2059
2060 /*
2061 * Second item: Received-FIS area
2062 */
2063 pp->rx_fis = mem;
2064 pp->rx_fis_dma = mem_dma;
2065
2066 mem += AHCI_RX_FIS_SZ;
2067 mem_dma += AHCI_RX_FIS_SZ;
2068
2069 /*
2070 * Third item: data area for storing a single command
2071 * and its scatter-gather table
2072 */
2073 pp->cmd_tbl = mem;
2074 pp->cmd_tbl_dma = mem_dma;
2075
a7384925 2076 /*
2dcb407e
JG		 2077 * Save off initial list of interrupts to be enabled.
2078 * This could be changed later
2079 */
a7384925
KCA		 2080 pp->intr_mask = DEF_PORT_IRQ;
2081
254950cd
TH		 2082 ap->private_data = pp;
2083
df69c9c5
JG		 2084 /* engage engines, captain */
2085 return ahci_port_resume(ap);
254950cd
TH		 2086}
2087
2088static void ahci_port_stop(struct ata_port *ap)
2089{
0be0aa98
TH		 2090 const char *emsg = NULL;
2091 int rc;
254950cd 2092
0be0aa98 2093 /* de-initialize port */
4447d351 2094 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2095 if (rc)
2096 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2097}
2098
4447d351 2099static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2100{
1da177e4 2101 int rc;
1da177e4 2102
1da177e4
LT		 2103 if (using_dac &&
2104 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2105 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2106 if (rc) {
2107 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2108 if (rc) {
a9524a76
JG		 2109 dev_printk(KERN_ERR, &pdev->dev,
2110 "64-bit DMA enable failed\n");
1da177e4
LT		 2111 return rc;
2112 }
2113 }
1da177e4
LT		 2114 } else {
2115 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2116 if (rc) {
a9524a76
JG		 2117 dev_printk(KERN_ERR, &pdev->dev,
2118 "32-bit DMA enable failed\n");
1da177e4
LT		 2119 return rc;
2120 }
2121 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2122 if (rc) {
a9524a76
JG		 2123 dev_printk(KERN_ERR, &pdev->dev,
2124 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2125 return rc;
2126 }
2127 }
1da177e4
LT		 2128 return 0;
2129}
2130
4447d351 2131static void ahci_print_info(struct ata_host *host)
1da177e4 2132{
4447d351
TH		 2133 struct ahci_host_priv *hpriv = host->private_data;
2134 struct pci_dev *pdev = to_pci_dev(host->dev);
2135 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2136 u32 vers, cap, impl, speed;
2137 const char *speed_s;
2138 u16 cc;
2139 const char *scc_s;
2140
2141 vers = readl(mmio + HOST_VERSION);
2142 cap = hpriv->cap;
2143 impl = hpriv->port_map;
2144
2145 speed = (cap >> 20) & 0xf;
2146 if (speed == 1)
2147 speed_s = "1.5";
2148 else if (speed == 2)
2149 speed_s = "3";
2150 else
2151 speed_s = "?";
2152
2153 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2154 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2155 scc_s = "IDE";
c9f89475 2156 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2157 scc_s = "SATA";
c9f89475 2158 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2159 scc_s = "RAID";
2160 else
2161 scc_s = "unknown";
2162
a9524a76
JG		 2163 dev_printk(KERN_INFO, &pdev->dev,
2164 "AHCI %02x%02x.%02x%02x "
1da177e4 2165 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2166 ,
1da177e4 2167
2dcb407e
JG		 2168 (vers >> 24) & 0xff,
2169 (vers >> 16) & 0xff,
2170 (vers >> 8) & 0xff,
2171 vers & 0xff,
1da177e4
LT		 2172
2173 ((cap >> 8) & 0x1f) + 1,
2174 (cap & 0x1f) + 1,
2175 speed_s,
2176 impl,
2177 scc_s);
2178
a9524a76
JG		 2179 dev_printk(KERN_INFO, &pdev->dev,
2180 "flags: "
203ef6c4
TH		 2181 "%s%s%s%s%s%s%s"
2182 "%s%s%s%s%s%s%s\n"
2dcb407e 2183 ,
1da177e4
LT		 2184
2185 cap & (1 << 31) ? "64bit " : "",
2186 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2187 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2188 cap & (1 << 28) ? "ilck " : "",
2189 cap & (1 << 27) ? "stag " : "",
2190 cap & (1 << 26) ? "pm " : "",
2191 cap & (1 << 25) ? "led " : "",
2192
2193 cap & (1 << 24) ? "clo " : "",
2194 cap & (1 << 19) ? "nz " : "",
2195 cap & (1 << 18) ? "only " : "",
2196 cap & (1 << 17) ? "pmp " : "",
2197 cap & (1 << 15) ? "pio " : "",
2198 cap & (1 << 14) ? "slum " : "",
2199 cap & (1 << 13) ? "part " : ""
2200 );
2201}
2202
edc93052
TH		 2203/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2204 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2205 * support PMP and the 4726 either directly exports the device
2206 * attached to the first downstream port or acts as a hardware storage
2207 * controller and emulate a single ATA device (can be RAID 0/1 or some
2208 * other configuration).
2209 *
2210 * When there's no device attached to the first downstream port of the
2211 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2212 * configure the 4726. However, ATA emulation of the device is very
2213 * lame. It doesn't send signature D2H Reg FIS after the initial
2214 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2215 *
2216 * The following function works around the problem by always using
2217 * hardreset on the port and not depending on receiving signature FIS
2218 * afterward. If signature FIS isn't received soon, ATA class is
2219 * assumed without follow-up softreset.
2220 */
2221static void ahci_p5wdh_workaround(struct ata_host *host)
2222{
2223 static struct dmi_system_id sysids[] = {
2224 {
2225 .ident = "P5W DH Deluxe",
2226 .matches = {
2227 DMI_MATCH(DMI_SYS_VENDOR,
2228 "ASUSTEK COMPUTER INC"),
2229 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2230 },
2231 },
2232 { }
2233 };
2234 struct pci_dev *pdev = to_pci_dev(host->dev);
2235
2236 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2237 dmi_check_system(sysids)) {
2238 struct ata_port *ap = host->ports[1];
2239
2240 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2241 "Deluxe on-board SIMG4726 workaround\n");
2242
2243 ap->ops = &ahci_p5wdh_ops;
2244 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2245 }
2246}
2247
24dc5f33 2248static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2249{
2250 static int printed_version;
4447d351
TH		 2251 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2252 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2253 struct device *dev = &pdev->dev;
1da177e4 2254 struct ahci_host_priv *hpriv;
4447d351
TH		 2255 struct ata_host *host;
2256 int i, rc;
1da177e4
LT		 2257
2258 VPRINTK("ENTER\n");
2259
12fad3f9
TH		 2260 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2261
1da177e4 2262 if (!printed_version++)
a9524a76 2263 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2264
4447d351 2265 /* acquire resources */
24dc5f33 2266 rc = pcim_enable_device(pdev);
1da177e4
LT		 2267 if (rc)
2268 return rc;
2269
0d5ff566
TH		 2270 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2271 if (rc == -EBUSY)
24dc5f33 2272 pcim_pin_device(pdev);
0d5ff566 2273 if (rc)
24dc5f33 2274 return rc;
1da177e4 2275
24dc5f33
TH		 2276 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2277 if (!hpriv)
2278 return -ENOMEM;
417a1a6d
TH		 2279 hpriv->flags |= (unsigned long)pi.private_data;
2280
2281 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2282 pci_intx(pdev, 1);
1da177e4 2283
4447d351 2284 /* save initial config */
417a1a6d 2285 ahci_save_initial_config(pdev, hpriv);
1da177e4 2286
4447d351 2287 /* prepare host */
274c1fde 2288 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2289 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2290
7d50b60b
TH		 2291 if (hpriv->cap & HOST_CAP_PMP)
2292 pi.flags |= ATA_FLAG_PMP;
2293
4447d351
TH		 2294 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2295 if (!host)
2296 return -ENOMEM;
2297 host->iomap = pcim_iomap_table(pdev);
2298 host->private_data = hpriv;
2299
2300 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2301 struct ata_port *ap = host->ports[i];
2302 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2303
cbcdd875
TH		 2304 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2305 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2306 0x100 + ap->port_no * 0x80, "port");
2307
31556594
KCA		 2308 /* set initial link pm policy */
2309 ap->pm_policy = NOT_AVAILABLE;
2310
dab632e8 2311 /* standard SATA port setup */
203ef6c4 2312 if (hpriv->port_map & (1 << i))
4447d351 2313 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2314
2315 /* disabled/not-implemented port */
2316 else
2317 ap->ops = &ata_dummy_port_ops;
4447d351 2318 }
d447df14 2319
edc93052
TH		 2320 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2321 ahci_p5wdh_workaround(host);
2322
4447d351
TH		 2323 /* initialize adapter */
2324 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2325 if (rc)
24dc5f33 2326 return rc;
1da177e4 2327
4447d351
TH		 2328 rc = ahci_reset_controller(host);
2329 if (rc)
2330 return rc;
1da177e4 2331
4447d351
TH		 2332 ahci_init_controller(host);
2333 ahci_print_info(host);
1da177e4 2334
4447d351
TH		 2335 pci_set_master(pdev);
2336 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2337 &ahci_sht);
907f4678 2338}
1da177e4
LT		 2339
2340static int __init ahci_init(void)
2341{
b7887196 2342 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2343}
2344
1da177e4
LT		 2345static void __exit ahci_exit(void)
2346{
2347 pci_unregister_driver(&ahci_pci_driver);
2348}
2349
2350
2351MODULE_AUTHOR("Jeff Garzik");
2352MODULE_DESCRIPTION("AHCI SATA low-level driver");
2353MODULE_LICENSE("GPL");
2354MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2355MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2356
2357module_init(ahci_init);
2358module_exit(ahci_exit);
Linux kernel - Deliverables
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