Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
87943acf DM |
52 | /* Enclosure Management Control */ |
53 | #define EM_CTRL_MSG_TYPE 0x000f0000 | |
54 | ||
55 | /* Enclosure Management LED Message Type */ | |
56 | #define EM_MSG_LED_HBA_PORT 0x0000000f | |
57 | #define EM_MSG_LED_PMP_SLOT 0x0000ff00 | |
58 | #define EM_MSG_LED_VALUE 0xffff0000 | |
59 | #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 | |
60 | #define EM_MSG_LED_VALUE_OFF 0xfff80000 | |
61 | #define EM_MSG_LED_VALUE_ON 0x00010000 | |
62 | ||
a22e6444 | 63 | static int ahci_skip_host_reset; |
f3d7f23f AV |
64 | static int ahci_ignore_sss; |
65 | ||
a22e6444 TH |
66 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); |
67 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
68 | ||
f3d7f23f AV |
69 | module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); |
70 | MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); | |
71 | ||
31556594 KCA |
72 | static int ahci_enable_alpm(struct ata_port *ap, |
73 | enum link_pm policy); | |
74 | static void ahci_disable_alpm(struct ata_port *ap); | |
18f7ba4c KCA |
75 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf); |
76 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
77 | size_t size); | |
78 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
79 | ssize_t size); | |
80 | #define MAX_SLOTS 8 | |
4c1e9aa4 | 81 | #define MAX_RETRY 15 |
1da177e4 LT |
82 | |
83 | enum { | |
84 | AHCI_PCI_BAR = 5, | |
648a88be | 85 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
86 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
87 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
12fad3f9 | 88 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 89 | AHCI_CMD_SZ = 32, |
12fad3f9 | 90 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 91 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 92 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
93 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
94 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
95 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
96 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
97 | AHCI_RX_FIS_SZ, |
98 | AHCI_IRQ_ON_SG = (1 << 31), | |
99 | AHCI_CMD_ATAPI = (1 << 5), | |
100 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 101 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
102 | AHCI_CMD_RESET = (1 << 8), |
103 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
104 | |
105 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 106 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 107 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
108 | |
109 | board_ahci = 0, | |
7a234aff TH |
110 | board_ahci_vt8251 = 1, |
111 | board_ahci_ign_iferr = 2, | |
112 | board_ahci_sb600 = 3, | |
113 | board_ahci_mv = 4, | |
e427fe04 | 114 | board_ahci_sb700 = 5, /* for SB700 and SB800 */ |
e297d99e | 115 | board_ahci_mcp65 = 6, |
9a3b103c | 116 | board_ahci_nopmp = 7, |
aa431dd3 | 117 | board_ahci_yesncq = 8, |
1da177e4 LT |
118 | |
119 | /* global controller registers */ | |
120 | HOST_CAP = 0x00, /* host capabilities */ | |
121 | HOST_CTL = 0x04, /* global host control */ | |
122 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
123 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
124 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
18f7ba4c KCA |
125 | HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
126 | HOST_EM_CTL = 0x20, /* Enclosure Management Control */ | |
1da177e4 LT |
127 | |
128 | /* HOST_CTL bits */ | |
129 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
130 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
131 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
132 | ||
133 | /* HOST_CAP bits */ | |
18f7ba4c | 134 | HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ |
0be0aa98 | 135 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 136 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 137 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 138 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 139 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 140 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 141 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 142 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
143 | |
144 | /* registers for each SATA port */ | |
145 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
146 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
147 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
148 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
149 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
150 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
151 | PORT_CMD = 0x18, /* port command */ | |
152 | PORT_TFDATA = 0x20, /* taskfile data */ | |
153 | PORT_SIG = 0x24, /* device TF signature */ | |
154 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
155 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
156 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
157 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
158 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 159 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
160 | |
161 | /* PORT_IRQ_{STAT,MASK} bits */ | |
162 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
163 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
164 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
165 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
166 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
167 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
168 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
169 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
170 | ||
171 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
172 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
173 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
174 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
175 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
176 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
177 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
178 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
179 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
180 | ||
78cd52d0 TH |
181 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
182 | PORT_IRQ_IF_ERR | | |
183 | PORT_IRQ_CONNECT | | |
4296971d | 184 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
185 | PORT_IRQ_UNK_FIS | |
186 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
187 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
188 | PORT_IRQ_TF_ERR | | |
189 | PORT_IRQ_HBUS_DATA_ERR, | |
190 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
191 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
192 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
193 | |
194 | /* PORT_CMD bits */ | |
31556594 KCA |
195 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
196 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 197 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 198 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
199 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
200 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
201 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 202 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
203 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
204 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
205 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
206 | ||
0be0aa98 | 207 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
208 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
209 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
210 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 211 | |
417a1a6d TH |
212 | /* hpriv->flags bits */ |
213 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
214 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
215 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
216 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
217 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
218 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 219 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 220 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
a878539e | 221 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
e297d99e | 222 | AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
9b10ae86 | 223 | AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ |
417a1a6d | 224 | |
bf2af2a2 | 225 | /* ap->flags bits */ |
1188c0d8 TH |
226 | |
227 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
228 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
229 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
230 | ATA_FLAG_IPM, | |
c4f7792c TH |
231 | |
232 | ICH_MAP = 0x90, /* ICH MAP register */ | |
18f7ba4c KCA |
233 | |
234 | /* em_ctl bits */ | |
235 | EM_CTL_RST = (1 << 9), /* Reset */ | |
236 | EM_CTL_TM = (1 << 8), /* Transmit Message */ | |
237 | EM_CTL_ALHD = (1 << 26), /* Activity LED */ | |
1da177e4 LT |
238 | }; |
239 | ||
240 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
241 | __le32 opts; |
242 | __le32 status; | |
243 | __le32 tbl_addr; | |
244 | __le32 tbl_addr_hi; | |
245 | __le32 reserved[4]; | |
1da177e4 LT |
246 | }; |
247 | ||
248 | struct ahci_sg { | |
4ca4e439 AV |
249 | __le32 addr; |
250 | __le32 addr_hi; | |
251 | __le32 reserved; | |
252 | __le32 flags_size; | |
1da177e4 LT |
253 | }; |
254 | ||
18f7ba4c KCA |
255 | struct ahci_em_priv { |
256 | enum sw_activity blink_policy; | |
257 | struct timer_list timer; | |
258 | unsigned long saved_activity; | |
259 | unsigned long activity; | |
260 | unsigned long led_state; | |
261 | }; | |
262 | ||
1da177e4 | 263 | struct ahci_host_priv { |
417a1a6d | 264 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
265 | u32 cap; /* cap to use */ |
266 | u32 port_map; /* port map to use */ | |
267 | u32 saved_cap; /* saved initial cap */ | |
268 | u32 saved_port_map; /* saved initial port_map */ | |
18f7ba4c | 269 | u32 em_loc; /* enclosure management location */ |
1da177e4 LT |
270 | }; |
271 | ||
272 | struct ahci_port_priv { | |
7d50b60b | 273 | struct ata_link *active_link; |
1da177e4 LT |
274 | struct ahci_cmd_hdr *cmd_slot; |
275 | dma_addr_t cmd_slot_dma; | |
276 | void *cmd_tbl; | |
277 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
278 | void *rx_fis; |
279 | dma_addr_t rx_fis_dma; | |
0291f95f | 280 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
281 | unsigned int ncq_saw_d2h:1; |
282 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 283 | unsigned int ncq_saw_sdb:1; |
a7384925 | 284 | u32 intr_mask; /* interrupts to enable */ |
18f7ba4c KCA |
285 | struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info |
286 | * per PM slot */ | |
1da177e4 LT |
287 | }; |
288 | ||
82ef04fb TH |
289 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
290 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
2dcb407e | 291 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 292 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
4c9bf4e7 | 293 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
1da177e4 LT |
294 | static int ahci_port_start(struct ata_port *ap); |
295 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 | 296 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
78cd52d0 TH |
297 | static void ahci_freeze(struct ata_port *ap); |
298 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
299 | static void ahci_pmp_attach(struct ata_port *ap); |
300 | static void ahci_pmp_detach(struct ata_port *ap); | |
a1efdaba TH |
301 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
302 | unsigned long deadline); | |
bd17243a SH |
303 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, |
304 | unsigned long deadline); | |
a1efdaba TH |
305 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
306 | unsigned long deadline); | |
307 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, | |
308 | unsigned long deadline); | |
309 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, | |
310 | unsigned long deadline); | |
311 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
78cd52d0 TH |
312 | static void ahci_error_handler(struct ata_port *ap); |
313 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
df69c9c5 | 314 | static int ahci_port_resume(struct ata_port *ap); |
a878539e | 315 | static void ahci_dev_config(struct ata_device *dev); |
dab632e8 JG |
316 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
317 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
318 | u32 opts); | |
438ac6d5 | 319 | #ifdef CONFIG_PM |
c1332875 | 320 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
321 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
322 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 323 | #endif |
18f7ba4c KCA |
324 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); |
325 | static ssize_t ahci_activity_store(struct ata_device *dev, | |
326 | enum sw_activity val); | |
327 | static void ahci_init_sw_activity(struct ata_link *link); | |
1da177e4 | 328 | |
ee959b00 TJ |
329 | static struct device_attribute *ahci_shost_attrs[] = { |
330 | &dev_attr_link_power_management_policy, | |
18f7ba4c KCA |
331 | &dev_attr_em_message_type, |
332 | &dev_attr_em_message, | |
333 | NULL | |
334 | }; | |
335 | ||
336 | static struct device_attribute *ahci_sdev_attrs[] = { | |
337 | &dev_attr_sw_activity, | |
45fabbb7 | 338 | &dev_attr_unload_heads, |
31556594 KCA |
339 | NULL |
340 | }; | |
341 | ||
193515d5 | 342 | static struct scsi_host_template ahci_sht = { |
68d1d07b | 343 | ATA_NCQ_SHT(DRV_NAME), |
12fad3f9 | 344 | .can_queue = AHCI_MAX_CMDS - 1, |
1da177e4 | 345 | .sg_tablesize = AHCI_MAX_SG, |
1da177e4 | 346 | .dma_boundary = AHCI_DMA_BOUNDARY, |
31556594 | 347 | .shost_attrs = ahci_shost_attrs, |
18f7ba4c | 348 | .sdev_attrs = ahci_sdev_attrs, |
1da177e4 LT |
349 | }; |
350 | ||
029cfd6b TH |
351 | static struct ata_port_operations ahci_ops = { |
352 | .inherits = &sata_pmp_port_ops, | |
353 | ||
7d50b60b | 354 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
355 | .qc_prep = ahci_qc_prep, |
356 | .qc_issue = ahci_qc_issue, | |
4c9bf4e7 | 357 | .qc_fill_rtf = ahci_qc_fill_rtf, |
1da177e4 | 358 | |
78cd52d0 TH |
359 | .freeze = ahci_freeze, |
360 | .thaw = ahci_thaw, | |
a1efdaba TH |
361 | .softreset = ahci_softreset, |
362 | .hardreset = ahci_hardreset, | |
363 | .postreset = ahci_postreset, | |
071f44b1 | 364 | .pmp_softreset = ahci_softreset, |
78cd52d0 TH |
365 | .error_handler = ahci_error_handler, |
366 | .post_internal_cmd = ahci_post_internal_cmd, | |
6bd99b4e TH |
367 | .dev_config = ahci_dev_config, |
368 | ||
ad616ffb TH |
369 | .scr_read = ahci_scr_read, |
370 | .scr_write = ahci_scr_write, | |
7d50b60b TH |
371 | .pmp_attach = ahci_pmp_attach, |
372 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 373 | |
029cfd6b TH |
374 | .enable_pm = ahci_enable_alpm, |
375 | .disable_pm = ahci_disable_alpm, | |
18f7ba4c KCA |
376 | .em_show = ahci_led_show, |
377 | .em_store = ahci_led_store, | |
378 | .sw_activity_show = ahci_activity_show, | |
379 | .sw_activity_store = ahci_activity_store, | |
438ac6d5 | 380 | #ifdef CONFIG_PM |
ad616ffb TH |
381 | .port_suspend = ahci_port_suspend, |
382 | .port_resume = ahci_port_resume, | |
438ac6d5 | 383 | #endif |
ad616ffb TH |
384 | .port_start = ahci_port_start, |
385 | .port_stop = ahci_port_stop, | |
386 | }; | |
387 | ||
029cfd6b TH |
388 | static struct ata_port_operations ahci_vt8251_ops = { |
389 | .inherits = &ahci_ops, | |
a1efdaba | 390 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 391 | }; |
edc93052 | 392 | |
029cfd6b TH |
393 | static struct ata_port_operations ahci_p5wdh_ops = { |
394 | .inherits = &ahci_ops, | |
a1efdaba | 395 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
396 | }; |
397 | ||
bd17243a SH |
398 | static struct ata_port_operations ahci_sb600_ops = { |
399 | .inherits = &ahci_ops, | |
400 | .softreset = ahci_sb600_softreset, | |
401 | .pmp_softreset = ahci_sb600_softreset, | |
402 | }; | |
403 | ||
417a1a6d TH |
404 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
405 | ||
98ac62de | 406 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
407 | /* board_ahci */ |
408 | { | |
1188c0d8 | 409 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 410 | .pio_mask = ATA_PIO4, |
469248ab | 411 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
412 | .port_ops = &ahci_ops, |
413 | }, | |
bf2af2a2 BJ |
414 | /* board_ahci_vt8251 */ |
415 | { | |
6949b914 | 416 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 417 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 418 | .pio_mask = ATA_PIO4, |
469248ab | 419 | .udma_mask = ATA_UDMA6, |
ad616ffb | 420 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 421 | }, |
41669553 TH |
422 | /* board_ahci_ign_iferr */ |
423 | { | |
417a1a6d TH |
424 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
425 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 426 | .pio_mask = ATA_PIO4, |
469248ab | 427 | .udma_mask = ATA_UDMA6, |
41669553 TH |
428 | .port_ops = &ahci_ops, |
429 | }, | |
55a61604 CH |
430 | /* board_ahci_sb600 */ |
431 | { | |
417a1a6d | 432 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
22b5e7a7 | 433 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | |
bd17243a | 434 | AHCI_HFLAG_SECT255), |
417a1a6d | 435 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 436 | .pio_mask = ATA_PIO4, |
469248ab | 437 | .udma_mask = ATA_UDMA6, |
bd17243a | 438 | .port_ops = &ahci_sb600_ops, |
55a61604 | 439 | }, |
cd70c266 JG |
440 | /* board_ahci_mv */ |
441 | { | |
417a1a6d | 442 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 443 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
cd70c266 | 444 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 445 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
14bdef98 | 446 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
447 | .udma_mask = ATA_UDMA6, |
448 | .port_ops = &ahci_ops, | |
449 | }, | |
e427fe04 | 450 | /* board_ahci_sb700, for SB700 and SB800 */ |
e39fc8c9 | 451 | { |
bd17243a | 452 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
e39fc8c9 | 453 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 454 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 455 | .udma_mask = ATA_UDMA6, |
bd17243a | 456 | .port_ops = &ahci_sb600_ops, |
e39fc8c9 | 457 | }, |
e297d99e TH |
458 | /* board_ahci_mcp65 */ |
459 | { | |
460 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), | |
461 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 462 | .pio_mask = ATA_PIO4, |
e297d99e TH |
463 | .udma_mask = ATA_UDMA6, |
464 | .port_ops = &ahci_ops, | |
465 | }, | |
9a3b103c TH |
466 | /* board_ahci_nopmp */ |
467 | { | |
468 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), | |
469 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 470 | .pio_mask = ATA_PIO4, |
9a3b103c TH |
471 | .udma_mask = ATA_UDMA6, |
472 | .port_ops = &ahci_ops, | |
473 | }, | |
aa431dd3 TH |
474 | /* board_ahci_yesncq */ |
475 | { | |
476 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), | |
477 | .flags = AHCI_FLAG_COMMON, | |
478 | .pio_mask = ATA_PIO4, | |
479 | .udma_mask = ATA_UDMA6, | |
480 | .port_ops = &ahci_ops, | |
481 | }, | |
1da177e4 LT |
482 | }; |
483 | ||
3b7d697d | 484 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 485 | /* Intel */ |
54bb3a94 JG |
486 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
487 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
488 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
489 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
490 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 491 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
492 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
493 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
494 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
495 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
496 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
497 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
498 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
499 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
500 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
501 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
502 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
503 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
504 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
505 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
506 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
507 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
508 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
509 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
510 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
511 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
512 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
513 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
514 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 JG |
515 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
516 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ | |
adcb5308 | 517 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 518 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
adcb5308 | 519 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 520 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ |
fe7fa31a | 521 | |
e34bb370 TH |
522 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
523 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
524 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
525 | |
526 | /* ATI */ | |
c65ec1c2 | 527 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
528 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
529 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
530 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
531 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
532 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
533 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
534 | |
535 | /* VIA */ | |
54bb3a94 | 536 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 537 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
538 | |
539 | /* NVIDIA */ | |
e297d99e TH |
540 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
541 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
542 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
543 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
544 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
545 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
546 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
547 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
aa431dd3 TH |
548 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */ |
549 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */ | |
550 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */ | |
551 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */ | |
552 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */ | |
553 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */ | |
554 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */ | |
555 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */ | |
556 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */ | |
557 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */ | |
558 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */ | |
559 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */ | |
560 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */ | |
561 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */ | |
562 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */ | |
563 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */ | |
564 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */ | |
565 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */ | |
566 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */ | |
567 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */ | |
568 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */ | |
569 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */ | |
570 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */ | |
571 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */ | |
0522b286 PC |
572 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
573 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
574 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
575 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
576 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
577 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
578 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
579 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
580 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
581 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
582 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
583 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 584 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
585 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
586 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
587 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
588 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
589 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
590 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
591 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
592 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
593 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
594 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
595 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
7adbe46b | 596 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ |
597 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ | |
598 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ | |
599 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ | |
600 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ | |
601 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ | |
602 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ | |
603 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ | |
604 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ | |
605 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ | |
606 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ | |
607 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ | |
fe7fa31a | 608 | |
95916edd | 609 | /* SiS */ |
20e2de4a TH |
610 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
611 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
612 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 613 | |
cd70c266 JG |
614 | /* Marvell */ |
615 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 616 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
cd70c266 | 617 | |
c77a036b MN |
618 | /* Promise */ |
619 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
620 | ||
415ae2b5 JG |
621 | /* Generic, PCI class code for AHCI */ |
622 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 623 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 624 | |
1da177e4 LT |
625 | { } /* terminate list */ |
626 | }; | |
627 | ||
628 | ||
629 | static struct pci_driver ahci_pci_driver = { | |
630 | .name = DRV_NAME, | |
631 | .id_table = ahci_pci_tbl, | |
632 | .probe = ahci_init_one, | |
24dc5f33 | 633 | .remove = ata_pci_remove_one, |
438ac6d5 | 634 | #ifdef CONFIG_PM |
c1332875 TH |
635 | .suspend = ahci_pci_device_suspend, |
636 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 637 | #endif |
1da177e4 LT |
638 | }; |
639 | ||
18f7ba4c KCA |
640 | static int ahci_em_messages = 1; |
641 | module_param(ahci_em_messages, int, 0444); | |
642 | /* add other LED protocol types when they become supported */ | |
643 | MODULE_PARM_DESC(ahci_em_messages, | |
644 | "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); | |
1da177e4 | 645 | |
5b66c829 AC |
646 | #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) |
647 | static int marvell_enable; | |
648 | #else | |
649 | static int marvell_enable = 1; | |
650 | #endif | |
651 | module_param(marvell_enable, int, 0644); | |
652 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
653 | ||
654 | ||
98fa4b60 TH |
655 | static inline int ahci_nr_ports(u32 cap) |
656 | { | |
657 | return (cap & 0x1f) + 1; | |
658 | } | |
659 | ||
dab632e8 JG |
660 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
661 | unsigned int port_no) | |
1da177e4 | 662 | { |
dab632e8 | 663 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 664 | |
dab632e8 JG |
665 | return mmio + 0x100 + (port_no * 0x80); |
666 | } | |
667 | ||
668 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
669 | { | |
670 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
671 | } |
672 | ||
b710a1f4 TH |
673 | static void ahci_enable_ahci(void __iomem *mmio) |
674 | { | |
15fe982e | 675 | int i; |
b710a1f4 TH |
676 | u32 tmp; |
677 | ||
678 | /* turn on AHCI_EN */ | |
679 | tmp = readl(mmio + HOST_CTL); | |
15fe982e TH |
680 | if (tmp & HOST_AHCI_EN) |
681 | return; | |
682 | ||
683 | /* Some controllers need AHCI_EN to be written multiple times. | |
684 | * Try a few times before giving up. | |
685 | */ | |
686 | for (i = 0; i < 5; i++) { | |
b710a1f4 TH |
687 | tmp |= HOST_AHCI_EN; |
688 | writel(tmp, mmio + HOST_CTL); | |
689 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
15fe982e TH |
690 | if (tmp & HOST_AHCI_EN) |
691 | return; | |
692 | msleep(10); | |
b710a1f4 | 693 | } |
15fe982e TH |
694 | |
695 | WARN_ON(1); | |
b710a1f4 TH |
696 | } |
697 | ||
d447df14 TH |
698 | /** |
699 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 700 | * @pdev: target PCI device |
4447d351 | 701 | * @hpriv: host private area to store config values |
d447df14 TH |
702 | * |
703 | * Some registers containing configuration info might be setup by | |
704 | * BIOS and might be cleared on reset. This function saves the | |
705 | * initial values of those registers into @hpriv such that they | |
706 | * can be restored after controller reset. | |
707 | * | |
708 | * If inconsistent, config values are fixed up by this function. | |
709 | * | |
710 | * LOCKING: | |
711 | * None. | |
712 | */ | |
4447d351 | 713 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 714 | struct ahci_host_priv *hpriv) |
d447df14 | 715 | { |
4447d351 | 716 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 717 | u32 cap, port_map; |
17199b18 | 718 | int i; |
c40e7cb8 | 719 | int mv; |
d447df14 | 720 | |
b710a1f4 TH |
721 | /* make sure AHCI mode is enabled before accessing CAP */ |
722 | ahci_enable_ahci(mmio); | |
723 | ||
d447df14 TH |
724 | /* Values prefixed with saved_ are written back to host after |
725 | * reset. Values without are used for driver operation. | |
726 | */ | |
727 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
728 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
729 | ||
274c1fde | 730 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 731 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
732 | dev_printk(KERN_INFO, &pdev->dev, |
733 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
734 | cap &= ~HOST_CAP_64; | |
735 | } | |
736 | ||
417a1a6d | 737 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
738 | dev_printk(KERN_INFO, &pdev->dev, |
739 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
740 | cap &= ~HOST_CAP_NCQ; | |
741 | } | |
742 | ||
e297d99e TH |
743 | if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { |
744 | dev_printk(KERN_INFO, &pdev->dev, | |
745 | "controller can do NCQ, turning on CAP_NCQ\n"); | |
746 | cap |= HOST_CAP_NCQ; | |
747 | } | |
748 | ||
258cd846 | 749 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
6949b914 TH |
750 | dev_printk(KERN_INFO, &pdev->dev, |
751 | "controller can't do PMP, turning off CAP_PMP\n"); | |
752 | cap &= ~HOST_CAP_PMP; | |
753 | } | |
754 | ||
d799e083 TH |
755 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && |
756 | port_map != 1) { | |
757 | dev_printk(KERN_INFO, &pdev->dev, | |
758 | "JMB361 has only one port, port_map 0x%x -> 0x%x\n", | |
759 | port_map, 1); | |
760 | port_map = 1; | |
761 | } | |
762 | ||
cd70c266 JG |
763 | /* |
764 | * Temporary Marvell 6145 hack: PATA port presence | |
765 | * is asserted through the standard AHCI port | |
766 | * presence register, as bit 4 (counting from 0) | |
767 | */ | |
417a1a6d | 768 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
769 | if (pdev->device == 0x6121) |
770 | mv = 0x3; | |
771 | else | |
772 | mv = 0xf; | |
cd70c266 JG |
773 | dev_printk(KERN_ERR, &pdev->dev, |
774 | "MV_AHCI HACK: port_map %x -> %x\n", | |
c40e7cb8 JAR |
775 | port_map, |
776 | port_map & mv); | |
5b66c829 AC |
777 | dev_printk(KERN_ERR, &pdev->dev, |
778 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
cd70c266 | 779 | |
c40e7cb8 | 780 | port_map &= mv; |
cd70c266 JG |
781 | } |
782 | ||
17199b18 | 783 | /* cross check port_map and cap.n_ports */ |
7a234aff | 784 | if (port_map) { |
837f5f8f | 785 | int map_ports = 0; |
17199b18 | 786 | |
837f5f8f TH |
787 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
788 | if (port_map & (1 << i)) | |
789 | map_ports++; | |
17199b18 | 790 | |
837f5f8f TH |
791 | /* If PI has more ports than n_ports, whine, clear |
792 | * port_map and let it be generated from n_ports. | |
17199b18 | 793 | */ |
837f5f8f | 794 | if (map_ports > ahci_nr_ports(cap)) { |
4447d351 | 795 | dev_printk(KERN_WARNING, &pdev->dev, |
837f5f8f TH |
796 | "implemented port map (0x%x) contains more " |
797 | "ports than nr_ports (%u), using nr_ports\n", | |
798 | port_map, ahci_nr_ports(cap)); | |
7a234aff TH |
799 | port_map = 0; |
800 | } | |
801 | } | |
802 | ||
803 | /* fabricate port_map from cap.nr_ports */ | |
804 | if (!port_map) { | |
17199b18 | 805 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
806 | dev_printk(KERN_WARNING, &pdev->dev, |
807 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
808 | ||
809 | /* write the fixed up value to the PI register */ | |
810 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
811 | } |
812 | ||
d447df14 TH |
813 | /* record values to use during operation */ |
814 | hpriv->cap = cap; | |
815 | hpriv->port_map = port_map; | |
816 | } | |
817 | ||
818 | /** | |
819 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 820 | * @host: target ATA host |
d447df14 TH |
821 | * |
822 | * Restore initial config stored by ahci_save_initial_config(). | |
823 | * | |
824 | * LOCKING: | |
825 | * None. | |
826 | */ | |
4447d351 | 827 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 828 | { |
4447d351 TH |
829 | struct ahci_host_priv *hpriv = host->private_data; |
830 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
831 | ||
d447df14 TH |
832 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
833 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
834 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
835 | } | |
836 | ||
203ef6c4 | 837 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 838 | { |
203ef6c4 TH |
839 | static const int offset[] = { |
840 | [SCR_STATUS] = PORT_SCR_STAT, | |
841 | [SCR_CONTROL] = PORT_SCR_CTL, | |
842 | [SCR_ERROR] = PORT_SCR_ERR, | |
843 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
844 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
845 | }; | |
846 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 847 | |
203ef6c4 TH |
848 | if (sc_reg < ARRAY_SIZE(offset) && |
849 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
850 | return offset[sc_reg]; | |
da3dbb17 | 851 | return 0; |
1da177e4 LT |
852 | } |
853 | ||
82ef04fb | 854 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 | 855 | { |
82ef04fb TH |
856 | void __iomem *port_mmio = ahci_port_base(link->ap); |
857 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
203ef6c4 TH |
858 | |
859 | if (offset) { | |
860 | *val = readl(port_mmio + offset); | |
861 | return 0; | |
1da177e4 | 862 | } |
203ef6c4 TH |
863 | return -EINVAL; |
864 | } | |
1da177e4 | 865 | |
82ef04fb | 866 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
203ef6c4 | 867 | { |
82ef04fb TH |
868 | void __iomem *port_mmio = ahci_port_base(link->ap); |
869 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
203ef6c4 TH |
870 | |
871 | if (offset) { | |
872 | writel(val, port_mmio + offset); | |
873 | return 0; | |
874 | } | |
875 | return -EINVAL; | |
1da177e4 LT |
876 | } |
877 | ||
4447d351 | 878 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 879 | { |
4447d351 | 880 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
881 | u32 tmp; |
882 | ||
d8fcd116 | 883 | /* start DMA */ |
9f592056 | 884 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
885 | tmp |= PORT_CMD_START; |
886 | writel(tmp, port_mmio + PORT_CMD); | |
887 | readl(port_mmio + PORT_CMD); /* flush */ | |
888 | } | |
889 | ||
4447d351 | 890 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 891 | { |
4447d351 | 892 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
893 | u32 tmp; |
894 | ||
895 | tmp = readl(port_mmio + PORT_CMD); | |
896 | ||
d8fcd116 | 897 | /* check if the HBA is idle */ |
254950cd TH |
898 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
899 | return 0; | |
900 | ||
d8fcd116 | 901 | /* setting HBA to idle */ |
254950cd TH |
902 | tmp &= ~PORT_CMD_START; |
903 | writel(tmp, port_mmio + PORT_CMD); | |
904 | ||
d8fcd116 | 905 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 906 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 907 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 908 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
909 | return -EIO; |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
4447d351 | 914 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 915 | { |
4447d351 TH |
916 | void __iomem *port_mmio = ahci_port_base(ap); |
917 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
918 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
919 | u32 tmp; |
920 | ||
921 | /* set FIS registers */ | |
4447d351 TH |
922 | if (hpriv->cap & HOST_CAP_64) |
923 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
924 | port_mmio + PORT_LST_ADDR_HI); | |
925 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 926 | |
4447d351 TH |
927 | if (hpriv->cap & HOST_CAP_64) |
928 | writel((pp->rx_fis_dma >> 16) >> 16, | |
929 | port_mmio + PORT_FIS_ADDR_HI); | |
930 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
931 | |
932 | /* enable FIS reception */ | |
933 | tmp = readl(port_mmio + PORT_CMD); | |
934 | tmp |= PORT_CMD_FIS_RX; | |
935 | writel(tmp, port_mmio + PORT_CMD); | |
936 | ||
937 | /* flush */ | |
938 | readl(port_mmio + PORT_CMD); | |
939 | } | |
940 | ||
4447d351 | 941 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 942 | { |
4447d351 | 943 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
944 | u32 tmp; |
945 | ||
946 | /* disable FIS reception */ | |
947 | tmp = readl(port_mmio + PORT_CMD); | |
948 | tmp &= ~PORT_CMD_FIS_RX; | |
949 | writel(tmp, port_mmio + PORT_CMD); | |
950 | ||
951 | /* wait for completion, spec says 500ms, give it 1000 */ | |
952 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
953 | PORT_CMD_FIS_ON, 10, 1000); | |
954 | if (tmp & PORT_CMD_FIS_ON) | |
955 | return -EBUSY; | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
4447d351 | 960 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 961 | { |
4447d351 TH |
962 | struct ahci_host_priv *hpriv = ap->host->private_data; |
963 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
964 | u32 cmd; |
965 | ||
966 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
967 | ||
968 | /* spin up device */ | |
4447d351 | 969 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
970 | cmd |= PORT_CMD_SPIN_UP; |
971 | writel(cmd, port_mmio + PORT_CMD); | |
972 | } | |
973 | ||
974 | /* wake up link */ | |
975 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
976 | } | |
977 | ||
31556594 KCA |
978 | static void ahci_disable_alpm(struct ata_port *ap) |
979 | { | |
980 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
981 | void __iomem *port_mmio = ahci_port_base(ap); | |
982 | u32 cmd; | |
983 | struct ahci_port_priv *pp = ap->private_data; | |
984 | ||
985 | /* IPM bits should be disabled by libata-core */ | |
986 | /* get the existing command bits */ | |
987 | cmd = readl(port_mmio + PORT_CMD); | |
988 | ||
989 | /* disable ALPM and ASP */ | |
990 | cmd &= ~PORT_CMD_ASP; | |
991 | cmd &= ~PORT_CMD_ALPE; | |
992 | ||
993 | /* force the interface back to active */ | |
994 | cmd |= PORT_CMD_ICC_ACTIVE; | |
995 | ||
996 | /* write out new cmd value */ | |
997 | writel(cmd, port_mmio + PORT_CMD); | |
998 | cmd = readl(port_mmio + PORT_CMD); | |
999 | ||
1000 | /* wait 10ms to be sure we've come out of any low power state */ | |
1001 | msleep(10); | |
1002 | ||
1003 | /* clear out any PhyRdy stuff from interrupt status */ | |
1004 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
1005 | ||
1006 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
82ef04fb | 1007 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
31556594 KCA |
1008 | |
1009 | /* | |
1010 | * Clear flag to indicate that we should ignore all PhyRdy | |
1011 | * state changes | |
1012 | */ | |
1013 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
1014 | ||
1015 | /* | |
1016 | * Enable interrupts on Phy Ready. | |
1017 | */ | |
1018 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
1019 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
1020 | ||
1021 | /* | |
1022 | * don't change the link pm policy - we can be called | |
1023 | * just to turn of link pm temporarily | |
1024 | */ | |
1025 | } | |
1026 | ||
1027 | static int ahci_enable_alpm(struct ata_port *ap, | |
1028 | enum link_pm policy) | |
1029 | { | |
1030 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1031 | void __iomem *port_mmio = ahci_port_base(ap); | |
1032 | u32 cmd; | |
1033 | struct ahci_port_priv *pp = ap->private_data; | |
1034 | u32 asp; | |
1035 | ||
1036 | /* Make sure the host is capable of link power management */ | |
1037 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
1038 | return -EINVAL; | |
1039 | ||
1040 | switch (policy) { | |
1041 | case MAX_PERFORMANCE: | |
1042 | case NOT_AVAILABLE: | |
1043 | /* | |
1044 | * if we came here with NOT_AVAILABLE, | |
1045 | * it just means this is the first time we | |
1046 | * have tried to enable - default to max performance, | |
1047 | * and let the user go to lower power modes on request. | |
1048 | */ | |
1049 | ahci_disable_alpm(ap); | |
1050 | return 0; | |
1051 | case MIN_POWER: | |
1052 | /* configure HBA to enter SLUMBER */ | |
1053 | asp = PORT_CMD_ASP; | |
1054 | break; | |
1055 | case MEDIUM_POWER: | |
1056 | /* configure HBA to enter PARTIAL */ | |
1057 | asp = 0; | |
1058 | break; | |
1059 | default: | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | ||
1063 | /* | |
1064 | * Disable interrupts on Phy Ready. This keeps us from | |
1065 | * getting woken up due to spurious phy ready interrupts | |
1066 | * TBD - Hot plug should be done via polling now, is | |
1067 | * that even supported? | |
1068 | */ | |
1069 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
1070 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
1071 | ||
1072 | /* | |
1073 | * Set a flag to indicate that we should ignore all PhyRdy | |
1074 | * state changes since these can happen now whenever we | |
1075 | * change link state | |
1076 | */ | |
1077 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
1078 | ||
1079 | /* get the existing command bits */ | |
1080 | cmd = readl(port_mmio + PORT_CMD); | |
1081 | ||
1082 | /* | |
1083 | * Set ASP based on Policy | |
1084 | */ | |
1085 | cmd |= asp; | |
1086 | ||
1087 | /* | |
1088 | * Setting this bit will instruct the HBA to aggressively | |
1089 | * enter a lower power link state when it's appropriate and | |
1090 | * based on the value set above for ASP | |
1091 | */ | |
1092 | cmd |= PORT_CMD_ALPE; | |
1093 | ||
1094 | /* write out new cmd value */ | |
1095 | writel(cmd, port_mmio + PORT_CMD); | |
1096 | cmd = readl(port_mmio + PORT_CMD); | |
1097 | ||
1098 | /* IPM bits should be set by libata-core */ | |
1099 | return 0; | |
1100 | } | |
1101 | ||
438ac6d5 | 1102 | #ifdef CONFIG_PM |
4447d351 | 1103 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 1104 | { |
4447d351 TH |
1105 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1106 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
1107 | u32 cmd, scontrol; |
1108 | ||
4447d351 | 1109 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 1110 | return; |
0be0aa98 | 1111 | |
07c53dac TH |
1112 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
1113 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
1114 | scontrol &= ~0xf; | |
1115 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 1116 | |
07c53dac TH |
1117 | /* then set PxCMD.SUD to 0 */ |
1118 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1119 | cmd &= ~PORT_CMD_SPIN_UP; | |
1120 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 1121 | } |
438ac6d5 | 1122 | #endif |
0be0aa98 | 1123 | |
df69c9c5 | 1124 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 1125 | { |
18f7ba4c KCA |
1126 | struct ahci_port_priv *pp = ap->private_data; |
1127 | struct ata_link *link; | |
1128 | struct ahci_em_priv *emp; | |
4c1e9aa4 DM |
1129 | ssize_t rc; |
1130 | int i; | |
18f7ba4c | 1131 | |
0be0aa98 | 1132 | /* enable FIS reception */ |
4447d351 | 1133 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
1134 | |
1135 | /* enable DMA */ | |
4447d351 | 1136 | ahci_start_engine(ap); |
18f7ba4c KCA |
1137 | |
1138 | /* turn on LEDs */ | |
1139 | if (ap->flags & ATA_FLAG_EM) { | |
1eca4365 | 1140 | ata_for_each_link(link, ap, EDGE) { |
18f7ba4c | 1141 | emp = &pp->em_priv[link->pmp]; |
4c1e9aa4 DM |
1142 | |
1143 | /* EM Transmit bit maybe busy during init */ | |
1144 | for (i = 0; i < MAX_RETRY; i++) { | |
1145 | rc = ahci_transmit_led_message(ap, | |
1146 | emp->led_state, | |
1147 | 4); | |
1148 | if (rc == -EBUSY) | |
1149 | udelay(100); | |
1150 | else | |
1151 | break; | |
1152 | } | |
18f7ba4c KCA |
1153 | } |
1154 | } | |
1155 | ||
1156 | if (ap->flags & ATA_FLAG_SW_ACTIVITY) | |
1eca4365 | 1157 | ata_for_each_link(link, ap, EDGE) |
18f7ba4c KCA |
1158 | ahci_init_sw_activity(link); |
1159 | ||
0be0aa98 TH |
1160 | } |
1161 | ||
4447d351 | 1162 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
1163 | { |
1164 | int rc; | |
1165 | ||
1166 | /* disable DMA */ | |
4447d351 | 1167 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1168 | if (rc) { |
1169 | *emsg = "failed to stop engine"; | |
1170 | return rc; | |
1171 | } | |
1172 | ||
1173 | /* disable FIS reception */ | |
4447d351 | 1174 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1175 | if (rc) { |
1176 | *emsg = "failed stop FIS RX"; | |
1177 | return rc; | |
1178 | } | |
1179 | ||
0be0aa98 TH |
1180 | return 0; |
1181 | } | |
1182 | ||
4447d351 | 1183 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1184 | { |
4447d351 | 1185 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1186 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1187 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1188 | u32 tmp; |
d91542c1 | 1189 | |
3cc3eb11 JG |
1190 | /* we must be in AHCI mode, before using anything |
1191 | * AHCI-specific, such as HOST_RESET. | |
1192 | */ | |
b710a1f4 | 1193 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1194 | |
1195 | /* global controller reset */ | |
a22e6444 TH |
1196 | if (!ahci_skip_host_reset) { |
1197 | tmp = readl(mmio + HOST_CTL); | |
1198 | if ((tmp & HOST_RESET) == 0) { | |
1199 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1200 | readl(mmio + HOST_CTL); /* flush */ | |
1201 | } | |
d91542c1 | 1202 | |
24920c8a ZR |
1203 | /* |
1204 | * to perform host reset, OS should set HOST_RESET | |
1205 | * and poll until this bit is read to be "0". | |
1206 | * reset must complete within 1 second, or | |
a22e6444 TH |
1207 | * the hardware should be considered fried. |
1208 | */ | |
24920c8a ZR |
1209 | tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, |
1210 | HOST_RESET, 10, 1000); | |
d91542c1 | 1211 | |
a22e6444 TH |
1212 | if (tmp & HOST_RESET) { |
1213 | dev_printk(KERN_ERR, host->dev, | |
1214 | "controller reset failed (0x%x)\n", tmp); | |
1215 | return -EIO; | |
1216 | } | |
d91542c1 | 1217 | |
a22e6444 TH |
1218 | /* turn on AHCI mode */ |
1219 | ahci_enable_ahci(mmio); | |
98fa4b60 | 1220 | |
a22e6444 TH |
1221 | /* Some registers might be cleared on reset. Restore |
1222 | * initial values. | |
1223 | */ | |
1224 | ahci_restore_initial_config(host); | |
1225 | } else | |
1226 | dev_printk(KERN_INFO, host->dev, | |
1227 | "skipping global host reset\n"); | |
d91542c1 TH |
1228 | |
1229 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1230 | u16 tmp16; | |
1231 | ||
1232 | /* configure PCS */ | |
1233 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1234 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1235 | tmp16 |= hpriv->port_map; | |
1236 | pci_write_config_word(pdev, 0x92, tmp16); | |
1237 | } | |
d91542c1 TH |
1238 | } |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
18f7ba4c KCA |
1243 | static void ahci_sw_activity(struct ata_link *link) |
1244 | { | |
1245 | struct ata_port *ap = link->ap; | |
1246 | struct ahci_port_priv *pp = ap->private_data; | |
1247 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1248 | ||
1249 | if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) | |
1250 | return; | |
1251 | ||
1252 | emp->activity++; | |
1253 | if (!timer_pending(&emp->timer)) | |
1254 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); | |
1255 | } | |
1256 | ||
1257 | static void ahci_sw_activity_blink(unsigned long arg) | |
1258 | { | |
1259 | struct ata_link *link = (struct ata_link *)arg; | |
1260 | struct ata_port *ap = link->ap; | |
1261 | struct ahci_port_priv *pp = ap->private_data; | |
1262 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1263 | unsigned long led_message = emp->led_state; | |
1264 | u32 activity_led_state; | |
eb40963c | 1265 | unsigned long flags; |
18f7ba4c | 1266 | |
87943acf | 1267 | led_message &= EM_MSG_LED_VALUE; |
18f7ba4c KCA |
1268 | led_message |= ap->port_no | (link->pmp << 8); |
1269 | ||
1270 | /* check to see if we've had activity. If so, | |
1271 | * toggle state of LED and reset timer. If not, | |
1272 | * turn LED to desired idle state. | |
1273 | */ | |
eb40963c | 1274 | spin_lock_irqsave(ap->lock, flags); |
18f7ba4c KCA |
1275 | if (emp->saved_activity != emp->activity) { |
1276 | emp->saved_activity = emp->activity; | |
1277 | /* get the current LED state */ | |
87943acf | 1278 | activity_led_state = led_message & EM_MSG_LED_VALUE_ON; |
18f7ba4c KCA |
1279 | |
1280 | if (activity_led_state) | |
1281 | activity_led_state = 0; | |
1282 | else | |
1283 | activity_led_state = 1; | |
1284 | ||
1285 | /* clear old state */ | |
87943acf | 1286 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1287 | |
1288 | /* toggle state */ | |
1289 | led_message |= (activity_led_state << 16); | |
1290 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); | |
1291 | } else { | |
1292 | /* switch to idle */ | |
87943acf | 1293 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1294 | if (emp->blink_policy == BLINK_OFF) |
1295 | led_message |= (1 << 16); | |
1296 | } | |
eb40963c | 1297 | spin_unlock_irqrestore(ap->lock, flags); |
18f7ba4c KCA |
1298 | ahci_transmit_led_message(ap, led_message, 4); |
1299 | } | |
1300 | ||
1301 | static void ahci_init_sw_activity(struct ata_link *link) | |
1302 | { | |
1303 | struct ata_port *ap = link->ap; | |
1304 | struct ahci_port_priv *pp = ap->private_data; | |
1305 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1306 | ||
1307 | /* init activity stats, setup timer */ | |
1308 | emp->saved_activity = emp->activity = 0; | |
1309 | setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); | |
1310 | ||
1311 | /* check our blink policy and set flag for link if it's enabled */ | |
1312 | if (emp->blink_policy) | |
1313 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1314 | } | |
1315 | ||
1316 | static int ahci_reset_em(struct ata_host *host) | |
1317 | { | |
1318 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1319 | u32 em_ctl; | |
1320 | ||
1321 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1322 | if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
1330 | ssize_t size) | |
1331 | { | |
1332 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1333 | struct ahci_port_priv *pp = ap->private_data; | |
1334 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | |
1335 | u32 em_ctl; | |
1336 | u32 message[] = {0, 0}; | |
93082f0b | 1337 | unsigned long flags; |
18f7ba4c KCA |
1338 | int pmp; |
1339 | struct ahci_em_priv *emp; | |
1340 | ||
1341 | /* get the slot number from the message */ | |
87943acf | 1342 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
18f7ba4c KCA |
1343 | if (pmp < MAX_SLOTS) |
1344 | emp = &pp->em_priv[pmp]; | |
1345 | else | |
1346 | return -EINVAL; | |
1347 | ||
1348 | spin_lock_irqsave(ap->lock, flags); | |
1349 | ||
1350 | /* | |
1351 | * if we are still busy transmitting a previous message, | |
1352 | * do not allow | |
1353 | */ | |
1354 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1355 | if (em_ctl & EM_CTL_TM) { | |
1356 | spin_unlock_irqrestore(ap->lock, flags); | |
4c1e9aa4 | 1357 | return -EBUSY; |
18f7ba4c KCA |
1358 | } |
1359 | ||
1360 | /* | |
1361 | * create message header - this is all zero except for | |
1362 | * the message size, which is 4 bytes. | |
1363 | */ | |
1364 | message[0] |= (4 << 8); | |
1365 | ||
1366 | /* ignore 0:4 of byte zero, fill in port info yourself */ | |
87943acf | 1367 | message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); |
18f7ba4c KCA |
1368 | |
1369 | /* write message to EM_LOC */ | |
1370 | writel(message[0], mmio + hpriv->em_loc); | |
1371 | writel(message[1], mmio + hpriv->em_loc+4); | |
1372 | ||
1373 | /* save off new led state for port/slot */ | |
208f2a88 | 1374 | emp->led_state = state; |
18f7ba4c KCA |
1375 | |
1376 | /* | |
1377 | * tell hardware to transmit the message | |
1378 | */ | |
1379 | writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); | |
1380 | ||
1381 | spin_unlock_irqrestore(ap->lock, flags); | |
1382 | return size; | |
1383 | } | |
1384 | ||
1385 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf) | |
1386 | { | |
1387 | struct ahci_port_priv *pp = ap->private_data; | |
1388 | struct ata_link *link; | |
1389 | struct ahci_em_priv *emp; | |
1390 | int rc = 0; | |
1391 | ||
1eca4365 | 1392 | ata_for_each_link(link, ap, EDGE) { |
18f7ba4c KCA |
1393 | emp = &pp->em_priv[link->pmp]; |
1394 | rc += sprintf(buf, "%lx\n", emp->led_state); | |
1395 | } | |
1396 | return rc; | |
1397 | } | |
1398 | ||
1399 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
1400 | size_t size) | |
1401 | { | |
1402 | int state; | |
1403 | int pmp; | |
1404 | struct ahci_port_priv *pp = ap->private_data; | |
1405 | struct ahci_em_priv *emp; | |
1406 | ||
1407 | state = simple_strtoul(buf, NULL, 0); | |
1408 | ||
1409 | /* get the slot number from the message */ | |
87943acf | 1410 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
18f7ba4c KCA |
1411 | if (pmp < MAX_SLOTS) |
1412 | emp = &pp->em_priv[pmp]; | |
1413 | else | |
1414 | return -EINVAL; | |
1415 | ||
1416 | /* mask off the activity bits if we are in sw_activity | |
1417 | * mode, user should turn off sw_activity before setting | |
1418 | * activity led through em_message | |
1419 | */ | |
1420 | if (emp->blink_policy) | |
87943acf | 1421 | state &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1422 | |
1423 | return ahci_transmit_led_message(ap, state, size); | |
1424 | } | |
1425 | ||
1426 | static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) | |
1427 | { | |
1428 | struct ata_link *link = dev->link; | |
1429 | struct ata_port *ap = link->ap; | |
1430 | struct ahci_port_priv *pp = ap->private_data; | |
1431 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1432 | u32 port_led_state = emp->led_state; | |
1433 | ||
1434 | /* save the desired Activity LED behavior */ | |
1435 | if (val == OFF) { | |
1436 | /* clear LFLAG */ | |
1437 | link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); | |
1438 | ||
1439 | /* set the LED to OFF */ | |
87943acf | 1440 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
18f7ba4c KCA |
1441 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
1442 | ahci_transmit_led_message(ap, port_led_state, 4); | |
1443 | } else { | |
1444 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1445 | if (val == BLINK_OFF) { | |
1446 | /* set LED to ON for idle */ | |
87943acf | 1447 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
18f7ba4c | 1448 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
87943acf | 1449 | port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ |
18f7ba4c KCA |
1450 | ahci_transmit_led_message(ap, port_led_state, 4); |
1451 | } | |
1452 | } | |
1453 | emp->blink_policy = val; | |
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) | |
1458 | { | |
1459 | struct ata_link *link = dev->link; | |
1460 | struct ata_port *ap = link->ap; | |
1461 | struct ahci_port_priv *pp = ap->private_data; | |
1462 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1463 | ||
1464 | /* display the saved value of activity behavior for this | |
1465 | * disk. | |
1466 | */ | |
1467 | return sprintf(buf, "%d\n", emp->blink_policy); | |
1468 | } | |
1469 | ||
2bcd866b JG |
1470 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1471 | int port_no, void __iomem *mmio, | |
1472 | void __iomem *port_mmio) | |
1473 | { | |
1474 | const char *emsg = NULL; | |
1475 | int rc; | |
1476 | u32 tmp; | |
1477 | ||
1478 | /* make sure port is not active */ | |
1479 | rc = ahci_deinit_port(ap, &emsg); | |
1480 | if (rc) | |
1481 | dev_printk(KERN_WARNING, &pdev->dev, | |
1482 | "%s (%d)\n", emsg, rc); | |
1483 | ||
1484 | /* clear SError */ | |
1485 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1486 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1487 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1488 | ||
1489 | /* clear port IRQ */ | |
1490 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1491 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1492 | if (tmp) | |
1493 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1494 | ||
1495 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1496 | } | |
1497 | ||
4447d351 | 1498 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1499 | { |
417a1a6d | 1500 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1501 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1502 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1503 | int i; |
cd70c266 | 1504 | void __iomem *port_mmio; |
d91542c1 | 1505 | u32 tmp; |
c40e7cb8 | 1506 | int mv; |
d91542c1 | 1507 | |
417a1a6d | 1508 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
1509 | if (pdev->device == 0x6121) |
1510 | mv = 2; | |
1511 | else | |
1512 | mv = 4; | |
1513 | port_mmio = __ahci_port_base(host, mv); | |
cd70c266 JG |
1514 | |
1515 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1516 | ||
1517 | /* clear port IRQ */ | |
1518 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1519 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1520 | if (tmp) | |
1521 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1522 | } | |
1523 | ||
4447d351 TH |
1524 | for (i = 0; i < host->n_ports; i++) { |
1525 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1526 | |
cd70c266 | 1527 | port_mmio = ahci_port_base(ap); |
4447d351 | 1528 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1529 | continue; |
d91542c1 | 1530 | |
2bcd866b | 1531 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1532 | } |
1533 | ||
1534 | tmp = readl(mmio + HOST_CTL); | |
1535 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1536 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1537 | tmp = readl(mmio + HOST_CTL); | |
1538 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1539 | } | |
1540 | ||
a878539e JG |
1541 | static void ahci_dev_config(struct ata_device *dev) |
1542 | { | |
1543 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1544 | ||
4cde32fc | 1545 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
a878539e | 1546 | dev->max_sectors = 255; |
4cde32fc JG |
1547 | ata_dev_printk(dev, KERN_INFO, |
1548 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
1549 | } | |
a878539e JG |
1550 | } |
1551 | ||
422b7595 | 1552 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1553 | { |
4447d351 | 1554 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1555 | struct ata_taskfile tf; |
422b7595 TH |
1556 | u32 tmp; |
1557 | ||
1558 | tmp = readl(port_mmio + PORT_SIG); | |
1559 | tf.lbah = (tmp >> 24) & 0xff; | |
1560 | tf.lbam = (tmp >> 16) & 0xff; | |
1561 | tf.lbal = (tmp >> 8) & 0xff; | |
1562 | tf.nsect = (tmp) & 0xff; | |
1563 | ||
1564 | return ata_dev_classify(&tf); | |
1565 | } | |
1566 | ||
12fad3f9 TH |
1567 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1568 | u32 opts) | |
cc9278ed | 1569 | { |
12fad3f9 TH |
1570 | dma_addr_t cmd_tbl_dma; |
1571 | ||
1572 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1573 | ||
1574 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1575 | pp->cmd_slot[tag].status = 0; | |
1576 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1577 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1578 | } |
1579 | ||
d2e75dff | 1580 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1581 | { |
350756f6 | 1582 | void __iomem *port_mmio = ahci_port_base(ap); |
cca3974e | 1583 | struct ahci_host_priv *hpriv = ap->host->private_data; |
520d06f9 | 1584 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
bf2af2a2 | 1585 | u32 tmp; |
d2e75dff | 1586 | int busy, rc; |
bf2af2a2 | 1587 | |
d2e75dff | 1588 | /* do we need to kick the port? */ |
520d06f9 | 1589 | busy = status & (ATA_BUSY | ATA_DRQ); |
d2e75dff TH |
1590 | if (!busy && !force_restart) |
1591 | return 0; | |
1592 | ||
1593 | /* stop engine */ | |
1594 | rc = ahci_stop_engine(ap); | |
1595 | if (rc) | |
1596 | goto out_restart; | |
1597 | ||
1598 | /* need to do CLO? */ | |
1599 | if (!busy) { | |
1600 | rc = 0; | |
1601 | goto out_restart; | |
1602 | } | |
1603 | ||
1604 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1605 | rc = -EOPNOTSUPP; | |
1606 | goto out_restart; | |
1607 | } | |
bf2af2a2 | 1608 | |
d2e75dff | 1609 | /* perform CLO */ |
bf2af2a2 BJ |
1610 | tmp = readl(port_mmio + PORT_CMD); |
1611 | tmp |= PORT_CMD_CLO; | |
1612 | writel(tmp, port_mmio + PORT_CMD); | |
1613 | ||
d2e75dff | 1614 | rc = 0; |
bf2af2a2 BJ |
1615 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1616 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1617 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1618 | rc = -EIO; |
bf2af2a2 | 1619 | |
d2e75dff TH |
1620 | /* restart engine */ |
1621 | out_restart: | |
1622 | ahci_start_engine(ap); | |
1623 | return rc; | |
bf2af2a2 BJ |
1624 | } |
1625 | ||
91c4a2e0 TH |
1626 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1627 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1628 | unsigned long timeout_msec) | |
bf2af2a2 | 1629 | { |
91c4a2e0 | 1630 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1631 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1632 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1633 | u8 *fis = pp->cmd_tbl; |
1634 | u32 tmp; | |
1635 | ||
1636 | /* prep the command */ | |
1637 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1638 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1639 | ||
1640 | /* issue & wait */ | |
1641 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1642 | ||
1643 | if (timeout_msec) { | |
1644 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1645 | 1, timeout_msec); | |
1646 | if (tmp & 0x1) { | |
1647 | ahci_kick_engine(ap, 1); | |
1648 | return -EBUSY; | |
1649 | } | |
1650 | } else | |
1651 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
bd17243a SH |
1656 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
1657 | int pmp, unsigned long deadline, | |
1658 | int (*check_ready)(struct ata_link *link)) | |
91c4a2e0 | 1659 | { |
cc0680a5 | 1660 | struct ata_port *ap = link->ap; |
4658f79b | 1661 | const char *reason = NULL; |
2cbb79eb | 1662 | unsigned long now, msecs; |
4658f79b | 1663 | struct ata_taskfile tf; |
4658f79b TH |
1664 | int rc; |
1665 | ||
1666 | DPRINTK("ENTER\n"); | |
1667 | ||
1668 | /* prepare for SRST (AHCI-1.1 10.4.1) */ | |
d2e75dff | 1669 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1670 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1671 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1672 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1673 | |
cc0680a5 | 1674 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1675 | |
1676 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1677 | msecs = 0; |
1678 | now = jiffies; | |
1679 | if (time_after(now, deadline)) | |
1680 | msecs = jiffies_to_msecs(deadline - now); | |
1681 | ||
4658f79b | 1682 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1683 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1684 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1685 | rc = -EIO; |
1686 | reason = "1st FIS failed"; | |
1687 | goto fail; | |
1688 | } | |
1689 | ||
1690 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1691 | msleep(1); | |
1692 | ||
1693 | /* issue the second D2H Register FIS */ | |
4658f79b | 1694 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1695 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1696 | |
705e76be | 1697 | /* wait for link to become ready */ |
bd17243a | 1698 | rc = ata_wait_after_reset(link, deadline, check_ready); |
9b89391c TH |
1699 | /* link occupied, -ENODEV too is an error */ |
1700 | if (rc) { | |
1701 | reason = "device not ready"; | |
1702 | goto fail; | |
4658f79b | 1703 | } |
9b89391c | 1704 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1705 | |
1706 | DPRINTK("EXIT, class=%u\n", *class); | |
1707 | return 0; | |
1708 | ||
4658f79b | 1709 | fail: |
cc0680a5 | 1710 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1711 | return rc; |
1712 | } | |
1713 | ||
bd17243a SH |
1714 | static int ahci_check_ready(struct ata_link *link) |
1715 | { | |
1716 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1717 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1718 | ||
1719 | return ata_check_ready(status); | |
1720 | } | |
1721 | ||
1722 | static int ahci_softreset(struct ata_link *link, unsigned int *class, | |
1723 | unsigned long deadline) | |
1724 | { | |
1725 | int pmp = sata_srst_pmp(link); | |
1726 | ||
1727 | DPRINTK("ENTER\n"); | |
1728 | ||
1729 | return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); | |
1730 | } | |
1731 | ||
1732 | static int ahci_sb600_check_ready(struct ata_link *link) | |
1733 | { | |
1734 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1735 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1736 | u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); | |
1737 | ||
1738 | /* | |
1739 | * There is no need to check TFDATA if BAD PMP is found due to HW bug, | |
1740 | * which can save timeout delay. | |
1741 | */ | |
1742 | if (irq_status & PORT_IRQ_BAD_PMP) | |
1743 | return -EIO; | |
1744 | ||
1745 | return ata_check_ready(status); | |
1746 | } | |
1747 | ||
1748 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, | |
1749 | unsigned long deadline) | |
1750 | { | |
1751 | struct ata_port *ap = link->ap; | |
1752 | void __iomem *port_mmio = ahci_port_base(ap); | |
1753 | int pmp = sata_srst_pmp(link); | |
1754 | int rc; | |
1755 | u32 irq_sts; | |
1756 | ||
1757 | DPRINTK("ENTER\n"); | |
1758 | ||
1759 | rc = ahci_do_softreset(link, class, pmp, deadline, | |
1760 | ahci_sb600_check_ready); | |
1761 | ||
1762 | /* | |
1763 | * Soft reset fails on some ATI chips with IPMS set when PMP | |
1764 | * is enabled but SATA HDD/ODD is connected to SATA port, | |
1765 | * do soft reset again to port 0. | |
1766 | */ | |
1767 | if (rc == -EIO) { | |
1768 | irq_sts = readl(port_mmio + PORT_IRQ_STAT); | |
1769 | if (irq_sts & PORT_IRQ_BAD_PMP) { | |
1770 | ata_link_printk(link, KERN_WARNING, | |
1771 | "failed due to HW bug, retry pmp=0\n"); | |
1772 | rc = ahci_do_softreset(link, class, 0, deadline, | |
1773 | ahci_check_ready); | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | return rc; | |
1778 | } | |
1779 | ||
cc0680a5 | 1780 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1781 | unsigned long deadline) |
422b7595 | 1782 | { |
9dadd45b | 1783 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
cc0680a5 | 1784 | struct ata_port *ap = link->ap; |
4296971d TH |
1785 | struct ahci_port_priv *pp = ap->private_data; |
1786 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1787 | struct ata_taskfile tf; | |
9dadd45b | 1788 | bool online; |
4bd00f6a TH |
1789 | int rc; |
1790 | ||
1791 | DPRINTK("ENTER\n"); | |
1da177e4 | 1792 | |
4447d351 | 1793 | ahci_stop_engine(ap); |
4296971d TH |
1794 | |
1795 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1796 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1797 | tf.command = 0x80; |
9977126c | 1798 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1799 | |
9dadd45b TH |
1800 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1801 | ahci_check_ready); | |
4296971d | 1802 | |
4447d351 | 1803 | ahci_start_engine(ap); |
1da177e4 | 1804 | |
9dadd45b | 1805 | if (online) |
4bd00f6a | 1806 | *class = ahci_dev_classify(ap); |
1da177e4 | 1807 | |
4bd00f6a TH |
1808 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1809 | return rc; | |
1810 | } | |
1811 | ||
cc0680a5 | 1812 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1813 | unsigned long deadline) |
ad616ffb | 1814 | { |
cc0680a5 | 1815 | struct ata_port *ap = link->ap; |
9dadd45b | 1816 | bool online; |
ad616ffb TH |
1817 | int rc; |
1818 | ||
1819 | DPRINTK("ENTER\n"); | |
1820 | ||
4447d351 | 1821 | ahci_stop_engine(ap); |
ad616ffb | 1822 | |
cc0680a5 | 1823 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
9dadd45b | 1824 | deadline, &online, NULL); |
ad616ffb | 1825 | |
4447d351 | 1826 | ahci_start_engine(ap); |
ad616ffb TH |
1827 | |
1828 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1829 | ||
1830 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1831 | * request follow-up softreset. | |
1832 | */ | |
9dadd45b | 1833 | return online ? -EAGAIN : rc; |
ad616ffb TH |
1834 | } |
1835 | ||
edc93052 TH |
1836 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1837 | unsigned long deadline) | |
1838 | { | |
1839 | struct ata_port *ap = link->ap; | |
1840 | struct ahci_port_priv *pp = ap->private_data; | |
1841 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1842 | struct ata_taskfile tf; | |
9dadd45b | 1843 | bool online; |
edc93052 TH |
1844 | int rc; |
1845 | ||
1846 | ahci_stop_engine(ap); | |
1847 | ||
1848 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1849 | ata_tf_init(link->device, &tf); | |
1850 | tf.command = 0x80; | |
1851 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1852 | ||
1853 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
9dadd45b | 1854 | deadline, &online, NULL); |
edc93052 TH |
1855 | |
1856 | ahci_start_engine(ap); | |
1857 | ||
edc93052 TH |
1858 | /* The pseudo configuration device on SIMG4726 attached to |
1859 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1860 | * hardreset if no device is attached to the first downstream | |
1861 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1862 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1863 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1864 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1865 | * | |
1866 | * Wait for two seconds. Devices attached to downstream port | |
1867 | * which can't process the following IDENTIFY after this will | |
1868 | * have to be reset again. For most cases, this should | |
1869 | * suffice while making probing snappish enough. | |
1870 | */ | |
9dadd45b TH |
1871 | if (online) { |
1872 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
1873 | ahci_check_ready); | |
1874 | if (rc) | |
1875 | ahci_kick_engine(ap, 0); | |
1876 | } | |
9dadd45b | 1877 | return rc; |
edc93052 TH |
1878 | } |
1879 | ||
cc0680a5 | 1880 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1881 | { |
cc0680a5 | 1882 | struct ata_port *ap = link->ap; |
4447d351 | 1883 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1884 | u32 new_tmp, tmp; |
1885 | ||
203c75b8 | 1886 | ata_std_postreset(link, class); |
02eaa666 JG |
1887 | |
1888 | /* Make sure port's ATAPI bit is set appropriately */ | |
1889 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1890 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1891 | new_tmp |= PORT_CMD_ATAPI; |
1892 | else | |
1893 | new_tmp &= ~PORT_CMD_ATAPI; | |
1894 | if (new_tmp != tmp) { | |
1895 | writel(new_tmp, port_mmio + PORT_CMD); | |
1896 | readl(port_mmio + PORT_CMD); /* flush */ | |
1897 | } | |
1da177e4 LT |
1898 | } |
1899 | ||
12fad3f9 | 1900 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1901 | { |
cedc9a47 | 1902 | struct scatterlist *sg; |
ff2aeb1e TH |
1903 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
1904 | unsigned int si; | |
1da177e4 LT |
1905 | |
1906 | VPRINTK("ENTER\n"); | |
1907 | ||
1908 | /* | |
1909 | * Next, the S/G list. | |
1910 | */ | |
ff2aeb1e | 1911 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
1912 | dma_addr_t addr = sg_dma_address(sg); |
1913 | u32 sg_len = sg_dma_len(sg); | |
1914 | ||
ff2aeb1e TH |
1915 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
1916 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1917 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 1918 | } |
828d09de | 1919 | |
ff2aeb1e | 1920 | return si; |
1da177e4 LT |
1921 | } |
1922 | ||
1923 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1924 | { | |
a0ea7328 JG |
1925 | struct ata_port *ap = qc->ap; |
1926 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1927 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1928 | void *cmd_tbl; |
1da177e4 LT |
1929 | u32 opts; |
1930 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1931 | unsigned int n_elem; |
1da177e4 | 1932 | |
1da177e4 LT |
1933 | /* |
1934 | * Fill in command table information. First, the header, | |
1935 | * a SATA Register - Host to Device command FIS. | |
1936 | */ | |
12fad3f9 TH |
1937 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1938 | ||
7d50b60b | 1939 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1940 | if (is_atapi) { |
12fad3f9 TH |
1941 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1942 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1943 | } |
1da177e4 | 1944 | |
cc9278ed TH |
1945 | n_elem = 0; |
1946 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1947 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1948 | |
cc9278ed TH |
1949 | /* |
1950 | * Fill in command slot information. | |
1951 | */ | |
7d50b60b | 1952 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1953 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1954 | opts |= AHCI_CMD_WRITE; | |
1955 | if (is_atapi) | |
4b10e559 | 1956 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1957 | |
12fad3f9 | 1958 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1959 | } |
1960 | ||
78cd52d0 | 1961 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1962 | { |
417a1a6d | 1963 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1964 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1965 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1966 | struct ata_link *link = NULL; | |
1967 | struct ata_queued_cmd *active_qc; | |
1968 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1969 | u32 serror; |
1da177e4 | 1970 | |
7d50b60b | 1971 | /* determine active link */ |
1eca4365 | 1972 | ata_for_each_link(link, ap, EDGE) |
7d50b60b TH |
1973 | if (ata_link_active(link)) |
1974 | break; | |
1975 | if (!link) | |
1976 | link = &ap->link; | |
1977 | ||
1978 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1979 | active_ehi = &link->eh_info; | |
1980 | ||
1981 | /* record irq stat */ | |
1982 | ata_ehi_clear_desc(host_ehi); | |
1983 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1984 | |
78cd52d0 | 1985 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
82ef04fb TH |
1986 | ahci_scr_read(&ap->link, SCR_ERROR, &serror); |
1987 | ahci_scr_write(&ap->link, SCR_ERROR, serror); | |
7d50b60b | 1988 | host_ehi->serror |= serror; |
78cd52d0 | 1989 | |
41669553 | 1990 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1991 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1992 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1993 | ||
55a61604 | 1994 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1995 | /* If qc is active, charge it; otherwise, the active |
1996 | * link. There's no active qc on NCQ errors. It will | |
1997 | * be determined by EH by reading log page 10h. | |
1998 | */ | |
1999 | if (active_qc) | |
2000 | active_qc->err_mask |= AC_ERR_DEV; | |
2001 | else | |
2002 | active_ehi->err_mask |= AC_ERR_DEV; | |
2003 | ||
417a1a6d | 2004 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
2005 | host_ehi->serror &= ~SERR_INTERNAL; |
2006 | } | |
2007 | ||
2008 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
2009 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
2010 | ||
2011 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 2012 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b TH |
2013 | ata_ehi_push_desc(active_ehi, |
2014 | "unknown FIS %08x %08x %08x %08x" , | |
2015 | unk[0], unk[1], unk[2], unk[3]); | |
2016 | } | |
2017 | ||
071f44b1 | 2018 | if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { |
7d50b60b | 2019 | active_ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 2020 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b | 2021 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
55a61604 | 2022 | } |
78cd52d0 TH |
2023 | |
2024 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b | 2025 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
cf480626 | 2026 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 2027 | ata_ehi_push_desc(host_ehi, "host bus error"); |
1da177e4 LT |
2028 | } |
2029 | ||
78cd52d0 | 2030 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b | 2031 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
cf480626 | 2032 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 2033 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
78cd52d0 | 2034 | } |
1da177e4 | 2035 | |
78cd52d0 | 2036 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
2037 | ata_ehi_hotplugged(host_ehi); |
2038 | ata_ehi_push_desc(host_ehi, "%s", | |
2039 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
2040 | "connection status changed" : "PHY RDY changed"); |
2041 | } | |
2042 | ||
78cd52d0 | 2043 | /* okay, let's hand over to EH */ |
a72ec4ce | 2044 | |
78cd52d0 TH |
2045 | if (irq_stat & PORT_IRQ_FREEZE) |
2046 | ata_port_freeze(ap); | |
2047 | else | |
2048 | ata_port_abort(ap); | |
1da177e4 LT |
2049 | } |
2050 | ||
df69c9c5 | 2051 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 2052 | { |
350756f6 | 2053 | void __iomem *port_mmio = ahci_port_base(ap); |
9af5c9c9 | 2054 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 2055 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 2056 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 2057 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 2058 | u32 status, qc_active; |
459ad688 | 2059 | int rc; |
1da177e4 LT |
2060 | |
2061 | status = readl(port_mmio + PORT_IRQ_STAT); | |
2062 | writel(status, port_mmio + PORT_IRQ_STAT); | |
2063 | ||
b06ce3e5 TH |
2064 | /* ignore BAD_PMP while resetting */ |
2065 | if (unlikely(resetting)) | |
2066 | status &= ~PORT_IRQ_BAD_PMP; | |
2067 | ||
31556594 KCA |
2068 | /* If we are getting PhyRdy, this is |
2069 | * just a power state change, we should | |
2070 | * clear out this, plus the PhyRdy/Comm | |
2071 | * Wake bits from Serror | |
2072 | */ | |
2073 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
2074 | (status & PORT_IRQ_PHYRDY)) { | |
2075 | status &= ~PORT_IRQ_PHYRDY; | |
82ef04fb | 2076 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
31556594 KCA |
2077 | } |
2078 | ||
78cd52d0 TH |
2079 | if (unlikely(status & PORT_IRQ_ERROR)) { |
2080 | ahci_error_intr(ap, status); | |
2081 | return; | |
1da177e4 LT |
2082 | } |
2083 | ||
2f294968 | 2084 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
2085 | /* If SNotification is available, leave notification |
2086 | * handling to sata_async_notification(). If not, | |
2087 | * emulate it by snooping SDB FIS RX area. | |
2088 | * | |
2089 | * Snooping FIS RX area is probably cheaper than | |
2090 | * poking SNotification but some constrollers which | |
2091 | * implement SNotification, ICH9 for example, don't | |
2092 | * store AN SDB FIS into receive area. | |
2f294968 | 2093 | */ |
5f226c6b | 2094 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 2095 | sata_async_notification(ap); |
5f226c6b TH |
2096 | else { |
2097 | /* If the 'N' bit in word 0 of the FIS is set, | |
2098 | * we just received asynchronous notification. | |
2099 | * Tell libata about it. | |
2100 | */ | |
2101 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
2102 | u32 f0 = le32_to_cpu(f[0]); | |
2103 | ||
2104 | if (f0 & (1 << 15)) | |
2105 | sata_async_notification(ap); | |
2106 | } | |
2f294968 KCA |
2107 | } |
2108 | ||
7d50b60b TH |
2109 | /* pp->active_link is valid iff any command is in flight */ |
2110 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
2111 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
2112 | else | |
2113 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
2114 | ||
79f97dad | 2115 | rc = ata_qc_complete_multiple(ap, qc_active); |
b06ce3e5 | 2116 | |
459ad688 TH |
2117 | /* while resetting, invalid completions are expected */ |
2118 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 | 2119 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 2120 | ehi->action |= ATA_EH_RESET; |
12fad3f9 | 2121 | ata_port_freeze(ap); |
1da177e4 | 2122 | } |
1da177e4 LT |
2123 | } |
2124 | ||
7d12e780 | 2125 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 2126 | { |
cca3974e | 2127 | struct ata_host *host = dev_instance; |
1da177e4 LT |
2128 | struct ahci_host_priv *hpriv; |
2129 | unsigned int i, handled = 0; | |
ea6ba10b | 2130 | void __iomem *mmio; |
d28f87aa | 2131 | u32 irq_stat, irq_masked; |
1da177e4 LT |
2132 | |
2133 | VPRINTK("ENTER\n"); | |
2134 | ||
cca3974e | 2135 | hpriv = host->private_data; |
0d5ff566 | 2136 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
2137 | |
2138 | /* sigh. 0xffffffff is a valid return from h/w */ | |
2139 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1da177e4 LT |
2140 | if (!irq_stat) |
2141 | return IRQ_NONE; | |
2142 | ||
d28f87aa TH |
2143 | irq_masked = irq_stat & hpriv->port_map; |
2144 | ||
2dcb407e | 2145 | spin_lock(&host->lock); |
1da177e4 | 2146 | |
2dcb407e | 2147 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 2148 | struct ata_port *ap; |
1da177e4 | 2149 | |
d28f87aa | 2150 | if (!(irq_masked & (1 << i))) |
67846b30 JG |
2151 | continue; |
2152 | ||
cca3974e | 2153 | ap = host->ports[i]; |
67846b30 | 2154 | if (ap) { |
df69c9c5 | 2155 | ahci_port_intr(ap); |
67846b30 JG |
2156 | VPRINTK("port %u\n", i); |
2157 | } else { | |
2158 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 2159 | if (ata_ratelimit()) |
cca3974e | 2160 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 2161 | "interrupt on disabled port %u\n", i); |
1da177e4 | 2162 | } |
67846b30 | 2163 | |
1da177e4 LT |
2164 | handled = 1; |
2165 | } | |
2166 | ||
d28f87aa TH |
2167 | /* HOST_IRQ_STAT behaves as level triggered latch meaning that |
2168 | * it should be cleared after all the port events are cleared; | |
2169 | * otherwise, it will raise a spurious interrupt after each | |
2170 | * valid one. Please read section 10.6.2 of ahci 1.1 for more | |
2171 | * information. | |
2172 | * | |
2173 | * Also, use the unmasked value to clear interrupt as spurious | |
2174 | * pending event on a dummy port might cause screaming IRQ. | |
2175 | */ | |
ea0c62f7 TH |
2176 | writel(irq_stat, mmio + HOST_IRQ_STAT); |
2177 | ||
cca3974e | 2178 | spin_unlock(&host->lock); |
1da177e4 LT |
2179 | |
2180 | VPRINTK("EXIT\n"); | |
2181 | ||
2182 | return IRQ_RETVAL(handled); | |
2183 | } | |
2184 | ||
9a3d9eb0 | 2185 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
2186 | { |
2187 | struct ata_port *ap = qc->ap; | |
4447d351 | 2188 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
2189 | struct ahci_port_priv *pp = ap->private_data; |
2190 | ||
2191 | /* Keep track of the currently active link. It will be used | |
2192 | * in completion path to determine whether NCQ phase is in | |
2193 | * progress. | |
2194 | */ | |
2195 | pp->active_link = qc->dev->link; | |
1da177e4 | 2196 | |
12fad3f9 TH |
2197 | if (qc->tf.protocol == ATA_PROT_NCQ) |
2198 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
2199 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 | 2200 | |
18f7ba4c KCA |
2201 | ahci_sw_activity(qc->dev->link); |
2202 | ||
1da177e4 LT |
2203 | return 0; |
2204 | } | |
2205 | ||
4c9bf4e7 TH |
2206 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
2207 | { | |
2208 | struct ahci_port_priv *pp = qc->ap->private_data; | |
2209 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
2210 | ||
2211 | ata_tf_from_fis(d2h_fis, &qc->result_tf); | |
2212 | return true; | |
2213 | } | |
2214 | ||
78cd52d0 TH |
2215 | static void ahci_freeze(struct ata_port *ap) |
2216 | { | |
4447d351 | 2217 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
2218 | |
2219 | /* turn IRQ off */ | |
2220 | writel(0, port_mmio + PORT_IRQ_MASK); | |
2221 | } | |
2222 | ||
2223 | static void ahci_thaw(struct ata_port *ap) | |
2224 | { | |
0d5ff566 | 2225 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 2226 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 2227 | u32 tmp; |
a7384925 | 2228 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
2229 | |
2230 | /* clear IRQ */ | |
2231 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
2232 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 2233 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 2234 | |
1c954a4d TH |
2235 | /* turn IRQ back on */ |
2236 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
2237 | } |
2238 | ||
2239 | static void ahci_error_handler(struct ata_port *ap) | |
2240 | { | |
b51e9e5d | 2241 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 2242 | /* restart engine */ |
4447d351 TH |
2243 | ahci_stop_engine(ap); |
2244 | ahci_start_engine(ap); | |
78cd52d0 TH |
2245 | } |
2246 | ||
a1efdaba | 2247 | sata_pmp_error_handler(ap); |
edc93052 TH |
2248 | } |
2249 | ||
78cd52d0 TH |
2250 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
2251 | { | |
2252 | struct ata_port *ap = qc->ap; | |
2253 | ||
d2e75dff TH |
2254 | /* make DMA engine forget about the failed command */ |
2255 | if (qc->flags & ATA_QCFLAG_FAILED) | |
2256 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
2257 | } |
2258 | ||
7d50b60b TH |
2259 | static void ahci_pmp_attach(struct ata_port *ap) |
2260 | { | |
2261 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 2262 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
2263 | u32 cmd; |
2264 | ||
2265 | cmd = readl(port_mmio + PORT_CMD); | |
2266 | cmd |= PORT_CMD_PMP; | |
2267 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
2268 | |
2269 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
2270 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
2271 | } |
2272 | ||
2273 | static void ahci_pmp_detach(struct ata_port *ap) | |
2274 | { | |
2275 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 2276 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
2277 | u32 cmd; |
2278 | ||
2279 | cmd = readl(port_mmio + PORT_CMD); | |
2280 | cmd &= ~PORT_CMD_PMP; | |
2281 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
2282 | |
2283 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
2284 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
2285 | } |
2286 | ||
028a2596 AD |
2287 | static int ahci_port_resume(struct ata_port *ap) |
2288 | { | |
2289 | ahci_power_up(ap); | |
2290 | ahci_start_port(ap); | |
2291 | ||
071f44b1 | 2292 | if (sata_pmp_attached(ap)) |
7d50b60b TH |
2293 | ahci_pmp_attach(ap); |
2294 | else | |
2295 | ahci_pmp_detach(ap); | |
2296 | ||
028a2596 AD |
2297 | return 0; |
2298 | } | |
2299 | ||
438ac6d5 | 2300 | #ifdef CONFIG_PM |
c1332875 TH |
2301 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
2302 | { | |
c1332875 TH |
2303 | const char *emsg = NULL; |
2304 | int rc; | |
2305 | ||
4447d351 | 2306 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 2307 | if (rc == 0) |
4447d351 | 2308 | ahci_power_down(ap); |
8e16f941 | 2309 | else { |
c1332875 | 2310 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 2311 | ahci_start_port(ap); |
c1332875 TH |
2312 | } |
2313 | ||
2314 | return rc; | |
2315 | } | |
2316 | ||
c1332875 TH |
2317 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
2318 | { | |
cca3974e | 2319 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
9b10ae86 | 2320 | struct ahci_host_priv *hpriv = host->private_data; |
0d5ff566 | 2321 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
2322 | u32 ctl; |
2323 | ||
9b10ae86 TH |
2324 | if (mesg.event & PM_EVENT_SUSPEND && |
2325 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
2326 | dev_printk(KERN_ERR, &pdev->dev, | |
2327 | "BIOS update required for suspend/resume\n"); | |
2328 | return -EIO; | |
2329 | } | |
2330 | ||
3a2d5b70 | 2331 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
2332 | /* AHCI spec rev1.1 section 8.3.3: |
2333 | * Software must disable interrupts prior to requesting a | |
2334 | * transition of the HBA to D3 state. | |
2335 | */ | |
2336 | ctl = readl(mmio + HOST_CTL); | |
2337 | ctl &= ~HOST_IRQ_EN; | |
2338 | writel(ctl, mmio + HOST_CTL); | |
2339 | readl(mmio + HOST_CTL); /* flush */ | |
2340 | } | |
2341 | ||
2342 | return ata_pci_device_suspend(pdev, mesg); | |
2343 | } | |
2344 | ||
2345 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
2346 | { | |
cca3974e | 2347 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
2348 | int rc; |
2349 | ||
553c4aa6 TH |
2350 | rc = ata_pci_device_do_resume(pdev); |
2351 | if (rc) | |
2352 | return rc; | |
c1332875 TH |
2353 | |
2354 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 2355 | rc = ahci_reset_controller(host); |
c1332875 TH |
2356 | if (rc) |
2357 | return rc; | |
2358 | ||
4447d351 | 2359 | ahci_init_controller(host); |
c1332875 TH |
2360 | } |
2361 | ||
cca3974e | 2362 | ata_host_resume(host); |
c1332875 TH |
2363 | |
2364 | return 0; | |
2365 | } | |
438ac6d5 | 2366 | #endif |
c1332875 | 2367 | |
254950cd TH |
2368 | static int ahci_port_start(struct ata_port *ap) |
2369 | { | |
cca3974e | 2370 | struct device *dev = ap->host->dev; |
254950cd | 2371 | struct ahci_port_priv *pp; |
254950cd TH |
2372 | void *mem; |
2373 | dma_addr_t mem_dma; | |
254950cd | 2374 | |
24dc5f33 | 2375 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
2376 | if (!pp) |
2377 | return -ENOMEM; | |
254950cd | 2378 | |
24dc5f33 TH |
2379 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
2380 | GFP_KERNEL); | |
2381 | if (!mem) | |
254950cd | 2382 | return -ENOMEM; |
254950cd TH |
2383 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
2384 | ||
2385 | /* | |
2386 | * First item in chunk of DMA memory: 32-slot command table, | |
2387 | * 32 bytes each in size | |
2388 | */ | |
2389 | pp->cmd_slot = mem; | |
2390 | pp->cmd_slot_dma = mem_dma; | |
2391 | ||
2392 | mem += AHCI_CMD_SLOT_SZ; | |
2393 | mem_dma += AHCI_CMD_SLOT_SZ; | |
2394 | ||
2395 | /* | |
2396 | * Second item: Received-FIS area | |
2397 | */ | |
2398 | pp->rx_fis = mem; | |
2399 | pp->rx_fis_dma = mem_dma; | |
2400 | ||
2401 | mem += AHCI_RX_FIS_SZ; | |
2402 | mem_dma += AHCI_RX_FIS_SZ; | |
2403 | ||
2404 | /* | |
2405 | * Third item: data area for storing a single command | |
2406 | * and its scatter-gather table | |
2407 | */ | |
2408 | pp->cmd_tbl = mem; | |
2409 | pp->cmd_tbl_dma = mem_dma; | |
2410 | ||
a7384925 | 2411 | /* |
2dcb407e JG |
2412 | * Save off initial list of interrupts to be enabled. |
2413 | * This could be changed later | |
2414 | */ | |
a7384925 KCA |
2415 | pp->intr_mask = DEF_PORT_IRQ; |
2416 | ||
254950cd TH |
2417 | ap->private_data = pp; |
2418 | ||
df69c9c5 JG |
2419 | /* engage engines, captain */ |
2420 | return ahci_port_resume(ap); | |
254950cd TH |
2421 | } |
2422 | ||
2423 | static void ahci_port_stop(struct ata_port *ap) | |
2424 | { | |
0be0aa98 TH |
2425 | const char *emsg = NULL; |
2426 | int rc; | |
254950cd | 2427 | |
0be0aa98 | 2428 | /* de-initialize port */ |
4447d351 | 2429 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
2430 | if (rc) |
2431 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
2432 | } |
2433 | ||
4447d351 | 2434 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 2435 | { |
1da177e4 | 2436 | int rc; |
1da177e4 | 2437 | |
1da177e4 | 2438 | if (using_dac && |
6a35528a YH |
2439 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
2440 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
1da177e4 | 2441 | if (rc) { |
284901a9 | 2442 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2443 | if (rc) { |
a9524a76 JG |
2444 | dev_printk(KERN_ERR, &pdev->dev, |
2445 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2446 | return rc; |
2447 | } | |
2448 | } | |
1da177e4 | 2449 | } else { |
284901a9 | 2450 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2451 | if (rc) { |
a9524a76 JG |
2452 | dev_printk(KERN_ERR, &pdev->dev, |
2453 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2454 | return rc; |
2455 | } | |
284901a9 | 2456 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2457 | if (rc) { |
a9524a76 JG |
2458 | dev_printk(KERN_ERR, &pdev->dev, |
2459 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2460 | return rc; |
2461 | } | |
2462 | } | |
1da177e4 LT |
2463 | return 0; |
2464 | } | |
2465 | ||
4447d351 | 2466 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2467 | { |
4447d351 TH |
2468 | struct ahci_host_priv *hpriv = host->private_data; |
2469 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2470 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2471 | u32 vers, cap, impl, speed; |
2472 | const char *speed_s; | |
2473 | u16 cc; | |
2474 | const char *scc_s; | |
2475 | ||
2476 | vers = readl(mmio + HOST_VERSION); | |
2477 | cap = hpriv->cap; | |
2478 | impl = hpriv->port_map; | |
2479 | ||
2480 | speed = (cap >> 20) & 0xf; | |
2481 | if (speed == 1) | |
2482 | speed_s = "1.5"; | |
2483 | else if (speed == 2) | |
2484 | speed_s = "3"; | |
8522ee25 SH |
2485 | else if (speed == 3) |
2486 | speed_s = "6"; | |
1da177e4 LT |
2487 | else |
2488 | speed_s = "?"; | |
2489 | ||
2490 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2491 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2492 | scc_s = "IDE"; |
c9f89475 | 2493 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2494 | scc_s = "SATA"; |
c9f89475 | 2495 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2496 | scc_s = "RAID"; |
2497 | else | |
2498 | scc_s = "unknown"; | |
2499 | ||
a9524a76 JG |
2500 | dev_printk(KERN_INFO, &pdev->dev, |
2501 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2502 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2503 | , |
1da177e4 | 2504 | |
2dcb407e JG |
2505 | (vers >> 24) & 0xff, |
2506 | (vers >> 16) & 0xff, | |
2507 | (vers >> 8) & 0xff, | |
2508 | vers & 0xff, | |
1da177e4 LT |
2509 | |
2510 | ((cap >> 8) & 0x1f) + 1, | |
2511 | (cap & 0x1f) + 1, | |
2512 | speed_s, | |
2513 | impl, | |
2514 | scc_s); | |
2515 | ||
a9524a76 JG |
2516 | dev_printk(KERN_INFO, &pdev->dev, |
2517 | "flags: " | |
203ef6c4 | 2518 | "%s%s%s%s%s%s%s" |
18f7ba4c KCA |
2519 | "%s%s%s%s%s%s%s" |
2520 | "%s\n" | |
2dcb407e | 2521 | , |
1da177e4 LT |
2522 | |
2523 | cap & (1 << 31) ? "64bit " : "", | |
2524 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2525 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2526 | cap & (1 << 28) ? "ilck " : "", |
2527 | cap & (1 << 27) ? "stag " : "", | |
2528 | cap & (1 << 26) ? "pm " : "", | |
2529 | cap & (1 << 25) ? "led " : "", | |
2530 | ||
2531 | cap & (1 << 24) ? "clo " : "", | |
2532 | cap & (1 << 19) ? "nz " : "", | |
2533 | cap & (1 << 18) ? "only " : "", | |
2534 | cap & (1 << 17) ? "pmp " : "", | |
2535 | cap & (1 << 15) ? "pio " : "", | |
2536 | cap & (1 << 14) ? "slum " : "", | |
18f7ba4c KCA |
2537 | cap & (1 << 13) ? "part " : "", |
2538 | cap & (1 << 6) ? "ems ": "" | |
1da177e4 LT |
2539 | ); |
2540 | } | |
2541 | ||
edc93052 TH |
2542 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2543 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2544 | * support PMP and the 4726 either directly exports the device | |
2545 | * attached to the first downstream port or acts as a hardware storage | |
2546 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2547 | * other configuration). | |
2548 | * | |
2549 | * When there's no device attached to the first downstream port of the | |
2550 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2551 | * configure the 4726. However, ATA emulation of the device is very | |
2552 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2553 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2554 | * | |
2555 | * The following function works around the problem by always using | |
2556 | * hardreset on the port and not depending on receiving signature FIS | |
2557 | * afterward. If signature FIS isn't received soon, ATA class is | |
2558 | * assumed without follow-up softreset. | |
2559 | */ | |
2560 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2561 | { | |
2562 | static struct dmi_system_id sysids[] = { | |
2563 | { | |
2564 | .ident = "P5W DH Deluxe", | |
2565 | .matches = { | |
2566 | DMI_MATCH(DMI_SYS_VENDOR, | |
2567 | "ASUSTEK COMPUTER INC"), | |
2568 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2569 | }, | |
2570 | }, | |
2571 | { } | |
2572 | }; | |
2573 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2574 | ||
2575 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2576 | dmi_check_system(sysids)) { | |
2577 | struct ata_port *ap = host->ports[1]; | |
2578 | ||
2579 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2580 | "Deluxe on-board SIMG4726 workaround\n"); | |
2581 | ||
2582 | ap->ops = &ahci_p5wdh_ops; | |
2583 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2584 | } | |
2585 | } | |
2586 | ||
1fd68434 RW |
2587 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
2588 | { | |
2589 | static const struct dmi_system_id broken_systems[] = { | |
2590 | { | |
2591 | .ident = "HP Compaq nx6310", | |
2592 | .matches = { | |
2593 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2594 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
2595 | }, | |
2596 | /* PCI slot number of the controller */ | |
2597 | .driver_data = (void *)0x1FUL, | |
2598 | }, | |
d2f9c061 MR |
2599 | { |
2600 | .ident = "HP Compaq 6720s", | |
2601 | .matches = { | |
2602 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2603 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
2604 | }, | |
2605 | /* PCI slot number of the controller */ | |
2606 | .driver_data = (void *)0x1FUL, | |
2607 | }, | |
1fd68434 RW |
2608 | |
2609 | { } /* terminate list */ | |
2610 | }; | |
2611 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
2612 | ||
2613 | if (dmi) { | |
2614 | unsigned long slot = (unsigned long)dmi->driver_data; | |
2615 | /* apply the quirk only to on-board controllers */ | |
2616 | return slot == PCI_SLOT(pdev->devfn); | |
2617 | } | |
2618 | ||
2619 | return false; | |
2620 | } | |
2621 | ||
9b10ae86 TH |
2622 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
2623 | { | |
2624 | static const struct dmi_system_id sysids[] = { | |
2625 | /* | |
2626 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
2627 | * to the harddisk doesn't become online after | |
2628 | * resuming from STR. Warn and fail suspend. | |
2629 | */ | |
2630 | { | |
2631 | .ident = "dv4", | |
2632 | .matches = { | |
2633 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2634 | DMI_MATCH(DMI_PRODUCT_NAME, | |
2635 | "HP Pavilion dv4 Notebook PC"), | |
2636 | }, | |
2637 | .driver_data = "F.30", /* cutoff BIOS version */ | |
2638 | }, | |
2639 | { | |
2640 | .ident = "dv5", | |
2641 | .matches = { | |
2642 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2643 | DMI_MATCH(DMI_PRODUCT_NAME, | |
2644 | "HP Pavilion dv5 Notebook PC"), | |
2645 | }, | |
2646 | .driver_data = "F.16", /* cutoff BIOS version */ | |
2647 | }, | |
2648 | { | |
2649 | .ident = "dv6", | |
2650 | .matches = { | |
2651 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2652 | DMI_MATCH(DMI_PRODUCT_NAME, | |
2653 | "HP Pavilion dv6 Notebook PC"), | |
2654 | }, | |
2655 | .driver_data = "F.21", /* cutoff BIOS version */ | |
2656 | }, | |
2657 | { | |
2658 | .ident = "HDX18", | |
2659 | .matches = { | |
2660 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
2661 | DMI_MATCH(DMI_PRODUCT_NAME, | |
2662 | "HP HDX18 Notebook PC"), | |
2663 | }, | |
2664 | .driver_data = "F.23", /* cutoff BIOS version */ | |
2665 | }, | |
2666 | { } /* terminate list */ | |
2667 | }; | |
2668 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
2669 | const char *ver; | |
2670 | ||
2671 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
2672 | return false; | |
2673 | ||
2674 | ver = dmi_get_system_info(DMI_BIOS_VERSION); | |
2675 | ||
2676 | return !ver || strcmp(ver, dmi->driver_data) < 0; | |
2677 | } | |
2678 | ||
24dc5f33 | 2679 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2680 | { |
2681 | static int printed_version; | |
e297d99e TH |
2682 | unsigned int board_id = ent->driver_data; |
2683 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 2684 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 2685 | struct device *dev = &pdev->dev; |
1da177e4 | 2686 | struct ahci_host_priv *hpriv; |
4447d351 | 2687 | struct ata_host *host; |
837f5f8f | 2688 | int n_ports, i, rc; |
1da177e4 LT |
2689 | |
2690 | VPRINTK("ENTER\n"); | |
2691 | ||
12fad3f9 TH |
2692 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2693 | ||
1da177e4 | 2694 | if (!printed_version++) |
a9524a76 | 2695 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2696 | |
5b66c829 AC |
2697 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
2698 | can drive them all so if both drivers are selected make sure | |
2699 | AHCI stays out of the way */ | |
2700 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
2701 | return -ENODEV; | |
2702 | ||
4447d351 | 2703 | /* acquire resources */ |
24dc5f33 | 2704 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2705 | if (rc) |
2706 | return rc; | |
2707 | ||
dea55137 TH |
2708 | /* AHCI controllers often implement SFF compatible interface. |
2709 | * Grab all PCI BARs just in case. | |
2710 | */ | |
2711 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
0d5ff566 | 2712 | if (rc == -EBUSY) |
24dc5f33 | 2713 | pcim_pin_device(pdev); |
0d5ff566 | 2714 | if (rc) |
24dc5f33 | 2715 | return rc; |
1da177e4 | 2716 | |
c4f7792c TH |
2717 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2718 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2719 | u8 map; | |
2720 | ||
2721 | /* ICH6s share the same PCI ID for both piix and ahci | |
2722 | * modes. Enabling ahci mode while MAP indicates | |
2723 | * combined mode is a bad idea. Yield to ata_piix. | |
2724 | */ | |
2725 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2726 | if (map & 0x3) { | |
2727 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2728 | "combined mode, can't enable AHCI mode\n"); | |
2729 | return -ENODEV; | |
2730 | } | |
2731 | } | |
2732 | ||
24dc5f33 TH |
2733 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2734 | if (!hpriv) | |
2735 | return -ENOMEM; | |
417a1a6d TH |
2736 | hpriv->flags |= (unsigned long)pi.private_data; |
2737 | ||
e297d99e TH |
2738 | /* MCP65 revision A1 and A2 can't do MSI */ |
2739 | if (board_id == board_ahci_mcp65 && | |
2740 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
2741 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
2742 | ||
e427fe04 SH |
2743 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
2744 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
2745 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
2746 | ||
a5bfc471 TH |
2747 | if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) |
2748 | pci_enable_msi(pdev); | |
1da177e4 | 2749 | |
4447d351 | 2750 | /* save initial config */ |
417a1a6d | 2751 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2752 | |
4447d351 | 2753 | /* prepare host */ |
274c1fde | 2754 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2755 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2756 | |
7d50b60b TH |
2757 | if (hpriv->cap & HOST_CAP_PMP) |
2758 | pi.flags |= ATA_FLAG_PMP; | |
2759 | ||
18f7ba4c KCA |
2760 | if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) { |
2761 | u8 messages; | |
2762 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; | |
2763 | u32 em_loc = readl(mmio + HOST_EM_LOC); | |
2764 | u32 em_ctl = readl(mmio + HOST_EM_CTL); | |
2765 | ||
87943acf | 2766 | messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; |
18f7ba4c KCA |
2767 | |
2768 | /* we only support LED message type right now */ | |
2769 | if ((messages & 0x01) && (ahci_em_messages == 1)) { | |
2770 | /* store em_loc */ | |
2771 | hpriv->em_loc = ((em_loc >> 16) * 4); | |
2772 | pi.flags |= ATA_FLAG_EM; | |
2773 | if (!(em_ctl & EM_CTL_ALHD)) | |
2774 | pi.flags |= ATA_FLAG_SW_ACTIVITY; | |
2775 | } | |
2776 | } | |
2777 | ||
1fd68434 RW |
2778 | if (ahci_broken_system_poweroff(pdev)) { |
2779 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
2780 | dev_info(&pdev->dev, | |
2781 | "quirky BIOS, skipping spindown on poweroff\n"); | |
2782 | } | |
2783 | ||
9b10ae86 TH |
2784 | if (ahci_broken_suspend(pdev)) { |
2785 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
2786 | dev_printk(KERN_WARNING, &pdev->dev, | |
2787 | "BIOS update required for suspend/resume\n"); | |
2788 | } | |
2789 | ||
837f5f8f TH |
2790 | /* CAP.NP sometimes indicate the index of the last enabled |
2791 | * port, at other times, that of the last possible port, so | |
2792 | * determining the maximum port number requires looking at | |
2793 | * both CAP.NP and port_map. | |
2794 | */ | |
2795 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
2796 | ||
2797 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
2798 | if (!host) |
2799 | return -ENOMEM; | |
2800 | host->iomap = pcim_iomap_table(pdev); | |
2801 | host->private_data = hpriv; | |
2802 | ||
f3d7f23f | 2803 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 2804 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f AV |
2805 | else |
2806 | printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); | |
886ad09f | 2807 | |
18f7ba4c KCA |
2808 | if (pi.flags & ATA_FLAG_EM) |
2809 | ahci_reset_em(host); | |
2810 | ||
4447d351 | 2811 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 2812 | struct ata_port *ap = host->ports[i]; |
4447d351 | 2813 | |
cbcdd875 TH |
2814 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2815 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2816 | 0x100 + ap->port_no * 0x80, "port"); | |
2817 | ||
31556594 KCA |
2818 | /* set initial link pm policy */ |
2819 | ap->pm_policy = NOT_AVAILABLE; | |
2820 | ||
18f7ba4c KCA |
2821 | /* set enclosure management message type */ |
2822 | if (ap->flags & ATA_FLAG_EM) | |
2823 | ap->em_message_type = ahci_em_messages; | |
2824 | ||
2825 | ||
dab632e8 | 2826 | /* disabled/not-implemented port */ |
350756f6 | 2827 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 2828 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 2829 | } |
d447df14 | 2830 | |
edc93052 TH |
2831 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2832 | ahci_p5wdh_workaround(host); | |
2833 | ||
4447d351 TH |
2834 | /* initialize adapter */ |
2835 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2836 | if (rc) |
24dc5f33 | 2837 | return rc; |
1da177e4 | 2838 | |
4447d351 TH |
2839 | rc = ahci_reset_controller(host); |
2840 | if (rc) | |
2841 | return rc; | |
1da177e4 | 2842 | |
4447d351 TH |
2843 | ahci_init_controller(host); |
2844 | ahci_print_info(host); | |
1da177e4 | 2845 | |
4447d351 TH |
2846 | pci_set_master(pdev); |
2847 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2848 | &ahci_sht); | |
907f4678 | 2849 | } |
1da177e4 LT |
2850 | |
2851 | static int __init ahci_init(void) | |
2852 | { | |
b7887196 | 2853 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2854 | } |
2855 | ||
1da177e4 LT |
2856 | static void __exit ahci_exit(void) |
2857 | { | |
2858 | pci_unregister_driver(&ahci_pci_driver); | |
2859 | } | |
2860 | ||
2861 | ||
2862 | MODULE_AUTHOR("Jeff Garzik"); | |
2863 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2864 | MODULE_LICENSE("GPL"); | |
2865 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2866 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2867 | |
2868 | module_init(ahci_init); | |
2869 | module_exit(ahci_exit); |