Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
5a0e3ad6 | 45 | #include <linux/gfp.h> |
1da177e4 | 46 | #include <scsi/scsi_host.h> |
193515d5 | 47 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 48 | #include <linux/libata.h> |
1da177e4 LT |
49 | |
50 | #define DRV_NAME "ahci" | |
7d50b60b | 51 | #define DRV_VERSION "3.0" |
1da177e4 | 52 | |
87943acf DM |
53 | /* Enclosure Management Control */ |
54 | #define EM_CTRL_MSG_TYPE 0x000f0000 | |
55 | ||
56 | /* Enclosure Management LED Message Type */ | |
57 | #define EM_MSG_LED_HBA_PORT 0x0000000f | |
58 | #define EM_MSG_LED_PMP_SLOT 0x0000ff00 | |
59 | #define EM_MSG_LED_VALUE 0xffff0000 | |
60 | #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 | |
61 | #define EM_MSG_LED_VALUE_OFF 0xfff80000 | |
62 | #define EM_MSG_LED_VALUE_ON 0x00010000 | |
63 | ||
a22e6444 | 64 | static int ahci_skip_host_reset; |
f3d7f23f AV |
65 | static int ahci_ignore_sss; |
66 | ||
a22e6444 TH |
67 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); |
68 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
69 | ||
f3d7f23f AV |
70 | module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); |
71 | MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); | |
72 | ||
31556594 KCA |
73 | static int ahci_enable_alpm(struct ata_port *ap, |
74 | enum link_pm policy); | |
75 | static void ahci_disable_alpm(struct ata_port *ap); | |
18f7ba4c KCA |
76 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf); |
77 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
78 | size_t size); | |
79 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
80 | ssize_t size); | |
1da177e4 LT |
81 | |
82 | enum { | |
83 | AHCI_PCI_BAR = 5, | |
648a88be | 84 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
85 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
86 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
12fad3f9 | 87 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 88 | AHCI_CMD_SZ = 32, |
12fad3f9 | 89 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 90 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 91 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
92 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
93 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
94 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
95 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 | 96 | AHCI_RX_FIS_SZ, |
d6ef3153 SH |
97 | AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + |
98 | AHCI_CMD_TBL_AR_SZ + | |
99 | (AHCI_RX_FIS_SZ * 16), | |
1da177e4 LT |
100 | AHCI_IRQ_ON_SG = (1 << 31), |
101 | AHCI_CMD_ATAPI = (1 << 5), | |
102 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 103 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
104 | AHCI_CMD_RESET = (1 << 8), |
105 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
106 | |
107 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 108 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 109 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
110 | |
111 | board_ahci = 0, | |
7a234aff TH |
112 | board_ahci_vt8251 = 1, |
113 | board_ahci_ign_iferr = 2, | |
114 | board_ahci_sb600 = 3, | |
115 | board_ahci_mv = 4, | |
e427fe04 | 116 | board_ahci_sb700 = 5, /* for SB700 and SB800 */ |
e297d99e | 117 | board_ahci_mcp65 = 6, |
9a3b103c | 118 | board_ahci_nopmp = 7, |
aa431dd3 | 119 | board_ahci_yesncq = 8, |
1b677afd | 120 | board_ahci_nosntf = 9, |
1da177e4 LT |
121 | |
122 | /* global controller registers */ | |
123 | HOST_CAP = 0x00, /* host capabilities */ | |
124 | HOST_CTL = 0x04, /* global host control */ | |
125 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
126 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
127 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
18f7ba4c KCA |
128 | HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
129 | HOST_EM_CTL = 0x20, /* Enclosure Management Control */ | |
4c521c8e | 130 | HOST_CAP2 = 0x24, /* host capabilities, extended */ |
1da177e4 LT |
131 | |
132 | /* HOST_CTL bits */ | |
133 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
134 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
135 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
136 | ||
137 | /* HOST_CAP bits */ | |
4c521c8e | 138 | HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ |
18f7ba4c | 139 | HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ |
4c521c8e RH |
140 | HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ |
141 | HOST_CAP_PART = (1 << 13), /* Partial state capable */ | |
142 | HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ | |
143 | HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ | |
144 | HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ | |
7d50b60b | 145 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
4c521c8e | 146 | HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ |
22b49985 | 147 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
4c521c8e | 148 | HOST_CAP_LED = (1 << 25), /* Supports activity LED */ |
31556594 | 149 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 150 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
4c521c8e | 151 | HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ |
203ef6c4 | 152 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 153 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 154 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 | 155 | |
4c521c8e RH |
156 | /* HOST_CAP2 bits */ |
157 | HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ | |
158 | HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ | |
159 | HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ | |
160 | ||
1da177e4 LT |
161 | /* registers for each SATA port */ |
162 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
163 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
164 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
165 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
166 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
167 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
168 | PORT_CMD = 0x18, /* port command */ | |
169 | PORT_TFDATA = 0x20, /* taskfile data */ | |
170 | PORT_SIG = 0x24, /* device TF signature */ | |
171 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
172 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
173 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
174 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
175 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 176 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
d6ef3153 | 177 | PORT_FBS = 0x40, /* FIS-based Switching */ |
1da177e4 LT |
178 | |
179 | /* PORT_IRQ_{STAT,MASK} bits */ | |
180 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
181 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
182 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
183 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
184 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
185 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
186 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
187 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
188 | ||
189 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
190 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
191 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
192 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
193 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
194 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
195 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
196 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
197 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
198 | ||
78cd52d0 TH |
199 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
200 | PORT_IRQ_IF_ERR | | |
201 | PORT_IRQ_CONNECT | | |
4296971d | 202 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
203 | PORT_IRQ_UNK_FIS | |
204 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
205 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
206 | PORT_IRQ_TF_ERR | | |
207 | PORT_IRQ_HBUS_DATA_ERR, | |
208 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
209 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
210 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
211 | |
212 | /* PORT_CMD bits */ | |
31556594 KCA |
213 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
214 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 215 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
d6ef3153 | 216 | PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ |
7d50b60b | 217 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
218 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
219 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
220 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 221 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
222 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
223 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
224 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
225 | ||
0be0aa98 | 226 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
227 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
228 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
229 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 230 | |
d6ef3153 SH |
231 | PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ |
232 | PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ | |
233 | PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ | |
234 | PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ | |
235 | PORT_FBS_SDE = (1 << 2), /* FBS single device error */ | |
236 | PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ | |
237 | PORT_FBS_EN = (1 << 0), /* Enable FBS */ | |
238 | ||
417a1a6d TH |
239 | /* hpriv->flags bits */ |
240 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
241 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
242 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
243 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
244 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
245 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 246 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 247 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
a878539e | 248 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
e297d99e | 249 | AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
9b10ae86 | 250 | AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ |
5594639a TH |
251 | AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as |
252 | link offline */ | |
1b677afd | 253 | AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ |
417a1a6d | 254 | |
bf2af2a2 | 255 | /* ap->flags bits */ |
1188c0d8 TH |
256 | |
257 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
258 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
259 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
260 | ATA_FLAG_IPM, | |
c4f7792c TH |
261 | |
262 | ICH_MAP = 0x90, /* ICH MAP register */ | |
18f7ba4c | 263 | |
d50ce07d TH |
264 | /* em constants */ |
265 | EM_MAX_SLOTS = 8, | |
266 | EM_MAX_RETRY = 5, | |
267 | ||
18f7ba4c KCA |
268 | /* em_ctl bits */ |
269 | EM_CTL_RST = (1 << 9), /* Reset */ | |
270 | EM_CTL_TM = (1 << 8), /* Transmit Message */ | |
271 | EM_CTL_ALHD = (1 << 26), /* Activity LED */ | |
1da177e4 LT |
272 | }; |
273 | ||
274 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
275 | __le32 opts; |
276 | __le32 status; | |
277 | __le32 tbl_addr; | |
278 | __le32 tbl_addr_hi; | |
279 | __le32 reserved[4]; | |
1da177e4 LT |
280 | }; |
281 | ||
282 | struct ahci_sg { | |
4ca4e439 AV |
283 | __le32 addr; |
284 | __le32 addr_hi; | |
285 | __le32 reserved; | |
286 | __le32 flags_size; | |
1da177e4 LT |
287 | }; |
288 | ||
18f7ba4c KCA |
289 | struct ahci_em_priv { |
290 | enum sw_activity blink_policy; | |
291 | struct timer_list timer; | |
292 | unsigned long saved_activity; | |
293 | unsigned long activity; | |
294 | unsigned long led_state; | |
295 | }; | |
296 | ||
1da177e4 | 297 | struct ahci_host_priv { |
d8993349 | 298 | void __iomem * mmio; /* bus-independant mem map */ |
417a1a6d | 299 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 | 300 | u32 cap; /* cap to use */ |
4c521c8e | 301 | u32 cap2; /* cap2 to use */ |
d447df14 TH |
302 | u32 port_map; /* port map to use */ |
303 | u32 saved_cap; /* saved initial cap */ | |
4c521c8e | 304 | u32 saved_cap2; /* saved initial cap2 */ |
d447df14 | 305 | u32 saved_port_map; /* saved initial port_map */ |
18f7ba4c | 306 | u32 em_loc; /* enclosure management location */ |
1da177e4 LT |
307 | }; |
308 | ||
309 | struct ahci_port_priv { | |
7d50b60b | 310 | struct ata_link *active_link; |
1da177e4 LT |
311 | struct ahci_cmd_hdr *cmd_slot; |
312 | dma_addr_t cmd_slot_dma; | |
313 | void *cmd_tbl; | |
314 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
315 | void *rx_fis; |
316 | dma_addr_t rx_fis_dma; | |
0291f95f | 317 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
318 | unsigned int ncq_saw_d2h:1; |
319 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 320 | unsigned int ncq_saw_sdb:1; |
a7384925 | 321 | u32 intr_mask; /* interrupts to enable */ |
d6ef3153 SH |
322 | bool fbs_supported; /* set iff FBS is supported */ |
323 | bool fbs_enabled; /* set iff FBS is enabled */ | |
324 | int fbs_last_dev; /* save FBS.DEV of last FIS */ | |
d50ce07d TH |
325 | /* enclosure management info per PM slot */ |
326 | struct ahci_em_priv em_priv[EM_MAX_SLOTS]; | |
1da177e4 LT |
327 | }; |
328 | ||
82ef04fb TH |
329 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
330 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
2dcb407e | 331 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 332 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
4c9bf4e7 | 333 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
1da177e4 LT |
334 | static int ahci_port_start(struct ata_port *ap); |
335 | static void ahci_port_stop(struct ata_port *ap); | |
d6ef3153 | 336 | static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); |
1da177e4 | 337 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
78cd52d0 TH |
338 | static void ahci_freeze(struct ata_port *ap); |
339 | static void ahci_thaw(struct ata_port *ap); | |
d6ef3153 SH |
340 | static void ahci_enable_fbs(struct ata_port *ap); |
341 | static void ahci_disable_fbs(struct ata_port *ap); | |
7d50b60b TH |
342 | static void ahci_pmp_attach(struct ata_port *ap); |
343 | static void ahci_pmp_detach(struct ata_port *ap); | |
a1efdaba TH |
344 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
345 | unsigned long deadline); | |
bd17243a SH |
346 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, |
347 | unsigned long deadline); | |
a1efdaba TH |
348 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
349 | unsigned long deadline); | |
350 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, | |
351 | unsigned long deadline); | |
352 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, | |
353 | unsigned long deadline); | |
354 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
78cd52d0 TH |
355 | static void ahci_error_handler(struct ata_port *ap); |
356 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
df69c9c5 | 357 | static int ahci_port_resume(struct ata_port *ap); |
a878539e | 358 | static void ahci_dev_config(struct ata_device *dev); |
dab632e8 JG |
359 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
360 | u32 opts); | |
438ac6d5 | 361 | #ifdef CONFIG_PM |
c1332875 | 362 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
363 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
364 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 365 | #endif |
18f7ba4c KCA |
366 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); |
367 | static ssize_t ahci_activity_store(struct ata_device *dev, | |
368 | enum sw_activity val); | |
369 | static void ahci_init_sw_activity(struct ata_link *link); | |
1da177e4 | 370 | |
77cdec1a MG |
371 | static ssize_t ahci_show_host_caps(struct device *dev, |
372 | struct device_attribute *attr, char *buf); | |
4c521c8e RH |
373 | static ssize_t ahci_show_host_cap2(struct device *dev, |
374 | struct device_attribute *attr, char *buf); | |
77cdec1a MG |
375 | static ssize_t ahci_show_host_version(struct device *dev, |
376 | struct device_attribute *attr, char *buf); | |
377 | static ssize_t ahci_show_port_cmd(struct device *dev, | |
378 | struct device_attribute *attr, char *buf); | |
379 | ||
9ffc5da5 RH |
380 | static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); |
381 | static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); | |
382 | static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); | |
383 | static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); | |
77cdec1a | 384 | |
ee959b00 TJ |
385 | static struct device_attribute *ahci_shost_attrs[] = { |
386 | &dev_attr_link_power_management_policy, | |
18f7ba4c KCA |
387 | &dev_attr_em_message_type, |
388 | &dev_attr_em_message, | |
77cdec1a | 389 | &dev_attr_ahci_host_caps, |
4c521c8e | 390 | &dev_attr_ahci_host_cap2, |
77cdec1a MG |
391 | &dev_attr_ahci_host_version, |
392 | &dev_attr_ahci_port_cmd, | |
18f7ba4c KCA |
393 | NULL |
394 | }; | |
395 | ||
396 | static struct device_attribute *ahci_sdev_attrs[] = { | |
397 | &dev_attr_sw_activity, | |
45fabbb7 | 398 | &dev_attr_unload_heads, |
31556594 KCA |
399 | NULL |
400 | }; | |
401 | ||
193515d5 | 402 | static struct scsi_host_template ahci_sht = { |
68d1d07b | 403 | ATA_NCQ_SHT(DRV_NAME), |
12fad3f9 | 404 | .can_queue = AHCI_MAX_CMDS - 1, |
1da177e4 | 405 | .sg_tablesize = AHCI_MAX_SG, |
1da177e4 | 406 | .dma_boundary = AHCI_DMA_BOUNDARY, |
31556594 | 407 | .shost_attrs = ahci_shost_attrs, |
18f7ba4c | 408 | .sdev_attrs = ahci_sdev_attrs, |
1da177e4 LT |
409 | }; |
410 | ||
029cfd6b TH |
411 | static struct ata_port_operations ahci_ops = { |
412 | .inherits = &sata_pmp_port_ops, | |
413 | ||
d6ef3153 | 414 | .qc_defer = ahci_pmp_qc_defer, |
1da177e4 LT |
415 | .qc_prep = ahci_qc_prep, |
416 | .qc_issue = ahci_qc_issue, | |
4c9bf4e7 | 417 | .qc_fill_rtf = ahci_qc_fill_rtf, |
1da177e4 | 418 | |
78cd52d0 TH |
419 | .freeze = ahci_freeze, |
420 | .thaw = ahci_thaw, | |
a1efdaba TH |
421 | .softreset = ahci_softreset, |
422 | .hardreset = ahci_hardreset, | |
423 | .postreset = ahci_postreset, | |
071f44b1 | 424 | .pmp_softreset = ahci_softreset, |
78cd52d0 TH |
425 | .error_handler = ahci_error_handler, |
426 | .post_internal_cmd = ahci_post_internal_cmd, | |
6bd99b4e TH |
427 | .dev_config = ahci_dev_config, |
428 | ||
ad616ffb TH |
429 | .scr_read = ahci_scr_read, |
430 | .scr_write = ahci_scr_write, | |
7d50b60b TH |
431 | .pmp_attach = ahci_pmp_attach, |
432 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 433 | |
029cfd6b TH |
434 | .enable_pm = ahci_enable_alpm, |
435 | .disable_pm = ahci_disable_alpm, | |
18f7ba4c KCA |
436 | .em_show = ahci_led_show, |
437 | .em_store = ahci_led_store, | |
438 | .sw_activity_show = ahci_activity_show, | |
439 | .sw_activity_store = ahci_activity_store, | |
438ac6d5 | 440 | #ifdef CONFIG_PM |
ad616ffb TH |
441 | .port_suspend = ahci_port_suspend, |
442 | .port_resume = ahci_port_resume, | |
438ac6d5 | 443 | #endif |
ad616ffb TH |
444 | .port_start = ahci_port_start, |
445 | .port_stop = ahci_port_stop, | |
446 | }; | |
447 | ||
029cfd6b TH |
448 | static struct ata_port_operations ahci_vt8251_ops = { |
449 | .inherits = &ahci_ops, | |
a1efdaba | 450 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 451 | }; |
edc93052 | 452 | |
029cfd6b TH |
453 | static struct ata_port_operations ahci_p5wdh_ops = { |
454 | .inherits = &ahci_ops, | |
a1efdaba | 455 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
456 | }; |
457 | ||
bd17243a SH |
458 | static struct ata_port_operations ahci_sb600_ops = { |
459 | .inherits = &ahci_ops, | |
460 | .softreset = ahci_sb600_softreset, | |
461 | .pmp_softreset = ahci_sb600_softreset, | |
462 | }; | |
463 | ||
417a1a6d TH |
464 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
465 | ||
98ac62de | 466 | static const struct ata_port_info ahci_port_info[] = { |
4da646b7 | 467 | [board_ahci] = |
1da177e4 | 468 | { |
1188c0d8 | 469 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 470 | .pio_mask = ATA_PIO4, |
469248ab | 471 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
472 | .port_ops = &ahci_ops, |
473 | }, | |
4da646b7 | 474 | [board_ahci_vt8251] = |
bf2af2a2 | 475 | { |
6949b914 | 476 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 477 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 478 | .pio_mask = ATA_PIO4, |
469248ab | 479 | .udma_mask = ATA_UDMA6, |
ad616ffb | 480 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 481 | }, |
4da646b7 | 482 | [board_ahci_ign_iferr] = |
41669553 | 483 | { |
417a1a6d TH |
484 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
485 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 486 | .pio_mask = ATA_PIO4, |
469248ab | 487 | .udma_mask = ATA_UDMA6, |
41669553 TH |
488 | .port_ops = &ahci_ops, |
489 | }, | |
4da646b7 | 490 | [board_ahci_sb600] = |
55a61604 | 491 | { |
417a1a6d | 492 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
2fcad9d2 TH |
493 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | |
494 | AHCI_HFLAG_32BIT_ONLY), | |
417a1a6d | 495 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 496 | .pio_mask = ATA_PIO4, |
469248ab | 497 | .udma_mask = ATA_UDMA6, |
bd17243a | 498 | .port_ops = &ahci_sb600_ops, |
55a61604 | 499 | }, |
4da646b7 | 500 | [board_ahci_mv] = |
cd70c266 | 501 | { |
417a1a6d | 502 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 503 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
cd70c266 | 504 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 505 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
14bdef98 | 506 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
507 | .udma_mask = ATA_UDMA6, |
508 | .port_ops = &ahci_ops, | |
509 | }, | |
4da646b7 | 510 | [board_ahci_sb700] = /* for SB700 and SB800 */ |
e39fc8c9 | 511 | { |
bd17243a | 512 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
e39fc8c9 | 513 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 514 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 515 | .udma_mask = ATA_UDMA6, |
bd17243a | 516 | .port_ops = &ahci_sb600_ops, |
e39fc8c9 | 517 | }, |
4da646b7 | 518 | [board_ahci_mcp65] = |
e297d99e TH |
519 | { |
520 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), | |
521 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 522 | .pio_mask = ATA_PIO4, |
e297d99e TH |
523 | .udma_mask = ATA_UDMA6, |
524 | .port_ops = &ahci_ops, | |
525 | }, | |
4da646b7 | 526 | [board_ahci_nopmp] = |
9a3b103c TH |
527 | { |
528 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), | |
529 | .flags = AHCI_FLAG_COMMON, | |
14bdef98 | 530 | .pio_mask = ATA_PIO4, |
9a3b103c TH |
531 | .udma_mask = ATA_UDMA6, |
532 | .port_ops = &ahci_ops, | |
533 | }, | |
1b677afd | 534 | [board_ahci_yesncq] = |
aa431dd3 TH |
535 | { |
536 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), | |
537 | .flags = AHCI_FLAG_COMMON, | |
538 | .pio_mask = ATA_PIO4, | |
539 | .udma_mask = ATA_UDMA6, | |
540 | .port_ops = &ahci_ops, | |
541 | }, | |
1b677afd SL |
542 | [board_ahci_nosntf] = |
543 | { | |
544 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), | |
545 | .flags = AHCI_FLAG_COMMON, | |
546 | .pio_mask = ATA_PIO4, | |
547 | .udma_mask = ATA_UDMA6, | |
548 | .port_ops = &ahci_ops, | |
549 | }, | |
1da177e4 LT |
550 | }; |
551 | ||
3b7d697d | 552 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 553 | /* Intel */ |
54bb3a94 JG |
554 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
555 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
556 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
557 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
558 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 559 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
560 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
561 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
562 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
563 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff | 564 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
1b677afd | 565 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ |
7a234aff TH |
566 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
567 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
568 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
569 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
570 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
571 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
572 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
573 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
574 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
575 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
576 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
577 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
578 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
579 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
580 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
581 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
582 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 | 583 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
b2dde6af | 584 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
16ad1ad9 | 585 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
c1f57d9b DM |
586 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
587 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ | |
adcb5308 | 588 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 589 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
c1f57d9b | 590 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ |
adcb5308 | 591 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 592 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ |
c1f57d9b | 593 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
5623cab8 SH |
594 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
595 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ | |
596 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ | |
597 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ | |
598 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ | |
599 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ | |
fe7fa31a | 600 | |
e34bb370 TH |
601 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
602 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
603 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
604 | |
605 | /* ATI */ | |
c65ec1c2 | 606 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
607 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
608 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
609 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
610 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
611 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
612 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a | 613 | |
e2dd90b1 | 614 | /* AMD */ |
5deab536 | 615 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
e2dd90b1 SH |
616 | /* AMD is using RAID class only for ahci controllers */ |
617 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
618 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, | |
619 | ||
fe7fa31a | 620 | /* VIA */ |
54bb3a94 | 621 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 622 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
623 | |
624 | /* NVIDIA */ | |
e297d99e TH |
625 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
626 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
627 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
628 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
629 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
630 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
631 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
632 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
aa431dd3 TH |
633 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */ |
634 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */ | |
635 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */ | |
636 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */ | |
637 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */ | |
638 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */ | |
639 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */ | |
640 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */ | |
641 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */ | |
642 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */ | |
643 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */ | |
644 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */ | |
726206f8 | 645 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */ |
603037c3 TH |
646 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq }, /* Linux ID */ |
647 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq }, /* Linux ID */ | |
648 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq }, /* Linux ID */ | |
649 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq }, /* Linux ID */ | |
650 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq }, /* Linux ID */ | |
651 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq }, /* Linux ID */ | |
652 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq }, /* Linux ID */ | |
653 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq }, /* Linux ID */ | |
654 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq }, /* Linux ID */ | |
655 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq }, /* Linux ID */ | |
656 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq }, /* Linux ID */ | |
657 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq }, /* Linux ID */ | |
658 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq }, /* Linux ID */ | |
659 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq }, /* Linux ID */ | |
660 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq }, /* Linux ID */ | |
aa431dd3 TH |
661 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */ |
662 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */ | |
663 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */ | |
664 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */ | |
665 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */ | |
666 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */ | |
667 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */ | |
668 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */ | |
669 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */ | |
670 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */ | |
671 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */ | |
672 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */ | |
0522b286 PC |
673 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
674 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
675 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
676 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
677 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
678 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
679 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
680 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
681 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
682 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
683 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
684 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 685 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
686 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
687 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
688 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
689 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
690 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
691 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
692 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
693 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
694 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
695 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
696 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
7adbe46b | 697 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ |
698 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ | |
699 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ | |
700 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ | |
701 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ | |
702 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ | |
703 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ | |
704 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ | |
705 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ | |
706 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ | |
707 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ | |
708 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ | |
fe7fa31a | 709 | |
95916edd | 710 | /* SiS */ |
20e2de4a TH |
711 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
712 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
713 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 714 | |
cd70c266 JG |
715 | /* Marvell */ |
716 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 717 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
cd70c266 | 718 | |
c77a036b MN |
719 | /* Promise */ |
720 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
721 | ||
415ae2b5 JG |
722 | /* Generic, PCI class code for AHCI */ |
723 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 724 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 725 | |
1da177e4 LT |
726 | { } /* terminate list */ |
727 | }; | |
728 | ||
729 | ||
730 | static struct pci_driver ahci_pci_driver = { | |
731 | .name = DRV_NAME, | |
732 | .id_table = ahci_pci_tbl, | |
733 | .probe = ahci_init_one, | |
24dc5f33 | 734 | .remove = ata_pci_remove_one, |
438ac6d5 | 735 | #ifdef CONFIG_PM |
c1332875 TH |
736 | .suspend = ahci_pci_device_suspend, |
737 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 738 | #endif |
1da177e4 LT |
739 | }; |
740 | ||
18f7ba4c KCA |
741 | static int ahci_em_messages = 1; |
742 | module_param(ahci_em_messages, int, 0444); | |
743 | /* add other LED protocol types when they become supported */ | |
744 | MODULE_PARM_DESC(ahci_em_messages, | |
745 | "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); | |
1da177e4 | 746 | |
5b66c829 AC |
747 | #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) |
748 | static int marvell_enable; | |
749 | #else | |
750 | static int marvell_enable = 1; | |
751 | #endif | |
752 | module_param(marvell_enable, int, 0644); | |
753 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
754 | ||
755 | ||
98fa4b60 TH |
756 | static inline int ahci_nr_ports(u32 cap) |
757 | { | |
758 | return (cap & 0x1f) + 1; | |
759 | } | |
760 | ||
dab632e8 JG |
761 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
762 | unsigned int port_no) | |
1da177e4 | 763 | { |
d8993349 AV |
764 | struct ahci_host_priv *hpriv = host->private_data; |
765 | void __iomem *mmio = hpriv->mmio; | |
4447d351 | 766 | |
dab632e8 JG |
767 | return mmio + 0x100 + (port_no * 0x80); |
768 | } | |
769 | ||
770 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
771 | { | |
772 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
773 | } |
774 | ||
b710a1f4 TH |
775 | static void ahci_enable_ahci(void __iomem *mmio) |
776 | { | |
15fe982e | 777 | int i; |
b710a1f4 TH |
778 | u32 tmp; |
779 | ||
780 | /* turn on AHCI_EN */ | |
781 | tmp = readl(mmio + HOST_CTL); | |
15fe982e TH |
782 | if (tmp & HOST_AHCI_EN) |
783 | return; | |
784 | ||
785 | /* Some controllers need AHCI_EN to be written multiple times. | |
786 | * Try a few times before giving up. | |
787 | */ | |
788 | for (i = 0; i < 5; i++) { | |
b710a1f4 TH |
789 | tmp |= HOST_AHCI_EN; |
790 | writel(tmp, mmio + HOST_CTL); | |
791 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
15fe982e TH |
792 | if (tmp & HOST_AHCI_EN) |
793 | return; | |
794 | msleep(10); | |
b710a1f4 | 795 | } |
15fe982e TH |
796 | |
797 | WARN_ON(1); | |
b710a1f4 TH |
798 | } |
799 | ||
77cdec1a MG |
800 | static ssize_t ahci_show_host_caps(struct device *dev, |
801 | struct device_attribute *attr, char *buf) | |
802 | { | |
803 | struct Scsi_Host *shost = class_to_shost(dev); | |
804 | struct ata_port *ap = ata_shost_to_port(shost); | |
805 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
806 | ||
807 | return sprintf(buf, "%x\n", hpriv->cap); | |
808 | } | |
809 | ||
4c521c8e RH |
810 | static ssize_t ahci_show_host_cap2(struct device *dev, |
811 | struct device_attribute *attr, char *buf) | |
812 | { | |
813 | struct Scsi_Host *shost = class_to_shost(dev); | |
814 | struct ata_port *ap = ata_shost_to_port(shost); | |
815 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
816 | ||
817 | return sprintf(buf, "%x\n", hpriv->cap2); | |
818 | } | |
819 | ||
77cdec1a MG |
820 | static ssize_t ahci_show_host_version(struct device *dev, |
821 | struct device_attribute *attr, char *buf) | |
822 | { | |
823 | struct Scsi_Host *shost = class_to_shost(dev); | |
824 | struct ata_port *ap = ata_shost_to_port(shost); | |
d8993349 AV |
825 | struct ahci_host_priv *hpriv = ap->host->private_data; |
826 | void __iomem *mmio = hpriv->mmio; | |
77cdec1a MG |
827 | |
828 | return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); | |
829 | } | |
830 | ||
831 | static ssize_t ahci_show_port_cmd(struct device *dev, | |
832 | struct device_attribute *attr, char *buf) | |
833 | { | |
834 | struct Scsi_Host *shost = class_to_shost(dev); | |
835 | struct ata_port *ap = ata_shost_to_port(shost); | |
836 | void __iomem *port_mmio = ahci_port_base(ap); | |
837 | ||
838 | return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); | |
839 | } | |
840 | ||
d447df14 TH |
841 | /** |
842 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 843 | * @pdev: target PCI device |
4447d351 | 844 | * @hpriv: host private area to store config values |
d447df14 TH |
845 | * |
846 | * Some registers containing configuration info might be setup by | |
847 | * BIOS and might be cleared on reset. This function saves the | |
848 | * initial values of those registers into @hpriv such that they | |
849 | * can be restored after controller reset. | |
850 | * | |
851 | * If inconsistent, config values are fixed up by this function. | |
852 | * | |
853 | * LOCKING: | |
854 | * None. | |
855 | */ | |
4447d351 | 856 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 857 | struct ahci_host_priv *hpriv) |
d447df14 | 858 | { |
d8993349 | 859 | void __iomem *mmio = hpriv->mmio; |
4c521c8e | 860 | u32 cap, cap2, vers, port_map; |
17199b18 | 861 | int i; |
c40e7cb8 | 862 | int mv; |
d447df14 | 863 | |
b710a1f4 TH |
864 | /* make sure AHCI mode is enabled before accessing CAP */ |
865 | ahci_enable_ahci(mmio); | |
866 | ||
d447df14 TH |
867 | /* Values prefixed with saved_ are written back to host after |
868 | * reset. Values without are used for driver operation. | |
869 | */ | |
870 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
871 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
872 | ||
4c521c8e RH |
873 | /* CAP2 register is only defined for AHCI 1.2 and later */ |
874 | vers = readl(mmio + HOST_VERSION); | |
875 | if ((vers >> 16) > 1 || | |
876 | ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) | |
877 | hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); | |
878 | else | |
879 | hpriv->saved_cap2 = cap2 = 0; | |
880 | ||
274c1fde | 881 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 882 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
883 | dev_printk(KERN_INFO, &pdev->dev, |
884 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
885 | cap &= ~HOST_CAP_64; | |
886 | } | |
887 | ||
417a1a6d | 888 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
889 | dev_printk(KERN_INFO, &pdev->dev, |
890 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
891 | cap &= ~HOST_CAP_NCQ; | |
892 | } | |
893 | ||
e297d99e TH |
894 | if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { |
895 | dev_printk(KERN_INFO, &pdev->dev, | |
896 | "controller can do NCQ, turning on CAP_NCQ\n"); | |
897 | cap |= HOST_CAP_NCQ; | |
898 | } | |
899 | ||
258cd846 | 900 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
6949b914 TH |
901 | dev_printk(KERN_INFO, &pdev->dev, |
902 | "controller can't do PMP, turning off CAP_PMP\n"); | |
903 | cap &= ~HOST_CAP_PMP; | |
904 | } | |
905 | ||
1b677afd SL |
906 | if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { |
907 | dev_printk(KERN_INFO, &pdev->dev, | |
908 | "controller can't do SNTF, turning off CAP_SNTF\n"); | |
909 | cap &= ~HOST_CAP_SNTF; | |
910 | } | |
911 | ||
d799e083 TH |
912 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && |
913 | port_map != 1) { | |
914 | dev_printk(KERN_INFO, &pdev->dev, | |
915 | "JMB361 has only one port, port_map 0x%x -> 0x%x\n", | |
916 | port_map, 1); | |
917 | port_map = 1; | |
918 | } | |
919 | ||
cd70c266 JG |
920 | /* |
921 | * Temporary Marvell 6145 hack: PATA port presence | |
922 | * is asserted through the standard AHCI port | |
923 | * presence register, as bit 4 (counting from 0) | |
924 | */ | |
417a1a6d | 925 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
926 | if (pdev->device == 0x6121) |
927 | mv = 0x3; | |
928 | else | |
929 | mv = 0xf; | |
cd70c266 JG |
930 | dev_printk(KERN_ERR, &pdev->dev, |
931 | "MV_AHCI HACK: port_map %x -> %x\n", | |
c40e7cb8 JAR |
932 | port_map, |
933 | port_map & mv); | |
5b66c829 AC |
934 | dev_printk(KERN_ERR, &pdev->dev, |
935 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
cd70c266 | 936 | |
c40e7cb8 | 937 | port_map &= mv; |
cd70c266 JG |
938 | } |
939 | ||
17199b18 | 940 | /* cross check port_map and cap.n_ports */ |
7a234aff | 941 | if (port_map) { |
837f5f8f | 942 | int map_ports = 0; |
17199b18 | 943 | |
837f5f8f TH |
944 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
945 | if (port_map & (1 << i)) | |
946 | map_ports++; | |
17199b18 | 947 | |
837f5f8f TH |
948 | /* If PI has more ports than n_ports, whine, clear |
949 | * port_map and let it be generated from n_ports. | |
17199b18 | 950 | */ |
837f5f8f | 951 | if (map_ports > ahci_nr_ports(cap)) { |
4447d351 | 952 | dev_printk(KERN_WARNING, &pdev->dev, |
837f5f8f TH |
953 | "implemented port map (0x%x) contains more " |
954 | "ports than nr_ports (%u), using nr_ports\n", | |
955 | port_map, ahci_nr_ports(cap)); | |
7a234aff TH |
956 | port_map = 0; |
957 | } | |
958 | } | |
959 | ||
960 | /* fabricate port_map from cap.nr_ports */ | |
961 | if (!port_map) { | |
17199b18 | 962 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
963 | dev_printk(KERN_WARNING, &pdev->dev, |
964 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
965 | ||
966 | /* write the fixed up value to the PI register */ | |
967 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
968 | } |
969 | ||
d447df14 TH |
970 | /* record values to use during operation */ |
971 | hpriv->cap = cap; | |
4c521c8e | 972 | hpriv->cap2 = cap2; |
d447df14 TH |
973 | hpriv->port_map = port_map; |
974 | } | |
975 | ||
976 | /** | |
977 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 978 | * @host: target ATA host |
d447df14 TH |
979 | * |
980 | * Restore initial config stored by ahci_save_initial_config(). | |
981 | * | |
982 | * LOCKING: | |
983 | * None. | |
984 | */ | |
4447d351 | 985 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 986 | { |
4447d351 | 987 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 988 | void __iomem *mmio = hpriv->mmio; |
4447d351 | 989 | |
d447df14 | 990 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
4c521c8e RH |
991 | if (hpriv->saved_cap2) |
992 | writel(hpriv->saved_cap2, mmio + HOST_CAP2); | |
d447df14 TH |
993 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
994 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
995 | } | |
996 | ||
203ef6c4 | 997 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 998 | { |
203ef6c4 TH |
999 | static const int offset[] = { |
1000 | [SCR_STATUS] = PORT_SCR_STAT, | |
1001 | [SCR_CONTROL] = PORT_SCR_CTL, | |
1002 | [SCR_ERROR] = PORT_SCR_ERR, | |
1003 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
1004 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
1005 | }; | |
1006 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 1007 | |
203ef6c4 TH |
1008 | if (sc_reg < ARRAY_SIZE(offset) && |
1009 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
1010 | return offset[sc_reg]; | |
da3dbb17 | 1011 | return 0; |
1da177e4 LT |
1012 | } |
1013 | ||
82ef04fb | 1014 | static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 | 1015 | { |
82ef04fb TH |
1016 | void __iomem *port_mmio = ahci_port_base(link->ap); |
1017 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
203ef6c4 TH |
1018 | |
1019 | if (offset) { | |
1020 | *val = readl(port_mmio + offset); | |
1021 | return 0; | |
1da177e4 | 1022 | } |
203ef6c4 TH |
1023 | return -EINVAL; |
1024 | } | |
1da177e4 | 1025 | |
82ef04fb | 1026 | static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
203ef6c4 | 1027 | { |
82ef04fb TH |
1028 | void __iomem *port_mmio = ahci_port_base(link->ap); |
1029 | int offset = ahci_scr_offset(link->ap, sc_reg); | |
203ef6c4 TH |
1030 | |
1031 | if (offset) { | |
1032 | writel(val, port_mmio + offset); | |
1033 | return 0; | |
1034 | } | |
1035 | return -EINVAL; | |
1da177e4 LT |
1036 | } |
1037 | ||
4447d351 | 1038 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 1039 | { |
4447d351 | 1040 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
1041 | u32 tmp; |
1042 | ||
d8fcd116 | 1043 | /* start DMA */ |
9f592056 | 1044 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
1045 | tmp |= PORT_CMD_START; |
1046 | writel(tmp, port_mmio + PORT_CMD); | |
1047 | readl(port_mmio + PORT_CMD); /* flush */ | |
1048 | } | |
1049 | ||
4447d351 | 1050 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 1051 | { |
4447d351 | 1052 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
1053 | u32 tmp; |
1054 | ||
1055 | tmp = readl(port_mmio + PORT_CMD); | |
1056 | ||
d8fcd116 | 1057 | /* check if the HBA is idle */ |
254950cd TH |
1058 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
1059 | return 0; | |
1060 | ||
d8fcd116 | 1061 | /* setting HBA to idle */ |
254950cd TH |
1062 | tmp &= ~PORT_CMD_START; |
1063 | writel(tmp, port_mmio + PORT_CMD); | |
1064 | ||
d8fcd116 | 1065 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 1066 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 1067 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 1068 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
1069 | return -EIO; |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
4447d351 | 1074 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 1075 | { |
4447d351 TH |
1076 | void __iomem *port_mmio = ahci_port_base(ap); |
1077 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1078 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
1079 | u32 tmp; |
1080 | ||
1081 | /* set FIS registers */ | |
4447d351 TH |
1082 | if (hpriv->cap & HOST_CAP_64) |
1083 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
1084 | port_mmio + PORT_LST_ADDR_HI); | |
1085 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 1086 | |
4447d351 TH |
1087 | if (hpriv->cap & HOST_CAP_64) |
1088 | writel((pp->rx_fis_dma >> 16) >> 16, | |
1089 | port_mmio + PORT_FIS_ADDR_HI); | |
1090 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
1091 | |
1092 | /* enable FIS reception */ | |
1093 | tmp = readl(port_mmio + PORT_CMD); | |
1094 | tmp |= PORT_CMD_FIS_RX; | |
1095 | writel(tmp, port_mmio + PORT_CMD); | |
1096 | ||
1097 | /* flush */ | |
1098 | readl(port_mmio + PORT_CMD); | |
1099 | } | |
1100 | ||
4447d351 | 1101 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 1102 | { |
4447d351 | 1103 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
1104 | u32 tmp; |
1105 | ||
1106 | /* disable FIS reception */ | |
1107 | tmp = readl(port_mmio + PORT_CMD); | |
1108 | tmp &= ~PORT_CMD_FIS_RX; | |
1109 | writel(tmp, port_mmio + PORT_CMD); | |
1110 | ||
1111 | /* wait for completion, spec says 500ms, give it 1000 */ | |
1112 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
1113 | PORT_CMD_FIS_ON, 10, 1000); | |
1114 | if (tmp & PORT_CMD_FIS_ON) | |
1115 | return -EBUSY; | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
4447d351 | 1120 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 1121 | { |
4447d351 TH |
1122 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1123 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
1124 | u32 cmd; |
1125 | ||
1126 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1127 | ||
1128 | /* spin up device */ | |
4447d351 | 1129 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
1130 | cmd |= PORT_CMD_SPIN_UP; |
1131 | writel(cmd, port_mmio + PORT_CMD); | |
1132 | } | |
1133 | ||
1134 | /* wake up link */ | |
1135 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
1136 | } | |
1137 | ||
31556594 KCA |
1138 | static void ahci_disable_alpm(struct ata_port *ap) |
1139 | { | |
1140 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1141 | void __iomem *port_mmio = ahci_port_base(ap); | |
1142 | u32 cmd; | |
1143 | struct ahci_port_priv *pp = ap->private_data; | |
1144 | ||
1145 | /* IPM bits should be disabled by libata-core */ | |
1146 | /* get the existing command bits */ | |
1147 | cmd = readl(port_mmio + PORT_CMD); | |
1148 | ||
1149 | /* disable ALPM and ASP */ | |
1150 | cmd &= ~PORT_CMD_ASP; | |
1151 | cmd &= ~PORT_CMD_ALPE; | |
1152 | ||
1153 | /* force the interface back to active */ | |
1154 | cmd |= PORT_CMD_ICC_ACTIVE; | |
1155 | ||
1156 | /* write out new cmd value */ | |
1157 | writel(cmd, port_mmio + PORT_CMD); | |
1158 | cmd = readl(port_mmio + PORT_CMD); | |
1159 | ||
1160 | /* wait 10ms to be sure we've come out of any low power state */ | |
1161 | msleep(10); | |
1162 | ||
1163 | /* clear out any PhyRdy stuff from interrupt status */ | |
1164 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
1165 | ||
1166 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
82ef04fb | 1167 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
31556594 KCA |
1168 | |
1169 | /* | |
1170 | * Clear flag to indicate that we should ignore all PhyRdy | |
1171 | * state changes | |
1172 | */ | |
1173 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
1174 | ||
1175 | /* | |
1176 | * Enable interrupts on Phy Ready. | |
1177 | */ | |
1178 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
1179 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
1180 | ||
1181 | /* | |
1182 | * don't change the link pm policy - we can be called | |
1183 | * just to turn of link pm temporarily | |
1184 | */ | |
1185 | } | |
1186 | ||
1187 | static int ahci_enable_alpm(struct ata_port *ap, | |
1188 | enum link_pm policy) | |
1189 | { | |
1190 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1191 | void __iomem *port_mmio = ahci_port_base(ap); | |
1192 | u32 cmd; | |
1193 | struct ahci_port_priv *pp = ap->private_data; | |
1194 | u32 asp; | |
1195 | ||
1196 | /* Make sure the host is capable of link power management */ | |
1197 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
1198 | return -EINVAL; | |
1199 | ||
1200 | switch (policy) { | |
1201 | case MAX_PERFORMANCE: | |
1202 | case NOT_AVAILABLE: | |
1203 | /* | |
1204 | * if we came here with NOT_AVAILABLE, | |
1205 | * it just means this is the first time we | |
1206 | * have tried to enable - default to max performance, | |
1207 | * and let the user go to lower power modes on request. | |
1208 | */ | |
1209 | ahci_disable_alpm(ap); | |
1210 | return 0; | |
1211 | case MIN_POWER: | |
1212 | /* configure HBA to enter SLUMBER */ | |
1213 | asp = PORT_CMD_ASP; | |
1214 | break; | |
1215 | case MEDIUM_POWER: | |
1216 | /* configure HBA to enter PARTIAL */ | |
1217 | asp = 0; | |
1218 | break; | |
1219 | default: | |
1220 | return -EINVAL; | |
1221 | } | |
1222 | ||
1223 | /* | |
1224 | * Disable interrupts on Phy Ready. This keeps us from | |
1225 | * getting woken up due to spurious phy ready interrupts | |
1226 | * TBD - Hot plug should be done via polling now, is | |
1227 | * that even supported? | |
1228 | */ | |
1229 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
1230 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
1231 | ||
1232 | /* | |
1233 | * Set a flag to indicate that we should ignore all PhyRdy | |
1234 | * state changes since these can happen now whenever we | |
1235 | * change link state | |
1236 | */ | |
1237 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
1238 | ||
1239 | /* get the existing command bits */ | |
1240 | cmd = readl(port_mmio + PORT_CMD); | |
1241 | ||
1242 | /* | |
1243 | * Set ASP based on Policy | |
1244 | */ | |
1245 | cmd |= asp; | |
1246 | ||
1247 | /* | |
1248 | * Setting this bit will instruct the HBA to aggressively | |
1249 | * enter a lower power link state when it's appropriate and | |
1250 | * based on the value set above for ASP | |
1251 | */ | |
1252 | cmd |= PORT_CMD_ALPE; | |
1253 | ||
1254 | /* write out new cmd value */ | |
1255 | writel(cmd, port_mmio + PORT_CMD); | |
1256 | cmd = readl(port_mmio + PORT_CMD); | |
1257 | ||
1258 | /* IPM bits should be set by libata-core */ | |
1259 | return 0; | |
1260 | } | |
1261 | ||
438ac6d5 | 1262 | #ifdef CONFIG_PM |
4447d351 | 1263 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 1264 | { |
4447d351 TH |
1265 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1266 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
1267 | u32 cmd, scontrol; |
1268 | ||
4447d351 | 1269 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 1270 | return; |
0be0aa98 | 1271 | |
07c53dac TH |
1272 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
1273 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
1274 | scontrol &= ~0xf; | |
1275 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 1276 | |
07c53dac TH |
1277 | /* then set PxCMD.SUD to 0 */ |
1278 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1279 | cmd &= ~PORT_CMD_SPIN_UP; | |
1280 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 1281 | } |
438ac6d5 | 1282 | #endif |
0be0aa98 | 1283 | |
df69c9c5 | 1284 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 1285 | { |
18f7ba4c KCA |
1286 | struct ahci_port_priv *pp = ap->private_data; |
1287 | struct ata_link *link; | |
1288 | struct ahci_em_priv *emp; | |
4c1e9aa4 DM |
1289 | ssize_t rc; |
1290 | int i; | |
18f7ba4c | 1291 | |
0be0aa98 | 1292 | /* enable FIS reception */ |
4447d351 | 1293 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
1294 | |
1295 | /* enable DMA */ | |
4447d351 | 1296 | ahci_start_engine(ap); |
18f7ba4c KCA |
1297 | |
1298 | /* turn on LEDs */ | |
1299 | if (ap->flags & ATA_FLAG_EM) { | |
1eca4365 | 1300 | ata_for_each_link(link, ap, EDGE) { |
18f7ba4c | 1301 | emp = &pp->em_priv[link->pmp]; |
4c1e9aa4 DM |
1302 | |
1303 | /* EM Transmit bit maybe busy during init */ | |
d50ce07d | 1304 | for (i = 0; i < EM_MAX_RETRY; i++) { |
4c1e9aa4 DM |
1305 | rc = ahci_transmit_led_message(ap, |
1306 | emp->led_state, | |
1307 | 4); | |
1308 | if (rc == -EBUSY) | |
d50ce07d | 1309 | msleep(1); |
4c1e9aa4 DM |
1310 | else |
1311 | break; | |
1312 | } | |
18f7ba4c KCA |
1313 | } |
1314 | } | |
1315 | ||
1316 | if (ap->flags & ATA_FLAG_SW_ACTIVITY) | |
1eca4365 | 1317 | ata_for_each_link(link, ap, EDGE) |
18f7ba4c KCA |
1318 | ahci_init_sw_activity(link); |
1319 | ||
0be0aa98 TH |
1320 | } |
1321 | ||
4447d351 | 1322 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
1323 | { |
1324 | int rc; | |
1325 | ||
1326 | /* disable DMA */ | |
4447d351 | 1327 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1328 | if (rc) { |
1329 | *emsg = "failed to stop engine"; | |
1330 | return rc; | |
1331 | } | |
1332 | ||
1333 | /* disable FIS reception */ | |
4447d351 | 1334 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1335 | if (rc) { |
1336 | *emsg = "failed stop FIS RX"; | |
1337 | return rc; | |
1338 | } | |
1339 | ||
0be0aa98 TH |
1340 | return 0; |
1341 | } | |
1342 | ||
4447d351 | 1343 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1344 | { |
4447d351 | 1345 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1346 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 1347 | void __iomem *mmio = hpriv->mmio; |
d447df14 | 1348 | u32 tmp; |
d91542c1 | 1349 | |
3cc3eb11 JG |
1350 | /* we must be in AHCI mode, before using anything |
1351 | * AHCI-specific, such as HOST_RESET. | |
1352 | */ | |
b710a1f4 | 1353 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1354 | |
1355 | /* global controller reset */ | |
a22e6444 TH |
1356 | if (!ahci_skip_host_reset) { |
1357 | tmp = readl(mmio + HOST_CTL); | |
1358 | if ((tmp & HOST_RESET) == 0) { | |
1359 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1360 | readl(mmio + HOST_CTL); /* flush */ | |
1361 | } | |
d91542c1 | 1362 | |
24920c8a ZR |
1363 | /* |
1364 | * to perform host reset, OS should set HOST_RESET | |
1365 | * and poll until this bit is read to be "0". | |
1366 | * reset must complete within 1 second, or | |
a22e6444 TH |
1367 | * the hardware should be considered fried. |
1368 | */ | |
24920c8a ZR |
1369 | tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, |
1370 | HOST_RESET, 10, 1000); | |
d91542c1 | 1371 | |
a22e6444 TH |
1372 | if (tmp & HOST_RESET) { |
1373 | dev_printk(KERN_ERR, host->dev, | |
1374 | "controller reset failed (0x%x)\n", tmp); | |
1375 | return -EIO; | |
1376 | } | |
d91542c1 | 1377 | |
a22e6444 TH |
1378 | /* turn on AHCI mode */ |
1379 | ahci_enable_ahci(mmio); | |
98fa4b60 | 1380 | |
a22e6444 TH |
1381 | /* Some registers might be cleared on reset. Restore |
1382 | * initial values. | |
1383 | */ | |
1384 | ahci_restore_initial_config(host); | |
1385 | } else | |
1386 | dev_printk(KERN_INFO, host->dev, | |
1387 | "skipping global host reset\n"); | |
d91542c1 TH |
1388 | |
1389 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1390 | u16 tmp16; | |
1391 | ||
1392 | /* configure PCS */ | |
1393 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1394 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1395 | tmp16 |= hpriv->port_map; | |
1396 | pci_write_config_word(pdev, 0x92, tmp16); | |
1397 | } | |
d91542c1 TH |
1398 | } |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
18f7ba4c KCA |
1403 | static void ahci_sw_activity(struct ata_link *link) |
1404 | { | |
1405 | struct ata_port *ap = link->ap; | |
1406 | struct ahci_port_priv *pp = ap->private_data; | |
1407 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1408 | ||
1409 | if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) | |
1410 | return; | |
1411 | ||
1412 | emp->activity++; | |
1413 | if (!timer_pending(&emp->timer)) | |
1414 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); | |
1415 | } | |
1416 | ||
1417 | static void ahci_sw_activity_blink(unsigned long arg) | |
1418 | { | |
1419 | struct ata_link *link = (struct ata_link *)arg; | |
1420 | struct ata_port *ap = link->ap; | |
1421 | struct ahci_port_priv *pp = ap->private_data; | |
1422 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1423 | unsigned long led_message = emp->led_state; | |
1424 | u32 activity_led_state; | |
eb40963c | 1425 | unsigned long flags; |
18f7ba4c | 1426 | |
87943acf | 1427 | led_message &= EM_MSG_LED_VALUE; |
18f7ba4c KCA |
1428 | led_message |= ap->port_no | (link->pmp << 8); |
1429 | ||
1430 | /* check to see if we've had activity. If so, | |
1431 | * toggle state of LED and reset timer. If not, | |
1432 | * turn LED to desired idle state. | |
1433 | */ | |
eb40963c | 1434 | spin_lock_irqsave(ap->lock, flags); |
18f7ba4c KCA |
1435 | if (emp->saved_activity != emp->activity) { |
1436 | emp->saved_activity = emp->activity; | |
1437 | /* get the current LED state */ | |
87943acf | 1438 | activity_led_state = led_message & EM_MSG_LED_VALUE_ON; |
18f7ba4c KCA |
1439 | |
1440 | if (activity_led_state) | |
1441 | activity_led_state = 0; | |
1442 | else | |
1443 | activity_led_state = 1; | |
1444 | ||
1445 | /* clear old state */ | |
87943acf | 1446 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1447 | |
1448 | /* toggle state */ | |
1449 | led_message |= (activity_led_state << 16); | |
1450 | mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); | |
1451 | } else { | |
1452 | /* switch to idle */ | |
87943acf | 1453 | led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1454 | if (emp->blink_policy == BLINK_OFF) |
1455 | led_message |= (1 << 16); | |
1456 | } | |
eb40963c | 1457 | spin_unlock_irqrestore(ap->lock, flags); |
18f7ba4c KCA |
1458 | ahci_transmit_led_message(ap, led_message, 4); |
1459 | } | |
1460 | ||
1461 | static void ahci_init_sw_activity(struct ata_link *link) | |
1462 | { | |
1463 | struct ata_port *ap = link->ap; | |
1464 | struct ahci_port_priv *pp = ap->private_data; | |
1465 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1466 | ||
1467 | /* init activity stats, setup timer */ | |
1468 | emp->saved_activity = emp->activity = 0; | |
1469 | setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); | |
1470 | ||
1471 | /* check our blink policy and set flag for link if it's enabled */ | |
1472 | if (emp->blink_policy) | |
1473 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1474 | } | |
1475 | ||
1476 | static int ahci_reset_em(struct ata_host *host) | |
1477 | { | |
d8993349 AV |
1478 | struct ahci_host_priv *hpriv = host->private_data; |
1479 | void __iomem *mmio = hpriv->mmio; | |
18f7ba4c KCA |
1480 | u32 em_ctl; |
1481 | ||
1482 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1483 | if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) | |
1484 | return -EINVAL; | |
1485 | ||
1486 | writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, | |
1491 | ssize_t size) | |
1492 | { | |
1493 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1494 | struct ahci_port_priv *pp = ap->private_data; | |
d8993349 | 1495 | void __iomem *mmio = hpriv->mmio; |
18f7ba4c KCA |
1496 | u32 em_ctl; |
1497 | u32 message[] = {0, 0}; | |
93082f0b | 1498 | unsigned long flags; |
18f7ba4c KCA |
1499 | int pmp; |
1500 | struct ahci_em_priv *emp; | |
1501 | ||
1502 | /* get the slot number from the message */ | |
87943acf | 1503 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
d50ce07d | 1504 | if (pmp < EM_MAX_SLOTS) |
18f7ba4c KCA |
1505 | emp = &pp->em_priv[pmp]; |
1506 | else | |
1507 | return -EINVAL; | |
1508 | ||
1509 | spin_lock_irqsave(ap->lock, flags); | |
1510 | ||
1511 | /* | |
1512 | * if we are still busy transmitting a previous message, | |
1513 | * do not allow | |
1514 | */ | |
1515 | em_ctl = readl(mmio + HOST_EM_CTL); | |
1516 | if (em_ctl & EM_CTL_TM) { | |
1517 | spin_unlock_irqrestore(ap->lock, flags); | |
4c1e9aa4 | 1518 | return -EBUSY; |
18f7ba4c KCA |
1519 | } |
1520 | ||
1521 | /* | |
1522 | * create message header - this is all zero except for | |
1523 | * the message size, which is 4 bytes. | |
1524 | */ | |
1525 | message[0] |= (4 << 8); | |
1526 | ||
1527 | /* ignore 0:4 of byte zero, fill in port info yourself */ | |
87943acf | 1528 | message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); |
18f7ba4c KCA |
1529 | |
1530 | /* write message to EM_LOC */ | |
1531 | writel(message[0], mmio + hpriv->em_loc); | |
1532 | writel(message[1], mmio + hpriv->em_loc+4); | |
1533 | ||
1534 | /* save off new led state for port/slot */ | |
208f2a88 | 1535 | emp->led_state = state; |
18f7ba4c KCA |
1536 | |
1537 | /* | |
1538 | * tell hardware to transmit the message | |
1539 | */ | |
1540 | writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); | |
1541 | ||
1542 | spin_unlock_irqrestore(ap->lock, flags); | |
1543 | return size; | |
1544 | } | |
1545 | ||
1546 | static ssize_t ahci_led_show(struct ata_port *ap, char *buf) | |
1547 | { | |
1548 | struct ahci_port_priv *pp = ap->private_data; | |
1549 | struct ata_link *link; | |
1550 | struct ahci_em_priv *emp; | |
1551 | int rc = 0; | |
1552 | ||
1eca4365 | 1553 | ata_for_each_link(link, ap, EDGE) { |
18f7ba4c KCA |
1554 | emp = &pp->em_priv[link->pmp]; |
1555 | rc += sprintf(buf, "%lx\n", emp->led_state); | |
1556 | } | |
1557 | return rc; | |
1558 | } | |
1559 | ||
1560 | static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, | |
1561 | size_t size) | |
1562 | { | |
1563 | int state; | |
1564 | int pmp; | |
1565 | struct ahci_port_priv *pp = ap->private_data; | |
1566 | struct ahci_em_priv *emp; | |
1567 | ||
1568 | state = simple_strtoul(buf, NULL, 0); | |
1569 | ||
1570 | /* get the slot number from the message */ | |
87943acf | 1571 | pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
d50ce07d | 1572 | if (pmp < EM_MAX_SLOTS) |
18f7ba4c KCA |
1573 | emp = &pp->em_priv[pmp]; |
1574 | else | |
1575 | return -EINVAL; | |
1576 | ||
1577 | /* mask off the activity bits if we are in sw_activity | |
1578 | * mode, user should turn off sw_activity before setting | |
1579 | * activity led through em_message | |
1580 | */ | |
1581 | if (emp->blink_policy) | |
87943acf | 1582 | state &= ~EM_MSG_LED_VALUE_ACTIVITY; |
18f7ba4c KCA |
1583 | |
1584 | return ahci_transmit_led_message(ap, state, size); | |
1585 | } | |
1586 | ||
1587 | static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) | |
1588 | { | |
1589 | struct ata_link *link = dev->link; | |
1590 | struct ata_port *ap = link->ap; | |
1591 | struct ahci_port_priv *pp = ap->private_data; | |
1592 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1593 | u32 port_led_state = emp->led_state; | |
1594 | ||
1595 | /* save the desired Activity LED behavior */ | |
1596 | if (val == OFF) { | |
1597 | /* clear LFLAG */ | |
1598 | link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); | |
1599 | ||
1600 | /* set the LED to OFF */ | |
87943acf | 1601 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
18f7ba4c KCA |
1602 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
1603 | ahci_transmit_led_message(ap, port_led_state, 4); | |
1604 | } else { | |
1605 | link->flags |= ATA_LFLAG_SW_ACTIVITY; | |
1606 | if (val == BLINK_OFF) { | |
1607 | /* set LED to ON for idle */ | |
87943acf | 1608 | port_led_state &= EM_MSG_LED_VALUE_OFF; |
18f7ba4c | 1609 | port_led_state |= (ap->port_no | (link->pmp << 8)); |
87943acf | 1610 | port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ |
18f7ba4c KCA |
1611 | ahci_transmit_led_message(ap, port_led_state, 4); |
1612 | } | |
1613 | } | |
1614 | emp->blink_policy = val; | |
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) | |
1619 | { | |
1620 | struct ata_link *link = dev->link; | |
1621 | struct ata_port *ap = link->ap; | |
1622 | struct ahci_port_priv *pp = ap->private_data; | |
1623 | struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; | |
1624 | ||
1625 | /* display the saved value of activity behavior for this | |
1626 | * disk. | |
1627 | */ | |
1628 | return sprintf(buf, "%d\n", emp->blink_policy); | |
1629 | } | |
1630 | ||
2bcd866b JG |
1631 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1632 | int port_no, void __iomem *mmio, | |
1633 | void __iomem *port_mmio) | |
1634 | { | |
1635 | const char *emsg = NULL; | |
1636 | int rc; | |
1637 | u32 tmp; | |
1638 | ||
1639 | /* make sure port is not active */ | |
1640 | rc = ahci_deinit_port(ap, &emsg); | |
1641 | if (rc) | |
1642 | dev_printk(KERN_WARNING, &pdev->dev, | |
1643 | "%s (%d)\n", emsg, rc); | |
1644 | ||
1645 | /* clear SError */ | |
1646 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1647 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1648 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1649 | ||
1650 | /* clear port IRQ */ | |
1651 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1652 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1653 | if (tmp) | |
1654 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1655 | ||
1656 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1657 | } | |
1658 | ||
4447d351 | 1659 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1660 | { |
417a1a6d | 1661 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1662 | struct pci_dev *pdev = to_pci_dev(host->dev); |
d8993349 | 1663 | void __iomem *mmio = hpriv->mmio; |
2bcd866b | 1664 | int i; |
cd70c266 | 1665 | void __iomem *port_mmio; |
d91542c1 | 1666 | u32 tmp; |
c40e7cb8 | 1667 | int mv; |
d91542c1 | 1668 | |
417a1a6d | 1669 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
1670 | if (pdev->device == 0x6121) |
1671 | mv = 2; | |
1672 | else | |
1673 | mv = 4; | |
1674 | port_mmio = __ahci_port_base(host, mv); | |
cd70c266 JG |
1675 | |
1676 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1677 | ||
1678 | /* clear port IRQ */ | |
1679 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1680 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1681 | if (tmp) | |
1682 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1683 | } | |
1684 | ||
4447d351 TH |
1685 | for (i = 0; i < host->n_ports; i++) { |
1686 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1687 | |
cd70c266 | 1688 | port_mmio = ahci_port_base(ap); |
4447d351 | 1689 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1690 | continue; |
d91542c1 | 1691 | |
2bcd866b | 1692 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1693 | } |
1694 | ||
1695 | tmp = readl(mmio + HOST_CTL); | |
1696 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1697 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1698 | tmp = readl(mmio + HOST_CTL); | |
1699 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1700 | } | |
1701 | ||
a878539e JG |
1702 | static void ahci_dev_config(struct ata_device *dev) |
1703 | { | |
1704 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1705 | ||
4cde32fc | 1706 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
a878539e | 1707 | dev->max_sectors = 255; |
4cde32fc JG |
1708 | ata_dev_printk(dev, KERN_INFO, |
1709 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
1710 | } | |
a878539e JG |
1711 | } |
1712 | ||
422b7595 | 1713 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1714 | { |
4447d351 | 1715 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1716 | struct ata_taskfile tf; |
422b7595 TH |
1717 | u32 tmp; |
1718 | ||
1719 | tmp = readl(port_mmio + PORT_SIG); | |
1720 | tf.lbah = (tmp >> 24) & 0xff; | |
1721 | tf.lbam = (tmp >> 16) & 0xff; | |
1722 | tf.lbal = (tmp >> 8) & 0xff; | |
1723 | tf.nsect = (tmp) & 0xff; | |
1724 | ||
1725 | return ata_dev_classify(&tf); | |
1726 | } | |
1727 | ||
12fad3f9 TH |
1728 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1729 | u32 opts) | |
cc9278ed | 1730 | { |
12fad3f9 TH |
1731 | dma_addr_t cmd_tbl_dma; |
1732 | ||
1733 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1734 | ||
1735 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1736 | pp->cmd_slot[tag].status = 0; | |
1737 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1738 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1739 | } |
1740 | ||
78d5ae39 | 1741 | static int ahci_kick_engine(struct ata_port *ap) |
4658f79b | 1742 | { |
350756f6 | 1743 | void __iomem *port_mmio = ahci_port_base(ap); |
cca3974e | 1744 | struct ahci_host_priv *hpriv = ap->host->private_data; |
520d06f9 | 1745 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
bf2af2a2 | 1746 | u32 tmp; |
d2e75dff | 1747 | int busy, rc; |
bf2af2a2 | 1748 | |
d2e75dff TH |
1749 | /* stop engine */ |
1750 | rc = ahci_stop_engine(ap); | |
1751 | if (rc) | |
1752 | goto out_restart; | |
1753 | ||
78d5ae39 SH |
1754 | /* need to do CLO? |
1755 | * always do CLO if PMP is attached (AHCI-1.3 9.2) | |
1756 | */ | |
1757 | busy = status & (ATA_BUSY | ATA_DRQ); | |
1758 | if (!busy && !sata_pmp_attached(ap)) { | |
d2e75dff TH |
1759 | rc = 0; |
1760 | goto out_restart; | |
1761 | } | |
1762 | ||
1763 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1764 | rc = -EOPNOTSUPP; | |
1765 | goto out_restart; | |
1766 | } | |
bf2af2a2 | 1767 | |
d2e75dff | 1768 | /* perform CLO */ |
bf2af2a2 BJ |
1769 | tmp = readl(port_mmio + PORT_CMD); |
1770 | tmp |= PORT_CMD_CLO; | |
1771 | writel(tmp, port_mmio + PORT_CMD); | |
1772 | ||
d2e75dff | 1773 | rc = 0; |
bf2af2a2 BJ |
1774 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1775 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1776 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1777 | rc = -EIO; |
bf2af2a2 | 1778 | |
d2e75dff TH |
1779 | /* restart engine */ |
1780 | out_restart: | |
1781 | ahci_start_engine(ap); | |
1782 | return rc; | |
bf2af2a2 BJ |
1783 | } |
1784 | ||
91c4a2e0 TH |
1785 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1786 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1787 | unsigned long timeout_msec) | |
bf2af2a2 | 1788 | { |
91c4a2e0 | 1789 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1790 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1791 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1792 | u8 *fis = pp->cmd_tbl; |
1793 | u32 tmp; | |
1794 | ||
1795 | /* prep the command */ | |
1796 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1797 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1798 | ||
1799 | /* issue & wait */ | |
1800 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1801 | ||
1802 | if (timeout_msec) { | |
1803 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1804 | 1, timeout_msec); | |
1805 | if (tmp & 0x1) { | |
78d5ae39 | 1806 | ahci_kick_engine(ap); |
91c4a2e0 TH |
1807 | return -EBUSY; |
1808 | } | |
1809 | } else | |
1810 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
bd17243a SH |
1815 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
1816 | int pmp, unsigned long deadline, | |
1817 | int (*check_ready)(struct ata_link *link)) | |
91c4a2e0 | 1818 | { |
cc0680a5 | 1819 | struct ata_port *ap = link->ap; |
5594639a | 1820 | struct ahci_host_priv *hpriv = ap->host->private_data; |
4658f79b | 1821 | const char *reason = NULL; |
2cbb79eb | 1822 | unsigned long now, msecs; |
4658f79b | 1823 | struct ata_taskfile tf; |
4658f79b TH |
1824 | int rc; |
1825 | ||
1826 | DPRINTK("ENTER\n"); | |
1827 | ||
1828 | /* prepare for SRST (AHCI-1.1 10.4.1) */ | |
78d5ae39 | 1829 | rc = ahci_kick_engine(ap); |
994056d7 | 1830 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1831 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1832 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1833 | |
cc0680a5 | 1834 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1835 | |
1836 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1837 | msecs = 0; |
1838 | now = jiffies; | |
1839 | if (time_after(now, deadline)) | |
1840 | msecs = jiffies_to_msecs(deadline - now); | |
1841 | ||
4658f79b | 1842 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1843 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1844 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1845 | rc = -EIO; |
1846 | reason = "1st FIS failed"; | |
1847 | goto fail; | |
1848 | } | |
1849 | ||
1850 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1851 | msleep(1); | |
1852 | ||
1853 | /* issue the second D2H Register FIS */ | |
4658f79b | 1854 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1855 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1856 | |
705e76be | 1857 | /* wait for link to become ready */ |
bd17243a | 1858 | rc = ata_wait_after_reset(link, deadline, check_ready); |
5594639a TH |
1859 | if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { |
1860 | /* | |
1861 | * Workaround for cases where link online status can't | |
1862 | * be trusted. Treat device readiness timeout as link | |
1863 | * offline. | |
1864 | */ | |
1865 | ata_link_printk(link, KERN_INFO, | |
1866 | "device not ready, treating as offline\n"); | |
1867 | *class = ATA_DEV_NONE; | |
1868 | } else if (rc) { | |
1869 | /* link occupied, -ENODEV too is an error */ | |
9b89391c TH |
1870 | reason = "device not ready"; |
1871 | goto fail; | |
5594639a TH |
1872 | } else |
1873 | *class = ahci_dev_classify(ap); | |
4658f79b TH |
1874 | |
1875 | DPRINTK("EXIT, class=%u\n", *class); | |
1876 | return 0; | |
1877 | ||
4658f79b | 1878 | fail: |
cc0680a5 | 1879 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1880 | return rc; |
1881 | } | |
1882 | ||
bd17243a SH |
1883 | static int ahci_check_ready(struct ata_link *link) |
1884 | { | |
1885 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1886 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1887 | ||
1888 | return ata_check_ready(status); | |
1889 | } | |
1890 | ||
1891 | static int ahci_softreset(struct ata_link *link, unsigned int *class, | |
1892 | unsigned long deadline) | |
1893 | { | |
1894 | int pmp = sata_srst_pmp(link); | |
1895 | ||
1896 | DPRINTK("ENTER\n"); | |
1897 | ||
1898 | return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); | |
1899 | } | |
1900 | ||
1901 | static int ahci_sb600_check_ready(struct ata_link *link) | |
1902 | { | |
1903 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1904 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1905 | u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); | |
1906 | ||
1907 | /* | |
1908 | * There is no need to check TFDATA if BAD PMP is found due to HW bug, | |
1909 | * which can save timeout delay. | |
1910 | */ | |
1911 | if (irq_status & PORT_IRQ_BAD_PMP) | |
1912 | return -EIO; | |
1913 | ||
1914 | return ata_check_ready(status); | |
1915 | } | |
1916 | ||
1917 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, | |
1918 | unsigned long deadline) | |
1919 | { | |
1920 | struct ata_port *ap = link->ap; | |
1921 | void __iomem *port_mmio = ahci_port_base(ap); | |
1922 | int pmp = sata_srst_pmp(link); | |
1923 | int rc; | |
1924 | u32 irq_sts; | |
1925 | ||
1926 | DPRINTK("ENTER\n"); | |
1927 | ||
1928 | rc = ahci_do_softreset(link, class, pmp, deadline, | |
1929 | ahci_sb600_check_ready); | |
1930 | ||
1931 | /* | |
1932 | * Soft reset fails on some ATI chips with IPMS set when PMP | |
1933 | * is enabled but SATA HDD/ODD is connected to SATA port, | |
1934 | * do soft reset again to port 0. | |
1935 | */ | |
1936 | if (rc == -EIO) { | |
1937 | irq_sts = readl(port_mmio + PORT_IRQ_STAT); | |
1938 | if (irq_sts & PORT_IRQ_BAD_PMP) { | |
1939 | ata_link_printk(link, KERN_WARNING, | |
b6931c1f SH |
1940 | "applying SB600 PMP SRST workaround " |
1941 | "and retrying\n"); | |
bd17243a SH |
1942 | rc = ahci_do_softreset(link, class, 0, deadline, |
1943 | ahci_check_ready); | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | return rc; | |
1948 | } | |
1949 | ||
cc0680a5 | 1950 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1951 | unsigned long deadline) |
422b7595 | 1952 | { |
9dadd45b | 1953 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
cc0680a5 | 1954 | struct ata_port *ap = link->ap; |
4296971d TH |
1955 | struct ahci_port_priv *pp = ap->private_data; |
1956 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1957 | struct ata_taskfile tf; | |
9dadd45b | 1958 | bool online; |
4bd00f6a TH |
1959 | int rc; |
1960 | ||
1961 | DPRINTK("ENTER\n"); | |
1da177e4 | 1962 | |
4447d351 | 1963 | ahci_stop_engine(ap); |
4296971d TH |
1964 | |
1965 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1966 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1967 | tf.command = 0x80; |
9977126c | 1968 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1969 | |
9dadd45b TH |
1970 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1971 | ahci_check_ready); | |
4296971d | 1972 | |
4447d351 | 1973 | ahci_start_engine(ap); |
1da177e4 | 1974 | |
9dadd45b | 1975 | if (online) |
4bd00f6a | 1976 | *class = ahci_dev_classify(ap); |
1da177e4 | 1977 | |
4bd00f6a TH |
1978 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1979 | return rc; | |
1980 | } | |
1981 | ||
cc0680a5 | 1982 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1983 | unsigned long deadline) |
ad616ffb | 1984 | { |
cc0680a5 | 1985 | struct ata_port *ap = link->ap; |
9dadd45b | 1986 | bool online; |
ad616ffb TH |
1987 | int rc; |
1988 | ||
1989 | DPRINTK("ENTER\n"); | |
1990 | ||
4447d351 | 1991 | ahci_stop_engine(ap); |
ad616ffb | 1992 | |
cc0680a5 | 1993 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
9dadd45b | 1994 | deadline, &online, NULL); |
ad616ffb | 1995 | |
4447d351 | 1996 | ahci_start_engine(ap); |
ad616ffb TH |
1997 | |
1998 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1999 | ||
2000 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
2001 | * request follow-up softreset. | |
2002 | */ | |
9dadd45b | 2003 | return online ? -EAGAIN : rc; |
ad616ffb TH |
2004 | } |
2005 | ||
edc93052 TH |
2006 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
2007 | unsigned long deadline) | |
2008 | { | |
2009 | struct ata_port *ap = link->ap; | |
2010 | struct ahci_port_priv *pp = ap->private_data; | |
2011 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
2012 | struct ata_taskfile tf; | |
9dadd45b | 2013 | bool online; |
edc93052 TH |
2014 | int rc; |
2015 | ||
2016 | ahci_stop_engine(ap); | |
2017 | ||
2018 | /* clear D2H reception area to properly wait for D2H FIS */ | |
2019 | ata_tf_init(link->device, &tf); | |
2020 | tf.command = 0x80; | |
2021 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
2022 | ||
2023 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
9dadd45b | 2024 | deadline, &online, NULL); |
edc93052 TH |
2025 | |
2026 | ahci_start_engine(ap); | |
2027 | ||
edc93052 TH |
2028 | /* The pseudo configuration device on SIMG4726 attached to |
2029 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
2030 | * hardreset if no device is attached to the first downstream | |
2031 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
2032 | * work around this, wait for !BSY only briefly. If BSY isn't | |
2033 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
2034 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
2035 | * | |
2036 | * Wait for two seconds. Devices attached to downstream port | |
2037 | * which can't process the following IDENTIFY after this will | |
2038 | * have to be reset again. For most cases, this should | |
2039 | * suffice while making probing snappish enough. | |
2040 | */ | |
9dadd45b TH |
2041 | if (online) { |
2042 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
2043 | ahci_check_ready); | |
2044 | if (rc) | |
78d5ae39 | 2045 | ahci_kick_engine(ap); |
9dadd45b | 2046 | } |
9dadd45b | 2047 | return rc; |
edc93052 TH |
2048 | } |
2049 | ||
cc0680a5 | 2050 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 2051 | { |
cc0680a5 | 2052 | struct ata_port *ap = link->ap; |
4447d351 | 2053 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
2054 | u32 new_tmp, tmp; |
2055 | ||
203c75b8 | 2056 | ata_std_postreset(link, class); |
02eaa666 JG |
2057 | |
2058 | /* Make sure port's ATAPI bit is set appropriately */ | |
2059 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 2060 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
2061 | new_tmp |= PORT_CMD_ATAPI; |
2062 | else | |
2063 | new_tmp &= ~PORT_CMD_ATAPI; | |
2064 | if (new_tmp != tmp) { | |
2065 | writel(new_tmp, port_mmio + PORT_CMD); | |
2066 | readl(port_mmio + PORT_CMD); /* flush */ | |
2067 | } | |
1da177e4 LT |
2068 | } |
2069 | ||
12fad3f9 | 2070 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 2071 | { |
cedc9a47 | 2072 | struct scatterlist *sg; |
ff2aeb1e TH |
2073 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
2074 | unsigned int si; | |
1da177e4 LT |
2075 | |
2076 | VPRINTK("ENTER\n"); | |
2077 | ||
2078 | /* | |
2079 | * Next, the S/G list. | |
2080 | */ | |
ff2aeb1e | 2081 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
2082 | dma_addr_t addr = sg_dma_address(sg); |
2083 | u32 sg_len = sg_dma_len(sg); | |
2084 | ||
ff2aeb1e TH |
2085 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
2086 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
2087 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 2088 | } |
828d09de | 2089 | |
ff2aeb1e | 2090 | return si; |
1da177e4 LT |
2091 | } |
2092 | ||
d6ef3153 SH |
2093 | static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) |
2094 | { | |
2095 | struct ata_port *ap = qc->ap; | |
2096 | struct ahci_port_priv *pp = ap->private_data; | |
2097 | ||
2098 | if (!sata_pmp_attached(ap) || pp->fbs_enabled) | |
2099 | return ata_std_qc_defer(qc); | |
2100 | else | |
2101 | return sata_pmp_qc_defer_cmd_switch(qc); | |
2102 | } | |
2103 | ||
1da177e4 LT |
2104 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
2105 | { | |
a0ea7328 JG |
2106 | struct ata_port *ap = qc->ap; |
2107 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 2108 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 2109 | void *cmd_tbl; |
1da177e4 LT |
2110 | u32 opts; |
2111 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 2112 | unsigned int n_elem; |
1da177e4 | 2113 | |
1da177e4 LT |
2114 | /* |
2115 | * Fill in command table information. First, the header, | |
2116 | * a SATA Register - Host to Device command FIS. | |
2117 | */ | |
12fad3f9 TH |
2118 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
2119 | ||
7d50b60b | 2120 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 2121 | if (is_atapi) { |
12fad3f9 TH |
2122 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
2123 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 2124 | } |
1da177e4 | 2125 | |
cc9278ed TH |
2126 | n_elem = 0; |
2127 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 2128 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 2129 | |
cc9278ed TH |
2130 | /* |
2131 | * Fill in command slot information. | |
2132 | */ | |
7d50b60b | 2133 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
2134 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
2135 | opts |= AHCI_CMD_WRITE; | |
2136 | if (is_atapi) | |
4b10e559 | 2137 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 2138 | |
12fad3f9 | 2139 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
2140 | } |
2141 | ||
d6ef3153 SH |
2142 | static void ahci_fbs_dec_intr(struct ata_port *ap) |
2143 | { | |
2144 | struct ahci_port_priv *pp = ap->private_data; | |
2145 | void __iomem *port_mmio = ahci_port_base(ap); | |
2146 | u32 fbs = readl(port_mmio + PORT_FBS); | |
2147 | int retries = 3; | |
2148 | ||
2149 | DPRINTK("ENTER\n"); | |
2150 | BUG_ON(!pp->fbs_enabled); | |
2151 | ||
2152 | /* time to wait for DEC is not specified by AHCI spec, | |
2153 | * add a retry loop for safety. | |
2154 | */ | |
2155 | writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); | |
2156 | fbs = readl(port_mmio + PORT_FBS); | |
2157 | while ((fbs & PORT_FBS_DEC) && retries--) { | |
2158 | udelay(1); | |
2159 | fbs = readl(port_mmio + PORT_FBS); | |
2160 | } | |
2161 | ||
2162 | if (fbs & PORT_FBS_DEC) | |
2163 | dev_printk(KERN_ERR, ap->host->dev, | |
2164 | "failed to clear device error\n"); | |
2165 | } | |
2166 | ||
78cd52d0 | 2167 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 2168 | { |
417a1a6d | 2169 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 2170 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
2171 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
2172 | struct ata_link *link = NULL; | |
2173 | struct ata_queued_cmd *active_qc; | |
2174 | struct ata_eh_info *active_ehi; | |
d6ef3153 | 2175 | bool fbs_need_dec = false; |
78cd52d0 | 2176 | u32 serror; |
1da177e4 | 2177 | |
d6ef3153 SH |
2178 | /* determine active link with error */ |
2179 | if (pp->fbs_enabled) { | |
2180 | void __iomem *port_mmio = ahci_port_base(ap); | |
2181 | u32 fbs = readl(port_mmio + PORT_FBS); | |
2182 | int pmp = fbs >> PORT_FBS_DWE_OFFSET; | |
2183 | ||
2184 | if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && | |
2185 | ata_link_online(&ap->pmp_link[pmp])) { | |
2186 | link = &ap->pmp_link[pmp]; | |
2187 | fbs_need_dec = true; | |
2188 | } | |
2189 | ||
2190 | } else | |
2191 | ata_for_each_link(link, ap, EDGE) | |
2192 | if (ata_link_active(link)) | |
2193 | break; | |
2194 | ||
7d50b60b TH |
2195 | if (!link) |
2196 | link = &ap->link; | |
2197 | ||
2198 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
2199 | active_ehi = &link->eh_info; | |
2200 | ||
2201 | /* record irq stat */ | |
2202 | ata_ehi_clear_desc(host_ehi); | |
2203 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 2204 | |
78cd52d0 | 2205 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
82ef04fb TH |
2206 | ahci_scr_read(&ap->link, SCR_ERROR, &serror); |
2207 | ahci_scr_write(&ap->link, SCR_ERROR, serror); | |
7d50b60b | 2208 | host_ehi->serror |= serror; |
78cd52d0 | 2209 | |
41669553 | 2210 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 2211 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
2212 | irq_stat &= ~PORT_IRQ_IF_ERR; |
2213 | ||
55a61604 | 2214 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
2215 | /* If qc is active, charge it; otherwise, the active |
2216 | * link. There's no active qc on NCQ errors. It will | |
2217 | * be determined by EH by reading log page 10h. | |
2218 | */ | |
2219 | if (active_qc) | |
2220 | active_qc->err_mask |= AC_ERR_DEV; | |
2221 | else | |
2222 | active_ehi->err_mask |= AC_ERR_DEV; | |
2223 | ||
417a1a6d | 2224 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
2225 | host_ehi->serror &= ~SERR_INTERNAL; |
2226 | } | |
2227 | ||
2228 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
2229 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
2230 | ||
2231 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 2232 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b TH |
2233 | ata_ehi_push_desc(active_ehi, |
2234 | "unknown FIS %08x %08x %08x %08x" , | |
2235 | unk[0], unk[1], unk[2], unk[3]); | |
2236 | } | |
2237 | ||
071f44b1 | 2238 | if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { |
7d50b60b | 2239 | active_ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 2240 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b | 2241 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
55a61604 | 2242 | } |
78cd52d0 TH |
2243 | |
2244 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b | 2245 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
cf480626 | 2246 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 2247 | ata_ehi_push_desc(host_ehi, "host bus error"); |
1da177e4 LT |
2248 | } |
2249 | ||
78cd52d0 | 2250 | if (irq_stat & PORT_IRQ_IF_ERR) { |
d6ef3153 SH |
2251 | if (fbs_need_dec) |
2252 | active_ehi->err_mask |= AC_ERR_DEV; | |
2253 | else { | |
2254 | host_ehi->err_mask |= AC_ERR_ATA_BUS; | |
2255 | host_ehi->action |= ATA_EH_RESET; | |
2256 | } | |
2257 | ||
7d50b60b | 2258 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
78cd52d0 | 2259 | } |
1da177e4 | 2260 | |
78cd52d0 | 2261 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
2262 | ata_ehi_hotplugged(host_ehi); |
2263 | ata_ehi_push_desc(host_ehi, "%s", | |
2264 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
2265 | "connection status changed" : "PHY RDY changed"); |
2266 | } | |
2267 | ||
78cd52d0 | 2268 | /* okay, let's hand over to EH */ |
a72ec4ce | 2269 | |
78cd52d0 TH |
2270 | if (irq_stat & PORT_IRQ_FREEZE) |
2271 | ata_port_freeze(ap); | |
d6ef3153 SH |
2272 | else if (fbs_need_dec) { |
2273 | ata_link_abort(link); | |
2274 | ahci_fbs_dec_intr(ap); | |
2275 | } else | |
78cd52d0 | 2276 | ata_port_abort(ap); |
1da177e4 LT |
2277 | } |
2278 | ||
df69c9c5 | 2279 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 2280 | { |
350756f6 | 2281 | void __iomem *port_mmio = ahci_port_base(ap); |
9af5c9c9 | 2282 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 2283 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 2284 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 2285 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
5db5b021 | 2286 | u32 status, qc_active = 0; |
459ad688 | 2287 | int rc; |
1da177e4 LT |
2288 | |
2289 | status = readl(port_mmio + PORT_IRQ_STAT); | |
2290 | writel(status, port_mmio + PORT_IRQ_STAT); | |
2291 | ||
b06ce3e5 TH |
2292 | /* ignore BAD_PMP while resetting */ |
2293 | if (unlikely(resetting)) | |
2294 | status &= ~PORT_IRQ_BAD_PMP; | |
2295 | ||
31556594 KCA |
2296 | /* If we are getting PhyRdy, this is |
2297 | * just a power state change, we should | |
2298 | * clear out this, plus the PhyRdy/Comm | |
2299 | * Wake bits from Serror | |
2300 | */ | |
2301 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
2302 | (status & PORT_IRQ_PHYRDY)) { | |
2303 | status &= ~PORT_IRQ_PHYRDY; | |
82ef04fb | 2304 | ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); |
31556594 KCA |
2305 | } |
2306 | ||
78cd52d0 TH |
2307 | if (unlikely(status & PORT_IRQ_ERROR)) { |
2308 | ahci_error_intr(ap, status); | |
2309 | return; | |
1da177e4 LT |
2310 | } |
2311 | ||
2f294968 | 2312 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
2313 | /* If SNotification is available, leave notification |
2314 | * handling to sata_async_notification(). If not, | |
2315 | * emulate it by snooping SDB FIS RX area. | |
2316 | * | |
2317 | * Snooping FIS RX area is probably cheaper than | |
2318 | * poking SNotification but some constrollers which | |
2319 | * implement SNotification, ICH9 for example, don't | |
2320 | * store AN SDB FIS into receive area. | |
2f294968 | 2321 | */ |
5f226c6b | 2322 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 2323 | sata_async_notification(ap); |
5f226c6b TH |
2324 | else { |
2325 | /* If the 'N' bit in word 0 of the FIS is set, | |
2326 | * we just received asynchronous notification. | |
2327 | * Tell libata about it. | |
d6ef3153 SH |
2328 | * |
2329 | * Lack of SNotification should not appear in | |
2330 | * ahci 1.2, so the workaround is unnecessary | |
2331 | * when FBS is enabled. | |
5f226c6b | 2332 | */ |
d6ef3153 SH |
2333 | if (pp->fbs_enabled) |
2334 | WARN_ON_ONCE(1); | |
2335 | else { | |
2336 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
2337 | u32 f0 = le32_to_cpu(f[0]); | |
2338 | if (f0 & (1 << 15)) | |
2339 | sata_async_notification(ap); | |
2340 | } | |
5f226c6b | 2341 | } |
2f294968 KCA |
2342 | } |
2343 | ||
5db5b021 SH |
2344 | /* pp->active_link is not reliable once FBS is enabled, both |
2345 | * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because | |
2346 | * NCQ and non-NCQ commands may be in flight at the same time. | |
2347 | */ | |
2348 | if (pp->fbs_enabled) { | |
2349 | if (ap->qc_active) { | |
2350 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
2351 | qc_active |= readl(port_mmio + PORT_CMD_ISSUE); | |
2352 | } | |
2353 | } else { | |
2354 | /* pp->active_link is valid iff any command is in flight */ | |
2355 | if (ap->qc_active && pp->active_link->sactive) | |
2356 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
2357 | else | |
2358 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
2359 | } | |
12fad3f9 | 2360 | |
79f97dad | 2361 | rc = ata_qc_complete_multiple(ap, qc_active); |
b06ce3e5 | 2362 | |
459ad688 TH |
2363 | /* while resetting, invalid completions are expected */ |
2364 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 | 2365 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 2366 | ehi->action |= ATA_EH_RESET; |
12fad3f9 | 2367 | ata_port_freeze(ap); |
1da177e4 | 2368 | } |
1da177e4 LT |
2369 | } |
2370 | ||
7d12e780 | 2371 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 2372 | { |
cca3974e | 2373 | struct ata_host *host = dev_instance; |
1da177e4 LT |
2374 | struct ahci_host_priv *hpriv; |
2375 | unsigned int i, handled = 0; | |
ea6ba10b | 2376 | void __iomem *mmio; |
d28f87aa | 2377 | u32 irq_stat, irq_masked; |
1da177e4 LT |
2378 | |
2379 | VPRINTK("ENTER\n"); | |
2380 | ||
cca3974e | 2381 | hpriv = host->private_data; |
d8993349 | 2382 | mmio = hpriv->mmio; |
1da177e4 LT |
2383 | |
2384 | /* sigh. 0xffffffff is a valid return from h/w */ | |
2385 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1da177e4 LT |
2386 | if (!irq_stat) |
2387 | return IRQ_NONE; | |
2388 | ||
d28f87aa TH |
2389 | irq_masked = irq_stat & hpriv->port_map; |
2390 | ||
2dcb407e | 2391 | spin_lock(&host->lock); |
1da177e4 | 2392 | |
2dcb407e | 2393 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 2394 | struct ata_port *ap; |
1da177e4 | 2395 | |
d28f87aa | 2396 | if (!(irq_masked & (1 << i))) |
67846b30 JG |
2397 | continue; |
2398 | ||
cca3974e | 2399 | ap = host->ports[i]; |
67846b30 | 2400 | if (ap) { |
df69c9c5 | 2401 | ahci_port_intr(ap); |
67846b30 JG |
2402 | VPRINTK("port %u\n", i); |
2403 | } else { | |
2404 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 2405 | if (ata_ratelimit()) |
cca3974e | 2406 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 2407 | "interrupt on disabled port %u\n", i); |
1da177e4 | 2408 | } |
67846b30 | 2409 | |
1da177e4 LT |
2410 | handled = 1; |
2411 | } | |
2412 | ||
d28f87aa TH |
2413 | /* HOST_IRQ_STAT behaves as level triggered latch meaning that |
2414 | * it should be cleared after all the port events are cleared; | |
2415 | * otherwise, it will raise a spurious interrupt after each | |
2416 | * valid one. Please read section 10.6.2 of ahci 1.1 for more | |
2417 | * information. | |
2418 | * | |
2419 | * Also, use the unmasked value to clear interrupt as spurious | |
2420 | * pending event on a dummy port might cause screaming IRQ. | |
2421 | */ | |
ea0c62f7 TH |
2422 | writel(irq_stat, mmio + HOST_IRQ_STAT); |
2423 | ||
cca3974e | 2424 | spin_unlock(&host->lock); |
1da177e4 LT |
2425 | |
2426 | VPRINTK("EXIT\n"); | |
2427 | ||
2428 | return IRQ_RETVAL(handled); | |
2429 | } | |
2430 | ||
9a3d9eb0 | 2431 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
2432 | { |
2433 | struct ata_port *ap = qc->ap; | |
4447d351 | 2434 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
2435 | struct ahci_port_priv *pp = ap->private_data; |
2436 | ||
2437 | /* Keep track of the currently active link. It will be used | |
2438 | * in completion path to determine whether NCQ phase is in | |
2439 | * progress. | |
2440 | */ | |
2441 | pp->active_link = qc->dev->link; | |
1da177e4 | 2442 | |
12fad3f9 TH |
2443 | if (qc->tf.protocol == ATA_PROT_NCQ) |
2444 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
d6ef3153 SH |
2445 | |
2446 | if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { | |
2447 | u32 fbs = readl(port_mmio + PORT_FBS); | |
2448 | fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); | |
2449 | fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; | |
2450 | writel(fbs, port_mmio + PORT_FBS); | |
2451 | pp->fbs_last_dev = qc->dev->link->pmp; | |
2452 | } | |
2453 | ||
12fad3f9 | 2454 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
1da177e4 | 2455 | |
18f7ba4c KCA |
2456 | ahci_sw_activity(qc->dev->link); |
2457 | ||
1da177e4 LT |
2458 | return 0; |
2459 | } | |
2460 | ||
4c9bf4e7 TH |
2461 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
2462 | { | |
2463 | struct ahci_port_priv *pp = qc->ap->private_data; | |
2464 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
2465 | ||
d6ef3153 SH |
2466 | if (pp->fbs_enabled) |
2467 | d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; | |
2468 | ||
4c9bf4e7 TH |
2469 | ata_tf_from_fis(d2h_fis, &qc->result_tf); |
2470 | return true; | |
2471 | } | |
2472 | ||
78cd52d0 TH |
2473 | static void ahci_freeze(struct ata_port *ap) |
2474 | { | |
4447d351 | 2475 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
2476 | |
2477 | /* turn IRQ off */ | |
2478 | writel(0, port_mmio + PORT_IRQ_MASK); | |
2479 | } | |
2480 | ||
2481 | static void ahci_thaw(struct ata_port *ap) | |
2482 | { | |
d8993349 AV |
2483 | struct ahci_host_priv *hpriv = ap->host->private_data; |
2484 | void __iomem *mmio = hpriv->mmio; | |
4447d351 | 2485 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 2486 | u32 tmp; |
a7384925 | 2487 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
2488 | |
2489 | /* clear IRQ */ | |
2490 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
2491 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 2492 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 2493 | |
1c954a4d TH |
2494 | /* turn IRQ back on */ |
2495 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
2496 | } |
2497 | ||
2498 | static void ahci_error_handler(struct ata_port *ap) | |
2499 | { | |
b51e9e5d | 2500 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 2501 | /* restart engine */ |
4447d351 TH |
2502 | ahci_stop_engine(ap); |
2503 | ahci_start_engine(ap); | |
78cd52d0 TH |
2504 | } |
2505 | ||
a1efdaba | 2506 | sata_pmp_error_handler(ap); |
edc93052 TH |
2507 | } |
2508 | ||
78cd52d0 TH |
2509 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
2510 | { | |
2511 | struct ata_port *ap = qc->ap; | |
2512 | ||
d2e75dff TH |
2513 | /* make DMA engine forget about the failed command */ |
2514 | if (qc->flags & ATA_QCFLAG_FAILED) | |
78d5ae39 | 2515 | ahci_kick_engine(ap); |
78cd52d0 TH |
2516 | } |
2517 | ||
d6ef3153 SH |
2518 | static void ahci_enable_fbs(struct ata_port *ap) |
2519 | { | |
2520 | struct ahci_port_priv *pp = ap->private_data; | |
2521 | void __iomem *port_mmio = ahci_port_base(ap); | |
2522 | u32 fbs; | |
2523 | int rc; | |
2524 | ||
2525 | if (!pp->fbs_supported) | |
2526 | return; | |
2527 | ||
2528 | fbs = readl(port_mmio + PORT_FBS); | |
2529 | if (fbs & PORT_FBS_EN) { | |
2530 | pp->fbs_enabled = true; | |
2531 | pp->fbs_last_dev = -1; /* initialization */ | |
2532 | return; | |
2533 | } | |
2534 | ||
2535 | rc = ahci_stop_engine(ap); | |
2536 | if (rc) | |
2537 | return; | |
2538 | ||
2539 | writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); | |
2540 | fbs = readl(port_mmio + PORT_FBS); | |
2541 | if (fbs & PORT_FBS_EN) { | |
2542 | dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); | |
2543 | pp->fbs_enabled = true; | |
2544 | pp->fbs_last_dev = -1; /* initialization */ | |
2545 | } else | |
2546 | dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); | |
2547 | ||
2548 | ahci_start_engine(ap); | |
2549 | } | |
2550 | ||
2551 | static void ahci_disable_fbs(struct ata_port *ap) | |
2552 | { | |
2553 | struct ahci_port_priv *pp = ap->private_data; | |
2554 | void __iomem *port_mmio = ahci_port_base(ap); | |
2555 | u32 fbs; | |
2556 | int rc; | |
2557 | ||
2558 | if (!pp->fbs_supported) | |
2559 | return; | |
2560 | ||
2561 | fbs = readl(port_mmio + PORT_FBS); | |
2562 | if ((fbs & PORT_FBS_EN) == 0) { | |
2563 | pp->fbs_enabled = false; | |
2564 | return; | |
2565 | } | |
2566 | ||
2567 | rc = ahci_stop_engine(ap); | |
2568 | if (rc) | |
2569 | return; | |
2570 | ||
2571 | writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); | |
2572 | fbs = readl(port_mmio + PORT_FBS); | |
2573 | if (fbs & PORT_FBS_EN) | |
2574 | dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); | |
2575 | else { | |
2576 | dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); | |
2577 | pp->fbs_enabled = false; | |
2578 | } | |
2579 | ||
2580 | ahci_start_engine(ap); | |
2581 | } | |
2582 | ||
7d50b60b TH |
2583 | static void ahci_pmp_attach(struct ata_port *ap) |
2584 | { | |
2585 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 2586 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
2587 | u32 cmd; |
2588 | ||
2589 | cmd = readl(port_mmio + PORT_CMD); | |
2590 | cmd |= PORT_CMD_PMP; | |
2591 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d | 2592 | |
d6ef3153 SH |
2593 | ahci_enable_fbs(ap); |
2594 | ||
1c954a4d TH |
2595 | pp->intr_mask |= PORT_IRQ_BAD_PMP; |
2596 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
2597 | } |
2598 | ||
2599 | static void ahci_pmp_detach(struct ata_port *ap) | |
2600 | { | |
2601 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 2602 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
2603 | u32 cmd; |
2604 | ||
d6ef3153 SH |
2605 | ahci_disable_fbs(ap); |
2606 | ||
7d50b60b TH |
2607 | cmd = readl(port_mmio + PORT_CMD); |
2608 | cmd &= ~PORT_CMD_PMP; | |
2609 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
2610 | |
2611 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
2612 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
2613 | } |
2614 | ||
028a2596 AD |
2615 | static int ahci_port_resume(struct ata_port *ap) |
2616 | { | |
2617 | ahci_power_up(ap); | |
2618 | ahci_start_port(ap); | |
2619 | ||
071f44b1 | 2620 | if (sata_pmp_attached(ap)) |
7d50b60b TH |
2621 | ahci_pmp_attach(ap); |
2622 | else | |
2623 | ahci_pmp_detach(ap); | |
2624 | ||
028a2596 AD |
2625 | return 0; |
2626 | } | |
2627 | ||
438ac6d5 | 2628 | #ifdef CONFIG_PM |
c1332875 TH |
2629 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
2630 | { | |
c1332875 TH |
2631 | const char *emsg = NULL; |
2632 | int rc; | |
2633 | ||
4447d351 | 2634 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 2635 | if (rc == 0) |
4447d351 | 2636 | ahci_power_down(ap); |
8e16f941 | 2637 | else { |
c1332875 | 2638 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 2639 | ahci_start_port(ap); |
c1332875 TH |
2640 | } |
2641 | ||
2642 | return rc; | |
2643 | } | |
2644 | ||
c1332875 TH |
2645 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
2646 | { | |
cca3974e | 2647 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
9b10ae86 | 2648 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 2649 | void __iomem *mmio = hpriv->mmio; |
c1332875 TH |
2650 | u32 ctl; |
2651 | ||
9b10ae86 TH |
2652 | if (mesg.event & PM_EVENT_SUSPEND && |
2653 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
2654 | dev_printk(KERN_ERR, &pdev->dev, | |
2655 | "BIOS update required for suspend/resume\n"); | |
2656 | return -EIO; | |
2657 | } | |
2658 | ||
3a2d5b70 | 2659 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
2660 | /* AHCI spec rev1.1 section 8.3.3: |
2661 | * Software must disable interrupts prior to requesting a | |
2662 | * transition of the HBA to D3 state. | |
2663 | */ | |
2664 | ctl = readl(mmio + HOST_CTL); | |
2665 | ctl &= ~HOST_IRQ_EN; | |
2666 | writel(ctl, mmio + HOST_CTL); | |
2667 | readl(mmio + HOST_CTL); /* flush */ | |
2668 | } | |
2669 | ||
2670 | return ata_pci_device_suspend(pdev, mesg); | |
2671 | } | |
2672 | ||
2673 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
2674 | { | |
cca3974e | 2675 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
2676 | int rc; |
2677 | ||
553c4aa6 TH |
2678 | rc = ata_pci_device_do_resume(pdev); |
2679 | if (rc) | |
2680 | return rc; | |
c1332875 TH |
2681 | |
2682 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 2683 | rc = ahci_reset_controller(host); |
c1332875 TH |
2684 | if (rc) |
2685 | return rc; | |
2686 | ||
4447d351 | 2687 | ahci_init_controller(host); |
c1332875 TH |
2688 | } |
2689 | ||
cca3974e | 2690 | ata_host_resume(host); |
c1332875 TH |
2691 | |
2692 | return 0; | |
2693 | } | |
438ac6d5 | 2694 | #endif |
c1332875 | 2695 | |
254950cd TH |
2696 | static int ahci_port_start(struct ata_port *ap) |
2697 | { | |
d6ef3153 | 2698 | struct ahci_host_priv *hpriv = ap->host->private_data; |
cca3974e | 2699 | struct device *dev = ap->host->dev; |
254950cd | 2700 | struct ahci_port_priv *pp; |
254950cd TH |
2701 | void *mem; |
2702 | dma_addr_t mem_dma; | |
d6ef3153 | 2703 | size_t dma_sz, rx_fis_sz; |
254950cd | 2704 | |
24dc5f33 | 2705 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
2706 | if (!pp) |
2707 | return -ENOMEM; | |
254950cd | 2708 | |
d6ef3153 SH |
2709 | /* check FBS capability */ |
2710 | if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { | |
2711 | void __iomem *port_mmio = ahci_port_base(ap); | |
2712 | u32 cmd = readl(port_mmio + PORT_CMD); | |
2713 | if (cmd & PORT_CMD_FBSCP) | |
2714 | pp->fbs_supported = true; | |
2715 | else | |
2716 | dev_printk(KERN_WARNING, dev, | |
2717 | "The port is not capable of FBS\n"); | |
2718 | } | |
2719 | ||
2720 | if (pp->fbs_supported) { | |
2721 | dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; | |
2722 | rx_fis_sz = AHCI_RX_FIS_SZ * 16; | |
2723 | } else { | |
2724 | dma_sz = AHCI_PORT_PRIV_DMA_SZ; | |
2725 | rx_fis_sz = AHCI_RX_FIS_SZ; | |
2726 | } | |
2727 | ||
2728 | mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); | |
24dc5f33 | 2729 | if (!mem) |
254950cd | 2730 | return -ENOMEM; |
d6ef3153 | 2731 | memset(mem, 0, dma_sz); |
254950cd TH |
2732 | |
2733 | /* | |
2734 | * First item in chunk of DMA memory: 32-slot command table, | |
2735 | * 32 bytes each in size | |
2736 | */ | |
2737 | pp->cmd_slot = mem; | |
2738 | pp->cmd_slot_dma = mem_dma; | |
2739 | ||
2740 | mem += AHCI_CMD_SLOT_SZ; | |
2741 | mem_dma += AHCI_CMD_SLOT_SZ; | |
2742 | ||
2743 | /* | |
2744 | * Second item: Received-FIS area | |
2745 | */ | |
2746 | pp->rx_fis = mem; | |
2747 | pp->rx_fis_dma = mem_dma; | |
2748 | ||
d6ef3153 SH |
2749 | mem += rx_fis_sz; |
2750 | mem_dma += rx_fis_sz; | |
254950cd TH |
2751 | |
2752 | /* | |
2753 | * Third item: data area for storing a single command | |
2754 | * and its scatter-gather table | |
2755 | */ | |
2756 | pp->cmd_tbl = mem; | |
2757 | pp->cmd_tbl_dma = mem_dma; | |
2758 | ||
a7384925 | 2759 | /* |
2dcb407e JG |
2760 | * Save off initial list of interrupts to be enabled. |
2761 | * This could be changed later | |
2762 | */ | |
a7384925 KCA |
2763 | pp->intr_mask = DEF_PORT_IRQ; |
2764 | ||
254950cd TH |
2765 | ap->private_data = pp; |
2766 | ||
df69c9c5 JG |
2767 | /* engage engines, captain */ |
2768 | return ahci_port_resume(ap); | |
254950cd TH |
2769 | } |
2770 | ||
2771 | static void ahci_port_stop(struct ata_port *ap) | |
2772 | { | |
0be0aa98 TH |
2773 | const char *emsg = NULL; |
2774 | int rc; | |
254950cd | 2775 | |
0be0aa98 | 2776 | /* de-initialize port */ |
4447d351 | 2777 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
2778 | if (rc) |
2779 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
2780 | } |
2781 | ||
4447d351 | 2782 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 2783 | { |
1da177e4 | 2784 | int rc; |
1da177e4 | 2785 | |
1da177e4 | 2786 | if (using_dac && |
6a35528a YH |
2787 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
2788 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
1da177e4 | 2789 | if (rc) { |
284901a9 | 2790 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2791 | if (rc) { |
a9524a76 JG |
2792 | dev_printk(KERN_ERR, &pdev->dev, |
2793 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2794 | return rc; |
2795 | } | |
2796 | } | |
1da177e4 | 2797 | } else { |
284901a9 | 2798 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2799 | if (rc) { |
a9524a76 JG |
2800 | dev_printk(KERN_ERR, &pdev->dev, |
2801 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2802 | return rc; |
2803 | } | |
284901a9 | 2804 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2805 | if (rc) { |
a9524a76 JG |
2806 | dev_printk(KERN_ERR, &pdev->dev, |
2807 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2808 | return rc; |
2809 | } | |
2810 | } | |
1da177e4 LT |
2811 | return 0; |
2812 | } | |
2813 | ||
4447d351 | 2814 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2815 | { |
4447d351 TH |
2816 | struct ahci_host_priv *hpriv = host->private_data; |
2817 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
d8993349 | 2818 | void __iomem *mmio = hpriv->mmio; |
4c521c8e | 2819 | u32 vers, cap, cap2, impl, speed; |
1da177e4 LT |
2820 | const char *speed_s; |
2821 | u16 cc; | |
2822 | const char *scc_s; | |
2823 | ||
2824 | vers = readl(mmio + HOST_VERSION); | |
2825 | cap = hpriv->cap; | |
4c521c8e | 2826 | cap2 = hpriv->cap2; |
1da177e4 LT |
2827 | impl = hpriv->port_map; |
2828 | ||
2829 | speed = (cap >> 20) & 0xf; | |
2830 | if (speed == 1) | |
2831 | speed_s = "1.5"; | |
2832 | else if (speed == 2) | |
2833 | speed_s = "3"; | |
8522ee25 SH |
2834 | else if (speed == 3) |
2835 | speed_s = "6"; | |
1da177e4 LT |
2836 | else |
2837 | speed_s = "?"; | |
2838 | ||
2839 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2840 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2841 | scc_s = "IDE"; |
c9f89475 | 2842 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2843 | scc_s = "SATA"; |
c9f89475 | 2844 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2845 | scc_s = "RAID"; |
2846 | else | |
2847 | scc_s = "unknown"; | |
2848 | ||
a9524a76 JG |
2849 | dev_printk(KERN_INFO, &pdev->dev, |
2850 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2851 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2852 | , |
1da177e4 | 2853 | |
2dcb407e JG |
2854 | (vers >> 24) & 0xff, |
2855 | (vers >> 16) & 0xff, | |
2856 | (vers >> 8) & 0xff, | |
2857 | vers & 0xff, | |
1da177e4 LT |
2858 | |
2859 | ((cap >> 8) & 0x1f) + 1, | |
2860 | (cap & 0x1f) + 1, | |
2861 | speed_s, | |
2862 | impl, | |
2863 | scc_s); | |
2864 | ||
a9524a76 JG |
2865 | dev_printk(KERN_INFO, &pdev->dev, |
2866 | "flags: " | |
203ef6c4 | 2867 | "%s%s%s%s%s%s%s" |
18f7ba4c | 2868 | "%s%s%s%s%s%s%s" |
4c521c8e | 2869 | "%s%s%s%s%s%s\n" |
2dcb407e | 2870 | , |
1da177e4 | 2871 | |
4c521c8e RH |
2872 | cap & HOST_CAP_64 ? "64bit " : "", |
2873 | cap & HOST_CAP_NCQ ? "ncq " : "", | |
2874 | cap & HOST_CAP_SNTF ? "sntf " : "", | |
2875 | cap & HOST_CAP_MPS ? "ilck " : "", | |
2876 | cap & HOST_CAP_SSS ? "stag " : "", | |
2877 | cap & HOST_CAP_ALPM ? "pm " : "", | |
2878 | cap & HOST_CAP_LED ? "led " : "", | |
2879 | cap & HOST_CAP_CLO ? "clo " : "", | |
2880 | cap & HOST_CAP_ONLY ? "only " : "", | |
2881 | cap & HOST_CAP_PMP ? "pmp " : "", | |
2882 | cap & HOST_CAP_FBS ? "fbs " : "", | |
2883 | cap & HOST_CAP_PIO_MULTI ? "pio " : "", | |
2884 | cap & HOST_CAP_SSC ? "slum " : "", | |
2885 | cap & HOST_CAP_PART ? "part " : "", | |
2886 | cap & HOST_CAP_CCC ? "ccc " : "", | |
2887 | cap & HOST_CAP_EMS ? "ems " : "", | |
2888 | cap & HOST_CAP_SXS ? "sxs " : "", | |
2889 | cap2 & HOST_CAP2_APST ? "apst " : "", | |
2890 | cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", | |
2891 | cap2 & HOST_CAP2_BOH ? "boh " : "" | |
1da177e4 LT |
2892 | ); |
2893 | } | |
2894 | ||
edc93052 TH |
2895 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2896 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2897 | * support PMP and the 4726 either directly exports the device | |
2898 | * attached to the first downstream port or acts as a hardware storage | |
2899 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2900 | * other configuration). | |
2901 | * | |
2902 | * When there's no device attached to the first downstream port of the | |
2903 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2904 | * configure the 4726. However, ATA emulation of the device is very | |
2905 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2906 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2907 | * | |
2908 | * The following function works around the problem by always using | |
2909 | * hardreset on the port and not depending on receiving signature FIS | |
2910 | * afterward. If signature FIS isn't received soon, ATA class is | |
2911 | * assumed without follow-up softreset. | |
2912 | */ | |
2913 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2914 | { | |
2915 | static struct dmi_system_id sysids[] = { | |
2916 | { | |
2917 | .ident = "P5W DH Deluxe", | |
2918 | .matches = { | |
2919 | DMI_MATCH(DMI_SYS_VENDOR, | |
2920 | "ASUSTEK COMPUTER INC"), | |
2921 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2922 | }, | |
2923 | }, | |
2924 | { } | |
2925 | }; | |
2926 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2927 | ||
2928 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2929 | dmi_check_system(sysids)) { | |
2930 | struct ata_port *ap = host->ports[1]; | |
2931 | ||
2932 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2933 | "Deluxe on-board SIMG4726 workaround\n"); | |
2934 | ||
2935 | ap->ops = &ahci_p5wdh_ops; | |
2936 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2937 | } | |
2938 | } | |
2939 | ||
2fcad9d2 TH |
2940 | /* only some SB600 ahci controllers can do 64bit DMA */ |
2941 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) | |
58a09b38 SH |
2942 | { |
2943 | static const struct dmi_system_id sysids[] = { | |
03d783bf TH |
2944 | /* |
2945 | * The oldest version known to be broken is 0901 and | |
2946 | * working is 1501 which was released on 2007-10-26. | |
2fcad9d2 TH |
2947 | * Enable 64bit DMA on 1501 and anything newer. |
2948 | * | |
03d783bf TH |
2949 | * Please read bko#9412 for more info. |
2950 | */ | |
58a09b38 SH |
2951 | { |
2952 | .ident = "ASUS M2A-VM", | |
2953 | .matches = { | |
2954 | DMI_MATCH(DMI_BOARD_VENDOR, | |
2955 | "ASUSTeK Computer INC."), | |
2956 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), | |
2957 | }, | |
03d783bf | 2958 | .driver_data = "20071026", /* yyyymmdd */ |
58a09b38 | 2959 | }, |
e65cc194 MN |
2960 | /* |
2961 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) | |
2962 | * support 64bit DMA. | |
2963 | * | |
2964 | * BIOS versions earlier than 1.5 had the Manufacturer DMI | |
2965 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". | |
2966 | * This spelling mistake was fixed in BIOS version 1.5, so | |
2967 | * 1.5 and later have the Manufacturer as | |
2968 | * "MICRO-STAR INTERNATIONAL CO.,LTD". | |
2969 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". | |
2970 | * | |
2971 | * BIOS versions earlier than 1.9 had a Board Product Name | |
2972 | * DMI field of "MS-7376". This was changed to be | |
2973 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still | |
2974 | * match on DMI_BOARD_NAME of "MS-7376". | |
2975 | */ | |
2976 | { | |
2977 | .ident = "MSI K9A2 Platinum", | |
2978 | .matches = { | |
2979 | DMI_MATCH(DMI_BOARD_VENDOR, | |
2980 | "MICRO-STAR INTER"), | |
2981 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), | |
2982 | }, | |
2983 | }, | |
58a09b38 SH |
2984 | { } |
2985 | }; | |
03d783bf | 2986 | const struct dmi_system_id *match; |
2fcad9d2 TH |
2987 | int year, month, date; |
2988 | char buf[9]; | |
58a09b38 | 2989 | |
03d783bf | 2990 | match = dmi_first_match(sysids); |
58a09b38 | 2991 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
03d783bf | 2992 | !match) |
58a09b38 SH |
2993 | return false; |
2994 | ||
e65cc194 MN |
2995 | if (!match->driver_data) |
2996 | goto enable_64bit; | |
2997 | ||
2fcad9d2 TH |
2998 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
2999 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
03d783bf | 3000 | |
e65cc194 MN |
3001 | if (strcmp(buf, match->driver_data) >= 0) |
3002 | goto enable_64bit; | |
3003 | else { | |
03d783bf TH |
3004 | dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, " |
3005 | "forcing 32bit DMA, update BIOS\n", match->ident); | |
2fcad9d2 TH |
3006 | return false; |
3007 | } | |
e65cc194 MN |
3008 | |
3009 | enable_64bit: | |
3010 | dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n", | |
3011 | match->ident); | |
3012 | return true; | |
58a09b38 SH |
3013 | } |
3014 | ||
1fd68434 RW |
3015 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
3016 | { | |
3017 | static const struct dmi_system_id broken_systems[] = { | |
3018 | { | |
3019 | .ident = "HP Compaq nx6310", | |
3020 | .matches = { | |
3021 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3022 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
3023 | }, | |
3024 | /* PCI slot number of the controller */ | |
3025 | .driver_data = (void *)0x1FUL, | |
3026 | }, | |
d2f9c061 MR |
3027 | { |
3028 | .ident = "HP Compaq 6720s", | |
3029 | .matches = { | |
3030 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3031 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
3032 | }, | |
3033 | /* PCI slot number of the controller */ | |
3034 | .driver_data = (void *)0x1FUL, | |
3035 | }, | |
1fd68434 RW |
3036 | |
3037 | { } /* terminate list */ | |
3038 | }; | |
3039 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
3040 | ||
3041 | if (dmi) { | |
3042 | unsigned long slot = (unsigned long)dmi->driver_data; | |
3043 | /* apply the quirk only to on-board controllers */ | |
3044 | return slot == PCI_SLOT(pdev->devfn); | |
3045 | } | |
3046 | ||
3047 | return false; | |
3048 | } | |
3049 | ||
9b10ae86 TH |
3050 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
3051 | { | |
3052 | static const struct dmi_system_id sysids[] = { | |
3053 | /* | |
3054 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
3055 | * to the harddisk doesn't become online after | |
3056 | * resuming from STR. Warn and fail suspend. | |
9deb3431 TH |
3057 | * |
3058 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 | |
3059 | * | |
3060 | * Use dates instead of versions to match as HP is | |
3061 | * apparently recycling both product and version | |
3062 | * strings. | |
3063 | * | |
3064 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 | |
9b10ae86 TH |
3065 | */ |
3066 | { | |
3067 | .ident = "dv4", | |
3068 | .matches = { | |
3069 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3070 | DMI_MATCH(DMI_PRODUCT_NAME, | |
3071 | "HP Pavilion dv4 Notebook PC"), | |
3072 | }, | |
9deb3431 | 3073 | .driver_data = "20090105", /* F.30 */ |
9b10ae86 TH |
3074 | }, |
3075 | { | |
3076 | .ident = "dv5", | |
3077 | .matches = { | |
3078 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3079 | DMI_MATCH(DMI_PRODUCT_NAME, | |
3080 | "HP Pavilion dv5 Notebook PC"), | |
3081 | }, | |
9deb3431 | 3082 | .driver_data = "20090506", /* F.16 */ |
9b10ae86 TH |
3083 | }, |
3084 | { | |
3085 | .ident = "dv6", | |
3086 | .matches = { | |
3087 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3088 | DMI_MATCH(DMI_PRODUCT_NAME, | |
3089 | "HP Pavilion dv6 Notebook PC"), | |
3090 | }, | |
9deb3431 | 3091 | .driver_data = "20090423", /* F.21 */ |
9b10ae86 TH |
3092 | }, |
3093 | { | |
3094 | .ident = "HDX18", | |
3095 | .matches = { | |
3096 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
3097 | DMI_MATCH(DMI_PRODUCT_NAME, | |
3098 | "HP HDX18 Notebook PC"), | |
3099 | }, | |
9deb3431 | 3100 | .driver_data = "20090430", /* F.23 */ |
9b10ae86 | 3101 | }, |
cedc9bf9 TH |
3102 | /* |
3103 | * Acer eMachines G725 has the same problem. BIOS | |
3104 | * V1.03 is known to be broken. V3.04 is known to | |
3105 | * work. Inbetween, there are V1.06, V2.06 and V3.03 | |
3106 | * that we don't have much idea about. For now, | |
3107 | * blacklist anything older than V3.04. | |
9deb3431 TH |
3108 | * |
3109 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 | |
cedc9bf9 TH |
3110 | */ |
3111 | { | |
3112 | .ident = "G725", | |
3113 | .matches = { | |
3114 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), | |
3115 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), | |
3116 | }, | |
9deb3431 | 3117 | .driver_data = "20091216", /* V3.04 */ |
cedc9bf9 | 3118 | }, |
9b10ae86 TH |
3119 | { } /* terminate list */ |
3120 | }; | |
3121 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
9deb3431 TH |
3122 | int year, month, date; |
3123 | char buf[9]; | |
9b10ae86 TH |
3124 | |
3125 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
3126 | return false; | |
3127 | ||
9deb3431 TH |
3128 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
3129 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
9b10ae86 | 3130 | |
9deb3431 | 3131 | return strcmp(buf, dmi->driver_data) < 0; |
9b10ae86 TH |
3132 | } |
3133 | ||
5594639a TH |
3134 | static bool ahci_broken_online(struct pci_dev *pdev) |
3135 | { | |
3136 | #define ENCODE_BUSDEVFN(bus, slot, func) \ | |
3137 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) | |
3138 | static const struct dmi_system_id sysids[] = { | |
3139 | /* | |
3140 | * There are several gigabyte boards which use | |
3141 | * SIMG5723s configured as hardware RAID. Certain | |
3142 | * 5723 firmware revisions shipped there keep the link | |
3143 | * online but fail to answer properly to SRST or | |
3144 | * IDENTIFY when no device is attached downstream | |
3145 | * causing libata to retry quite a few times leading | |
3146 | * to excessive detection delay. | |
3147 | * | |
3148 | * As these firmwares respond to the second reset try | |
3149 | * with invalid device signature, considering unknown | |
3150 | * sig as offline works around the problem acceptably. | |
3151 | */ | |
3152 | { | |
3153 | .ident = "EP45-DQ6", | |
3154 | .matches = { | |
3155 | DMI_MATCH(DMI_BOARD_VENDOR, | |
3156 | "Gigabyte Technology Co., Ltd."), | |
3157 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), | |
3158 | }, | |
3159 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), | |
3160 | }, | |
3161 | { | |
3162 | .ident = "EP45-DS5", | |
3163 | .matches = { | |
3164 | DMI_MATCH(DMI_BOARD_VENDOR, | |
3165 | "Gigabyte Technology Co., Ltd."), | |
3166 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), | |
3167 | }, | |
3168 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), | |
3169 | }, | |
3170 | { } /* terminate list */ | |
3171 | }; | |
3172 | #undef ENCODE_BUSDEVFN | |
3173 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
3174 | unsigned int val; | |
3175 | ||
3176 | if (!dmi) | |
3177 | return false; | |
3178 | ||
3179 | val = (unsigned long)dmi->driver_data; | |
3180 | ||
3181 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); | |
3182 | } | |
3183 | ||
8e513217 | 3184 | #ifdef CONFIG_ATA_ACPI |
f80ae7e4 TH |
3185 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
3186 | { | |
3187 | static const struct dmi_system_id sysids[] = { | |
3188 | /* | |
3189 | * Aspire 3810T issues a bunch of SATA enable commands | |
3190 | * via _GTF including an invalid one and one which is | |
3191 | * rejected by the device. Among the successful ones | |
3192 | * is FPDMA non-zero offset enable which when enabled | |
3193 | * only on the drive side leads to NCQ command | |
3194 | * failures. Filter it out. | |
3195 | */ | |
3196 | { | |
3197 | .ident = "Aspire 3810T", | |
3198 | .matches = { | |
3199 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
3200 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), | |
3201 | }, | |
3202 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, | |
3203 | }, | |
3204 | { } | |
3205 | }; | |
3206 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
3207 | unsigned int filter; | |
3208 | int i; | |
3209 | ||
3210 | if (!dmi) | |
3211 | return; | |
3212 | ||
3213 | filter = (unsigned long)dmi->driver_data; | |
3214 | dev_printk(KERN_INFO, host->dev, | |
3215 | "applying extra ACPI _GTF filter 0x%x for %s\n", | |
3216 | filter, dmi->ident); | |
3217 | ||
3218 | for (i = 0; i < host->n_ports; i++) { | |
3219 | struct ata_port *ap = host->ports[i]; | |
3220 | struct ata_link *link; | |
3221 | struct ata_device *dev; | |
3222 | ||
3223 | ata_for_each_link(link, ap, EDGE) | |
3224 | ata_for_each_dev(dev, link, ALL) | |
3225 | dev->gtf_filter |= filter; | |
3226 | } | |
3227 | } | |
8e513217 MT |
3228 | #else |
3229 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) | |
3230 | {} | |
3231 | #endif | |
f80ae7e4 | 3232 | |
24dc5f33 | 3233 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
3234 | { |
3235 | static int printed_version; | |
e297d99e TH |
3236 | unsigned int board_id = ent->driver_data; |
3237 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 3238 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 3239 | struct device *dev = &pdev->dev; |
1da177e4 | 3240 | struct ahci_host_priv *hpriv; |
4447d351 | 3241 | struct ata_host *host; |
837f5f8f | 3242 | int n_ports, i, rc; |
1da177e4 LT |
3243 | |
3244 | VPRINTK("ENTER\n"); | |
3245 | ||
12fad3f9 TH |
3246 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
3247 | ||
1da177e4 | 3248 | if (!printed_version++) |
a9524a76 | 3249 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 3250 | |
5b66c829 AC |
3251 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
3252 | can drive them all so if both drivers are selected make sure | |
3253 | AHCI stays out of the way */ | |
3254 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
3255 | return -ENODEV; | |
3256 | ||
7a02267e MN |
3257 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
3258 | * At the moment, we can only use the AHCI mode. Let the users know | |
3259 | * that for SAS drives they're out of luck. | |
3260 | */ | |
3261 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) | |
3262 | dev_printk(KERN_INFO, &pdev->dev, "PDC42819 " | |
3263 | "can only drive SATA devices with this driver\n"); | |
3264 | ||
4447d351 | 3265 | /* acquire resources */ |
24dc5f33 | 3266 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
3267 | if (rc) |
3268 | return rc; | |
3269 | ||
dea55137 TH |
3270 | /* AHCI controllers often implement SFF compatible interface. |
3271 | * Grab all PCI BARs just in case. | |
3272 | */ | |
3273 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
0d5ff566 | 3274 | if (rc == -EBUSY) |
24dc5f33 | 3275 | pcim_pin_device(pdev); |
0d5ff566 | 3276 | if (rc) |
24dc5f33 | 3277 | return rc; |
1da177e4 | 3278 | |
c4f7792c TH |
3279 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
3280 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
3281 | u8 map; | |
3282 | ||
3283 | /* ICH6s share the same PCI ID for both piix and ahci | |
3284 | * modes. Enabling ahci mode while MAP indicates | |
3285 | * combined mode is a bad idea. Yield to ata_piix. | |
3286 | */ | |
3287 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
3288 | if (map & 0x3) { | |
3289 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
3290 | "combined mode, can't enable AHCI mode\n"); | |
3291 | return -ENODEV; | |
3292 | } | |
3293 | } | |
3294 | ||
24dc5f33 TH |
3295 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
3296 | if (!hpriv) | |
3297 | return -ENOMEM; | |
417a1a6d TH |
3298 | hpriv->flags |= (unsigned long)pi.private_data; |
3299 | ||
e297d99e TH |
3300 | /* MCP65 revision A1 and A2 can't do MSI */ |
3301 | if (board_id == board_ahci_mcp65 && | |
3302 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
3303 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
3304 | ||
e427fe04 SH |
3305 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
3306 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
3307 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
3308 | ||
2fcad9d2 TH |
3309 | /* only some SB600s can do 64bit DMA */ |
3310 | if (ahci_sb600_enable_64bit(pdev)) | |
3311 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; | |
58a09b38 | 3312 | |
31b239ad TH |
3313 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) |
3314 | pci_intx(pdev, 1); | |
1da177e4 | 3315 | |
d8993349 AV |
3316 | hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
3317 | ||
4447d351 | 3318 | /* save initial config */ |
417a1a6d | 3319 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 3320 | |
4447d351 | 3321 | /* prepare host */ |
453d3131 RH |
3322 | if (hpriv->cap & HOST_CAP_NCQ) { |
3323 | pi.flags |= ATA_FLAG_NCQ; | |
3324 | /* Auto-activate optimization is supposed to be supported on | |
3325 | all AHCI controllers indicating NCQ support, but it seems | |
3326 | to be broken at least on some NVIDIA MCP79 chipsets. | |
3327 | Until we get info on which NVIDIA chipsets don't have this | |
3328 | issue, if any, disable AA on all NVIDIA AHCIs. */ | |
3329 | if (pdev->vendor != PCI_VENDOR_ID_NVIDIA) | |
3330 | pi.flags |= ATA_FLAG_FPDMA_AA; | |
3331 | } | |
1da177e4 | 3332 | |
7d50b60b TH |
3333 | if (hpriv->cap & HOST_CAP_PMP) |
3334 | pi.flags |= ATA_FLAG_PMP; | |
3335 | ||
18f7ba4c KCA |
3336 | if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) { |
3337 | u8 messages; | |
d8993349 | 3338 | void __iomem *mmio = hpriv->mmio; |
18f7ba4c KCA |
3339 | u32 em_loc = readl(mmio + HOST_EM_LOC); |
3340 | u32 em_ctl = readl(mmio + HOST_EM_CTL); | |
3341 | ||
87943acf | 3342 | messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; |
18f7ba4c KCA |
3343 | |
3344 | /* we only support LED message type right now */ | |
3345 | if ((messages & 0x01) && (ahci_em_messages == 1)) { | |
3346 | /* store em_loc */ | |
3347 | hpriv->em_loc = ((em_loc >> 16) * 4); | |
3348 | pi.flags |= ATA_FLAG_EM; | |
3349 | if (!(em_ctl & EM_CTL_ALHD)) | |
3350 | pi.flags |= ATA_FLAG_SW_ACTIVITY; | |
3351 | } | |
3352 | } | |
3353 | ||
1fd68434 RW |
3354 | if (ahci_broken_system_poweroff(pdev)) { |
3355 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
3356 | dev_info(&pdev->dev, | |
3357 | "quirky BIOS, skipping spindown on poweroff\n"); | |
3358 | } | |
3359 | ||
9b10ae86 TH |
3360 | if (ahci_broken_suspend(pdev)) { |
3361 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
3362 | dev_printk(KERN_WARNING, &pdev->dev, | |
3363 | "BIOS update required for suspend/resume\n"); | |
3364 | } | |
3365 | ||
5594639a TH |
3366 | if (ahci_broken_online(pdev)) { |
3367 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; | |
3368 | dev_info(&pdev->dev, | |
3369 | "online status unreliable, applying workaround\n"); | |
3370 | } | |
3371 | ||
837f5f8f TH |
3372 | /* CAP.NP sometimes indicate the index of the last enabled |
3373 | * port, at other times, that of the last possible port, so | |
3374 | * determining the maximum port number requires looking at | |
3375 | * both CAP.NP and port_map. | |
3376 | */ | |
3377 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
3378 | ||
3379 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
3380 | if (!host) |
3381 | return -ENOMEM; | |
4447d351 TH |
3382 | host->private_data = hpriv; |
3383 | ||
f3d7f23f | 3384 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 3385 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f AV |
3386 | else |
3387 | printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); | |
886ad09f | 3388 | |
18f7ba4c KCA |
3389 | if (pi.flags & ATA_FLAG_EM) |
3390 | ahci_reset_em(host); | |
3391 | ||
4447d351 | 3392 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 3393 | struct ata_port *ap = host->ports[i]; |
4447d351 | 3394 | |
cbcdd875 TH |
3395 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
3396 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
3397 | 0x100 + ap->port_no * 0x80, "port"); | |
3398 | ||
31556594 KCA |
3399 | /* set initial link pm policy */ |
3400 | ap->pm_policy = NOT_AVAILABLE; | |
3401 | ||
18f7ba4c KCA |
3402 | /* set enclosure management message type */ |
3403 | if (ap->flags & ATA_FLAG_EM) | |
3404 | ap->em_message_type = ahci_em_messages; | |
3405 | ||
3406 | ||
dab632e8 | 3407 | /* disabled/not-implemented port */ |
350756f6 | 3408 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 3409 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 3410 | } |
d447df14 | 3411 | |
edc93052 TH |
3412 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
3413 | ahci_p5wdh_workaround(host); | |
3414 | ||
f80ae7e4 TH |
3415 | /* apply gtf filter quirk */ |
3416 | ahci_gtf_filter_workaround(host); | |
3417 | ||
4447d351 TH |
3418 | /* initialize adapter */ |
3419 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 3420 | if (rc) |
24dc5f33 | 3421 | return rc; |
1da177e4 | 3422 | |
4447d351 TH |
3423 | rc = ahci_reset_controller(host); |
3424 | if (rc) | |
3425 | return rc; | |
1da177e4 | 3426 | |
4447d351 TH |
3427 | ahci_init_controller(host); |
3428 | ahci_print_info(host); | |
1da177e4 | 3429 | |
4447d351 TH |
3430 | pci_set_master(pdev); |
3431 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
3432 | &ahci_sht); | |
907f4678 | 3433 | } |
1da177e4 LT |
3434 | |
3435 | static int __init ahci_init(void) | |
3436 | { | |
b7887196 | 3437 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
3438 | } |
3439 | ||
1da177e4 LT |
3440 | static void __exit ahci_exit(void) |
3441 | { | |
3442 | pci_unregister_driver(&ahci_pci_driver); | |
3443 | } | |
3444 | ||
3445 | ||
3446 | MODULE_AUTHOR("Jeff Garzik"); | |
3447 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
3448 | MODULE_LICENSE("GPL"); | |
3449 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 3450 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
3451 | |
3452 | module_init(ahci_init); | |
3453 | module_exit(ahci_exit); |