Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
31556594 KCA |
52 | static int ahci_enable_alpm(struct ata_port *ap, |
53 | enum link_pm policy); | |
54 | static void ahci_disable_alpm(struct ata_port *ap); | |
1da177e4 LT |
55 | |
56 | enum { | |
57 | AHCI_PCI_BAR = 5, | |
648a88be | 58 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
59 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
60 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
be5d8218 | 61 | AHCI_USE_CLUSTERING = 1, |
12fad3f9 | 62 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 63 | AHCI_CMD_SZ = 32, |
12fad3f9 | 64 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 65 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 66 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
67 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
68 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
69 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
70 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
71 | AHCI_RX_FIS_SZ, |
72 | AHCI_IRQ_ON_SG = (1 << 31), | |
73 | AHCI_CMD_ATAPI = (1 << 5), | |
74 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 75 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
76 | AHCI_CMD_RESET = (1 << 8), |
77 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
78 | |
79 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 80 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 81 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
82 | |
83 | board_ahci = 0, | |
7a234aff TH |
84 | board_ahci_vt8251 = 1, |
85 | board_ahci_ign_iferr = 2, | |
86 | board_ahci_sb600 = 3, | |
87 | board_ahci_mv = 4, | |
1da177e4 LT |
88 | |
89 | /* global controller registers */ | |
90 | HOST_CAP = 0x00, /* host capabilities */ | |
91 | HOST_CTL = 0x04, /* global host control */ | |
92 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
93 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
94 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
95 | ||
96 | /* HOST_CTL bits */ | |
97 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
98 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
99 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
100 | ||
101 | /* HOST_CAP bits */ | |
0be0aa98 | 102 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 103 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 104 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 105 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 106 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 107 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 108 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 109 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
110 | |
111 | /* registers for each SATA port */ | |
112 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
113 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
114 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
115 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
116 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
117 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
118 | PORT_CMD = 0x18, /* port command */ | |
119 | PORT_TFDATA = 0x20, /* taskfile data */ | |
120 | PORT_SIG = 0x24, /* device TF signature */ | |
121 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
122 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
123 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
124 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
125 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 126 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
127 | |
128 | /* PORT_IRQ_{STAT,MASK} bits */ | |
129 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
130 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
131 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
132 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
133 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
134 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
135 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
136 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
137 | ||
138 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
139 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
140 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
141 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
142 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
143 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
144 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
145 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
146 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
147 | ||
78cd52d0 TH |
148 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
149 | PORT_IRQ_IF_ERR | | |
150 | PORT_IRQ_CONNECT | | |
4296971d | 151 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
152 | PORT_IRQ_UNK_FIS | |
153 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
154 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
155 | PORT_IRQ_TF_ERR | | |
156 | PORT_IRQ_HBUS_DATA_ERR, | |
157 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
158 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
159 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
160 | |
161 | /* PORT_CMD bits */ | |
31556594 KCA |
162 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
163 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 164 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 165 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
166 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
167 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
168 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 169 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
170 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
171 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
172 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
173 | ||
0be0aa98 | 174 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
175 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
176 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
177 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 178 | |
417a1a6d TH |
179 | /* hpriv->flags bits */ |
180 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
181 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
182 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
183 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
184 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
185 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 186 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 187 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
417a1a6d | 188 | |
bf2af2a2 | 189 | /* ap->flags bits */ |
1188c0d8 TH |
190 | |
191 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
192 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
193 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
194 | ATA_FLAG_IPM, | |
0c88758b | 195 | AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, |
c4f7792c TH |
196 | |
197 | ICH_MAP = 0x90, /* ICH MAP register */ | |
1da177e4 LT |
198 | }; |
199 | ||
200 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
201 | __le32 opts; |
202 | __le32 status; | |
203 | __le32 tbl_addr; | |
204 | __le32 tbl_addr_hi; | |
205 | __le32 reserved[4]; | |
1da177e4 LT |
206 | }; |
207 | ||
208 | struct ahci_sg { | |
4ca4e439 AV |
209 | __le32 addr; |
210 | __le32 addr_hi; | |
211 | __le32 reserved; | |
212 | __le32 flags_size; | |
1da177e4 LT |
213 | }; |
214 | ||
215 | struct ahci_host_priv { | |
417a1a6d | 216 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
217 | u32 cap; /* cap to use */ |
218 | u32 port_map; /* port map to use */ | |
219 | u32 saved_cap; /* saved initial cap */ | |
220 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
221 | }; |
222 | ||
223 | struct ahci_port_priv { | |
7d50b60b | 224 | struct ata_link *active_link; |
1da177e4 LT |
225 | struct ahci_cmd_hdr *cmd_slot; |
226 | dma_addr_t cmd_slot_dma; | |
227 | void *cmd_tbl; | |
228 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
229 | void *rx_fis; |
230 | dma_addr_t rx_fis_dma; | |
0291f95f | 231 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
232 | unsigned int ncq_saw_d2h:1; |
233 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 234 | unsigned int ncq_saw_sdb:1; |
a7384925 | 235 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
236 | }; |
237 | ||
da3dbb17 TH |
238 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
239 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
2dcb407e | 240 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 241 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 242 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
243 | static int ahci_port_start(struct ata_port *ap); |
244 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
245 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
246 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
247 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
248 | static void ahci_freeze(struct ata_port *ap); |
249 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
250 | static void ahci_pmp_attach(struct ata_port *ap); |
251 | static void ahci_pmp_detach(struct ata_port *ap); | |
78cd52d0 | 252 | static void ahci_error_handler(struct ata_port *ap); |
ad616ffb | 253 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
edc93052 | 254 | static void ahci_p5wdh_error_handler(struct ata_port *ap); |
78cd52d0 | 255 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
df69c9c5 | 256 | static int ahci_port_resume(struct ata_port *ap); |
dab632e8 JG |
257 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
258 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
259 | u32 opts); | |
438ac6d5 | 260 | #ifdef CONFIG_PM |
c1332875 | 261 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
262 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
263 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 264 | #endif |
1da177e4 | 265 | |
31556594 KCA |
266 | static struct class_device_attribute *ahci_shost_attrs[] = { |
267 | &class_device_attr_link_power_management_policy, | |
268 | NULL | |
269 | }; | |
270 | ||
193515d5 | 271 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
272 | .module = THIS_MODULE, |
273 | .name = DRV_NAME, | |
274 | .ioctl = ata_scsi_ioctl, | |
275 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
276 | .change_queue_depth = ata_scsi_change_queue_depth, |
277 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
278 | .this_id = ATA_SHT_THIS_ID, |
279 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
280 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
281 | .emulated = ATA_SHT_EMULATED, | |
282 | .use_clustering = AHCI_USE_CLUSTERING, | |
283 | .proc_name = DRV_NAME, | |
284 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
285 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 286 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 287 | .bios_param = ata_std_bios_param, |
31556594 | 288 | .shost_attrs = ahci_shost_attrs, |
1da177e4 LT |
289 | }; |
290 | ||
057ace5e | 291 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
292 | .check_status = ahci_check_status, |
293 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
294 | .dev_select = ata_noop_dev_select, |
295 | ||
296 | .tf_read = ahci_tf_read, | |
297 | ||
7d50b60b | 298 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
299 | .qc_prep = ahci_qc_prep, |
300 | .qc_issue = ahci_qc_issue, | |
301 | ||
1da177e4 LT |
302 | .irq_clear = ahci_irq_clear, |
303 | ||
304 | .scr_read = ahci_scr_read, | |
305 | .scr_write = ahci_scr_write, | |
306 | ||
78cd52d0 TH |
307 | .freeze = ahci_freeze, |
308 | .thaw = ahci_thaw, | |
309 | ||
310 | .error_handler = ahci_error_handler, | |
311 | .post_internal_cmd = ahci_post_internal_cmd, | |
312 | ||
7d50b60b TH |
313 | .pmp_attach = ahci_pmp_attach, |
314 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 315 | |
438ac6d5 | 316 | #ifdef CONFIG_PM |
c1332875 TH |
317 | .port_suspend = ahci_port_suspend, |
318 | .port_resume = ahci_port_resume, | |
438ac6d5 | 319 | #endif |
31556594 KCA |
320 | .enable_pm = ahci_enable_alpm, |
321 | .disable_pm = ahci_disable_alpm, | |
c1332875 | 322 | |
1da177e4 LT |
323 | .port_start = ahci_port_start, |
324 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
325 | }; |
326 | ||
ad616ffb | 327 | static const struct ata_port_operations ahci_vt8251_ops = { |
ad616ffb TH |
328 | .check_status = ahci_check_status, |
329 | .check_altstatus = ahci_check_status, | |
330 | .dev_select = ata_noop_dev_select, | |
331 | ||
332 | .tf_read = ahci_tf_read, | |
333 | ||
7d50b60b | 334 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
ad616ffb TH |
335 | .qc_prep = ahci_qc_prep, |
336 | .qc_issue = ahci_qc_issue, | |
337 | ||
ad616ffb TH |
338 | .irq_clear = ahci_irq_clear, |
339 | ||
340 | .scr_read = ahci_scr_read, | |
341 | .scr_write = ahci_scr_write, | |
342 | ||
343 | .freeze = ahci_freeze, | |
344 | .thaw = ahci_thaw, | |
345 | ||
346 | .error_handler = ahci_vt8251_error_handler, | |
347 | .post_internal_cmd = ahci_post_internal_cmd, | |
348 | ||
7d50b60b TH |
349 | .pmp_attach = ahci_pmp_attach, |
350 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 351 | |
438ac6d5 | 352 | #ifdef CONFIG_PM |
ad616ffb TH |
353 | .port_suspend = ahci_port_suspend, |
354 | .port_resume = ahci_port_resume, | |
438ac6d5 | 355 | #endif |
ad616ffb TH |
356 | |
357 | .port_start = ahci_port_start, | |
358 | .port_stop = ahci_port_stop, | |
359 | }; | |
360 | ||
edc93052 TH |
361 | static const struct ata_port_operations ahci_p5wdh_ops = { |
362 | .check_status = ahci_check_status, | |
363 | .check_altstatus = ahci_check_status, | |
364 | .dev_select = ata_noop_dev_select, | |
365 | ||
366 | .tf_read = ahci_tf_read, | |
367 | ||
368 | .qc_defer = sata_pmp_qc_defer_cmd_switch, | |
369 | .qc_prep = ahci_qc_prep, | |
370 | .qc_issue = ahci_qc_issue, | |
371 | ||
372 | .irq_clear = ahci_irq_clear, | |
373 | ||
374 | .scr_read = ahci_scr_read, | |
375 | .scr_write = ahci_scr_write, | |
376 | ||
377 | .freeze = ahci_freeze, | |
378 | .thaw = ahci_thaw, | |
379 | ||
380 | .error_handler = ahci_p5wdh_error_handler, | |
381 | .post_internal_cmd = ahci_post_internal_cmd, | |
382 | ||
383 | .pmp_attach = ahci_pmp_attach, | |
384 | .pmp_detach = ahci_pmp_detach, | |
385 | ||
386 | #ifdef CONFIG_PM | |
387 | .port_suspend = ahci_port_suspend, | |
388 | .port_resume = ahci_port_resume, | |
389 | #endif | |
390 | ||
391 | .port_start = ahci_port_start, | |
392 | .port_stop = ahci_port_stop, | |
393 | }; | |
394 | ||
417a1a6d TH |
395 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
396 | ||
98ac62de | 397 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
398 | /* board_ahci */ |
399 | { | |
1188c0d8 | 400 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 401 | .link_flags = AHCI_LFLAG_COMMON, |
7da79312 | 402 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 403 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
404 | .port_ops = &ahci_ops, |
405 | }, | |
bf2af2a2 BJ |
406 | /* board_ahci_vt8251 */ |
407 | { | |
6949b914 | 408 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 409 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 410 | .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, |
bf2af2a2 | 411 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 412 | .udma_mask = ATA_UDMA6, |
ad616ffb | 413 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 414 | }, |
41669553 TH |
415 | /* board_ahci_ign_iferr */ |
416 | { | |
417a1a6d TH |
417 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
418 | .flags = AHCI_FLAG_COMMON, | |
0c88758b | 419 | .link_flags = AHCI_LFLAG_COMMON, |
41669553 | 420 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 421 | .udma_mask = ATA_UDMA6, |
41669553 TH |
422 | .port_ops = &ahci_ops, |
423 | }, | |
55a61604 CH |
424 | /* board_ahci_sb600 */ |
425 | { | |
417a1a6d | 426 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
6949b914 | 427 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP), |
417a1a6d | 428 | .flags = AHCI_FLAG_COMMON, |
0c88758b | 429 | .link_flags = AHCI_LFLAG_COMMON, |
55a61604 | 430 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 431 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
432 | .port_ops = &ahci_ops, |
433 | }, | |
cd70c266 JG |
434 | /* board_ahci_mv */ |
435 | { | |
417a1a6d TH |
436 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
437 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 438 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 439 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
0c88758b | 440 | .link_flags = AHCI_LFLAG_COMMON, |
cd70c266 JG |
441 | .pio_mask = 0x1f, /* pio0-4 */ |
442 | .udma_mask = ATA_UDMA6, | |
443 | .port_ops = &ahci_ops, | |
444 | }, | |
1da177e4 LT |
445 | }; |
446 | ||
3b7d697d | 447 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 448 | /* Intel */ |
54bb3a94 JG |
449 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
450 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
451 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
452 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
453 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 454 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
455 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
456 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
457 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
458 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
459 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
460 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
461 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
462 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
463 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
464 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
465 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
466 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
467 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
468 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
469 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
470 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
471 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
472 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
473 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
474 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
475 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
476 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
477 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
fe7fa31a | 478 | |
e34bb370 TH |
479 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
480 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
481 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
482 | |
483 | /* ATI */ | |
c65ec1c2 | 484 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
c69c0892 | 485 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */ |
486 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */ | |
487 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */ | |
488 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */ | |
489 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */ | |
490 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
491 | |
492 | /* VIA */ | |
54bb3a94 | 493 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 494 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
495 | |
496 | /* NVIDIA */ | |
54bb3a94 JG |
497 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
498 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
501 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
502 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
509 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
510 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
511 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
512 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
515 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
516 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
517 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
518 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
519 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
520 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
521 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
522 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
523 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
524 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
525 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
526 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
527 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
528 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
529 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
530 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
531 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
532 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
533 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
534 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
535 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
536 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
537 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
538 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
539 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
540 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 541 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
542 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
543 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
544 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
545 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
546 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
547 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
548 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
549 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
550 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
551 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
552 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
fe7fa31a | 553 | |
95916edd | 554 | /* SiS */ |
54bb3a94 JG |
555 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
556 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
557 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 558 | |
cd70c266 JG |
559 | /* Marvell */ |
560 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
561 | ||
415ae2b5 JG |
562 | /* Generic, PCI class code for AHCI */ |
563 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 564 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 565 | |
1da177e4 LT |
566 | { } /* terminate list */ |
567 | }; | |
568 | ||
569 | ||
570 | static struct pci_driver ahci_pci_driver = { | |
571 | .name = DRV_NAME, | |
572 | .id_table = ahci_pci_tbl, | |
573 | .probe = ahci_init_one, | |
24dc5f33 | 574 | .remove = ata_pci_remove_one, |
438ac6d5 | 575 | #ifdef CONFIG_PM |
c1332875 TH |
576 | .suspend = ahci_pci_device_suspend, |
577 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 578 | #endif |
1da177e4 LT |
579 | }; |
580 | ||
581 | ||
98fa4b60 TH |
582 | static inline int ahci_nr_ports(u32 cap) |
583 | { | |
584 | return (cap & 0x1f) + 1; | |
585 | } | |
586 | ||
dab632e8 JG |
587 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
588 | unsigned int port_no) | |
1da177e4 | 589 | { |
dab632e8 | 590 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 591 | |
dab632e8 JG |
592 | return mmio + 0x100 + (port_no * 0x80); |
593 | } | |
594 | ||
595 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
596 | { | |
597 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
598 | } |
599 | ||
b710a1f4 TH |
600 | static void ahci_enable_ahci(void __iomem *mmio) |
601 | { | |
602 | u32 tmp; | |
603 | ||
604 | /* turn on AHCI_EN */ | |
605 | tmp = readl(mmio + HOST_CTL); | |
606 | if (!(tmp & HOST_AHCI_EN)) { | |
607 | tmp |= HOST_AHCI_EN; | |
608 | writel(tmp, mmio + HOST_CTL); | |
609 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
610 | WARN_ON(!(tmp & HOST_AHCI_EN)); | |
611 | } | |
612 | } | |
613 | ||
d447df14 TH |
614 | /** |
615 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 616 | * @pdev: target PCI device |
4447d351 | 617 | * @hpriv: host private area to store config values |
d447df14 TH |
618 | * |
619 | * Some registers containing configuration info might be setup by | |
620 | * BIOS and might be cleared on reset. This function saves the | |
621 | * initial values of those registers into @hpriv such that they | |
622 | * can be restored after controller reset. | |
623 | * | |
624 | * If inconsistent, config values are fixed up by this function. | |
625 | * | |
626 | * LOCKING: | |
627 | * None. | |
628 | */ | |
4447d351 | 629 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 630 | struct ahci_host_priv *hpriv) |
d447df14 | 631 | { |
4447d351 | 632 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 633 | u32 cap, port_map; |
17199b18 | 634 | int i; |
d447df14 | 635 | |
b710a1f4 TH |
636 | /* make sure AHCI mode is enabled before accessing CAP */ |
637 | ahci_enable_ahci(mmio); | |
638 | ||
d447df14 TH |
639 | /* Values prefixed with saved_ are written back to host after |
640 | * reset. Values without are used for driver operation. | |
641 | */ | |
642 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
643 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
644 | ||
274c1fde | 645 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 646 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
647 | dev_printk(KERN_INFO, &pdev->dev, |
648 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
649 | cap &= ~HOST_CAP_64; | |
650 | } | |
651 | ||
417a1a6d | 652 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
653 | dev_printk(KERN_INFO, &pdev->dev, |
654 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
655 | cap &= ~HOST_CAP_NCQ; | |
656 | } | |
657 | ||
6949b914 TH |
658 | if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
659 | dev_printk(KERN_INFO, &pdev->dev, | |
660 | "controller can't do PMP, turning off CAP_PMP\n"); | |
661 | cap &= ~HOST_CAP_PMP; | |
662 | } | |
663 | ||
cd70c266 JG |
664 | /* |
665 | * Temporary Marvell 6145 hack: PATA port presence | |
666 | * is asserted through the standard AHCI port | |
667 | * presence register, as bit 4 (counting from 0) | |
668 | */ | |
417a1a6d | 669 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
670 | dev_printk(KERN_ERR, &pdev->dev, |
671 | "MV_AHCI HACK: port_map %x -> %x\n", | |
672 | hpriv->port_map, | |
673 | hpriv->port_map & 0xf); | |
674 | ||
675 | port_map &= 0xf; | |
676 | } | |
677 | ||
17199b18 | 678 | /* cross check port_map and cap.n_ports */ |
7a234aff | 679 | if (port_map) { |
17199b18 TH |
680 | u32 tmp_port_map = port_map; |
681 | int n_ports = ahci_nr_ports(cap); | |
682 | ||
683 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
684 | if (tmp_port_map & (1 << i)) { | |
685 | n_ports--; | |
686 | tmp_port_map &= ~(1 << i); | |
687 | } | |
688 | } | |
689 | ||
7a234aff TH |
690 | /* If n_ports and port_map are inconsistent, whine and |
691 | * clear port_map and let it be generated from n_ports. | |
17199b18 | 692 | */ |
7a234aff | 693 | if (n_ports || tmp_port_map) { |
4447d351 | 694 | dev_printk(KERN_WARNING, &pdev->dev, |
17199b18 | 695 | "nr_ports (%u) and implemented port map " |
7a234aff | 696 | "(0x%x) don't match, using nr_ports\n", |
17199b18 | 697 | ahci_nr_ports(cap), port_map); |
7a234aff TH |
698 | port_map = 0; |
699 | } | |
700 | } | |
701 | ||
702 | /* fabricate port_map from cap.nr_ports */ | |
703 | if (!port_map) { | |
17199b18 | 704 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
705 | dev_printk(KERN_WARNING, &pdev->dev, |
706 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
707 | ||
708 | /* write the fixed up value to the PI register */ | |
709 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
710 | } |
711 | ||
d447df14 TH |
712 | /* record values to use during operation */ |
713 | hpriv->cap = cap; | |
714 | hpriv->port_map = port_map; | |
715 | } | |
716 | ||
717 | /** | |
718 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 719 | * @host: target ATA host |
d447df14 TH |
720 | * |
721 | * Restore initial config stored by ahci_save_initial_config(). | |
722 | * | |
723 | * LOCKING: | |
724 | * None. | |
725 | */ | |
4447d351 | 726 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 727 | { |
4447d351 TH |
728 | struct ahci_host_priv *hpriv = host->private_data; |
729 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
730 | ||
d447df14 TH |
731 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
732 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
733 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
734 | } | |
735 | ||
203ef6c4 | 736 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 737 | { |
203ef6c4 TH |
738 | static const int offset[] = { |
739 | [SCR_STATUS] = PORT_SCR_STAT, | |
740 | [SCR_CONTROL] = PORT_SCR_CTL, | |
741 | [SCR_ERROR] = PORT_SCR_ERR, | |
742 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
743 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
744 | }; | |
745 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 746 | |
203ef6c4 TH |
747 | if (sc_reg < ARRAY_SIZE(offset) && |
748 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
749 | return offset[sc_reg]; | |
da3dbb17 | 750 | return 0; |
1da177e4 LT |
751 | } |
752 | ||
203ef6c4 | 753 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 754 | { |
203ef6c4 TH |
755 | void __iomem *port_mmio = ahci_port_base(ap); |
756 | int offset = ahci_scr_offset(ap, sc_reg); | |
757 | ||
758 | if (offset) { | |
759 | *val = readl(port_mmio + offset); | |
760 | return 0; | |
1da177e4 | 761 | } |
203ef6c4 TH |
762 | return -EINVAL; |
763 | } | |
1da177e4 | 764 | |
203ef6c4 TH |
765 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
766 | { | |
767 | void __iomem *port_mmio = ahci_port_base(ap); | |
768 | int offset = ahci_scr_offset(ap, sc_reg); | |
769 | ||
770 | if (offset) { | |
771 | writel(val, port_mmio + offset); | |
772 | return 0; | |
773 | } | |
774 | return -EINVAL; | |
1da177e4 LT |
775 | } |
776 | ||
4447d351 | 777 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 778 | { |
4447d351 | 779 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
780 | u32 tmp; |
781 | ||
d8fcd116 | 782 | /* start DMA */ |
9f592056 | 783 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
784 | tmp |= PORT_CMD_START; |
785 | writel(tmp, port_mmio + PORT_CMD); | |
786 | readl(port_mmio + PORT_CMD); /* flush */ | |
787 | } | |
788 | ||
4447d351 | 789 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 790 | { |
4447d351 | 791 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
792 | u32 tmp; |
793 | ||
794 | tmp = readl(port_mmio + PORT_CMD); | |
795 | ||
d8fcd116 | 796 | /* check if the HBA is idle */ |
254950cd TH |
797 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
798 | return 0; | |
799 | ||
d8fcd116 | 800 | /* setting HBA to idle */ |
254950cd TH |
801 | tmp &= ~PORT_CMD_START; |
802 | writel(tmp, port_mmio + PORT_CMD); | |
803 | ||
d8fcd116 | 804 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 805 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 806 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 807 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
808 | return -EIO; |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
4447d351 | 813 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 814 | { |
4447d351 TH |
815 | void __iomem *port_mmio = ahci_port_base(ap); |
816 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
817 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
818 | u32 tmp; |
819 | ||
820 | /* set FIS registers */ | |
4447d351 TH |
821 | if (hpriv->cap & HOST_CAP_64) |
822 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
823 | port_mmio + PORT_LST_ADDR_HI); | |
824 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 825 | |
4447d351 TH |
826 | if (hpriv->cap & HOST_CAP_64) |
827 | writel((pp->rx_fis_dma >> 16) >> 16, | |
828 | port_mmio + PORT_FIS_ADDR_HI); | |
829 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
830 | |
831 | /* enable FIS reception */ | |
832 | tmp = readl(port_mmio + PORT_CMD); | |
833 | tmp |= PORT_CMD_FIS_RX; | |
834 | writel(tmp, port_mmio + PORT_CMD); | |
835 | ||
836 | /* flush */ | |
837 | readl(port_mmio + PORT_CMD); | |
838 | } | |
839 | ||
4447d351 | 840 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 841 | { |
4447d351 | 842 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
843 | u32 tmp; |
844 | ||
845 | /* disable FIS reception */ | |
846 | tmp = readl(port_mmio + PORT_CMD); | |
847 | tmp &= ~PORT_CMD_FIS_RX; | |
848 | writel(tmp, port_mmio + PORT_CMD); | |
849 | ||
850 | /* wait for completion, spec says 500ms, give it 1000 */ | |
851 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
852 | PORT_CMD_FIS_ON, 10, 1000); | |
853 | if (tmp & PORT_CMD_FIS_ON) | |
854 | return -EBUSY; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
4447d351 | 859 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 860 | { |
4447d351 TH |
861 | struct ahci_host_priv *hpriv = ap->host->private_data; |
862 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
863 | u32 cmd; |
864 | ||
865 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
866 | ||
867 | /* spin up device */ | |
4447d351 | 868 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
869 | cmd |= PORT_CMD_SPIN_UP; |
870 | writel(cmd, port_mmio + PORT_CMD); | |
871 | } | |
872 | ||
873 | /* wake up link */ | |
874 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
875 | } | |
876 | ||
31556594 KCA |
877 | static void ahci_disable_alpm(struct ata_port *ap) |
878 | { | |
879 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
880 | void __iomem *port_mmio = ahci_port_base(ap); | |
881 | u32 cmd; | |
882 | struct ahci_port_priv *pp = ap->private_data; | |
883 | ||
884 | /* IPM bits should be disabled by libata-core */ | |
885 | /* get the existing command bits */ | |
886 | cmd = readl(port_mmio + PORT_CMD); | |
887 | ||
888 | /* disable ALPM and ASP */ | |
889 | cmd &= ~PORT_CMD_ASP; | |
890 | cmd &= ~PORT_CMD_ALPE; | |
891 | ||
892 | /* force the interface back to active */ | |
893 | cmd |= PORT_CMD_ICC_ACTIVE; | |
894 | ||
895 | /* write out new cmd value */ | |
896 | writel(cmd, port_mmio + PORT_CMD); | |
897 | cmd = readl(port_mmio + PORT_CMD); | |
898 | ||
899 | /* wait 10ms to be sure we've come out of any low power state */ | |
900 | msleep(10); | |
901 | ||
902 | /* clear out any PhyRdy stuff from interrupt status */ | |
903 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
904 | ||
905 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
906 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
907 | ||
908 | /* | |
909 | * Clear flag to indicate that we should ignore all PhyRdy | |
910 | * state changes | |
911 | */ | |
912 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
913 | ||
914 | /* | |
915 | * Enable interrupts on Phy Ready. | |
916 | */ | |
917 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
918 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
919 | ||
920 | /* | |
921 | * don't change the link pm policy - we can be called | |
922 | * just to turn of link pm temporarily | |
923 | */ | |
924 | } | |
925 | ||
926 | static int ahci_enable_alpm(struct ata_port *ap, | |
927 | enum link_pm policy) | |
928 | { | |
929 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
930 | void __iomem *port_mmio = ahci_port_base(ap); | |
931 | u32 cmd; | |
932 | struct ahci_port_priv *pp = ap->private_data; | |
933 | u32 asp; | |
934 | ||
935 | /* Make sure the host is capable of link power management */ | |
936 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
937 | return -EINVAL; | |
938 | ||
939 | switch (policy) { | |
940 | case MAX_PERFORMANCE: | |
941 | case NOT_AVAILABLE: | |
942 | /* | |
943 | * if we came here with NOT_AVAILABLE, | |
944 | * it just means this is the first time we | |
945 | * have tried to enable - default to max performance, | |
946 | * and let the user go to lower power modes on request. | |
947 | */ | |
948 | ahci_disable_alpm(ap); | |
949 | return 0; | |
950 | case MIN_POWER: | |
951 | /* configure HBA to enter SLUMBER */ | |
952 | asp = PORT_CMD_ASP; | |
953 | break; | |
954 | case MEDIUM_POWER: | |
955 | /* configure HBA to enter PARTIAL */ | |
956 | asp = 0; | |
957 | break; | |
958 | default: | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | /* | |
963 | * Disable interrupts on Phy Ready. This keeps us from | |
964 | * getting woken up due to spurious phy ready interrupts | |
965 | * TBD - Hot plug should be done via polling now, is | |
966 | * that even supported? | |
967 | */ | |
968 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
969 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
970 | ||
971 | /* | |
972 | * Set a flag to indicate that we should ignore all PhyRdy | |
973 | * state changes since these can happen now whenever we | |
974 | * change link state | |
975 | */ | |
976 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
977 | ||
978 | /* get the existing command bits */ | |
979 | cmd = readl(port_mmio + PORT_CMD); | |
980 | ||
981 | /* | |
982 | * Set ASP based on Policy | |
983 | */ | |
984 | cmd |= asp; | |
985 | ||
986 | /* | |
987 | * Setting this bit will instruct the HBA to aggressively | |
988 | * enter a lower power link state when it's appropriate and | |
989 | * based on the value set above for ASP | |
990 | */ | |
991 | cmd |= PORT_CMD_ALPE; | |
992 | ||
993 | /* write out new cmd value */ | |
994 | writel(cmd, port_mmio + PORT_CMD); | |
995 | cmd = readl(port_mmio + PORT_CMD); | |
996 | ||
997 | /* IPM bits should be set by libata-core */ | |
998 | return 0; | |
999 | } | |
1000 | ||
438ac6d5 | 1001 | #ifdef CONFIG_PM |
4447d351 | 1002 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 1003 | { |
4447d351 TH |
1004 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1005 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
1006 | u32 cmd, scontrol; |
1007 | ||
4447d351 | 1008 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 1009 | return; |
0be0aa98 | 1010 | |
07c53dac TH |
1011 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
1012 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
1013 | scontrol &= ~0xf; | |
1014 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 1015 | |
07c53dac TH |
1016 | /* then set PxCMD.SUD to 0 */ |
1017 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1018 | cmd &= ~PORT_CMD_SPIN_UP; | |
1019 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 1020 | } |
438ac6d5 | 1021 | #endif |
0be0aa98 | 1022 | |
df69c9c5 | 1023 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 1024 | { |
0be0aa98 | 1025 | /* enable FIS reception */ |
4447d351 | 1026 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
1027 | |
1028 | /* enable DMA */ | |
4447d351 | 1029 | ahci_start_engine(ap); |
0be0aa98 TH |
1030 | } |
1031 | ||
4447d351 | 1032 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
1033 | { |
1034 | int rc; | |
1035 | ||
1036 | /* disable DMA */ | |
4447d351 | 1037 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1038 | if (rc) { |
1039 | *emsg = "failed to stop engine"; | |
1040 | return rc; | |
1041 | } | |
1042 | ||
1043 | /* disable FIS reception */ | |
4447d351 | 1044 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1045 | if (rc) { |
1046 | *emsg = "failed stop FIS RX"; | |
1047 | return rc; | |
1048 | } | |
1049 | ||
0be0aa98 TH |
1050 | return 0; |
1051 | } | |
1052 | ||
4447d351 | 1053 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1054 | { |
4447d351 | 1055 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1056 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1057 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1058 | u32 tmp; |
d91542c1 | 1059 | |
3cc3eb11 JG |
1060 | /* we must be in AHCI mode, before using anything |
1061 | * AHCI-specific, such as HOST_RESET. | |
1062 | */ | |
b710a1f4 | 1063 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1064 | |
1065 | /* global controller reset */ | |
b710a1f4 | 1066 | tmp = readl(mmio + HOST_CTL); |
d91542c1 TH |
1067 | if ((tmp & HOST_RESET) == 0) { |
1068 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1069 | readl(mmio + HOST_CTL); /* flush */ | |
1070 | } | |
1071 | ||
1072 | /* reset must complete within 1 second, or | |
1073 | * the hardware should be considered fried. | |
1074 | */ | |
1075 | ssleep(1); | |
1076 | ||
1077 | tmp = readl(mmio + HOST_CTL); | |
1078 | if (tmp & HOST_RESET) { | |
4447d351 | 1079 | dev_printk(KERN_ERR, host->dev, |
d91542c1 TH |
1080 | "controller reset failed (0x%x)\n", tmp); |
1081 | return -EIO; | |
1082 | } | |
1083 | ||
98fa4b60 | 1084 | /* turn on AHCI mode */ |
b710a1f4 | 1085 | ahci_enable_ahci(mmio); |
98fa4b60 | 1086 | |
d447df14 | 1087 | /* some registers might be cleared on reset. restore initial values */ |
4447d351 | 1088 | ahci_restore_initial_config(host); |
d91542c1 TH |
1089 | |
1090 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1091 | u16 tmp16; | |
1092 | ||
1093 | /* configure PCS */ | |
1094 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1095 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1096 | tmp16 |= hpriv->port_map; | |
1097 | pci_write_config_word(pdev, 0x92, tmp16); | |
1098 | } | |
d91542c1 TH |
1099 | } |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
2bcd866b JG |
1104 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1105 | int port_no, void __iomem *mmio, | |
1106 | void __iomem *port_mmio) | |
1107 | { | |
1108 | const char *emsg = NULL; | |
1109 | int rc; | |
1110 | u32 tmp; | |
1111 | ||
1112 | /* make sure port is not active */ | |
1113 | rc = ahci_deinit_port(ap, &emsg); | |
1114 | if (rc) | |
1115 | dev_printk(KERN_WARNING, &pdev->dev, | |
1116 | "%s (%d)\n", emsg, rc); | |
1117 | ||
1118 | /* clear SError */ | |
1119 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1120 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1121 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1122 | ||
1123 | /* clear port IRQ */ | |
1124 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1125 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1126 | if (tmp) | |
1127 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1128 | ||
1129 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1130 | } | |
1131 | ||
4447d351 | 1132 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1133 | { |
417a1a6d | 1134 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1135 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1136 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1137 | int i; |
cd70c266 | 1138 | void __iomem *port_mmio; |
d91542c1 TH |
1139 | u32 tmp; |
1140 | ||
417a1a6d | 1141 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
cd70c266 JG |
1142 | port_mmio = __ahci_port_base(host, 4); |
1143 | ||
1144 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1145 | ||
1146 | /* clear port IRQ */ | |
1147 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1148 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1149 | if (tmp) | |
1150 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1151 | } | |
1152 | ||
4447d351 TH |
1153 | for (i = 0; i < host->n_ports; i++) { |
1154 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1155 | |
cd70c266 | 1156 | port_mmio = ahci_port_base(ap); |
4447d351 | 1157 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1158 | continue; |
d91542c1 | 1159 | |
2bcd866b | 1160 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1161 | } |
1162 | ||
1163 | tmp = readl(mmio + HOST_CTL); | |
1164 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1165 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1166 | tmp = readl(mmio + HOST_CTL); | |
1167 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1168 | } | |
1169 | ||
422b7595 | 1170 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1171 | { |
4447d351 | 1172 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1173 | struct ata_taskfile tf; |
422b7595 TH |
1174 | u32 tmp; |
1175 | ||
1176 | tmp = readl(port_mmio + PORT_SIG); | |
1177 | tf.lbah = (tmp >> 24) & 0xff; | |
1178 | tf.lbam = (tmp >> 16) & 0xff; | |
1179 | tf.lbal = (tmp >> 8) & 0xff; | |
1180 | tf.nsect = (tmp) & 0xff; | |
1181 | ||
1182 | return ata_dev_classify(&tf); | |
1183 | } | |
1184 | ||
12fad3f9 TH |
1185 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1186 | u32 opts) | |
cc9278ed | 1187 | { |
12fad3f9 TH |
1188 | dma_addr_t cmd_tbl_dma; |
1189 | ||
1190 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1191 | ||
1192 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1193 | pp->cmd_slot[tag].status = 0; | |
1194 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1195 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1196 | } |
1197 | ||
d2e75dff | 1198 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1199 | { |
0d5ff566 | 1200 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 1201 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 | 1202 | u32 tmp; |
d2e75dff | 1203 | int busy, rc; |
bf2af2a2 | 1204 | |
d2e75dff TH |
1205 | /* do we need to kick the port? */ |
1206 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); | |
1207 | if (!busy && !force_restart) | |
1208 | return 0; | |
1209 | ||
1210 | /* stop engine */ | |
1211 | rc = ahci_stop_engine(ap); | |
1212 | if (rc) | |
1213 | goto out_restart; | |
1214 | ||
1215 | /* need to do CLO? */ | |
1216 | if (!busy) { | |
1217 | rc = 0; | |
1218 | goto out_restart; | |
1219 | } | |
1220 | ||
1221 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1222 | rc = -EOPNOTSUPP; | |
1223 | goto out_restart; | |
1224 | } | |
bf2af2a2 | 1225 | |
d2e75dff | 1226 | /* perform CLO */ |
bf2af2a2 BJ |
1227 | tmp = readl(port_mmio + PORT_CMD); |
1228 | tmp |= PORT_CMD_CLO; | |
1229 | writel(tmp, port_mmio + PORT_CMD); | |
1230 | ||
d2e75dff | 1231 | rc = 0; |
bf2af2a2 BJ |
1232 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1233 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1234 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1235 | rc = -EIO; |
bf2af2a2 | 1236 | |
d2e75dff TH |
1237 | /* restart engine */ |
1238 | out_restart: | |
1239 | ahci_start_engine(ap); | |
1240 | return rc; | |
bf2af2a2 BJ |
1241 | } |
1242 | ||
91c4a2e0 TH |
1243 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1244 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1245 | unsigned long timeout_msec) | |
bf2af2a2 | 1246 | { |
91c4a2e0 | 1247 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1248 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1249 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1250 | u8 *fis = pp->cmd_tbl; |
1251 | u32 tmp; | |
1252 | ||
1253 | /* prep the command */ | |
1254 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1255 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1256 | ||
1257 | /* issue & wait */ | |
1258 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1259 | ||
1260 | if (timeout_msec) { | |
1261 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1262 | 1, timeout_msec); | |
1263 | if (tmp & 0x1) { | |
1264 | ahci_kick_engine(ap, 1); | |
1265 | return -EBUSY; | |
1266 | } | |
1267 | } else | |
1268 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
cc0680a5 | 1273 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 | 1274 | int pmp, unsigned long deadline) |
91c4a2e0 | 1275 | { |
cc0680a5 | 1276 | struct ata_port *ap = link->ap; |
4658f79b | 1277 | const char *reason = NULL; |
2cbb79eb | 1278 | unsigned long now, msecs; |
4658f79b | 1279 | struct ata_taskfile tf; |
4658f79b TH |
1280 | int rc; |
1281 | ||
1282 | DPRINTK("ENTER\n"); | |
1283 | ||
cc0680a5 | 1284 | if (ata_link_offline(link)) { |
c2a65852 TH |
1285 | DPRINTK("PHY reports no device\n"); |
1286 | *class = ATA_DEV_NONE; | |
1287 | return 0; | |
1288 | } | |
1289 | ||
4658f79b | 1290 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff | 1291 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1292 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1293 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1294 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1295 | |
cc0680a5 | 1296 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1297 | |
1298 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1299 | msecs = 0; |
1300 | now = jiffies; | |
1301 | if (time_after(now, deadline)) | |
1302 | msecs = jiffies_to_msecs(deadline - now); | |
1303 | ||
4658f79b | 1304 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1305 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1306 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1307 | rc = -EIO; |
1308 | reason = "1st FIS failed"; | |
1309 | goto fail; | |
1310 | } | |
1311 | ||
1312 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1313 | msleep(1); | |
1314 | ||
1315 | /* issue the second D2H Register FIS */ | |
4658f79b | 1316 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1317 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1318 | |
88ff6eaf TH |
1319 | /* wait a while before checking status */ |
1320 | ata_wait_after_reset(ap, deadline); | |
4658f79b | 1321 | |
9b89391c TH |
1322 | rc = ata_wait_ready(ap, deadline); |
1323 | /* link occupied, -ENODEV too is an error */ | |
1324 | if (rc) { | |
1325 | reason = "device not ready"; | |
1326 | goto fail; | |
4658f79b | 1327 | } |
9b89391c | 1328 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1329 | |
1330 | DPRINTK("EXIT, class=%u\n", *class); | |
1331 | return 0; | |
1332 | ||
4658f79b | 1333 | fail: |
cc0680a5 | 1334 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1335 | return rc; |
1336 | } | |
1337 | ||
cc0680a5 | 1338 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 TH |
1339 | unsigned long deadline) |
1340 | { | |
7d50b60b TH |
1341 | int pmp = 0; |
1342 | ||
1343 | if (link->ap->flags & ATA_FLAG_PMP) | |
1344 | pmp = SATA_PMP_CTRL_PORT; | |
1345 | ||
1346 | return ahci_do_softreset(link, class, pmp, deadline); | |
a9cf5e85 TH |
1347 | } |
1348 | ||
cc0680a5 | 1349 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1350 | unsigned long deadline) |
422b7595 | 1351 | { |
cc0680a5 | 1352 | struct ata_port *ap = link->ap; |
4296971d TH |
1353 | struct ahci_port_priv *pp = ap->private_data; |
1354 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1355 | struct ata_taskfile tf; | |
4bd00f6a TH |
1356 | int rc; |
1357 | ||
1358 | DPRINTK("ENTER\n"); | |
1da177e4 | 1359 | |
4447d351 | 1360 | ahci_stop_engine(ap); |
4296971d TH |
1361 | |
1362 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1363 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1364 | tf.command = 0x80; |
9977126c | 1365 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1366 | |
cc0680a5 | 1367 | rc = sata_std_hardreset(link, class, deadline); |
4296971d | 1368 | |
4447d351 | 1369 | ahci_start_engine(ap); |
1da177e4 | 1370 | |
cc0680a5 | 1371 | if (rc == 0 && ata_link_online(link)) |
4bd00f6a | 1372 | *class = ahci_dev_classify(ap); |
7d50b60b | 1373 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
4bd00f6a | 1374 | *class = ATA_DEV_NONE; |
1da177e4 | 1375 | |
4bd00f6a TH |
1376 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1377 | return rc; | |
1378 | } | |
1379 | ||
cc0680a5 | 1380 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1381 | unsigned long deadline) |
ad616ffb | 1382 | { |
cc0680a5 | 1383 | struct ata_port *ap = link->ap; |
da3dbb17 | 1384 | u32 serror; |
ad616ffb TH |
1385 | int rc; |
1386 | ||
1387 | DPRINTK("ENTER\n"); | |
1388 | ||
4447d351 | 1389 | ahci_stop_engine(ap); |
ad616ffb | 1390 | |
cc0680a5 | 1391 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
d4b2bab4 | 1392 | deadline); |
ad616ffb TH |
1393 | |
1394 | /* vt8251 needs SError cleared for the port to operate */ | |
da3dbb17 TH |
1395 | ahci_scr_read(ap, SCR_ERROR, &serror); |
1396 | ahci_scr_write(ap, SCR_ERROR, serror); | |
ad616ffb | 1397 | |
4447d351 | 1398 | ahci_start_engine(ap); |
ad616ffb TH |
1399 | |
1400 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1401 | ||
1402 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1403 | * request follow-up softreset. | |
1404 | */ | |
1405 | return rc ?: -EAGAIN; | |
1406 | } | |
1407 | ||
edc93052 TH |
1408 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1409 | unsigned long deadline) | |
1410 | { | |
1411 | struct ata_port *ap = link->ap; | |
1412 | struct ahci_port_priv *pp = ap->private_data; | |
1413 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1414 | struct ata_taskfile tf; | |
1415 | int rc; | |
1416 | ||
1417 | ahci_stop_engine(ap); | |
1418 | ||
1419 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1420 | ata_tf_init(link->device, &tf); | |
1421 | tf.command = 0x80; | |
1422 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1423 | ||
1424 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
1425 | deadline); | |
1426 | ||
1427 | ahci_start_engine(ap); | |
1428 | ||
1429 | if (rc || ata_link_offline(link)) | |
1430 | return rc; | |
1431 | ||
1432 | /* spec mandates ">= 2ms" before checking status */ | |
1433 | msleep(150); | |
1434 | ||
1435 | /* The pseudo configuration device on SIMG4726 attached to | |
1436 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1437 | * hardreset if no device is attached to the first downstream | |
1438 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1439 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1440 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1441 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1442 | * | |
1443 | * Wait for two seconds. Devices attached to downstream port | |
1444 | * which can't process the following IDENTIFY after this will | |
1445 | * have to be reset again. For most cases, this should | |
1446 | * suffice while making probing snappish enough. | |
1447 | */ | |
1448 | rc = ata_wait_ready(ap, jiffies + 2 * HZ); | |
1449 | if (rc) | |
1450 | ahci_kick_engine(ap, 0); | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
cc0680a5 | 1455 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1456 | { |
cc0680a5 | 1457 | struct ata_port *ap = link->ap; |
4447d351 | 1458 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1459 | u32 new_tmp, tmp; |
1460 | ||
cc0680a5 | 1461 | ata_std_postreset(link, class); |
02eaa666 JG |
1462 | |
1463 | /* Make sure port's ATAPI bit is set appropriately */ | |
1464 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1465 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1466 | new_tmp |= PORT_CMD_ATAPI; |
1467 | else | |
1468 | new_tmp &= ~PORT_CMD_ATAPI; | |
1469 | if (new_tmp != tmp) { | |
1470 | writel(new_tmp, port_mmio + PORT_CMD); | |
1471 | readl(port_mmio + PORT_CMD); /* flush */ | |
1472 | } | |
1da177e4 LT |
1473 | } |
1474 | ||
7d50b60b TH |
1475 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
1476 | unsigned long deadline) | |
1477 | { | |
1478 | return ahci_do_softreset(link, class, link->pmp, deadline); | |
1479 | } | |
1480 | ||
1da177e4 LT |
1481 | static u8 ahci_check_status(struct ata_port *ap) |
1482 | { | |
0d5ff566 | 1483 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1484 | |
1485 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1486 | } | |
1487 | ||
1da177e4 LT |
1488 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1489 | { | |
1490 | struct ahci_port_priv *pp = ap->private_data; | |
1491 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1492 | ||
1493 | ata_tf_from_fis(d2h_fis, tf); | |
1494 | } | |
1495 | ||
12fad3f9 | 1496 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1497 | { |
cedc9a47 | 1498 | struct scatterlist *sg; |
ff2aeb1e TH |
1499 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
1500 | unsigned int si; | |
1da177e4 LT |
1501 | |
1502 | VPRINTK("ENTER\n"); | |
1503 | ||
1504 | /* | |
1505 | * Next, the S/G list. | |
1506 | */ | |
ff2aeb1e | 1507 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
1508 | dma_addr_t addr = sg_dma_address(sg); |
1509 | u32 sg_len = sg_dma_len(sg); | |
1510 | ||
ff2aeb1e TH |
1511 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
1512 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1513 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 1514 | } |
828d09de | 1515 | |
ff2aeb1e | 1516 | return si; |
1da177e4 LT |
1517 | } |
1518 | ||
1519 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1520 | { | |
a0ea7328 JG |
1521 | struct ata_port *ap = qc->ap; |
1522 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1523 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1524 | void *cmd_tbl; |
1da177e4 LT |
1525 | u32 opts; |
1526 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1527 | unsigned int n_elem; |
1da177e4 | 1528 | |
1da177e4 LT |
1529 | /* |
1530 | * Fill in command table information. First, the header, | |
1531 | * a SATA Register - Host to Device command FIS. | |
1532 | */ | |
12fad3f9 TH |
1533 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1534 | ||
7d50b60b | 1535 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1536 | if (is_atapi) { |
12fad3f9 TH |
1537 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1538 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1539 | } |
1da177e4 | 1540 | |
cc9278ed TH |
1541 | n_elem = 0; |
1542 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1543 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1544 | |
cc9278ed TH |
1545 | /* |
1546 | * Fill in command slot information. | |
1547 | */ | |
7d50b60b | 1548 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1549 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1550 | opts |= AHCI_CMD_WRITE; | |
1551 | if (is_atapi) | |
4b10e559 | 1552 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1553 | |
12fad3f9 | 1554 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1555 | } |
1556 | ||
78cd52d0 | 1557 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1558 | { |
417a1a6d | 1559 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1560 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1561 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1562 | struct ata_link *link = NULL; | |
1563 | struct ata_queued_cmd *active_qc; | |
1564 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1565 | u32 serror; |
1da177e4 | 1566 | |
7d50b60b TH |
1567 | /* determine active link */ |
1568 | ata_port_for_each_link(link, ap) | |
1569 | if (ata_link_active(link)) | |
1570 | break; | |
1571 | if (!link) | |
1572 | link = &ap->link; | |
1573 | ||
1574 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1575 | active_ehi = &link->eh_info; | |
1576 | ||
1577 | /* record irq stat */ | |
1578 | ata_ehi_clear_desc(host_ehi); | |
1579 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1580 | |
78cd52d0 | 1581 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1582 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1583 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1584 | host_ehi->serror |= serror; |
78cd52d0 | 1585 | |
41669553 | 1586 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1587 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1588 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1589 | ||
55a61604 | 1590 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1591 | /* If qc is active, charge it; otherwise, the active |
1592 | * link. There's no active qc on NCQ errors. It will | |
1593 | * be determined by EH by reading log page 10h. | |
1594 | */ | |
1595 | if (active_qc) | |
1596 | active_qc->err_mask |= AC_ERR_DEV; | |
1597 | else | |
1598 | active_ehi->err_mask |= AC_ERR_DEV; | |
1599 | ||
417a1a6d | 1600 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1601 | host_ehi->serror &= ~SERR_INTERNAL; |
1602 | } | |
1603 | ||
1604 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1605 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1606 | ||
1607 | active_ehi->err_mask |= AC_ERR_HSM; | |
1608 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1609 | ata_ehi_push_desc(active_ehi, | |
1610 | "unknown FIS %08x %08x %08x %08x" , | |
1611 | unk[0], unk[1], unk[2], unk[3]); | |
1612 | } | |
1613 | ||
1614 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1615 | active_ehi->err_mask |= AC_ERR_HSM; | |
1616 | active_ehi->action |= ATA_EH_SOFTRESET; | |
1617 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); | |
55a61604 | 1618 | } |
78cd52d0 TH |
1619 | |
1620 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b TH |
1621 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
1622 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1623 | ata_ehi_push_desc(host_ehi, "host bus error"); | |
1da177e4 LT |
1624 | } |
1625 | ||
78cd52d0 | 1626 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b TH |
1627 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
1628 | host_ehi->action |= ATA_EH_SOFTRESET; | |
1629 | ata_ehi_push_desc(host_ehi, "interface fatal error"); | |
78cd52d0 | 1630 | } |
1da177e4 | 1631 | |
78cd52d0 | 1632 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1633 | ata_ehi_hotplugged(host_ehi); |
1634 | ata_ehi_push_desc(host_ehi, "%s", | |
1635 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1636 | "connection status changed" : "PHY RDY changed"); |
1637 | } | |
1638 | ||
78cd52d0 | 1639 | /* okay, let's hand over to EH */ |
a72ec4ce | 1640 | |
78cd52d0 TH |
1641 | if (irq_stat & PORT_IRQ_FREEZE) |
1642 | ata_port_freeze(ap); | |
1643 | else | |
1644 | ata_port_abort(ap); | |
1da177e4 LT |
1645 | } |
1646 | ||
df69c9c5 | 1647 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1648 | { |
4447d351 | 1649 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
9af5c9c9 | 1650 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1651 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 1652 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 1653 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 1654 | u32 status, qc_active; |
459ad688 | 1655 | int rc; |
1da177e4 LT |
1656 | |
1657 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1658 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1659 | ||
b06ce3e5 TH |
1660 | /* ignore BAD_PMP while resetting */ |
1661 | if (unlikely(resetting)) | |
1662 | status &= ~PORT_IRQ_BAD_PMP; | |
1663 | ||
31556594 KCA |
1664 | /* If we are getting PhyRdy, this is |
1665 | * just a power state change, we should | |
1666 | * clear out this, plus the PhyRdy/Comm | |
1667 | * Wake bits from Serror | |
1668 | */ | |
1669 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
1670 | (status & PORT_IRQ_PHYRDY)) { | |
1671 | status &= ~PORT_IRQ_PHYRDY; | |
1672 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
1673 | } | |
1674 | ||
78cd52d0 TH |
1675 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1676 | ahci_error_intr(ap, status); | |
1677 | return; | |
1da177e4 LT |
1678 | } |
1679 | ||
2f294968 | 1680 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
1681 | /* If SNotification is available, leave notification |
1682 | * handling to sata_async_notification(). If not, | |
1683 | * emulate it by snooping SDB FIS RX area. | |
1684 | * | |
1685 | * Snooping FIS RX area is probably cheaper than | |
1686 | * poking SNotification but some constrollers which | |
1687 | * implement SNotification, ICH9 for example, don't | |
1688 | * store AN SDB FIS into receive area. | |
2f294968 | 1689 | */ |
5f226c6b | 1690 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 1691 | sata_async_notification(ap); |
5f226c6b TH |
1692 | else { |
1693 | /* If the 'N' bit in word 0 of the FIS is set, | |
1694 | * we just received asynchronous notification. | |
1695 | * Tell libata about it. | |
1696 | */ | |
1697 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1698 | u32 f0 = le32_to_cpu(f[0]); | |
1699 | ||
1700 | if (f0 & (1 << 15)) | |
1701 | sata_async_notification(ap); | |
1702 | } | |
2f294968 KCA |
1703 | } |
1704 | ||
7d50b60b TH |
1705 | /* pp->active_link is valid iff any command is in flight */ |
1706 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1707 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1708 | else | |
1709 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1710 | ||
1711 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
b06ce3e5 | 1712 | |
459ad688 TH |
1713 | /* while resetting, invalid completions are expected */ |
1714 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 TH |
1715 | ehi->err_mask |= AC_ERR_HSM; |
1716 | ehi->action |= ATA_EH_SOFTRESET; | |
1717 | ata_port_freeze(ap); | |
1da177e4 | 1718 | } |
1da177e4 LT |
1719 | } |
1720 | ||
1721 | static void ahci_irq_clear(struct ata_port *ap) | |
1722 | { | |
1723 | /* TODO */ | |
1724 | } | |
1725 | ||
7d12e780 | 1726 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1727 | { |
cca3974e | 1728 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1729 | struct ahci_host_priv *hpriv; |
1730 | unsigned int i, handled = 0; | |
ea6ba10b | 1731 | void __iomem *mmio; |
1da177e4 LT |
1732 | u32 irq_stat, irq_ack = 0; |
1733 | ||
1734 | VPRINTK("ENTER\n"); | |
1735 | ||
cca3974e | 1736 | hpriv = host->private_data; |
0d5ff566 | 1737 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1738 | |
1739 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1740 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1741 | irq_stat &= hpriv->port_map; | |
1742 | if (!irq_stat) | |
1743 | return IRQ_NONE; | |
1744 | ||
2dcb407e | 1745 | spin_lock(&host->lock); |
1da177e4 | 1746 | |
2dcb407e | 1747 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1748 | struct ata_port *ap; |
1da177e4 | 1749 | |
67846b30 JG |
1750 | if (!(irq_stat & (1 << i))) |
1751 | continue; | |
1752 | ||
cca3974e | 1753 | ap = host->ports[i]; |
67846b30 | 1754 | if (ap) { |
df69c9c5 | 1755 | ahci_port_intr(ap); |
67846b30 JG |
1756 | VPRINTK("port %u\n", i); |
1757 | } else { | |
1758 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1759 | if (ata_ratelimit()) |
cca3974e | 1760 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1761 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1762 | } |
67846b30 JG |
1763 | |
1764 | irq_ack |= (1 << i); | |
1da177e4 LT |
1765 | } |
1766 | ||
1767 | if (irq_ack) { | |
1768 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1769 | handled = 1; | |
1770 | } | |
1771 | ||
cca3974e | 1772 | spin_unlock(&host->lock); |
1da177e4 LT |
1773 | |
1774 | VPRINTK("EXIT\n"); | |
1775 | ||
1776 | return IRQ_RETVAL(handled); | |
1777 | } | |
1778 | ||
9a3d9eb0 | 1779 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1780 | { |
1781 | struct ata_port *ap = qc->ap; | |
4447d351 | 1782 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1783 | struct ahci_port_priv *pp = ap->private_data; |
1784 | ||
1785 | /* Keep track of the currently active link. It will be used | |
1786 | * in completion path to determine whether NCQ phase is in | |
1787 | * progress. | |
1788 | */ | |
1789 | pp->active_link = qc->dev->link; | |
1da177e4 | 1790 | |
12fad3f9 TH |
1791 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1792 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1793 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1794 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
78cd52d0 TH |
1799 | static void ahci_freeze(struct ata_port *ap) |
1800 | { | |
4447d351 | 1801 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1802 | |
1803 | /* turn IRQ off */ | |
1804 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1805 | } | |
1806 | ||
1807 | static void ahci_thaw(struct ata_port *ap) | |
1808 | { | |
0d5ff566 | 1809 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1810 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1811 | u32 tmp; |
a7384925 | 1812 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1813 | |
1814 | /* clear IRQ */ | |
1815 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1816 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1817 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1818 | |
1c954a4d TH |
1819 | /* turn IRQ back on */ |
1820 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1821 | } |
1822 | ||
1823 | static void ahci_error_handler(struct ata_port *ap) | |
1824 | { | |
b51e9e5d | 1825 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1826 | /* restart engine */ |
4447d351 TH |
1827 | ahci_stop_engine(ap); |
1828 | ahci_start_engine(ap); | |
78cd52d0 TH |
1829 | } |
1830 | ||
1831 | /* perform recovery */ | |
7d50b60b TH |
1832 | sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, |
1833 | ahci_hardreset, ahci_postreset, | |
1834 | sata_pmp_std_prereset, ahci_pmp_softreset, | |
1835 | sata_pmp_std_hardreset, sata_pmp_std_postreset); | |
78cd52d0 TH |
1836 | } |
1837 | ||
ad616ffb TH |
1838 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1839 | { | |
ad616ffb TH |
1840 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
1841 | /* restart engine */ | |
4447d351 TH |
1842 | ahci_stop_engine(ap); |
1843 | ahci_start_engine(ap); | |
ad616ffb TH |
1844 | } |
1845 | ||
1846 | /* perform recovery */ | |
1847 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1848 | ahci_postreset); | |
1849 | } | |
1850 | ||
edc93052 TH |
1851 | static void ahci_p5wdh_error_handler(struct ata_port *ap) |
1852 | { | |
1853 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | |
1854 | /* restart engine */ | |
1855 | ahci_stop_engine(ap); | |
1856 | ahci_start_engine(ap); | |
1857 | } | |
1858 | ||
1859 | /* perform recovery */ | |
1860 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset, | |
1861 | ahci_postreset); | |
1862 | } | |
1863 | ||
78cd52d0 TH |
1864 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1865 | { | |
1866 | struct ata_port *ap = qc->ap; | |
1867 | ||
d2e75dff TH |
1868 | /* make DMA engine forget about the failed command */ |
1869 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1870 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1871 | } |
1872 | ||
7d50b60b TH |
1873 | static void ahci_pmp_attach(struct ata_port *ap) |
1874 | { | |
1875 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1876 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1877 | u32 cmd; |
1878 | ||
1879 | cmd = readl(port_mmio + PORT_CMD); | |
1880 | cmd |= PORT_CMD_PMP; | |
1881 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1882 | |
1883 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
1884 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1885 | } |
1886 | ||
1887 | static void ahci_pmp_detach(struct ata_port *ap) | |
1888 | { | |
1889 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1890 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1891 | u32 cmd; |
1892 | ||
1893 | cmd = readl(port_mmio + PORT_CMD); | |
1894 | cmd &= ~PORT_CMD_PMP; | |
1895 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1896 | |
1897 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
1898 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1899 | } |
1900 | ||
028a2596 AD |
1901 | static int ahci_port_resume(struct ata_port *ap) |
1902 | { | |
1903 | ahci_power_up(ap); | |
1904 | ahci_start_port(ap); | |
1905 | ||
7d50b60b TH |
1906 | if (ap->nr_pmp_links) |
1907 | ahci_pmp_attach(ap); | |
1908 | else | |
1909 | ahci_pmp_detach(ap); | |
1910 | ||
028a2596 AD |
1911 | return 0; |
1912 | } | |
1913 | ||
438ac6d5 | 1914 | #ifdef CONFIG_PM |
c1332875 TH |
1915 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1916 | { | |
c1332875 TH |
1917 | const char *emsg = NULL; |
1918 | int rc; | |
1919 | ||
4447d351 | 1920 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1921 | if (rc == 0) |
4447d351 | 1922 | ahci_power_down(ap); |
8e16f941 | 1923 | else { |
c1332875 | 1924 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1925 | ahci_start_port(ap); |
c1332875 TH |
1926 | } |
1927 | ||
1928 | return rc; | |
1929 | } | |
1930 | ||
c1332875 TH |
1931 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1932 | { | |
cca3974e | 1933 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1934 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1935 | u32 ctl; |
1936 | ||
1937 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1938 | /* AHCI spec rev1.1 section 8.3.3: | |
1939 | * Software must disable interrupts prior to requesting a | |
1940 | * transition of the HBA to D3 state. | |
1941 | */ | |
1942 | ctl = readl(mmio + HOST_CTL); | |
1943 | ctl &= ~HOST_IRQ_EN; | |
1944 | writel(ctl, mmio + HOST_CTL); | |
1945 | readl(mmio + HOST_CTL); /* flush */ | |
1946 | } | |
1947 | ||
1948 | return ata_pci_device_suspend(pdev, mesg); | |
1949 | } | |
1950 | ||
1951 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1952 | { | |
cca3974e | 1953 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1954 | int rc; |
1955 | ||
553c4aa6 TH |
1956 | rc = ata_pci_device_do_resume(pdev); |
1957 | if (rc) | |
1958 | return rc; | |
c1332875 TH |
1959 | |
1960 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1961 | rc = ahci_reset_controller(host); |
c1332875 TH |
1962 | if (rc) |
1963 | return rc; | |
1964 | ||
4447d351 | 1965 | ahci_init_controller(host); |
c1332875 TH |
1966 | } |
1967 | ||
cca3974e | 1968 | ata_host_resume(host); |
c1332875 TH |
1969 | |
1970 | return 0; | |
1971 | } | |
438ac6d5 | 1972 | #endif |
c1332875 | 1973 | |
254950cd TH |
1974 | static int ahci_port_start(struct ata_port *ap) |
1975 | { | |
cca3974e | 1976 | struct device *dev = ap->host->dev; |
254950cd | 1977 | struct ahci_port_priv *pp; |
254950cd TH |
1978 | void *mem; |
1979 | dma_addr_t mem_dma; | |
1980 | int rc; | |
1981 | ||
24dc5f33 | 1982 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1983 | if (!pp) |
1984 | return -ENOMEM; | |
254950cd TH |
1985 | |
1986 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1987 | if (rc) |
254950cd | 1988 | return rc; |
254950cd | 1989 | |
24dc5f33 TH |
1990 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1991 | GFP_KERNEL); | |
1992 | if (!mem) | |
254950cd | 1993 | return -ENOMEM; |
254950cd TH |
1994 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1995 | ||
1996 | /* | |
1997 | * First item in chunk of DMA memory: 32-slot command table, | |
1998 | * 32 bytes each in size | |
1999 | */ | |
2000 | pp->cmd_slot = mem; | |
2001 | pp->cmd_slot_dma = mem_dma; | |
2002 | ||
2003 | mem += AHCI_CMD_SLOT_SZ; | |
2004 | mem_dma += AHCI_CMD_SLOT_SZ; | |
2005 | ||
2006 | /* | |
2007 | * Second item: Received-FIS area | |
2008 | */ | |
2009 | pp->rx_fis = mem; | |
2010 | pp->rx_fis_dma = mem_dma; | |
2011 | ||
2012 | mem += AHCI_RX_FIS_SZ; | |
2013 | mem_dma += AHCI_RX_FIS_SZ; | |
2014 | ||
2015 | /* | |
2016 | * Third item: data area for storing a single command | |
2017 | * and its scatter-gather table | |
2018 | */ | |
2019 | pp->cmd_tbl = mem; | |
2020 | pp->cmd_tbl_dma = mem_dma; | |
2021 | ||
a7384925 | 2022 | /* |
2dcb407e JG |
2023 | * Save off initial list of interrupts to be enabled. |
2024 | * This could be changed later | |
2025 | */ | |
a7384925 KCA |
2026 | pp->intr_mask = DEF_PORT_IRQ; |
2027 | ||
254950cd TH |
2028 | ap->private_data = pp; |
2029 | ||
df69c9c5 JG |
2030 | /* engage engines, captain */ |
2031 | return ahci_port_resume(ap); | |
254950cd TH |
2032 | } |
2033 | ||
2034 | static void ahci_port_stop(struct ata_port *ap) | |
2035 | { | |
0be0aa98 TH |
2036 | const char *emsg = NULL; |
2037 | int rc; | |
254950cd | 2038 | |
0be0aa98 | 2039 | /* de-initialize port */ |
4447d351 | 2040 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
2041 | if (rc) |
2042 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
2043 | } |
2044 | ||
4447d351 | 2045 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 2046 | { |
1da177e4 | 2047 | int rc; |
1da177e4 | 2048 | |
1da177e4 LT |
2049 | if (using_dac && |
2050 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
2051 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
2052 | if (rc) { | |
2053 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2054 | if (rc) { | |
a9524a76 JG |
2055 | dev_printk(KERN_ERR, &pdev->dev, |
2056 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2057 | return rc; |
2058 | } | |
2059 | } | |
1da177e4 LT |
2060 | } else { |
2061 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2062 | if (rc) { | |
a9524a76 JG |
2063 | dev_printk(KERN_ERR, &pdev->dev, |
2064 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2065 | return rc; |
2066 | } | |
2067 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2068 | if (rc) { | |
a9524a76 JG |
2069 | dev_printk(KERN_ERR, &pdev->dev, |
2070 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2071 | return rc; |
2072 | } | |
2073 | } | |
1da177e4 LT |
2074 | return 0; |
2075 | } | |
2076 | ||
4447d351 | 2077 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2078 | { |
4447d351 TH |
2079 | struct ahci_host_priv *hpriv = host->private_data; |
2080 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2081 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2082 | u32 vers, cap, impl, speed; |
2083 | const char *speed_s; | |
2084 | u16 cc; | |
2085 | const char *scc_s; | |
2086 | ||
2087 | vers = readl(mmio + HOST_VERSION); | |
2088 | cap = hpriv->cap; | |
2089 | impl = hpriv->port_map; | |
2090 | ||
2091 | speed = (cap >> 20) & 0xf; | |
2092 | if (speed == 1) | |
2093 | speed_s = "1.5"; | |
2094 | else if (speed == 2) | |
2095 | speed_s = "3"; | |
2096 | else | |
2097 | speed_s = "?"; | |
2098 | ||
2099 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2100 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2101 | scc_s = "IDE"; |
c9f89475 | 2102 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2103 | scc_s = "SATA"; |
c9f89475 | 2104 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2105 | scc_s = "RAID"; |
2106 | else | |
2107 | scc_s = "unknown"; | |
2108 | ||
a9524a76 JG |
2109 | dev_printk(KERN_INFO, &pdev->dev, |
2110 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2111 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2112 | , |
1da177e4 | 2113 | |
2dcb407e JG |
2114 | (vers >> 24) & 0xff, |
2115 | (vers >> 16) & 0xff, | |
2116 | (vers >> 8) & 0xff, | |
2117 | vers & 0xff, | |
1da177e4 LT |
2118 | |
2119 | ((cap >> 8) & 0x1f) + 1, | |
2120 | (cap & 0x1f) + 1, | |
2121 | speed_s, | |
2122 | impl, | |
2123 | scc_s); | |
2124 | ||
a9524a76 JG |
2125 | dev_printk(KERN_INFO, &pdev->dev, |
2126 | "flags: " | |
203ef6c4 TH |
2127 | "%s%s%s%s%s%s%s" |
2128 | "%s%s%s%s%s%s%s\n" | |
2dcb407e | 2129 | , |
1da177e4 LT |
2130 | |
2131 | cap & (1 << 31) ? "64bit " : "", | |
2132 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2133 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2134 | cap & (1 << 28) ? "ilck " : "", |
2135 | cap & (1 << 27) ? "stag " : "", | |
2136 | cap & (1 << 26) ? "pm " : "", | |
2137 | cap & (1 << 25) ? "led " : "", | |
2138 | ||
2139 | cap & (1 << 24) ? "clo " : "", | |
2140 | cap & (1 << 19) ? "nz " : "", | |
2141 | cap & (1 << 18) ? "only " : "", | |
2142 | cap & (1 << 17) ? "pmp " : "", | |
2143 | cap & (1 << 15) ? "pio " : "", | |
2144 | cap & (1 << 14) ? "slum " : "", | |
2145 | cap & (1 << 13) ? "part " : "" | |
2146 | ); | |
2147 | } | |
2148 | ||
edc93052 TH |
2149 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2150 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2151 | * support PMP and the 4726 either directly exports the device | |
2152 | * attached to the first downstream port or acts as a hardware storage | |
2153 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2154 | * other configuration). | |
2155 | * | |
2156 | * When there's no device attached to the first downstream port of the | |
2157 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2158 | * configure the 4726. However, ATA emulation of the device is very | |
2159 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2160 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2161 | * | |
2162 | * The following function works around the problem by always using | |
2163 | * hardreset on the port and not depending on receiving signature FIS | |
2164 | * afterward. If signature FIS isn't received soon, ATA class is | |
2165 | * assumed without follow-up softreset. | |
2166 | */ | |
2167 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2168 | { | |
2169 | static struct dmi_system_id sysids[] = { | |
2170 | { | |
2171 | .ident = "P5W DH Deluxe", | |
2172 | .matches = { | |
2173 | DMI_MATCH(DMI_SYS_VENDOR, | |
2174 | "ASUSTEK COMPUTER INC"), | |
2175 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2176 | }, | |
2177 | }, | |
2178 | { } | |
2179 | }; | |
2180 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2181 | ||
2182 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2183 | dmi_check_system(sysids)) { | |
2184 | struct ata_port *ap = host->ports[1]; | |
2185 | ||
2186 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2187 | "Deluxe on-board SIMG4726 workaround\n"); | |
2188 | ||
2189 | ap->ops = &ahci_p5wdh_ops; | |
2190 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2191 | } | |
2192 | } | |
2193 | ||
24dc5f33 | 2194 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2195 | { |
2196 | static int printed_version; | |
4447d351 TH |
2197 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
2198 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 2199 | struct device *dev = &pdev->dev; |
1da177e4 | 2200 | struct ahci_host_priv *hpriv; |
4447d351 TH |
2201 | struct ata_host *host; |
2202 | int i, rc; | |
1da177e4 LT |
2203 | |
2204 | VPRINTK("ENTER\n"); | |
2205 | ||
12fad3f9 TH |
2206 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2207 | ||
1da177e4 | 2208 | if (!printed_version++) |
a9524a76 | 2209 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2210 | |
4447d351 | 2211 | /* acquire resources */ |
24dc5f33 | 2212 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2213 | if (rc) |
2214 | return rc; | |
2215 | ||
0d5ff566 TH |
2216 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
2217 | if (rc == -EBUSY) | |
24dc5f33 | 2218 | pcim_pin_device(pdev); |
0d5ff566 | 2219 | if (rc) |
24dc5f33 | 2220 | return rc; |
1da177e4 | 2221 | |
c4f7792c TH |
2222 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2223 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2224 | u8 map; | |
2225 | ||
2226 | /* ICH6s share the same PCI ID for both piix and ahci | |
2227 | * modes. Enabling ahci mode while MAP indicates | |
2228 | * combined mode is a bad idea. Yield to ata_piix. | |
2229 | */ | |
2230 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2231 | if (map & 0x3) { | |
2232 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2233 | "combined mode, can't enable AHCI mode\n"); | |
2234 | return -ENODEV; | |
2235 | } | |
2236 | } | |
2237 | ||
24dc5f33 TH |
2238 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2239 | if (!hpriv) | |
2240 | return -ENOMEM; | |
417a1a6d TH |
2241 | hpriv->flags |= (unsigned long)pi.private_data; |
2242 | ||
2243 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) | |
2244 | pci_intx(pdev, 1); | |
1da177e4 | 2245 | |
4447d351 | 2246 | /* save initial config */ |
417a1a6d | 2247 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2248 | |
4447d351 | 2249 | /* prepare host */ |
274c1fde | 2250 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2251 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2252 | |
7d50b60b TH |
2253 | if (hpriv->cap & HOST_CAP_PMP) |
2254 | pi.flags |= ATA_FLAG_PMP; | |
2255 | ||
4447d351 TH |
2256 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
2257 | if (!host) | |
2258 | return -ENOMEM; | |
2259 | host->iomap = pcim_iomap_table(pdev); | |
2260 | host->private_data = hpriv; | |
2261 | ||
2262 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
2263 | struct ata_port *ap = host->ports[i]; |
2264 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 2265 | |
cbcdd875 TH |
2266 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2267 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2268 | 0x100 + ap->port_no * 0x80, "port"); | |
2269 | ||
31556594 KCA |
2270 | /* set initial link pm policy */ |
2271 | ap->pm_policy = NOT_AVAILABLE; | |
2272 | ||
dab632e8 | 2273 | /* standard SATA port setup */ |
203ef6c4 | 2274 | if (hpriv->port_map & (1 << i)) |
4447d351 | 2275 | ap->ioaddr.cmd_addr = port_mmio; |
dab632e8 JG |
2276 | |
2277 | /* disabled/not-implemented port */ | |
2278 | else | |
2279 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 2280 | } |
d447df14 | 2281 | |
edc93052 TH |
2282 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2283 | ahci_p5wdh_workaround(host); | |
2284 | ||
4447d351 TH |
2285 | /* initialize adapter */ |
2286 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2287 | if (rc) |
24dc5f33 | 2288 | return rc; |
1da177e4 | 2289 | |
4447d351 TH |
2290 | rc = ahci_reset_controller(host); |
2291 | if (rc) | |
2292 | return rc; | |
1da177e4 | 2293 | |
4447d351 TH |
2294 | ahci_init_controller(host); |
2295 | ahci_print_info(host); | |
1da177e4 | 2296 | |
4447d351 TH |
2297 | pci_set_master(pdev); |
2298 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2299 | &ahci_sht); | |
907f4678 | 2300 | } |
1da177e4 LT |
2301 | |
2302 | static int __init ahci_init(void) | |
2303 | { | |
b7887196 | 2304 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2305 | } |
2306 | ||
1da177e4 LT |
2307 | static void __exit ahci_exit(void) |
2308 | { | |
2309 | pci_unregister_driver(&ahci_pci_driver); | |
2310 | } | |
2311 | ||
2312 | ||
2313 | MODULE_AUTHOR("Jeff Garzik"); | |
2314 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2315 | MODULE_LICENSE("GPL"); | |
2316 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2317 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2318 | |
2319 | module_init(ahci_init); | |
2320 | module_exit(ahci_exit); |