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Merge branch 'for-linus' of git://git.samba.org/sfrench/cifs-2.6
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
98ac62de 106static const struct ata_port_info ahci_port_info[] = {
441577ef 107 /* by features */
facb8fa6 108 [board_ahci] = {
1188c0d8 109 .flags = AHCI_FLAG_COMMON,
14bdef98 110 .pio_mask = ATA_PIO4,
469248ab 111 .udma_mask = ATA_UDMA6,
1da177e4
LT		 112 .port_ops = &ahci_ops,
113 },
facb8fa6 114 [board_ahci_ign_iferr] = {
441577ef 115 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 116 .flags = AHCI_FLAG_COMMON,
14bdef98 117 .pio_mask = ATA_PIO4,
469248ab 118 .udma_mask = ATA_UDMA6,
441577ef 119 .port_ops = &ahci_ops,
bf2af2a2 120 },
facb8fa6 121 [board_ahci_nosntf] = {
441577ef 122 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 123 .flags = AHCI_FLAG_COMMON,
14bdef98 124 .pio_mask = ATA_PIO4,
469248ab 125 .udma_mask = ATA_UDMA6,
41669553
TH		 126 .port_ops = &ahci_ops,
127 },
facb8fa6 128 [board_ahci_yes_fbs] = {
5f173107
TH		 129 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
441577ef 135 /* by chipsets */
facb8fa6 136 [board_ahci_mcp65] = {
83f2b963
TH		 137 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
138 AHCI_HFLAG_YES_NCQ),
ae01b249 139 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
facb8fa6 144 [board_ahci_mcp77] = {
83f2b963
TH		 145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
facb8fa6 151 [board_ahci_mcp89] = {
83f2b963 152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 153 .flags = AHCI_FLAG_COMMON,
14bdef98 154 .pio_mask = ATA_PIO4,
469248ab 155 .udma_mask = ATA_UDMA6,
441577ef 156 .port_ops = &ahci_ops,
55a61604 157 },
facb8fa6 158 [board_ahci_mv] = {
417a1a6d 159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 160 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 162 .pio_mask = ATA_PIO4,
cd70c266
JG		 163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
facb8fa6 166 [board_ahci_sb600] = {
441577ef
TH		 167 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
168 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
169 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 170 .flags = AHCI_FLAG_COMMON,
14bdef98 171 .pio_mask = ATA_PIO4,
e39fc8c9 172 .udma_mask = ATA_UDMA6,
345347c5 173 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 174 },
facb8fa6 175 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
345347c5 180 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 181 },
facb8fa6 182 [board_ahci_vt8251] = {
441577ef 183 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
441577ef 187 .port_ops = &ahci_vt8251_ops,
1b677afd 188 },
1da177e4
LT		 189};
190
3b7d697d 191static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 192 /* Intel */
54bb3a94
JG		 193 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
194 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
195 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
196 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
197 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 198 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 199 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
200 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 203 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 204 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 205 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
207 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
209 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 220 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
221 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 222 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 223 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 224 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 225 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
226 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 227 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 228 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 229 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 230 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 231 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 232 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 233 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
236 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 239 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
240 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
241 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 242 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 243 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 244 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
247 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 250 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 251 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
252 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 259 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
260 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
262 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
fe7fa31a 267
e34bb370
TH		 268 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
269 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
270 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 271
272 /* ATI */
c65ec1c2 273 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 274 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
277 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 280
e2dd90b1 281 /* AMD */
5deab536 282 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 283 /* AMD is using RAID class only for ahci controllers */
284 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
285 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
286
fe7fa31a 287 /* VIA */
54bb3a94 288 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 289 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 290
291 /* NVIDIA */
e297d99e
TH		 292 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 300 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 376
95916edd 377 /* SiS */
20e2de4a
TH		 378 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
379 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
380 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 381
318893e1
AR		 382 /* ST Microelectronics */
383 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
384
cd70c266
JG		 385 /* Marvell */
386 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 387 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 388 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 389 .class = PCI_CLASS_STORAGE_SATA_AHCI,
390 .class_mask = 0xffffff,
5f173107 391 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 392 { PCI_DEVICE(0x1b4b, 0x9125),
393 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 394 { PCI_DEVICE(0x1b4b, 0x917a),
395 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
50be5e36
TH		 396 { PCI_DEVICE(0x1b4b, 0x91a3),
397 .driver_data = board_ahci_yes_fbs },
cd70c266 398
c77a036b
MN		 399 /* Promise */
400 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
401
c9703765
KYL		 402 /* Asmedia */
403 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
404
415ae2b5
JG		 405 /* Generic, PCI class code for AHCI */
406 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 407 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 408
1da177e4
LT		 409 { } /* terminate list */
410};
411
412
413static struct pci_driver ahci_pci_driver = {
414 .name = DRV_NAME,
415 .id_table = ahci_pci_tbl,
416 .probe = ahci_init_one,
24dc5f33 417 .remove = ata_pci_remove_one,
438ac6d5 418#ifdef CONFIG_PM
c1332875 419 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 420 .resume = ahci_pci_device_resume,
421#endif
422};
1da177e4 423
365cfa1e
AV		 424#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
425static int marvell_enable;
426#else
427static int marvell_enable = 1;
428#endif
429module_param(marvell_enable, int, 0644);
430MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 431
1da177e4 432
365cfa1e
AV		 433static void ahci_pci_save_initial_config(struct pci_dev *pdev,
434 struct ahci_host_priv *hpriv)
435{
436 unsigned int force_port_map = 0;
437 unsigned int mask_port_map = 0;
67846b30 438
365cfa1e
AV		 439 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
440 dev_info(&pdev->dev, "JMB361 has only one port\n");
441 force_port_map = 1;
1da177e4
LT		 442 }
443
365cfa1e
AV		 444 /*
445 * Temporary Marvell 6145 hack: PATA port presence
446 * is asserted through the standard AHCI port
447 * presence register, as bit 4 (counting from 0)
d28f87aa 448 */
365cfa1e
AV		 449 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
450 if (pdev->device == 0x6121)
451 mask_port_map = 0x3;
452 else
453 mask_port_map = 0xf;
454 dev_info(&pdev->dev,
455 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
456 }
1da177e4 457
365cfa1e
AV		 458 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
459 mask_port_map);
1da177e4
LT		 460}
461
365cfa1e 462static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 463{
365cfa1e 464 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 465
365cfa1e 466 ahci_reset_controller(host);
1da177e4 467
365cfa1e
AV		 468 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
469 struct ahci_host_priv *hpriv = host->private_data;
470 u16 tmp16;
d6ef3153 471
365cfa1e
AV		 472 /* configure PCS */
473 pci_read_config_word(pdev, 0x92, &tmp16);
474 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
475 tmp16 |= hpriv->port_map;
476 pci_write_config_word(pdev, 0x92, tmp16);
477 }
d6ef3153
SH		 478 }
479
1da177e4
LT		 480 return 0;
481}
482
365cfa1e 483static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 484{
365cfa1e
AV		 485 struct ahci_host_priv *hpriv = host->private_data;
486 struct pci_dev *pdev = to_pci_dev(host->dev);
487 void __iomem *port_mmio;
78cd52d0 488 u32 tmp;
365cfa1e 489 int mv;
78cd52d0 490
365cfa1e
AV		 491 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
492 if (pdev->device == 0x6121)
493 mv = 2;
494 else
495 mv = 4;
496 port_mmio = __ahci_port_base(host, mv);
78cd52d0 497
365cfa1e 498 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 499
365cfa1e
AV		 500 /* clear port IRQ */
501 tmp = readl(port_mmio + PORT_IRQ_STAT);
502 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
503 if (tmp)
504 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 505 }
506
365cfa1e 507 ahci_init_controller(host);
edc93052
TH		 508}
509
365cfa1e
AV		 510static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
511 unsigned long deadline)
d6ef3153 512{
365cfa1e
AV		 513 struct ata_port *ap = link->ap;
514 bool online;
d6ef3153
SH		 515 int rc;
516
365cfa1e 517 DPRINTK("ENTER\n");
d6ef3153 518
365cfa1e 519 ahci_stop_engine(ap);
d6ef3153 520
365cfa1e
AV		 521 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
522 deadline, &online, NULL);
d6ef3153
SH		 523
524 ahci_start_engine(ap);
d6ef3153 525
365cfa1e 526 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 527
365cfa1e
AV		 528 /* vt8251 doesn't clear BSY on signature FIS reception,
529 * request follow-up softreset.
530 */
531 return online ? -EAGAIN : rc;
7d50b60b
TH		 532}
533
365cfa1e
AV		 534static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
535 unsigned long deadline)
7d50b60b 536{
365cfa1e 537 struct ata_port *ap = link->ap;
1c954a4d 538 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 539 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
540 struct ata_taskfile tf;
541 bool online;
542 int rc;
7d50b60b 543
365cfa1e 544 ahci_stop_engine(ap);
028a2596 545
365cfa1e
AV		 546 /* clear D2H reception area to properly wait for D2H FIS */
547 ata_tf_init(link->device, &tf);
548 tf.command = 0x80;
549 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 550
365cfa1e
AV		 551 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
552 deadline, &online, NULL);
028a2596 553
365cfa1e 554 ahci_start_engine(ap);
c1332875 555
365cfa1e
AV		 556 /* The pseudo configuration device on SIMG4726 attached to
557 * ASUS P5W-DH Deluxe doesn't send signature FIS after
558 * hardreset if no device is attached to the first downstream
559 * port && the pseudo device locks up on SRST w/ PMP==0. To
560 * work around this, wait for !BSY only briefly. If BSY isn't
561 * cleared, perform CLO and proceed to IDENTIFY (achieved by
562 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
563 *
564 * Wait for two seconds. Devices attached to downstream port
565 * which can't process the following IDENTIFY after this will
566 * have to be reset again. For most cases, this should
567 * suffice while making probing snappish enough.
568 */
569 if (online) {
570 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
571 ahci_check_ready);
572 if (rc)
573 ahci_kick_engine(ap);
c1332875 574 }
c1332875
TH		 575 return rc;
576}
577
365cfa1e 578#ifdef CONFIG_PM
c1332875
TH		 579static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
580{
cca3974e 581 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 582 struct ahci_host_priv *hpriv = host->private_data;
d8993349 583 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 584 u32 ctl;
585
9b10ae86
TH		 586 if (mesg.event & PM_EVENT_SUSPEND &&
587 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 588 dev_err(&pdev->dev,
589 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 590 return -EIO;
591 }
592
3a2d5b70 593 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 594 /* AHCI spec rev1.1 section 8.3.3:
595 * Software must disable interrupts prior to requesting a
596 * transition of the HBA to D3 state.
597 */
598 ctl = readl(mmio + HOST_CTL);
599 ctl &= ~HOST_IRQ_EN;
600 writel(ctl, mmio + HOST_CTL);
601 readl(mmio + HOST_CTL); /* flush */
602 }
603
604 return ata_pci_device_suspend(pdev, mesg);
605}
606
607static int ahci_pci_device_resume(struct pci_dev *pdev)
608{
cca3974e 609 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 610 int rc;
611
553c4aa6
TH		 612 rc = ata_pci_device_do_resume(pdev);
613 if (rc)
614 return rc;
c1332875
TH		 615
616 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 617 rc = ahci_pci_reset_controller(host);
c1332875
TH		 618 if (rc)
619 return rc;
620
781d6550 621 ahci_pci_init_controller(host);
c1332875
TH		 622 }
623
cca3974e 624 ata_host_resume(host);
c1332875
TH		 625
626 return 0;
627}
438ac6d5 628#endif
c1332875 629
4447d351 630static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 631{
1da177e4 632 int rc;
1da177e4 633
318893e1
AR		 634 /*
635 * If the device fixup already set the dma_mask to some non-standard
636 * value, don't extend it here. This happens on STA2X11, for example.
637 */
638 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
639 return 0;
640
1da177e4 641 if (using_dac &&
6a35528a
YH		 642 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
643 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 644 if (rc) {
284901a9 645 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 646 if (rc) {
a44fec1f
JP		 647 dev_err(&pdev->dev,
648 "64-bit DMA enable failed\n");
1da177e4
LT		 649 return rc;
650 }
651 }
1da177e4 652 } else {
284901a9 653 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 654 if (rc) {
a44fec1f 655 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 656 return rc;
657 }
284901a9 658 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 659 if (rc) {
a44fec1f
JP		 660 dev_err(&pdev->dev,
661 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 662 return rc;
663 }
664 }
1da177e4
LT		 665 return 0;
666}
667
439fcaec
AV		 668static void ahci_pci_print_info(struct ata_host *host)
669{
670 struct pci_dev *pdev = to_pci_dev(host->dev);
671 u16 cc;
672 const char *scc_s;
673
674 pci_read_config_word(pdev, 0x0a, &cc);
675 if (cc == PCI_CLASS_STORAGE_IDE)
676 scc_s = "IDE";
677 else if (cc == PCI_CLASS_STORAGE_SATA)
678 scc_s = "SATA";
679 else if (cc == PCI_CLASS_STORAGE_RAID)
680 scc_s = "RAID";
681 else
682 scc_s = "unknown";
683
684 ahci_print_info(host, scc_s);
685}
686
edc93052
TH		 687/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
688 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
689 * support PMP and the 4726 either directly exports the device
690 * attached to the first downstream port or acts as a hardware storage
691 * controller and emulate a single ATA device (can be RAID 0/1 or some
692 * other configuration).
693 *
694 * When there's no device attached to the first downstream port of the
695 * 4726, "Config Disk" appears, which is a pseudo ATA device to
696 * configure the 4726. However, ATA emulation of the device is very
697 * lame. It doesn't send signature D2H Reg FIS after the initial
698 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
699 *
700 * The following function works around the problem by always using
701 * hardreset on the port and not depending on receiving signature FIS
702 * afterward. If signature FIS isn't received soon, ATA class is
703 * assumed without follow-up softreset.
704 */
705static void ahci_p5wdh_workaround(struct ata_host *host)
706{
707 static struct dmi_system_id sysids[] = {
708 {
709 .ident = "P5W DH Deluxe",
710 .matches = {
711 DMI_MATCH(DMI_SYS_VENDOR,
712 "ASUSTEK COMPUTER INC"),
713 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
714 },
715 },
716 { }
717 };
718 struct pci_dev *pdev = to_pci_dev(host->dev);
719
720 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
721 dmi_check_system(sysids)) {
722 struct ata_port *ap = host->ports[1];
723
a44fec1f
JP		 724 dev_info(&pdev->dev,
725 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 726
727 ap->ops = &ahci_p5wdh_ops;
728 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
729 }
730}
731
2fcad9d2
TH		 732/* only some SB600 ahci controllers can do 64bit DMA */
733static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 734{
735 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 736 /*
737 * The oldest version known to be broken is 0901 and
738 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 739 * Enable 64bit DMA on 1501 and anything newer.
740 *
03d783bf
TH		 741 * Please read bko#9412 for more info.
742 */
58a09b38
SH		 743 {
744 .ident = "ASUS M2A-VM",
745 .matches = {
746 DMI_MATCH(DMI_BOARD_VENDOR,
747 "ASUSTeK Computer INC."),
748 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
749 },
03d783bf 750 .driver_data = "20071026", /* yyyymmdd */
58a09b38 751 },
e65cc194
MN		 752 /*
753 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
754 * support 64bit DMA.
755 *
756 * BIOS versions earlier than 1.5 had the Manufacturer DMI
757 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
758 * This spelling mistake was fixed in BIOS version 1.5, so
759 * 1.5 and later have the Manufacturer as
760 * "MICRO-STAR INTERNATIONAL CO.,LTD".
761 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
762 *
763 * BIOS versions earlier than 1.9 had a Board Product Name
764 * DMI field of "MS-7376". This was changed to be
765 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
766 * match on DMI_BOARD_NAME of "MS-7376".
767 */
768 {
769 .ident = "MSI K9A2 Platinum",
770 .matches = {
771 DMI_MATCH(DMI_BOARD_VENDOR,
772 "MICRO-STAR INTER"),
773 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
774 },
775 },
ff0173c1
MN		 776 /*
777 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
778 * 64bit DMA.
779 *
780 * This board also had the typo mentioned above in the
781 * Manufacturer DMI field (fixed in BIOS version 1.5), so
782 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
783 */
784 {
785 .ident = "MSI K9AGM2",
786 .matches = {
787 DMI_MATCH(DMI_BOARD_VENDOR,
788 "MICRO-STAR INTER"),
789 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
790 },
791 },
3c4aa91f
MN		 792 /*
793 * All BIOS versions for the Asus M3A support 64bit DMA.
794 * (all release versions from 0301 to 1206 were tested)
795 */
796 {
797 .ident = "ASUS M3A",
798 .matches = {
799 DMI_MATCH(DMI_BOARD_VENDOR,
800 "ASUSTeK Computer INC."),
801 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
802 },
803 },
58a09b38
SH		 804 { }
805 };
03d783bf 806 const struct dmi_system_id *match;
2fcad9d2
TH		 807 int year, month, date;
808 char buf[9];
58a09b38 809
03d783bf 810 match = dmi_first_match(sysids);
58a09b38 811 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 812 !match)
58a09b38
SH		 813 return false;
814
e65cc194
MN		 815 if (!match->driver_data)
816 goto enable_64bit;
817
2fcad9d2
TH		 818 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
819 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 820
e65cc194
MN		 821 if (strcmp(buf, match->driver_data) >= 0)
822 goto enable_64bit;
823 else {
a44fec1f
JP		 824 dev_warn(&pdev->dev,
825 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
826 match->ident);
2fcad9d2
TH		 827 return false;
828 }
e65cc194
MN		 829
830enable_64bit:
a44fec1f 831 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 832 return true;
58a09b38
SH		 833}
834
1fd68434
RW		 835static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
836{
837 static const struct dmi_system_id broken_systems[] = {
838 {
839 .ident = "HP Compaq nx6310",
840 .matches = {
841 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
842 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
843 },
844 /* PCI slot number of the controller */
845 .driver_data = (void *)0x1FUL,
846 },
d2f9c061
MR		 847 {
848 .ident = "HP Compaq 6720s",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
851 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
852 },
853 /* PCI slot number of the controller */
854 .driver_data = (void *)0x1FUL,
855 },
1fd68434
RW		 856
857 { } /* terminate list */
858 };
859 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
860
861 if (dmi) {
862 unsigned long slot = (unsigned long)dmi->driver_data;
863 /* apply the quirk only to on-board controllers */
864 return slot == PCI_SLOT(pdev->devfn);
865 }
866
867 return false;
868}
869
9b10ae86
TH		 870static bool ahci_broken_suspend(struct pci_dev *pdev)
871{
872 static const struct dmi_system_id sysids[] = {
873 /*
874 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
875 * to the harddisk doesn't become online after
876 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 877 *
878 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
879 *
880 * Use dates instead of versions to match as HP is
881 * apparently recycling both product and version
882 * strings.
883 *
884 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 885 */
886 {
887 .ident = "dv4",
888 .matches = {
889 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
890 DMI_MATCH(DMI_PRODUCT_NAME,
891 "HP Pavilion dv4 Notebook PC"),
892 },
9deb3431 893 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 894 },
895 {
896 .ident = "dv5",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
899 DMI_MATCH(DMI_PRODUCT_NAME,
900 "HP Pavilion dv5 Notebook PC"),
901 },
9deb3431 902 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 903 },
904 {
905 .ident = "dv6",
906 .matches = {
907 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
908 DMI_MATCH(DMI_PRODUCT_NAME,
909 "HP Pavilion dv6 Notebook PC"),
910 },
9deb3431 911 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 912 },
913 {
914 .ident = "HDX18",
915 .matches = {
916 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
917 DMI_MATCH(DMI_PRODUCT_NAME,
918 "HP HDX18 Notebook PC"),
919 },
9deb3431 920 .driver_data = "20090430", /* F.23 */
9b10ae86 921 },
cedc9bf9
TH		 922 /*
923 * Acer eMachines G725 has the same problem. BIOS
924 * V1.03 is known to be broken. V3.04 is known to
25985edc 925 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 926 * that we don't have much idea about. For now,
927 * blacklist anything older than V3.04.
9deb3431
TH		 928 *
929 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 930 */
931 {
932 .ident = "G725",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
935 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
936 },
9deb3431 937 .driver_data = "20091216", /* V3.04 */
cedc9bf9 938 },
9b10ae86
TH		 939 { } /* terminate list */
940 };
941 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 942 int year, month, date;
943 char buf[9];
9b10ae86
TH		 944
945 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
946 return false;
947
9deb3431
TH		 948 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
949 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 950
9deb3431 951 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 952}
953
5594639a
TH		 954static bool ahci_broken_online(struct pci_dev *pdev)
955{
956#define ENCODE_BUSDEVFN(bus, slot, func) \
957 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
958 static const struct dmi_system_id sysids[] = {
959 /*
960 * There are several gigabyte boards which use
961 * SIMG5723s configured as hardware RAID. Certain
962 * 5723 firmware revisions shipped there keep the link
963 * online but fail to answer properly to SRST or
964 * IDENTIFY when no device is attached downstream
965 * causing libata to retry quite a few times leading
966 * to excessive detection delay.
967 *
968 * As these firmwares respond to the second reset try
969 * with invalid device signature, considering unknown
970 * sig as offline works around the problem acceptably.
971 */
972 {
973 .ident = "EP45-DQ6",
974 .matches = {
975 DMI_MATCH(DMI_BOARD_VENDOR,
976 "Gigabyte Technology Co., Ltd."),
977 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
978 },
979 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
980 },
981 {
982 .ident = "EP45-DS5",
983 .matches = {
984 DMI_MATCH(DMI_BOARD_VENDOR,
985 "Gigabyte Technology Co., Ltd."),
986 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
987 },
988 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
989 },
990 { } /* terminate list */
991 };
992#undef ENCODE_BUSDEVFN
993 const struct dmi_system_id *dmi = dmi_first_match(sysids);
994 unsigned int val;
995
996 if (!dmi)
997 return false;
998
999 val = (unsigned long)dmi->driver_data;
1000
1001 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1002}
1003
8e513217 1004#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1005static void ahci_gtf_filter_workaround(struct ata_host *host)
1006{
1007 static const struct dmi_system_id sysids[] = {
1008 /*
1009 * Aspire 3810T issues a bunch of SATA enable commands
1010 * via _GTF including an invalid one and one which is
1011 * rejected by the device. Among the successful ones
1012 * is FPDMA non-zero offset enable which when enabled
1013 * only on the drive side leads to NCQ command
1014 * failures. Filter it out.
1015 */
1016 {
1017 .ident = "Aspire 3810T",
1018 .matches = {
1019 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1020 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1021 },
1022 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1023 },
1024 { }
1025 };
1026 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1027 unsigned int filter;
1028 int i;
1029
1030 if (!dmi)
1031 return;
1032
1033 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1034 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1035 filter, dmi->ident);
f80ae7e4
TH		 1036
1037 for (i = 0; i < host->n_ports; i++) {
1038 struct ata_port *ap = host->ports[i];
1039 struct ata_link *link;
1040 struct ata_device *dev;
1041
1042 ata_for_each_link(link, ap, EDGE)
1043 ata_for_each_dev(dev, link, ALL)
1044 dev->gtf_filter |= filter;
1045 }
1046}
8e513217
MT		 1047#else
1048static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1049{}
1050#endif
f80ae7e4 1051
24dc5f33 1052static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1053{
e297d99e
TH		 1054 unsigned int board_id = ent->driver_data;
1055 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1056 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1057 struct device *dev = &pdev->dev;
1da177e4 1058 struct ahci_host_priv *hpriv;
4447d351 1059 struct ata_host *host;
837f5f8f 1060 int n_ports, i, rc;
318893e1 1061 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1062
1063 VPRINTK("ENTER\n");
1064
b429dd59 1065 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1066
06296a1e 1067 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1068
5b66c829
AC		 1069 /* The AHCI driver can only drive the SATA ports, the PATA driver
1070 can drive them all so if both drivers are selected make sure
1071 AHCI stays out of the way */
1072 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1073 return -ENODEV;
1074
c6353b45
TH		 1075 /*
1076 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1077 * ahci, use ata_generic instead.
1078 */
1079 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1080 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1081 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1082 pdev->subsystem_device == 0xcb89)
1083 return -ENODEV;
1084
7a02267e
MN		 1085 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1086 * At the moment, we can only use the AHCI mode. Let the users know
1087 * that for SAS drives they're out of luck.
1088 */
1089 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1090 dev_info(&pdev->dev,
1091 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1092
318893e1
AR		 1093 /* The Connext uses non-standard BAR */
1094 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1095 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1096
4447d351 1097 /* acquire resources */
24dc5f33 1098 rc = pcim_enable_device(pdev);
1da177e4
LT		 1099 if (rc)
1100 return rc;
1101
dea55137
TH		 1102 /* AHCI controllers often implement SFF compatible interface.
1103 * Grab all PCI BARs just in case.
1104 */
318893e1 1105 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1106 if (rc == -EBUSY)
24dc5f33 1107 pcim_pin_device(pdev);
0d5ff566 1108 if (rc)
24dc5f33 1109 return rc;
1da177e4 1110
c4f7792c
TH		 1111 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1112 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1113 u8 map;
1114
1115 /* ICH6s share the same PCI ID for both piix and ahci
1116 * modes. Enabling ahci mode while MAP indicates
1117 * combined mode is a bad idea. Yield to ata_piix.
1118 */
1119 pci_read_config_byte(pdev, ICH_MAP, &map);
1120 if (map & 0x3) {
a44fec1f
JP		 1121 dev_info(&pdev->dev,
1122 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1123 return -ENODEV;
1124 }
1125 }
1126
24dc5f33
TH		 1127 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1128 if (!hpriv)
1129 return -ENOMEM;
417a1a6d
TH		 1130 hpriv->flags |= (unsigned long)pi.private_data;
1131
e297d99e
TH		 1132 /* MCP65 revision A1 and A2 can't do MSI */
1133 if (board_id == board_ahci_mcp65 &&
1134 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1135 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1136
e427fe04
SH		 1137 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1138 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1139 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1140
2fcad9d2
TH		 1141 /* only some SB600s can do 64bit DMA */
1142 if (ahci_sb600_enable_64bit(pdev))
1143 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1144
31b239ad
TH		 1145 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1146 pci_intx(pdev, 1);
1da177e4 1147
318893e1 1148 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1149
4447d351 1150 /* save initial config */
394d6e53 1151 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1152
4447d351 1153 /* prepare host */
453d3131
RH		 1154 if (hpriv->cap & HOST_CAP_NCQ) {
1155 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1156 /*
1157 * Auto-activate optimization is supposed to be
1158 * supported on all AHCI controllers indicating NCQ
1159 * capability, but it seems to be broken on some
1160 * chipsets including NVIDIAs.
1161 */
1162 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1163 pi.flags |= ATA_FLAG_FPDMA_AA;
1164 }
1da177e4 1165
7d50b60b
TH		 1166 if (hpriv->cap & HOST_CAP_PMP)
1167 pi.flags |= ATA_FLAG_PMP;
1168
0cbb0e77 1169 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1170
1fd68434
RW		 1171 if (ahci_broken_system_poweroff(pdev)) {
1172 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1173 dev_info(&pdev->dev,
1174 "quirky BIOS, skipping spindown on poweroff\n");
1175 }
1176
9b10ae86
TH		 1177 if (ahci_broken_suspend(pdev)) {
1178 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1179 dev_warn(&pdev->dev,
1180 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1181 }
1182
5594639a
TH		 1183 if (ahci_broken_online(pdev)) {
1184 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1185 dev_info(&pdev->dev,
1186 "online status unreliable, applying workaround\n");
1187 }
1188
837f5f8f
TH		 1189 /* CAP.NP sometimes indicate the index of the last enabled
1190 * port, at other times, that of the last possible port, so
1191 * determining the maximum port number requires looking at
1192 * both CAP.NP and port_map.
1193 */
1194 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1195
1196 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1197 if (!host)
1198 return -ENOMEM;
4447d351
TH		 1199 host->private_data = hpriv;
1200
f3d7f23f 1201 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1202 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1203 else
1204 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1205
18f7ba4c
KCA		 1206 if (pi.flags & ATA_FLAG_EM)
1207 ahci_reset_em(host);
1208
4447d351 1209 for (i = 0; i < host->n_ports; i++) {
dab632e8 1210 struct ata_port *ap = host->ports[i];
4447d351 1211
318893e1
AR		 1212 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1213 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1214 0x100 + ap->port_no * 0x80, "port");
1215
18f7ba4c
KCA		 1216 /* set enclosure management message type */
1217 if (ap->flags & ATA_FLAG_EM)
008dbd61 1218 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1219
1220
dab632e8 1221 /* disabled/not-implemented port */
350756f6 1222 if (!(hpriv->port_map & (1 << i)))
dab632e8 1223 ap->ops = &ata_dummy_port_ops;
4447d351 1224 }
d447df14 1225
edc93052
TH		 1226 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1227 ahci_p5wdh_workaround(host);
1228
f80ae7e4
TH		 1229 /* apply gtf filter quirk */
1230 ahci_gtf_filter_workaround(host);
1231
4447d351
TH		 1232 /* initialize adapter */
1233 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1234 if (rc)
24dc5f33 1235 return rc;
1da177e4 1236
3303040d 1237 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1238 if (rc)
1239 return rc;
1da177e4 1240
781d6550 1241 ahci_pci_init_controller(host);
439fcaec 1242 ahci_pci_print_info(host);
1da177e4 1243
4447d351
TH		 1244 pci_set_master(pdev);
1245 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1246 &ahci_sht);
907f4678 1247}
1da177e4 1248
2fc75da0 1249module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1250
1251MODULE_AUTHOR("Jeff Garzik");
1252MODULE_DESCRIPTION("AHCI SATA low-level driver");
1253MODULE_LICENSE("GPL");
1254MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1255MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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