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pata_mpc52xx: reduce code size by simple change of constant data types
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
1da177e4 63
441577ef
TH		 64 /* board IDs for specific chipsets in alphabetical order */
65 board_ahci_mcp65,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /* aliases */
72 board_ahci_mcp_linux = board_ahci_mcp65,
73 board_ahci_mcp67 = board_ahci_mcp65,
74 board_ahci_mcp73 = board_ahci_mcp65,
75 board_ahci_mcp77 = board_ahci,
76 board_ahci_mcp79 = board_ahci,
77 board_ahci_mcp89 = board_ahci,
1da177e4
LT		 78};
79
2dcb407e 80static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 81static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
82 unsigned long deadline);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
029cfd6b
TH		 92static struct ata_port_operations ahci_vt8251_ops = {
93 .inherits = &ahci_ops,
a1efdaba 94 .hardreset = ahci_vt8251_hardreset,
029cfd6b 95};
edc93052 96
029cfd6b
TH		 97static struct ata_port_operations ahci_p5wdh_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 100};
101
bd17243a
SH		 102static struct ata_port_operations ahci_sb600_ops = {
103 .inherits = &ahci_ops,
104 .softreset = ahci_sb600_softreset,
105 .pmp_softreset = ahci_sb600_softreset,
106};
107
417a1a6d
TH		 108#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109
98ac62de 110static const struct ata_port_info ahci_port_info[] = {
441577ef 111 /* by features */
4da646b7 112 [board_ahci] =
1da177e4 113 {
1188c0d8 114 .flags = AHCI_FLAG_COMMON,
14bdef98 115 .pio_mask = ATA_PIO4,
469248ab 116 .udma_mask = ATA_UDMA6,
1da177e4
LT		 117 .port_ops = &ahci_ops,
118 },
441577ef 119 [board_ahci_ign_iferr] =
bf2af2a2 120 {
441577ef 121 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 122 .flags = AHCI_FLAG_COMMON,
14bdef98 123 .pio_mask = ATA_PIO4,
469248ab 124 .udma_mask = ATA_UDMA6,
441577ef 125 .port_ops = &ahci_ops,
bf2af2a2 126 },
441577ef 127 [board_ahci_nosntf] =
41669553 128 {
441577ef 129 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 130 .flags = AHCI_FLAG_COMMON,
14bdef98 131 .pio_mask = ATA_PIO4,
469248ab 132 .udma_mask = ATA_UDMA6,
41669553
TH		 133 .port_ops = &ahci_ops,
134 },
441577ef
TH		 135 /* by chipsets */
136 [board_ahci_mcp65] =
55a61604 137 {
441577ef 138 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
417a1a6d 139 .flags = AHCI_FLAG_COMMON,
14bdef98 140 .pio_mask = ATA_PIO4,
469248ab 141 .udma_mask = ATA_UDMA6,
441577ef 142 .port_ops = &ahci_ops,
55a61604 143 },
4da646b7 144 [board_ahci_mv] =
cd70c266 145 {
417a1a6d 146 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 147 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 148 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 149 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 150 .pio_mask = ATA_PIO4,
cd70c266
JG		 151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
441577ef 154 [board_ahci_sb600] =
e39fc8c9 155 {
441577ef
TH		 156 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
157 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
158 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 159 .flags = AHCI_FLAG_COMMON,
14bdef98 160 .pio_mask = ATA_PIO4,
e39fc8c9 161 .udma_mask = ATA_UDMA6,
bd17243a 162 .port_ops = &ahci_sb600_ops,
e39fc8c9 163 },
441577ef 164 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 165 {
441577ef 166 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
441577ef 170 .port_ops = &ahci_sb600_ops,
aa431dd3 171 },
441577ef 172 [board_ahci_vt8251] =
1b677afd 173 {
441577ef 174 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
441577ef 178 .port_ops = &ahci_vt8251_ops,
1b677afd 179 },
1da177e4
LT		 180};
181
3b7d697d 182static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 183 /* Intel */
54bb3a94
JG		 184 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
185 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
186 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
187 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
188 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 189 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 190 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
191 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
192 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
193 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 194 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 195 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 196 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
197 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
198 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
199 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
200 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
201 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
202 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
203 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
204 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
205 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
206 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
207 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
208 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
209 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 211 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
212 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 213 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 214 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 215 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 216 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
217 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 218 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 219 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 220 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 221 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 222 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 223 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 224 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
225 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
226 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
227 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
228 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
229 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
fe7fa31a 230
e34bb370
TH		 231 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
232 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
233 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 234
235 /* ATI */
c65ec1c2 236 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 237 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
238 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
239 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
240 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
241 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
242 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 243
e2dd90b1 244 /* AMD */
5deab536 245 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 246 /* AMD is using RAID class only for ahci controllers */
247 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
248 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
249
fe7fa31a 250 /* VIA */
54bb3a94 251 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 252 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 253
254 /* NVIDIA */
e297d99e
TH		 255 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
256 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
257 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
258 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
259 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
260 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
261 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
262 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 263 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
264 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
265 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
266 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
267 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
268 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
269 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
270 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
271 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
272 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
273 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
274 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
275 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
276 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
277 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
278 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
279 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
280 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
281 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
282 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
283 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
284 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
285 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
286 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
287 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
288 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
289 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
290 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
291 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
292 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
293 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
294 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
295 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
296 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
297 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
298 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
299 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
300 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
301 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
302 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
303 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
304 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
305 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
306 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
307 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
308 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
309 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
310 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
311 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
312 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
313 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
314 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
315 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
316 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
317 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
318 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
319 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
320 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
321 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
322 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
323 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
324 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
325 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
326 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
327 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
328 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
329 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
330 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
331 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
332 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
333 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
334 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
335 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
336 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
337 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
338 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 339
95916edd 340 /* SiS */
20e2de4a
TH		 341 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
342 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
343 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 344
cd70c266
JG		 345 /* Marvell */
346 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 347 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 348
c77a036b
MN		 349 /* Promise */
350 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
351
415ae2b5
JG		 352 /* Generic, PCI class code for AHCI */
353 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 354 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 355
1da177e4
LT		 356 { } /* terminate list */
357};
358
359
360static struct pci_driver ahci_pci_driver = {
361 .name = DRV_NAME,
362 .id_table = ahci_pci_tbl,
363 .probe = ahci_init_one,
24dc5f33 364 .remove = ata_pci_remove_one,
438ac6d5 365#ifdef CONFIG_PM
c1332875 366 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 367 .resume = ahci_pci_device_resume,
368#endif
369};
1da177e4 370
365cfa1e
AV		 371#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
372static int marvell_enable;
373#else
374static int marvell_enable = 1;
375#endif
376module_param(marvell_enable, int, 0644);
377MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 378
1da177e4 379
365cfa1e
AV		 380static void ahci_pci_save_initial_config(struct pci_dev *pdev,
381 struct ahci_host_priv *hpriv)
382{
383 unsigned int force_port_map = 0;
384 unsigned int mask_port_map = 0;
67846b30 385
365cfa1e
AV		 386 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
387 dev_info(&pdev->dev, "JMB361 has only one port\n");
388 force_port_map = 1;
1da177e4
LT		 389 }
390
365cfa1e
AV		 391 /*
392 * Temporary Marvell 6145 hack: PATA port presence
393 * is asserted through the standard AHCI port
394 * presence register, as bit 4 (counting from 0)
d28f87aa 395 */
365cfa1e
AV		 396 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
397 if (pdev->device == 0x6121)
398 mask_port_map = 0x3;
399 else
400 mask_port_map = 0xf;
401 dev_info(&pdev->dev,
402 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
403 }
1da177e4 404
365cfa1e
AV		 405 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
406 mask_port_map);
1da177e4
LT		 407}
408
365cfa1e 409static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 410{
365cfa1e 411 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 412
365cfa1e 413 ahci_reset_controller(host);
1da177e4 414
365cfa1e
AV		 415 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
416 struct ahci_host_priv *hpriv = host->private_data;
417 u16 tmp16;
d6ef3153 418
365cfa1e
AV		 419 /* configure PCS */
420 pci_read_config_word(pdev, 0x92, &tmp16);
421 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
422 tmp16 |= hpriv->port_map;
423 pci_write_config_word(pdev, 0x92, tmp16);
424 }
d6ef3153
SH		 425 }
426
1da177e4
LT		 427 return 0;
428}
429
365cfa1e 430static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 431{
365cfa1e
AV		 432 struct ahci_host_priv *hpriv = host->private_data;
433 struct pci_dev *pdev = to_pci_dev(host->dev);
434 void __iomem *port_mmio;
78cd52d0 435 u32 tmp;
365cfa1e 436 int mv;
78cd52d0 437
365cfa1e
AV		 438 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
439 if (pdev->device == 0x6121)
440 mv = 2;
441 else
442 mv = 4;
443 port_mmio = __ahci_port_base(host, mv);
78cd52d0 444
365cfa1e 445 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 446
365cfa1e
AV		 447 /* clear port IRQ */
448 tmp = readl(port_mmio + PORT_IRQ_STAT);
449 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
450 if (tmp)
451 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 452 }
453
365cfa1e 454 ahci_init_controller(host);
edc93052
TH		 455}
456
365cfa1e 457static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 458{
365cfa1e
AV		 459 void __iomem *port_mmio = ahci_port_base(link->ap);
460 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
461 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
462
463 /*
464 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
465 * which can save timeout delay.
466 */
467 if (irq_status & PORT_IRQ_BAD_PMP)
468 return -EIO;
78cd52d0 469
365cfa1e 470 return ata_check_ready(status);
78cd52d0
TH		 471}
472
365cfa1e
AV		 473static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
474 unsigned long deadline)
d6ef3153 475{
365cfa1e 476 struct ata_port *ap = link->ap;
d6ef3153 477 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 478 int pmp = sata_srst_pmp(link);
d6ef3153 479 int rc;
365cfa1e 480 u32 irq_sts;
d6ef3153 481
365cfa1e 482 DPRINTK("ENTER\n");
d6ef3153 483
365cfa1e
AV		 484 rc = ahci_do_softreset(link, class, pmp, deadline,
485 ahci_sb600_check_ready);
d6ef3153 486
365cfa1e
AV		 487 /*
488 * Soft reset fails on some ATI chips with IPMS set when PMP
489 * is enabled but SATA HDD/ODD is connected to SATA port,
490 * do soft reset again to port 0.
491 */
492 if (rc == -EIO) {
493 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
494 if (irq_sts & PORT_IRQ_BAD_PMP) {
495 ata_link_printk(link, KERN_WARNING,
496 "applying SB600 PMP SRST workaround "
497 "and retrying\n");
498 rc = ahci_do_softreset(link, class, 0, deadline,
499 ahci_check_ready);
500 }
501 }
d6ef3153 502
365cfa1e 503 return rc;
d6ef3153
SH		 504}
505
365cfa1e
AV		 506static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
507 unsigned long deadline)
d6ef3153 508{
365cfa1e
AV		 509 struct ata_port *ap = link->ap;
510 bool online;
d6ef3153
SH		 511 int rc;
512
365cfa1e 513 DPRINTK("ENTER\n");
d6ef3153 514
365cfa1e 515 ahci_stop_engine(ap);
d6ef3153 516
365cfa1e
AV		 517 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
518 deadline, &online, NULL);
d6ef3153
SH		 519
520 ahci_start_engine(ap);
d6ef3153 521
365cfa1e 522 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 523
365cfa1e
AV		 524 /* vt8251 doesn't clear BSY on signature FIS reception,
525 * request follow-up softreset.
526 */
527 return online ? -EAGAIN : rc;
7d50b60b
TH		 528}
529
365cfa1e
AV		 530static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
531 unsigned long deadline)
7d50b60b 532{
365cfa1e 533 struct ata_port *ap = link->ap;
1c954a4d 534 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 535 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
536 struct ata_taskfile tf;
537 bool online;
538 int rc;
7d50b60b 539
365cfa1e 540 ahci_stop_engine(ap);
028a2596 541
365cfa1e
AV		 542 /* clear D2H reception area to properly wait for D2H FIS */
543 ata_tf_init(link->device, &tf);
544 tf.command = 0x80;
545 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 546
365cfa1e
AV		 547 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
548 deadline, &online, NULL);
028a2596 549
365cfa1e 550 ahci_start_engine(ap);
c1332875 551
365cfa1e
AV		 552 /* The pseudo configuration device on SIMG4726 attached to
553 * ASUS P5W-DH Deluxe doesn't send signature FIS after
554 * hardreset if no device is attached to the first downstream
555 * port && the pseudo device locks up on SRST w/ PMP==0. To
556 * work around this, wait for !BSY only briefly. If BSY isn't
557 * cleared, perform CLO and proceed to IDENTIFY (achieved by
558 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
559 *
560 * Wait for two seconds. Devices attached to downstream port
561 * which can't process the following IDENTIFY after this will
562 * have to be reset again. For most cases, this should
563 * suffice while making probing snappish enough.
564 */
565 if (online) {
566 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
567 ahci_check_ready);
568 if (rc)
569 ahci_kick_engine(ap);
c1332875 570 }
c1332875
TH		 571 return rc;
572}
573
365cfa1e 574#ifdef CONFIG_PM
c1332875
TH		 575static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
576{
cca3974e 577 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 578 struct ahci_host_priv *hpriv = host->private_data;
d8993349 579 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 580 u32 ctl;
581
9b10ae86
TH		 582 if (mesg.event & PM_EVENT_SUSPEND &&
583 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
584 dev_printk(KERN_ERR, &pdev->dev,
585 "BIOS update required for suspend/resume\n");
586 return -EIO;
587 }
588
3a2d5b70 589 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 590 /* AHCI spec rev1.1 section 8.3.3:
591 * Software must disable interrupts prior to requesting a
592 * transition of the HBA to D3 state.
593 */
594 ctl = readl(mmio + HOST_CTL);
595 ctl &= ~HOST_IRQ_EN;
596 writel(ctl, mmio + HOST_CTL);
597 readl(mmio + HOST_CTL); /* flush */
598 }
599
600 return ata_pci_device_suspend(pdev, mesg);
601}
602
603static int ahci_pci_device_resume(struct pci_dev *pdev)
604{
cca3974e 605 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 606 int rc;
607
553c4aa6
TH		 608 rc = ata_pci_device_do_resume(pdev);
609 if (rc)
610 return rc;
c1332875
TH		 611
612 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 613 rc = ahci_pci_reset_controller(host);
c1332875
TH		 614 if (rc)
615 return rc;
616
781d6550 617 ahci_pci_init_controller(host);
c1332875
TH		 618 }
619
cca3974e 620 ata_host_resume(host);
c1332875
TH		 621
622 return 0;
623}
438ac6d5 624#endif
c1332875 625
4447d351 626static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 627{
1da177e4 628 int rc;
1da177e4 629
1da177e4 630 if (using_dac &&
6a35528a
YH		 631 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
632 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 633 if (rc) {
284901a9 634 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 635 if (rc) {
a9524a76
JG		 636 dev_printk(KERN_ERR, &pdev->dev,
637 "64-bit DMA enable failed\n");
1da177e4
LT		 638 return rc;
639 }
640 }
1da177e4 641 } else {
284901a9 642 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 643 if (rc) {
a9524a76
JG		 644 dev_printk(KERN_ERR, &pdev->dev,
645 "32-bit DMA enable failed\n");
1da177e4
LT		 646 return rc;
647 }
284901a9 648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 649 if (rc) {
a9524a76
JG		 650 dev_printk(KERN_ERR, &pdev->dev,
651 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 652 return rc;
653 }
654 }
1da177e4
LT		 655 return 0;
656}
657
439fcaec
AV		 658static void ahci_pci_print_info(struct ata_host *host)
659{
660 struct pci_dev *pdev = to_pci_dev(host->dev);
661 u16 cc;
662 const char *scc_s;
663
664 pci_read_config_word(pdev, 0x0a, &cc);
665 if (cc == PCI_CLASS_STORAGE_IDE)
666 scc_s = "IDE";
667 else if (cc == PCI_CLASS_STORAGE_SATA)
668 scc_s = "SATA";
669 else if (cc == PCI_CLASS_STORAGE_RAID)
670 scc_s = "RAID";
671 else
672 scc_s = "unknown";
673
674 ahci_print_info(host, scc_s);
675}
676
edc93052
TH		 677/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
678 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
679 * support PMP and the 4726 either directly exports the device
680 * attached to the first downstream port or acts as a hardware storage
681 * controller and emulate a single ATA device (can be RAID 0/1 or some
682 * other configuration).
683 *
684 * When there's no device attached to the first downstream port of the
685 * 4726, "Config Disk" appears, which is a pseudo ATA device to
686 * configure the 4726. However, ATA emulation of the device is very
687 * lame. It doesn't send signature D2H Reg FIS after the initial
688 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
689 *
690 * The following function works around the problem by always using
691 * hardreset on the port and not depending on receiving signature FIS
692 * afterward. If signature FIS isn't received soon, ATA class is
693 * assumed without follow-up softreset.
694 */
695static void ahci_p5wdh_workaround(struct ata_host *host)
696{
697 static struct dmi_system_id sysids[] = {
698 {
699 .ident = "P5W DH Deluxe",
700 .matches = {
701 DMI_MATCH(DMI_SYS_VENDOR,
702 "ASUSTEK COMPUTER INC"),
703 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
704 },
705 },
706 { }
707 };
708 struct pci_dev *pdev = to_pci_dev(host->dev);
709
710 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
711 dmi_check_system(sysids)) {
712 struct ata_port *ap = host->ports[1];
713
714 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
715 "Deluxe on-board SIMG4726 workaround\n");
716
717 ap->ops = &ahci_p5wdh_ops;
718 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
719 }
720}
721
2fcad9d2
TH		 722/* only some SB600 ahci controllers can do 64bit DMA */
723static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 724{
725 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 726 /*
727 * The oldest version known to be broken is 0901 and
728 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 729 * Enable 64bit DMA on 1501 and anything newer.
730 *
03d783bf
TH		 731 * Please read bko#9412 for more info.
732 */
58a09b38
SH		 733 {
734 .ident = "ASUS M2A-VM",
735 .matches = {
736 DMI_MATCH(DMI_BOARD_VENDOR,
737 "ASUSTeK Computer INC."),
738 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
739 },
03d783bf 740 .driver_data = "20071026", /* yyyymmdd */
58a09b38 741 },
e65cc194
MN		 742 /*
743 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
744 * support 64bit DMA.
745 *
746 * BIOS versions earlier than 1.5 had the Manufacturer DMI
747 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
748 * This spelling mistake was fixed in BIOS version 1.5, so
749 * 1.5 and later have the Manufacturer as
750 * "MICRO-STAR INTERNATIONAL CO.,LTD".
751 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
752 *
753 * BIOS versions earlier than 1.9 had a Board Product Name
754 * DMI field of "MS-7376". This was changed to be
755 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
756 * match on DMI_BOARD_NAME of "MS-7376".
757 */
758 {
759 .ident = "MSI K9A2 Platinum",
760 .matches = {
761 DMI_MATCH(DMI_BOARD_VENDOR,
762 "MICRO-STAR INTER"),
763 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
764 },
765 },
58a09b38
SH		 766 { }
767 };
03d783bf 768 const struct dmi_system_id *match;
2fcad9d2
TH		 769 int year, month, date;
770 char buf[9];
58a09b38 771
03d783bf 772 match = dmi_first_match(sysids);
58a09b38 773 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 774 !match)
58a09b38
SH		 775 return false;
776
e65cc194
MN		 777 if (!match->driver_data)
778 goto enable_64bit;
779
2fcad9d2
TH		 780 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
781 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 782
e65cc194
MN		 783 if (strcmp(buf, match->driver_data) >= 0)
784 goto enable_64bit;
785 else {
03d783bf
TH		 786 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
787 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 788 return false;
789 }
e65cc194
MN		 790
791enable_64bit:
792 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
793 match->ident);
794 return true;
58a09b38
SH		 795}
796
1fd68434
RW		 797static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
798{
799 static const struct dmi_system_id broken_systems[] = {
800 {
801 .ident = "HP Compaq nx6310",
802 .matches = {
803 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
804 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
805 },
806 /* PCI slot number of the controller */
807 .driver_data = (void *)0x1FUL,
808 },
d2f9c061
MR		 809 {
810 .ident = "HP Compaq 6720s",
811 .matches = {
812 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
813 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
814 },
815 /* PCI slot number of the controller */
816 .driver_data = (void *)0x1FUL,
817 },
1fd68434
RW		 818
819 { } /* terminate list */
820 };
821 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
822
823 if (dmi) {
824 unsigned long slot = (unsigned long)dmi->driver_data;
825 /* apply the quirk only to on-board controllers */
826 return slot == PCI_SLOT(pdev->devfn);
827 }
828
829 return false;
830}
831
9b10ae86
TH		 832static bool ahci_broken_suspend(struct pci_dev *pdev)
833{
834 static const struct dmi_system_id sysids[] = {
835 /*
836 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
837 * to the harddisk doesn't become online after
838 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 839 *
840 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
841 *
842 * Use dates instead of versions to match as HP is
843 * apparently recycling both product and version
844 * strings.
845 *
846 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 847 */
848 {
849 .ident = "dv4",
850 .matches = {
851 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
852 DMI_MATCH(DMI_PRODUCT_NAME,
853 "HP Pavilion dv4 Notebook PC"),
854 },
9deb3431 855 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 856 },
857 {
858 .ident = "dv5",
859 .matches = {
860 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
861 DMI_MATCH(DMI_PRODUCT_NAME,
862 "HP Pavilion dv5 Notebook PC"),
863 },
9deb3431 864 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 865 },
866 {
867 .ident = "dv6",
868 .matches = {
869 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
870 DMI_MATCH(DMI_PRODUCT_NAME,
871 "HP Pavilion dv6 Notebook PC"),
872 },
9deb3431 873 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 874 },
875 {
876 .ident = "HDX18",
877 .matches = {
878 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
879 DMI_MATCH(DMI_PRODUCT_NAME,
880 "HP HDX18 Notebook PC"),
881 },
9deb3431 882 .driver_data = "20090430", /* F.23 */
9b10ae86 883 },
cedc9bf9
TH		 884 /*
885 * Acer eMachines G725 has the same problem. BIOS
886 * V1.03 is known to be broken. V3.04 is known to
887 * work. Inbetween, there are V1.06, V2.06 and V3.03
888 * that we don't have much idea about. For now,
889 * blacklist anything older than V3.04.
9deb3431
TH		 890 *
891 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 892 */
893 {
894 .ident = "G725",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
897 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
898 },
9deb3431 899 .driver_data = "20091216", /* V3.04 */
cedc9bf9 900 },
9b10ae86
TH		 901 { } /* terminate list */
902 };
903 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 904 int year, month, date;
905 char buf[9];
9b10ae86
TH		 906
907 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
908 return false;
909
9deb3431
TH		 910 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
911 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 912
9deb3431 913 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 914}
915
5594639a
TH		 916static bool ahci_broken_online(struct pci_dev *pdev)
917{
918#define ENCODE_BUSDEVFN(bus, slot, func) \
919 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
920 static const struct dmi_system_id sysids[] = {
921 /*
922 * There are several gigabyte boards which use
923 * SIMG5723s configured as hardware RAID. Certain
924 * 5723 firmware revisions shipped there keep the link
925 * online but fail to answer properly to SRST or
926 * IDENTIFY when no device is attached downstream
927 * causing libata to retry quite a few times leading
928 * to excessive detection delay.
929 *
930 * As these firmwares respond to the second reset try
931 * with invalid device signature, considering unknown
932 * sig as offline works around the problem acceptably.
933 */
934 {
935 .ident = "EP45-DQ6",
936 .matches = {
937 DMI_MATCH(DMI_BOARD_VENDOR,
938 "Gigabyte Technology Co., Ltd."),
939 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
940 },
941 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
942 },
943 {
944 .ident = "EP45-DS5",
945 .matches = {
946 DMI_MATCH(DMI_BOARD_VENDOR,
947 "Gigabyte Technology Co., Ltd."),
948 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
949 },
950 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
951 },
952 { } /* terminate list */
953 };
954#undef ENCODE_BUSDEVFN
955 const struct dmi_system_id *dmi = dmi_first_match(sysids);
956 unsigned int val;
957
958 if (!dmi)
959 return false;
960
961 val = (unsigned long)dmi->driver_data;
962
963 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
964}
965
8e513217 966#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 967static void ahci_gtf_filter_workaround(struct ata_host *host)
968{
969 static const struct dmi_system_id sysids[] = {
970 /*
971 * Aspire 3810T issues a bunch of SATA enable commands
972 * via _GTF including an invalid one and one which is
973 * rejected by the device. Among the successful ones
974 * is FPDMA non-zero offset enable which when enabled
975 * only on the drive side leads to NCQ command
976 * failures. Filter it out.
977 */
978 {
979 .ident = "Aspire 3810T",
980 .matches = {
981 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
982 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
983 },
984 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
985 },
986 { }
987 };
988 const struct dmi_system_id *dmi = dmi_first_match(sysids);
989 unsigned int filter;
990 int i;
991
992 if (!dmi)
993 return;
994
995 filter = (unsigned long)dmi->driver_data;
996 dev_printk(KERN_INFO, host->dev,
997 "applying extra ACPI _GTF filter 0x%x for %s\n",
998 filter, dmi->ident);
999
1000 for (i = 0; i < host->n_ports; i++) {
1001 struct ata_port *ap = host->ports[i];
1002 struct ata_link *link;
1003 struct ata_device *dev;
1004
1005 ata_for_each_link(link, ap, EDGE)
1006 ata_for_each_dev(dev, link, ALL)
1007 dev->gtf_filter |= filter;
1008 }
1009}
8e513217
MT		 1010#else
1011static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1012{}
1013#endif
f80ae7e4 1014
24dc5f33 1015static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1016{
1017 static int printed_version;
e297d99e
TH		 1018 unsigned int board_id = ent->driver_data;
1019 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1020 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1021 struct device *dev = &pdev->dev;
1da177e4 1022 struct ahci_host_priv *hpriv;
4447d351 1023 struct ata_host *host;
837f5f8f 1024 int n_ports, i, rc;
1da177e4
LT		 1025
1026 VPRINTK("ENTER\n");
1027
12fad3f9
TH		 1028 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1029
1da177e4 1030 if (!printed_version++)
a9524a76 1031 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1032
5b66c829
AC		 1033 /* The AHCI driver can only drive the SATA ports, the PATA driver
1034 can drive them all so if both drivers are selected make sure
1035 AHCI stays out of the way */
1036 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1037 return -ENODEV;
1038
7a02267e
MN		 1039 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1040 * At the moment, we can only use the AHCI mode. Let the users know
1041 * that for SAS drives they're out of luck.
1042 */
1043 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1044 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1045 "can only drive SATA devices with this driver\n");
1046
4447d351 1047 /* acquire resources */
24dc5f33 1048 rc = pcim_enable_device(pdev);
1da177e4
LT		 1049 if (rc)
1050 return rc;
1051
dea55137
TH		 1052 /* AHCI controllers often implement SFF compatible interface.
1053 * Grab all PCI BARs just in case.
1054 */
1055 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1056 if (rc == -EBUSY)
24dc5f33 1057 pcim_pin_device(pdev);
0d5ff566 1058 if (rc)
24dc5f33 1059 return rc;
1da177e4 1060
c4f7792c
TH		 1061 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1062 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1063 u8 map;
1064
1065 /* ICH6s share the same PCI ID for both piix and ahci
1066 * modes. Enabling ahci mode while MAP indicates
1067 * combined mode is a bad idea. Yield to ata_piix.
1068 */
1069 pci_read_config_byte(pdev, ICH_MAP, &map);
1070 if (map & 0x3) {
1071 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1072 "combined mode, can't enable AHCI mode\n");
1073 return -ENODEV;
1074 }
1075 }
1076
24dc5f33
TH		 1077 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1078 if (!hpriv)
1079 return -ENOMEM;
417a1a6d
TH		 1080 hpriv->flags |= (unsigned long)pi.private_data;
1081
e297d99e
TH		 1082 /* MCP65 revision A1 and A2 can't do MSI */
1083 if (board_id == board_ahci_mcp65 &&
1084 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1085 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1086
e427fe04
SH		 1087 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1088 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1089 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1090
2fcad9d2
TH		 1091 /* only some SB600s can do 64bit DMA */
1092 if (ahci_sb600_enable_64bit(pdev))
1093 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1094
31b239ad
TH		 1095 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1096 pci_intx(pdev, 1);
1da177e4 1097
d8993349
AV		 1098 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1099
4447d351 1100 /* save initial config */
394d6e53 1101 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1102
4447d351 1103 /* prepare host */
453d3131
RH		 1104 if (hpriv->cap & HOST_CAP_NCQ) {
1105 pi.flags |= ATA_FLAG_NCQ;
1106 /* Auto-activate optimization is supposed to be supported on
1107 all AHCI controllers indicating NCQ support, but it seems
1108 to be broken at least on some NVIDIA MCP79 chipsets.
1109 Until we get info on which NVIDIA chipsets don't have this
1110 issue, if any, disable AA on all NVIDIA AHCIs. */
1111 if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
1112 pi.flags |= ATA_FLAG_FPDMA_AA;
1113 }
1da177e4 1114
7d50b60b
TH		 1115 if (hpriv->cap & HOST_CAP_PMP)
1116 pi.flags |= ATA_FLAG_PMP;
1117
0cbb0e77 1118 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1119
1fd68434
RW		 1120 if (ahci_broken_system_poweroff(pdev)) {
1121 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1122 dev_info(&pdev->dev,
1123 "quirky BIOS, skipping spindown on poweroff\n");
1124 }
1125
9b10ae86
TH		 1126 if (ahci_broken_suspend(pdev)) {
1127 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1128 dev_printk(KERN_WARNING, &pdev->dev,
1129 "BIOS update required for suspend/resume\n");
1130 }
1131
5594639a
TH		 1132 if (ahci_broken_online(pdev)) {
1133 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1134 dev_info(&pdev->dev,
1135 "online status unreliable, applying workaround\n");
1136 }
1137
837f5f8f
TH		 1138 /* CAP.NP sometimes indicate the index of the last enabled
1139 * port, at other times, that of the last possible port, so
1140 * determining the maximum port number requires looking at
1141 * both CAP.NP and port_map.
1142 */
1143 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1144
1145 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1146 if (!host)
1147 return -ENOMEM;
4447d351
TH		 1148 host->private_data = hpriv;
1149
f3d7f23f 1150 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1151 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1152 else
1153 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1154
18f7ba4c
KCA		 1155 if (pi.flags & ATA_FLAG_EM)
1156 ahci_reset_em(host);
1157
4447d351 1158 for (i = 0; i < host->n_ports; i++) {
dab632e8 1159 struct ata_port *ap = host->ports[i];
4447d351 1160
cbcdd875
TH		 1161 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1162 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1163 0x100 + ap->port_no * 0x80, "port");
1164
31556594
KCA		 1165 /* set initial link pm policy */
1166 ap->pm_policy = NOT_AVAILABLE;
1167
18f7ba4c
KCA		 1168 /* set enclosure management message type */
1169 if (ap->flags & ATA_FLAG_EM)
1170 ap->em_message_type = ahci_em_messages;
1171
1172
dab632e8 1173 /* disabled/not-implemented port */
350756f6 1174 if (!(hpriv->port_map & (1 << i)))
dab632e8 1175 ap->ops = &ata_dummy_port_ops;
4447d351 1176 }
d447df14 1177
edc93052
TH		 1178 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1179 ahci_p5wdh_workaround(host);
1180
f80ae7e4
TH		 1181 /* apply gtf filter quirk */
1182 ahci_gtf_filter_workaround(host);
1183
4447d351
TH		 1184 /* initialize adapter */
1185 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1186 if (rc)
24dc5f33 1187 return rc;
1da177e4 1188
3303040d 1189 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1190 if (rc)
1191 return rc;
1da177e4 1192
781d6550 1193 ahci_pci_init_controller(host);
439fcaec 1194 ahci_pci_print_info(host);
1da177e4 1195
4447d351
TH		 1196 pci_set_master(pdev);
1197 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1198 &ahci_sht);
907f4678 1199}
1da177e4
LT		 1200
1201static int __init ahci_init(void)
1202{
b7887196 1203 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1204}
1205
1da177e4
LT		 1206static void __exit ahci_exit(void)
1207{
1208 pci_unregister_driver(&ahci_pci_driver);
1209}
1210
1211
1212MODULE_AUTHOR("Jeff Garzik");
1213MODULE_DESCRIPTION("AHCI SATA low-level driver");
1214MODULE_LICENSE("GPL");
1215MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1216MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1217
1218module_init(ahci_init);
1219module_exit(ahci_exit);
Linux kernel - Deliverables
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