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[libata] sata_via: kill uninit'd var warning
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
87943acf
DM		 52/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
a22e6444 63static int ahci_skip_host_reset;
f3d7f23f
AV		 64static int ahci_ignore_sss;
65
a22e6444
TH		 66module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
f3d7f23f
AV		 69module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
31556594
KCA		 72static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 75static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
80#define MAX_SLOTS 8
4c1e9aa4 81#define MAX_RETRY 15
1da177e4
LT		 82
83enum {
84 AHCI_PCI_BAR = 5,
648a88be 85 AHCI_MAX_PORTS = 32,
1da177e4
LT		 86 AHCI_MAX_SG = 168, /* hardware max is 64K */
87 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 88 AHCI_MAX_CMDS = 32,
dd410ff1 89 AHCI_CMD_SZ = 32,
12fad3f9 90 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 91 AHCI_RX_FIS_SZ = 256,
a0ea7328 92 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 93 AHCI_CMD_TBL_HDR_SZ = 0x80,
94 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
95 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
96 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 97 AHCI_RX_FIS_SZ,
98 AHCI_IRQ_ON_SG = (1 << 31),
99 AHCI_CMD_ATAPI = (1 << 5),
100 AHCI_CMD_WRITE = (1 << 6),
4b10e559 101 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 102 AHCI_CMD_RESET = (1 << 8),
103 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 104
105 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 106 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 107 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 108
109 board_ahci = 0,
7a234aff
TH		 110 board_ahci_vt8251 = 1,
111 board_ahci_ign_iferr = 2,
112 board_ahci_sb600 = 3,
113 board_ahci_mv = 4,
e427fe04 114 board_ahci_sb700 = 5, /* for SB700 and SB800 */
e297d99e 115 board_ahci_mcp65 = 6,
9a3b103c 116 board_ahci_nopmp = 7,
1da177e4
LT		 117
118 /* global controller registers */
119 HOST_CAP = 0x00, /* host capabilities */
120 HOST_CTL = 0x04, /* global host control */
121 HOST_IRQ_STAT = 0x08, /* interrupt status */
122 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
123 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 124 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
125 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
1da177e4
LT		 126
127 /* HOST_CTL bits */
128 HOST_RESET = (1 << 0), /* reset controller; self-clear */
129 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
130 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
131
132 /* HOST_CAP bits */
18f7ba4c 133 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
0be0aa98 134 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 135 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 136 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 137 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 138 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 139 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 140 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 141 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 142
143 /* registers for each SATA port */
144 PORT_LST_ADDR = 0x00, /* command list DMA addr */
145 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
146 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
147 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
148 PORT_IRQ_STAT = 0x10, /* interrupt status */
149 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
150 PORT_CMD = 0x18, /* port command */
151 PORT_TFDATA = 0x20, /* taskfile data */
152 PORT_SIG = 0x24, /* device TF signature */
153 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 154 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
155 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
156 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
157 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 158 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 159
160 /* PORT_IRQ_{STAT,MASK} bits */
161 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
162 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
163 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
164 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
165 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
166 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
167 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
168 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
169
170 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
171 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
172 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
173 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
174 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
175 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
176 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
177 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
178 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
179
78cd52d0
TH		 180 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
181 PORT_IRQ_IF_ERR |
182 PORT_IRQ_CONNECT |
4296971d 183 PORT_IRQ_PHYRDY |
7d50b60b
TH		 184 PORT_IRQ_UNK_FIS |
185 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 186 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
187 PORT_IRQ_TF_ERR |
188 PORT_IRQ_HBUS_DATA_ERR,
189 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
190 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
191 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 192
193 /* PORT_CMD bits */
31556594
KCA		 194 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
195 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 196 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 197 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 198 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
199 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
200 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 201 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 202 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
203 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
204 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
205
0be0aa98 206 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 207 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
208 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
209 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 210
417a1a6d
TH		 211 /* hpriv->flags bits */
212 AHCI_HFLAG_NO_NCQ = (1 << 0),
213 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
214 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
215 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
216 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
217 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 218 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 219 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 220 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 221 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
417a1a6d 222
bf2af2a2 223 /* ap->flags bits */
1188c0d8
TH		 224
225 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
226 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 227 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
228 ATA_FLAG_IPM,
c4f7792c
TH		 229
230 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c
KCA		 231
232 /* em_ctl bits */
233 EM_CTL_RST = (1 << 9), /* Reset */
234 EM_CTL_TM = (1 << 8), /* Transmit Message */
235 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 236};
237
238struct ahci_cmd_hdr {
4ca4e439
AV		 239 __le32 opts;
240 __le32 status;
241 __le32 tbl_addr;
242 __le32 tbl_addr_hi;
243 __le32 reserved[4];
1da177e4
LT		 244};
245
246struct ahci_sg {
4ca4e439
AV		 247 __le32 addr;
248 __le32 addr_hi;
249 __le32 reserved;
250 __le32 flags_size;
1da177e4
LT		 251};
252
18f7ba4c
KCA		 253struct ahci_em_priv {
254 enum sw_activity blink_policy;
255 struct timer_list timer;
256 unsigned long saved_activity;
257 unsigned long activity;
258 unsigned long led_state;
259};
260
1da177e4 261struct ahci_host_priv {
417a1a6d 262 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 263 u32 cap; /* cap to use */
264 u32 port_map; /* port map to use */
265 u32 saved_cap; /* saved initial cap */
266 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 267 u32 em_loc; /* enclosure management location */
1da177e4
LT		 268};
269
270struct ahci_port_priv {
7d50b60b 271 struct ata_link *active_link;
1da177e4
LT		 272 struct ahci_cmd_hdr *cmd_slot;
273 dma_addr_t cmd_slot_dma;
274 void *cmd_tbl;
275 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 276 void *rx_fis;
277 dma_addr_t rx_fis_dma;
0291f95f 278 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 279 unsigned int ncq_saw_d2h:1;
280 unsigned int ncq_saw_dmas:1;
afb2d552 281 unsigned int ncq_saw_sdb:1;
a7384925 282 u32 intr_mask; /* interrupts to enable */
18f7ba4c
KCA		 283 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
284 * per PM slot */
1da177e4
LT		 285};
286
82ef04fb
TH		 287static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
288static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
2dcb407e 289static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 290static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 291static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 292static int ahci_port_start(struct ata_port *ap);
293static void ahci_port_stop(struct ata_port *ap);
1da177e4 294static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 295static void ahci_freeze(struct ata_port *ap);
296static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 297static void ahci_pmp_attach(struct ata_port *ap);
298static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 299static int ahci_softreset(struct ata_link *link, unsigned int *class,
300 unsigned long deadline);
bd17243a
SH		 301static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
302 unsigned long deadline);
a1efdaba
TH		 303static int ahci_hardreset(struct ata_link *link, unsigned int *class,
304 unsigned long deadline);
305static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
307static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
309static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 310static void ahci_error_handler(struct ata_port *ap);
311static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 312static int ahci_port_resume(struct ata_port *ap);
a878539e 313static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 314static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
315static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
316 u32 opts);
438ac6d5 317#ifdef CONFIG_PM
c1332875 318static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 319static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
320static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 321#endif
18f7ba4c
KCA		 322static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
323static ssize_t ahci_activity_store(struct ata_device *dev,
324 enum sw_activity val);
325static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 326
ee959b00
TJ		 327static struct device_attribute *ahci_shost_attrs[] = {
328 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 329 &dev_attr_em_message_type,
330 &dev_attr_em_message,
331 NULL
332};
333
334static struct device_attribute *ahci_sdev_attrs[] = {
335 &dev_attr_sw_activity,
45fabbb7 336 &dev_attr_unload_heads,
31556594
KCA		 337 NULL
338};
339
193515d5 340static struct scsi_host_template ahci_sht = {
68d1d07b 341 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 342 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 343 .sg_tablesize = AHCI_MAX_SG,
1da177e4 344 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 345 .shost_attrs = ahci_shost_attrs,
18f7ba4c 346 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 347};
348
029cfd6b
TH		 349static struct ata_port_operations ahci_ops = {
350 .inherits = &sata_pmp_port_ops,
351
7d50b60b 352 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 353 .qc_prep = ahci_qc_prep,
354 .qc_issue = ahci_qc_issue,
4c9bf4e7 355 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 356
78cd52d0
TH		 357 .freeze = ahci_freeze,
358 .thaw = ahci_thaw,
a1efdaba
TH		 359 .softreset = ahci_softreset,
360 .hardreset = ahci_hardreset,
361 .postreset = ahci_postreset,
071f44b1 362 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 363 .error_handler = ahci_error_handler,
364 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 365 .dev_config = ahci_dev_config,
366
ad616ffb
TH		 367 .scr_read = ahci_scr_read,
368 .scr_write = ahci_scr_write,
7d50b60b
TH		 369 .pmp_attach = ahci_pmp_attach,
370 .pmp_detach = ahci_pmp_detach,
7d50b60b 371
029cfd6b
TH		 372 .enable_pm = ahci_enable_alpm,
373 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 374 .em_show = ahci_led_show,
375 .em_store = ahci_led_store,
376 .sw_activity_show = ahci_activity_show,
377 .sw_activity_store = ahci_activity_store,
438ac6d5 378#ifdef CONFIG_PM
ad616ffb
TH		 379 .port_suspend = ahci_port_suspend,
380 .port_resume = ahci_port_resume,
438ac6d5 381#endif
ad616ffb
TH		 382 .port_start = ahci_port_start,
383 .port_stop = ahci_port_stop,
384};
385
029cfd6b
TH		 386static struct ata_port_operations ahci_vt8251_ops = {
387 .inherits = &ahci_ops,
a1efdaba 388 .hardreset = ahci_vt8251_hardreset,
029cfd6b 389};
edc93052 390
029cfd6b
TH		 391static struct ata_port_operations ahci_p5wdh_ops = {
392 .inherits = &ahci_ops,
a1efdaba 393 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 394};
395
bd17243a
SH		 396static struct ata_port_operations ahci_sb600_ops = {
397 .inherits = &ahci_ops,
398 .softreset = ahci_sb600_softreset,
399 .pmp_softreset = ahci_sb600_softreset,
400};
401
417a1a6d
TH		 402#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
403
98ac62de 404static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 405 /* board_ahci */
406 {
1188c0d8 407 .flags = AHCI_FLAG_COMMON,
14bdef98 408 .pio_mask = ATA_PIO4,
469248ab 409 .udma_mask = ATA_UDMA6,
1da177e4
LT		 410 .port_ops = &ahci_ops,
411 },
bf2af2a2
BJ		 412 /* board_ahci_vt8251 */
413 {
6949b914 414 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 415 .flags = AHCI_FLAG_COMMON,
14bdef98 416 .pio_mask = ATA_PIO4,
469248ab 417 .udma_mask = ATA_UDMA6,
ad616ffb 418 .port_ops = &ahci_vt8251_ops,
bf2af2a2 419 },
41669553
TH		 420 /* board_ahci_ign_iferr */
421 {
417a1a6d
TH		 422 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
423 .flags = AHCI_FLAG_COMMON,
14bdef98 424 .pio_mask = ATA_PIO4,
469248ab 425 .udma_mask = ATA_UDMA6,
41669553
TH		 426 .port_ops = &ahci_ops,
427 },
55a61604
CH		 428 /* board_ahci_sb600 */
429 {
417a1a6d 430 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
22b5e7a7 431 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
bd17243a 432 AHCI_HFLAG_SECT255),
417a1a6d 433 .flags = AHCI_FLAG_COMMON,
14bdef98 434 .pio_mask = ATA_PIO4,
469248ab 435 .udma_mask = ATA_UDMA6,
bd17243a 436 .port_ops = &ahci_sb600_ops,
55a61604 437 },
cd70c266
JG		 438 /* board_ahci_mv */
439 {
417a1a6d 440 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 441 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 442 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 443 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 444 .pio_mask = ATA_PIO4,
cd70c266
JG		 445 .udma_mask = ATA_UDMA6,
446 .port_ops = &ahci_ops,
447 },
e427fe04 448 /* board_ahci_sb700, for SB700 and SB800 */
e39fc8c9 449 {
bd17243a 450 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 451 .flags = AHCI_FLAG_COMMON,
14bdef98 452 .pio_mask = ATA_PIO4,
e39fc8c9 453 .udma_mask = ATA_UDMA6,
bd17243a 454 .port_ops = &ahci_sb600_ops,
e39fc8c9 455 },
e297d99e
TH		 456 /* board_ahci_mcp65 */
457 {
458 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
459 .flags = AHCI_FLAG_COMMON,
14bdef98 460 .pio_mask = ATA_PIO4,
e297d99e
TH		 461 .udma_mask = ATA_UDMA6,
462 .port_ops = &ahci_ops,
463 },
9a3b103c
TH		 464 /* board_ahci_nopmp */
465 {
466 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
467 .flags = AHCI_FLAG_COMMON,
14bdef98 468 .pio_mask = ATA_PIO4,
9a3b103c
TH		 469 .udma_mask = ATA_UDMA6,
470 .port_ops = &ahci_ops,
471 },
1da177e4
LT		 472};
473
3b7d697d 474static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 475 /* Intel */
54bb3a94
JG		 476 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
477 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
478 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
479 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
480 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 481 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 482 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
483 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
484 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
485 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 486 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
487 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
488 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
489 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
490 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
491 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
492 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
493 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
494 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
495 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
496 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
497 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
498 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
499 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
500 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
501 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
502 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 503 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
504 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 505 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
506 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
adcb5308 507 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 508 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
adcb5308 509 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 510 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
fe7fa31a 511
e34bb370
TH		 512 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
513 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
514 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 515
516 /* ATI */
c65ec1c2 517 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 518 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
519 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
520 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
521 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
522 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
523 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 524
525 /* VIA */
54bb3a94 526 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 527 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 528
529 /* NVIDIA */
e297d99e
TH		 530 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
531 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
532 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
533 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
534 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
535 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
536 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
537 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
6fbf5ba4
PC		 538 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
539 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
540 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
541 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 542 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
543 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
544 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
545 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
546 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
547 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
548 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
549 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 550 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
551 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
552 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
553 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
554 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
555 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
556 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
557 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
558 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
559 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
560 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
561 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
562 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
563 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
564 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
565 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
566 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
567 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
568 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
569 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
570 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
571 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
572 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
573 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 574 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
575 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
576 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
577 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 578 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
579 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
580 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
581 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
582 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
583 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
584 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
585 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
7adbe46b 586 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
587 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
588 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
589 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
590 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
591 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
592 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
593 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
594 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
595 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
596 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
597 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
fe7fa31a 598
95916edd 599 /* SiS */
20e2de4a
TH		 600 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
601 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
602 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 603
cd70c266
JG		 604 /* Marvell */
605 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 606 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 607
c77a036b
MN		 608 /* Promise */
609 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
610
415ae2b5
JG		 611 /* Generic, PCI class code for AHCI */
612 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 613 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 614
1da177e4
LT		 615 { } /* terminate list */
616};
617
618
619static struct pci_driver ahci_pci_driver = {
620 .name = DRV_NAME,
621 .id_table = ahci_pci_tbl,
622 .probe = ahci_init_one,
24dc5f33 623 .remove = ata_pci_remove_one,
438ac6d5 624#ifdef CONFIG_PM
c1332875
TH		 625 .suspend = ahci_pci_device_suspend,
626 .resume = ahci_pci_device_resume,
438ac6d5 627#endif
1da177e4
LT		 628};
629
18f7ba4c
KCA		 630static int ahci_em_messages = 1;
631module_param(ahci_em_messages, int, 0444);
632/* add other LED protocol types when they become supported */
633MODULE_PARM_DESC(ahci_em_messages,
634 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 635
5b66c829
AC		 636#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
637static int marvell_enable;
638#else
639static int marvell_enable = 1;
640#endif
641module_param(marvell_enable, int, 0644);
642MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
643
644
98fa4b60
TH		 645static inline int ahci_nr_ports(u32 cap)
646{
647 return (cap & 0x1f) + 1;
648}
649
dab632e8
JG		 650static inline void __iomem *__ahci_port_base(struct ata_host *host,
651 unsigned int port_no)
1da177e4 652{
dab632e8 653 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 654
dab632e8
JG		 655 return mmio + 0x100 + (port_no * 0x80);
656}
657
658static inline void __iomem *ahci_port_base(struct ata_port *ap)
659{
660 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 661}
662
b710a1f4
TH		 663static void ahci_enable_ahci(void __iomem *mmio)
664{
15fe982e 665 int i;
b710a1f4
TH		 666 u32 tmp;
667
668 /* turn on AHCI_EN */
669 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 670 if (tmp & HOST_AHCI_EN)
671 return;
672
673 /* Some controllers need AHCI_EN to be written multiple times.
674 * Try a few times before giving up.
675 */
676 for (i = 0; i < 5; i++) {
b710a1f4
TH		 677 tmp |= HOST_AHCI_EN;
678 writel(tmp, mmio + HOST_CTL);
679 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 680 if (tmp & HOST_AHCI_EN)
681 return;
682 msleep(10);
b710a1f4 683 }
15fe982e
TH		 684
685 WARN_ON(1);
b710a1f4
TH		 686}
687
d447df14
TH		 688/**
689 * ahci_save_initial_config - Save and fixup initial config values
4447d351 690 * @pdev: target PCI device
4447d351 691 * @hpriv: host private area to store config values
d447df14
TH		 692 *
693 * Some registers containing configuration info might be setup by
694 * BIOS and might be cleared on reset. This function saves the
695 * initial values of those registers into @hpriv such that they
696 * can be restored after controller reset.
697 *
698 * If inconsistent, config values are fixed up by this function.
699 *
700 * LOCKING:
701 * None.
702 */
4447d351 703static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 704 struct ahci_host_priv *hpriv)
d447df14 705{
4447d351 706 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 707 u32 cap, port_map;
17199b18 708 int i;
c40e7cb8 709 int mv;
d447df14 710
b710a1f4
TH		 711 /* make sure AHCI mode is enabled before accessing CAP */
712 ahci_enable_ahci(mmio);
713
d447df14
TH		 714 /* Values prefixed with saved_ are written back to host after
715 * reset. Values without are used for driver operation.
716 */
717 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
718 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
719
274c1fde 720 /* some chips have errata preventing 64bit use */
417a1a6d 721 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 722 dev_printk(KERN_INFO, &pdev->dev,
723 "controller can't do 64bit DMA, forcing 32bit\n");
724 cap &= ~HOST_CAP_64;
725 }
726
417a1a6d 727 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 728 dev_printk(KERN_INFO, &pdev->dev,
729 "controller can't do NCQ, turning off CAP_NCQ\n");
730 cap &= ~HOST_CAP_NCQ;
731 }
732
e297d99e
TH		 733 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
734 dev_printk(KERN_INFO, &pdev->dev,
735 "controller can do NCQ, turning on CAP_NCQ\n");
736 cap |= HOST_CAP_NCQ;
737 }
738
258cd846 739 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 740 dev_printk(KERN_INFO, &pdev->dev,
741 "controller can't do PMP, turning off CAP_PMP\n");
742 cap &= ~HOST_CAP_PMP;
743 }
744
d799e083
TH		 745 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
746 port_map != 1) {
747 dev_printk(KERN_INFO, &pdev->dev,
748 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
749 port_map, 1);
750 port_map = 1;
751 }
752
cd70c266
JG		 753 /*
754 * Temporary Marvell 6145 hack: PATA port presence
755 * is asserted through the standard AHCI port
756 * presence register, as bit 4 (counting from 0)
757 */
417a1a6d 758 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 759 if (pdev->device == 0x6121)
760 mv = 0x3;
761 else
762 mv = 0xf;
cd70c266
JG		 763 dev_printk(KERN_ERR, &pdev->dev,
764 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 765 port_map,
766 port_map & mv);
5b66c829
AC		 767 dev_printk(KERN_ERR, &pdev->dev,
768 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
cd70c266 769
c40e7cb8 770 port_map &= mv;
cd70c266
JG		 771 }
772
17199b18 773 /* cross check port_map and cap.n_ports */
7a234aff 774 if (port_map) {
837f5f8f 775 int map_ports = 0;
17199b18 776
837f5f8f
TH		 777 for (i = 0; i < AHCI_MAX_PORTS; i++)
778 if (port_map & (1 << i))
779 map_ports++;
17199b18 780
837f5f8f
TH		 781 /* If PI has more ports than n_ports, whine, clear
782 * port_map and let it be generated from n_ports.
17199b18 783 */
837f5f8f 784 if (map_ports > ahci_nr_ports(cap)) {
4447d351 785 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 786 "implemented port map (0x%x) contains more "
787 "ports than nr_ports (%u), using nr_ports\n",
788 port_map, ahci_nr_ports(cap));
7a234aff
TH		 789 port_map = 0;
790 }
791 }
792
793 /* fabricate port_map from cap.nr_ports */
794 if (!port_map) {
17199b18 795 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 796 dev_printk(KERN_WARNING, &pdev->dev,
797 "forcing PORTS_IMPL to 0x%x\n", port_map);
798
799 /* write the fixed up value to the PI register */
800 hpriv->saved_port_map = port_map;
17199b18
TH		 801 }
802
d447df14
TH		 803 /* record values to use during operation */
804 hpriv->cap = cap;
805 hpriv->port_map = port_map;
806}
807
808/**
809 * ahci_restore_initial_config - Restore initial config
4447d351 810 * @host: target ATA host
d447df14
TH		 811 *
812 * Restore initial config stored by ahci_save_initial_config().
813 *
814 * LOCKING:
815 * None.
816 */
4447d351 817static void ahci_restore_initial_config(struct ata_host *host)
d447df14 818{
4447d351
TH		 819 struct ahci_host_priv *hpriv = host->private_data;
820 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
821
d447df14
TH		 822 writel(hpriv->saved_cap, mmio + HOST_CAP);
823 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
824 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
825}
826
203ef6c4 827static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 828{
203ef6c4
TH		 829 static const int offset[] = {
830 [SCR_STATUS] = PORT_SCR_STAT,
831 [SCR_CONTROL] = PORT_SCR_CTL,
832 [SCR_ERROR] = PORT_SCR_ERR,
833 [SCR_ACTIVE] = PORT_SCR_ACT,
834 [SCR_NOTIFICATION] = PORT_SCR_NTF,
835 };
836 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 837
203ef6c4
TH		 838 if (sc_reg < ARRAY_SIZE(offset) &&
839 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
840 return offset[sc_reg];
da3dbb17 841 return 0;
1da177e4
LT		 842}
843
82ef04fb 844static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1da177e4 845{
82ef04fb
TH		 846 void __iomem *port_mmio = ahci_port_base(link->ap);
847 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 848
849 if (offset) {
850 *val = readl(port_mmio + offset);
851 return 0;
1da177e4 852 }
203ef6c4
TH		 853 return -EINVAL;
854}
1da177e4 855
82ef04fb 856static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
203ef6c4 857{
82ef04fb
TH		 858 void __iomem *port_mmio = ahci_port_base(link->ap);
859 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 860
861 if (offset) {
862 writel(val, port_mmio + offset);
863 return 0;
864 }
865 return -EINVAL;
1da177e4
LT		 866}
867
4447d351 868static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 869{
4447d351 870 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 871 u32 tmp;
872
d8fcd116 873 /* start DMA */
9f592056 874 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 875 tmp |= PORT_CMD_START;
876 writel(tmp, port_mmio + PORT_CMD);
877 readl(port_mmio + PORT_CMD); /* flush */
878}
879
4447d351 880static int ahci_stop_engine(struct ata_port *ap)
254950cd 881{
4447d351 882 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 883 u32 tmp;
884
885 tmp = readl(port_mmio + PORT_CMD);
886
d8fcd116 887 /* check if the HBA is idle */
254950cd
TH		 888 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
889 return 0;
890
d8fcd116 891 /* setting HBA to idle */
254950cd
TH		 892 tmp &= ~PORT_CMD_START;
893 writel(tmp, port_mmio + PORT_CMD);
894
d8fcd116 895 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 896 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 897 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 898 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 899 return -EIO;
900
901 return 0;
902}
903
4447d351 904static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 905{
4447d351
TH		 906 void __iomem *port_mmio = ahci_port_base(ap);
907 struct ahci_host_priv *hpriv = ap->host->private_data;
908 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 909 u32 tmp;
910
911 /* set FIS registers */
4447d351
TH		 912 if (hpriv->cap & HOST_CAP_64)
913 writel((pp->cmd_slot_dma >> 16) >> 16,
914 port_mmio + PORT_LST_ADDR_HI);
915 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 916
4447d351
TH		 917 if (hpriv->cap & HOST_CAP_64)
918 writel((pp->rx_fis_dma >> 16) >> 16,
919 port_mmio + PORT_FIS_ADDR_HI);
920 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 921
922 /* enable FIS reception */
923 tmp = readl(port_mmio + PORT_CMD);
924 tmp |= PORT_CMD_FIS_RX;
925 writel(tmp, port_mmio + PORT_CMD);
926
927 /* flush */
928 readl(port_mmio + PORT_CMD);
929}
930
4447d351 931static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 932{
4447d351 933 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 934 u32 tmp;
935
936 /* disable FIS reception */
937 tmp = readl(port_mmio + PORT_CMD);
938 tmp &= ~PORT_CMD_FIS_RX;
939 writel(tmp, port_mmio + PORT_CMD);
940
941 /* wait for completion, spec says 500ms, give it 1000 */
942 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
943 PORT_CMD_FIS_ON, 10, 1000);
944 if (tmp & PORT_CMD_FIS_ON)
945 return -EBUSY;
946
947 return 0;
948}
949
4447d351 950static void ahci_power_up(struct ata_port *ap)
0be0aa98 951{
4447d351
TH		 952 struct ahci_host_priv *hpriv = ap->host->private_data;
953 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 954 u32 cmd;
955
956 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
957
958 /* spin up device */
4447d351 959 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 960 cmd |= PORT_CMD_SPIN_UP;
961 writel(cmd, port_mmio + PORT_CMD);
962 }
963
964 /* wake up link */
965 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
966}
967
31556594
KCA		 968static void ahci_disable_alpm(struct ata_port *ap)
969{
970 struct ahci_host_priv *hpriv = ap->host->private_data;
971 void __iomem *port_mmio = ahci_port_base(ap);
972 u32 cmd;
973 struct ahci_port_priv *pp = ap->private_data;
974
975 /* IPM bits should be disabled by libata-core */
976 /* get the existing command bits */
977 cmd = readl(port_mmio + PORT_CMD);
978
979 /* disable ALPM and ASP */
980 cmd &= ~PORT_CMD_ASP;
981 cmd &= ~PORT_CMD_ALPE;
982
983 /* force the interface back to active */
984 cmd |= PORT_CMD_ICC_ACTIVE;
985
986 /* write out new cmd value */
987 writel(cmd, port_mmio + PORT_CMD);
988 cmd = readl(port_mmio + PORT_CMD);
989
990 /* wait 10ms to be sure we've come out of any low power state */
991 msleep(10);
992
993 /* clear out any PhyRdy stuff from interrupt status */
994 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
995
996 /* go ahead and clean out PhyRdy Change from Serror too */
82ef04fb 997 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 998
999 /*
1000 * Clear flag to indicate that we should ignore all PhyRdy
1001 * state changes
1002 */
1003 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1004
1005 /*
1006 * Enable interrupts on Phy Ready.
1007 */
1008 pp->intr_mask |= PORT_IRQ_PHYRDY;
1009 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1010
1011 /*
1012 * don't change the link pm policy - we can be called
1013 * just to turn of link pm temporarily
1014 */
1015}
1016
1017static int ahci_enable_alpm(struct ata_port *ap,
1018 enum link_pm policy)
1019{
1020 struct ahci_host_priv *hpriv = ap->host->private_data;
1021 void __iomem *port_mmio = ahci_port_base(ap);
1022 u32 cmd;
1023 struct ahci_port_priv *pp = ap->private_data;
1024 u32 asp;
1025
1026 /* Make sure the host is capable of link power management */
1027 if (!(hpriv->cap & HOST_CAP_ALPM))
1028 return -EINVAL;
1029
1030 switch (policy) {
1031 case MAX_PERFORMANCE:
1032 case NOT_AVAILABLE:
1033 /*
1034 * if we came here with NOT_AVAILABLE,
1035 * it just means this is the first time we
1036 * have tried to enable - default to max performance,
1037 * and let the user go to lower power modes on request.
1038 */
1039 ahci_disable_alpm(ap);
1040 return 0;
1041 case MIN_POWER:
1042 /* configure HBA to enter SLUMBER */
1043 asp = PORT_CMD_ASP;
1044 break;
1045 case MEDIUM_POWER:
1046 /* configure HBA to enter PARTIAL */
1047 asp = 0;
1048 break;
1049 default:
1050 return -EINVAL;
1051 }
1052
1053 /*
1054 * Disable interrupts on Phy Ready. This keeps us from
1055 * getting woken up due to spurious phy ready interrupts
1056 * TBD - Hot plug should be done via polling now, is
1057 * that even supported?
1058 */
1059 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1060 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1061
1062 /*
1063 * Set a flag to indicate that we should ignore all PhyRdy
1064 * state changes since these can happen now whenever we
1065 * change link state
1066 */
1067 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1068
1069 /* get the existing command bits */
1070 cmd = readl(port_mmio + PORT_CMD);
1071
1072 /*
1073 * Set ASP based on Policy
1074 */
1075 cmd |= asp;
1076
1077 /*
1078 * Setting this bit will instruct the HBA to aggressively
1079 * enter a lower power link state when it's appropriate and
1080 * based on the value set above for ASP
1081 */
1082 cmd |= PORT_CMD_ALPE;
1083
1084 /* write out new cmd value */
1085 writel(cmd, port_mmio + PORT_CMD);
1086 cmd = readl(port_mmio + PORT_CMD);
1087
1088 /* IPM bits should be set by libata-core */
1089 return 0;
1090}
1091
438ac6d5 1092#ifdef CONFIG_PM
4447d351 1093static void ahci_power_down(struct ata_port *ap)
0be0aa98 1094{
4447d351
TH		 1095 struct ahci_host_priv *hpriv = ap->host->private_data;
1096 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1097 u32 cmd, scontrol;
1098
4447d351 1099 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1100 return;
0be0aa98 1101
07c53dac
TH		 1102 /* put device into listen mode, first set PxSCTL.DET to 0 */
1103 scontrol = readl(port_mmio + PORT_SCR_CTL);
1104 scontrol &= ~0xf;
1105 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1106
07c53dac
TH		 1107 /* then set PxCMD.SUD to 0 */
1108 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1109 cmd &= ~PORT_CMD_SPIN_UP;
1110 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1111}
438ac6d5 1112#endif
0be0aa98 1113
df69c9c5 1114static void ahci_start_port(struct ata_port *ap)
0be0aa98 1115{
18f7ba4c
KCA		 1116 struct ahci_port_priv *pp = ap->private_data;
1117 struct ata_link *link;
1118 struct ahci_em_priv *emp;
4c1e9aa4
DM		 1119 ssize_t rc;
1120 int i;
18f7ba4c 1121
0be0aa98 1122 /* enable FIS reception */
4447d351 1123 ahci_start_fis_rx(ap);
0be0aa98
TH		 1124
1125 /* enable DMA */
4447d351 1126 ahci_start_engine(ap);
18f7ba4c
KCA		 1127
1128 /* turn on LEDs */
1129 if (ap->flags & ATA_FLAG_EM) {
1eca4365 1130 ata_for_each_link(link, ap, EDGE) {
18f7ba4c 1131 emp = &pp->em_priv[link->pmp];
4c1e9aa4
DM		 1132
1133 /* EM Transmit bit maybe busy during init */
1134 for (i = 0; i < MAX_RETRY; i++) {
1135 rc = ahci_transmit_led_message(ap,
1136 emp->led_state,
1137 4);
1138 if (rc == -EBUSY)
1139 udelay(100);
1140 else
1141 break;
1142 }
18f7ba4c
KCA		 1143 }
1144 }
1145
1146 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1eca4365 1147 ata_for_each_link(link, ap, EDGE)
18f7ba4c
KCA		 1148 ahci_init_sw_activity(link);
1149
0be0aa98
TH		 1150}
1151
4447d351 1152static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1153{
1154 int rc;
1155
1156 /* disable DMA */
4447d351 1157 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1158 if (rc) {
1159 *emsg = "failed to stop engine";
1160 return rc;
1161 }
1162
1163 /* disable FIS reception */
4447d351 1164 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1165 if (rc) {
1166 *emsg = "failed stop FIS RX";
1167 return rc;
1168 }
1169
0be0aa98
TH		 1170 return 0;
1171}
1172
4447d351 1173static int ahci_reset_controller(struct ata_host *host)
d91542c1 1174{
4447d351 1175 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1176 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1177 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1178 u32 tmp;
d91542c1 1179
3cc3eb11
JG		 1180 /* we must be in AHCI mode, before using anything
1181 * AHCI-specific, such as HOST_RESET.
1182 */
b710a1f4 1183 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1184
1185 /* global controller reset */
a22e6444
TH		 1186 if (!ahci_skip_host_reset) {
1187 tmp = readl(mmio + HOST_CTL);
1188 if ((tmp & HOST_RESET) == 0) {
1189 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1190 readl(mmio + HOST_CTL); /* flush */
1191 }
d91542c1 1192
24920c8a
ZR		 1193 /*
1194 * to perform host reset, OS should set HOST_RESET
1195 * and poll until this bit is read to be "0".
1196 * reset must complete within 1 second, or
a22e6444
TH		 1197 * the hardware should be considered fried.
1198 */
24920c8a
ZR		 1199 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1200 HOST_RESET, 10, 1000);
d91542c1 1201
a22e6444
TH		 1202 if (tmp & HOST_RESET) {
1203 dev_printk(KERN_ERR, host->dev,
1204 "controller reset failed (0x%x)\n", tmp);
1205 return -EIO;
1206 }
d91542c1 1207
a22e6444
TH		 1208 /* turn on AHCI mode */
1209 ahci_enable_ahci(mmio);
98fa4b60 1210
a22e6444
TH		 1211 /* Some registers might be cleared on reset. Restore
1212 * initial values.
1213 */
1214 ahci_restore_initial_config(host);
1215 } else
1216 dev_printk(KERN_INFO, host->dev,
1217 "skipping global host reset\n");
d91542c1
TH		 1218
1219 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1220 u16 tmp16;
1221
1222 /* configure PCS */
1223 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1224 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1225 tmp16 |= hpriv->port_map;
1226 pci_write_config_word(pdev, 0x92, tmp16);
1227 }
d91542c1
TH		 1228 }
1229
1230 return 0;
1231}
1232
18f7ba4c
KCA		 1233static void ahci_sw_activity(struct ata_link *link)
1234{
1235 struct ata_port *ap = link->ap;
1236 struct ahci_port_priv *pp = ap->private_data;
1237 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1238
1239 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1240 return;
1241
1242 emp->activity++;
1243 if (!timer_pending(&emp->timer))
1244 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1245}
1246
1247static void ahci_sw_activity_blink(unsigned long arg)
1248{
1249 struct ata_link *link = (struct ata_link *)arg;
1250 struct ata_port *ap = link->ap;
1251 struct ahci_port_priv *pp = ap->private_data;
1252 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1253 unsigned long led_message = emp->led_state;
1254 u32 activity_led_state;
eb40963c 1255 unsigned long flags;
18f7ba4c 1256
87943acf 1257 led_message &= EM_MSG_LED_VALUE;
18f7ba4c
KCA		 1258 led_message |= ap->port_no | (link->pmp << 8);
1259
1260 /* check to see if we've had activity. If so,
1261 * toggle state of LED and reset timer. If not,
1262 * turn LED to desired idle state.
1263 */
eb40963c 1264 spin_lock_irqsave(ap->lock, flags);
18f7ba4c
KCA		 1265 if (emp->saved_activity != emp->activity) {
1266 emp->saved_activity = emp->activity;
1267 /* get the current LED state */
87943acf 1268 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
18f7ba4c
KCA		 1269
1270 if (activity_led_state)
1271 activity_led_state = 0;
1272 else
1273 activity_led_state = 1;
1274
1275 /* clear old state */
87943acf 1276 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1277
1278 /* toggle state */
1279 led_message |= (activity_led_state << 16);
1280 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1281 } else {
1282 /* switch to idle */
87943acf 1283 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1284 if (emp->blink_policy == BLINK_OFF)
1285 led_message |= (1 << 16);
1286 }
eb40963c 1287 spin_unlock_irqrestore(ap->lock, flags);
18f7ba4c
KCA		 1288 ahci_transmit_led_message(ap, led_message, 4);
1289}
1290
1291static void ahci_init_sw_activity(struct ata_link *link)
1292{
1293 struct ata_port *ap = link->ap;
1294 struct ahci_port_priv *pp = ap->private_data;
1295 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1296
1297 /* init activity stats, setup timer */
1298 emp->saved_activity = emp->activity = 0;
1299 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1300
1301 /* check our blink policy and set flag for link if it's enabled */
1302 if (emp->blink_policy)
1303 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1304}
1305
1306static int ahci_reset_em(struct ata_host *host)
1307{
1308 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1309 u32 em_ctl;
1310
1311 em_ctl = readl(mmio + HOST_EM_CTL);
1312 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1313 return -EINVAL;
1314
1315 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1316 return 0;
1317}
1318
1319static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1320 ssize_t size)
1321{
1322 struct ahci_host_priv *hpriv = ap->host->private_data;
1323 struct ahci_port_priv *pp = ap->private_data;
1324 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1325 u32 em_ctl;
1326 u32 message[] = {0, 0};
93082f0b 1327 unsigned long flags;
18f7ba4c
KCA		 1328 int pmp;
1329 struct ahci_em_priv *emp;
1330
1331 /* get the slot number from the message */
87943acf 1332 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
18f7ba4c
KCA		 1333 if (pmp < MAX_SLOTS)
1334 emp = &pp->em_priv[pmp];
1335 else
1336 return -EINVAL;
1337
1338 spin_lock_irqsave(ap->lock, flags);
1339
1340 /*
1341 * if we are still busy transmitting a previous message,
1342 * do not allow
1343 */
1344 em_ctl = readl(mmio + HOST_EM_CTL);
1345 if (em_ctl & EM_CTL_TM) {
1346 spin_unlock_irqrestore(ap->lock, flags);
4c1e9aa4 1347 return -EBUSY;
18f7ba4c
KCA		 1348 }
1349
1350 /*
1351 * create message header - this is all zero except for
1352 * the message size, which is 4 bytes.
1353 */
1354 message[0] |= (4 << 8);
1355
1356 /* ignore 0:4 of byte zero, fill in port info yourself */
87943acf 1357 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
18f7ba4c
KCA		 1358
1359 /* write message to EM_LOC */
1360 writel(message[0], mmio + hpriv->em_loc);
1361 writel(message[1], mmio + hpriv->em_loc+4);
1362
1363 /* save off new led state for port/slot */
208f2a88 1364 emp->led_state = state;
18f7ba4c
KCA		 1365
1366 /*
1367 * tell hardware to transmit the message
1368 */
1369 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1370
1371 spin_unlock_irqrestore(ap->lock, flags);
1372 return size;
1373}
1374
1375static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1376{
1377 struct ahci_port_priv *pp = ap->private_data;
1378 struct ata_link *link;
1379 struct ahci_em_priv *emp;
1380 int rc = 0;
1381
1eca4365 1382 ata_for_each_link(link, ap, EDGE) {
18f7ba4c
KCA		 1383 emp = &pp->em_priv[link->pmp];
1384 rc += sprintf(buf, "%lx\n", emp->led_state);
1385 }
1386 return rc;
1387}
1388
1389static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1390 size_t size)
1391{
1392 int state;
1393 int pmp;
1394 struct ahci_port_priv *pp = ap->private_data;
1395 struct ahci_em_priv *emp;
1396
1397 state = simple_strtoul(buf, NULL, 0);
1398
1399 /* get the slot number from the message */
87943acf 1400 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
18f7ba4c
KCA		 1401 if (pmp < MAX_SLOTS)
1402 emp = &pp->em_priv[pmp];
1403 else
1404 return -EINVAL;
1405
1406 /* mask off the activity bits if we are in sw_activity
1407 * mode, user should turn off sw_activity before setting
1408 * activity led through em_message
1409 */
1410 if (emp->blink_policy)
87943acf 1411 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1412
1413 return ahci_transmit_led_message(ap, state, size);
1414}
1415
1416static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1417{
1418 struct ata_link *link = dev->link;
1419 struct ata_port *ap = link->ap;
1420 struct ahci_port_priv *pp = ap->private_data;
1421 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1422 u32 port_led_state = emp->led_state;
1423
1424 /* save the desired Activity LED behavior */
1425 if (val == OFF) {
1426 /* clear LFLAG */
1427 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1428
1429 /* set the LED to OFF */
87943acf 1430 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c
KCA		 1431 port_led_state |= (ap->port_no | (link->pmp << 8));
1432 ahci_transmit_led_message(ap, port_led_state, 4);
1433 } else {
1434 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1435 if (val == BLINK_OFF) {
1436 /* set LED to ON for idle */
87943acf 1437 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c 1438 port_led_state |= (ap->port_no | (link->pmp << 8));
87943acf 1439 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
18f7ba4c
KCA		 1440 ahci_transmit_led_message(ap, port_led_state, 4);
1441 }
1442 }
1443 emp->blink_policy = val;
1444 return 0;
1445}
1446
1447static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1448{
1449 struct ata_link *link = dev->link;
1450 struct ata_port *ap = link->ap;
1451 struct ahci_port_priv *pp = ap->private_data;
1452 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1453
1454 /* display the saved value of activity behavior for this
1455 * disk.
1456 */
1457 return sprintf(buf, "%d\n", emp->blink_policy);
1458}
1459
2bcd866b
JG		 1460static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1461 int port_no, void __iomem *mmio,
1462 void __iomem *port_mmio)
1463{
1464 const char *emsg = NULL;
1465 int rc;
1466 u32 tmp;
1467
1468 /* make sure port is not active */
1469 rc = ahci_deinit_port(ap, &emsg);
1470 if (rc)
1471 dev_printk(KERN_WARNING, &pdev->dev,
1472 "%s (%d)\n", emsg, rc);
1473
1474 /* clear SError */
1475 tmp = readl(port_mmio + PORT_SCR_ERR);
1476 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1477 writel(tmp, port_mmio + PORT_SCR_ERR);
1478
1479 /* clear port IRQ */
1480 tmp = readl(port_mmio + PORT_IRQ_STAT);
1481 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1482 if (tmp)
1483 writel(tmp, port_mmio + PORT_IRQ_STAT);
1484
1485 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1486}
1487
4447d351 1488static void ahci_init_controller(struct ata_host *host)
d91542c1 1489{
417a1a6d 1490 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1491 struct pci_dev *pdev = to_pci_dev(host->dev);
1492 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1493 int i;
cd70c266 1494 void __iomem *port_mmio;
d91542c1 1495 u32 tmp;
c40e7cb8 1496 int mv;
d91542c1 1497
417a1a6d 1498 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1499 if (pdev->device == 0x6121)
1500 mv = 2;
1501 else
1502 mv = 4;
1503 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1504
1505 writel(0, port_mmio + PORT_IRQ_MASK);
1506
1507 /* clear port IRQ */
1508 tmp = readl(port_mmio + PORT_IRQ_STAT);
1509 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1510 if (tmp)
1511 writel(tmp, port_mmio + PORT_IRQ_STAT);
1512 }
1513
4447d351
TH		 1514 for (i = 0; i < host->n_ports; i++) {
1515 struct ata_port *ap = host->ports[i];
d91542c1 1516
cd70c266 1517 port_mmio = ahci_port_base(ap);
4447d351 1518 if (ata_port_is_dummy(ap))
d91542c1 1519 continue;
d91542c1 1520
2bcd866b 1521 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1522 }
1523
1524 tmp = readl(mmio + HOST_CTL);
1525 VPRINTK("HOST_CTL 0x%x\n", tmp);
1526 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1527 tmp = readl(mmio + HOST_CTL);
1528 VPRINTK("HOST_CTL 0x%x\n", tmp);
1529}
1530
a878539e
JG		 1531static void ahci_dev_config(struct ata_device *dev)
1532{
1533 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1534
4cde32fc 1535 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1536 dev->max_sectors = 255;
4cde32fc
JG		 1537 ata_dev_printk(dev, KERN_INFO,
1538 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1539 }
a878539e
JG		 1540}
1541
422b7595 1542static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1543{
4447d351 1544 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1545 struct ata_taskfile tf;
422b7595
TH		 1546 u32 tmp;
1547
1548 tmp = readl(port_mmio + PORT_SIG);
1549 tf.lbah = (tmp >> 24) & 0xff;
1550 tf.lbam = (tmp >> 16) & 0xff;
1551 tf.lbal = (tmp >> 8) & 0xff;
1552 tf.nsect = (tmp) & 0xff;
1553
1554 return ata_dev_classify(&tf);
1555}
1556
12fad3f9
TH		 1557static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1558 u32 opts)
cc9278ed 1559{
12fad3f9
TH		 1560 dma_addr_t cmd_tbl_dma;
1561
1562 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1563
1564 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1565 pp->cmd_slot[tag].status = 0;
1566 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1567 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1568}
1569
d2e75dff 1570static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1571{
350756f6 1572 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1573 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1574 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1575 u32 tmp;
d2e75dff 1576 int busy, rc;
bf2af2a2 1577
d2e75dff 1578 /* do we need to kick the port? */
520d06f9 1579 busy = status & (ATA_BUSY | ATA_DRQ);
d2e75dff
TH		 1580 if (!busy && !force_restart)
1581 return 0;
1582
1583 /* stop engine */
1584 rc = ahci_stop_engine(ap);
1585 if (rc)
1586 goto out_restart;
1587
1588 /* need to do CLO? */
1589 if (!busy) {
1590 rc = 0;
1591 goto out_restart;
1592 }
1593
1594 if (!(hpriv->cap & HOST_CAP_CLO)) {
1595 rc = -EOPNOTSUPP;
1596 goto out_restart;
1597 }
bf2af2a2 1598
d2e75dff 1599 /* perform CLO */
bf2af2a2
BJ		 1600 tmp = readl(port_mmio + PORT_CMD);
1601 tmp |= PORT_CMD_CLO;
1602 writel(tmp, port_mmio + PORT_CMD);
1603
d2e75dff 1604 rc = 0;
bf2af2a2
BJ		 1605 tmp = ata_wait_register(port_mmio + PORT_CMD,
1606 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1607 if (tmp & PORT_CMD_CLO)
d2e75dff 1608 rc = -EIO;
bf2af2a2 1609
d2e75dff
TH		 1610 /* restart engine */
1611 out_restart:
1612 ahci_start_engine(ap);
1613 return rc;
bf2af2a2
BJ		 1614}
1615
91c4a2e0
TH		 1616static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1617 struct ata_taskfile *tf, int is_cmd, u16 flags,
1618 unsigned long timeout_msec)
bf2af2a2 1619{
91c4a2e0 1620 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1621 struct ahci_port_priv *pp = ap->private_data;
4447d351 1622 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1623 u8 *fis = pp->cmd_tbl;
1624 u32 tmp;
1625
1626 /* prep the command */
1627 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1628 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1629
1630 /* issue & wait */
1631 writel(1, port_mmio + PORT_CMD_ISSUE);
1632
1633 if (timeout_msec) {
1634 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1635 1, timeout_msec);
1636 if (tmp & 0x1) {
1637 ahci_kick_engine(ap, 1);
1638 return -EBUSY;
1639 }
1640 } else
1641 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1642
1643 return 0;
1644}
1645
bd17243a
SH		 1646static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1647 int pmp, unsigned long deadline,
1648 int (*check_ready)(struct ata_link *link))
91c4a2e0 1649{
cc0680a5 1650 struct ata_port *ap = link->ap;
4658f79b 1651 const char *reason = NULL;
2cbb79eb 1652 unsigned long now, msecs;
4658f79b 1653 struct ata_taskfile tf;
4658f79b
TH		 1654 int rc;
1655
1656 DPRINTK("ENTER\n");
1657
1658 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1659 rc = ahci_kick_engine(ap, 1);
994056d7 1660 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1661 ata_link_printk(link, KERN_WARNING,
994056d7 1662 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1663
cc0680a5 1664 ata_tf_init(link->device, &tf);
4658f79b
TH		 1665
1666 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1667 msecs = 0;
1668 now = jiffies;
1669 if (time_after(now, deadline))
1670 msecs = jiffies_to_msecs(deadline - now);
1671
4658f79b 1672 tf.ctl |= ATA_SRST;
a9cf5e85 1673 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1674 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1675 rc = -EIO;
1676 reason = "1st FIS failed";
1677 goto fail;
1678 }
1679
1680 /* spec says at least 5us, but be generous and sleep for 1ms */
1681 msleep(1);
1682
1683 /* issue the second D2H Register FIS */
4658f79b 1684 tf.ctl &= ~ATA_SRST;
a9cf5e85 1685 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1686
705e76be 1687 /* wait for link to become ready */
bd17243a 1688 rc = ata_wait_after_reset(link, deadline, check_ready);
9b89391c
TH		 1689 /* link occupied, -ENODEV too is an error */
1690 if (rc) {
1691 reason = "device not ready";
1692 goto fail;
4658f79b 1693 }
9b89391c 1694 *class = ahci_dev_classify(ap);
4658f79b
TH		 1695
1696 DPRINTK("EXIT, class=%u\n", *class);
1697 return 0;
1698
4658f79b 1699 fail:
cc0680a5 1700 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1701 return rc;
1702}
1703
bd17243a
SH		 1704static int ahci_check_ready(struct ata_link *link)
1705{
1706 void __iomem *port_mmio = ahci_port_base(link->ap);
1707 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1708
1709 return ata_check_ready(status);
1710}
1711
1712static int ahci_softreset(struct ata_link *link, unsigned int *class,
1713 unsigned long deadline)
1714{
1715 int pmp = sata_srst_pmp(link);
1716
1717 DPRINTK("ENTER\n");
1718
1719 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1720}
1721
1722static int ahci_sb600_check_ready(struct ata_link *link)
1723{
1724 void __iomem *port_mmio = ahci_port_base(link->ap);
1725 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1726 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1727
1728 /*
1729 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1730 * which can save timeout delay.
1731 */
1732 if (irq_status & PORT_IRQ_BAD_PMP)
1733 return -EIO;
1734
1735 return ata_check_ready(status);
1736}
1737
1738static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1739 unsigned long deadline)
1740{
1741 struct ata_port *ap = link->ap;
1742 void __iomem *port_mmio = ahci_port_base(ap);
1743 int pmp = sata_srst_pmp(link);
1744 int rc;
1745 u32 irq_sts;
1746
1747 DPRINTK("ENTER\n");
1748
1749 rc = ahci_do_softreset(link, class, pmp, deadline,
1750 ahci_sb600_check_ready);
1751
1752 /*
1753 * Soft reset fails on some ATI chips with IPMS set when PMP
1754 * is enabled but SATA HDD/ODD is connected to SATA port,
1755 * do soft reset again to port 0.
1756 */
1757 if (rc == -EIO) {
1758 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1759 if (irq_sts & PORT_IRQ_BAD_PMP) {
1760 ata_link_printk(link, KERN_WARNING,
1761 "failed due to HW bug, retry pmp=0\n");
1762 rc = ahci_do_softreset(link, class, 0, deadline,
1763 ahci_check_ready);
1764 }
1765 }
1766
1767 return rc;
1768}
1769
cc0680a5 1770static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1771 unsigned long deadline)
422b7595 1772{
9dadd45b 1773 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1774 struct ata_port *ap = link->ap;
4296971d
TH		 1775 struct ahci_port_priv *pp = ap->private_data;
1776 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1777 struct ata_taskfile tf;
9dadd45b 1778 bool online;
4bd00f6a
TH		 1779 int rc;
1780
1781 DPRINTK("ENTER\n");
1da177e4 1782
4447d351 1783 ahci_stop_engine(ap);
4296971d
TH		 1784
1785 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1786 ata_tf_init(link->device, &tf);
dfd7a3db 1787 tf.command = 0x80;
9977126c 1788 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1789
9dadd45b
TH		 1790 rc = sata_link_hardreset(link, timing, deadline, &online,
1791 ahci_check_ready);
4296971d 1792
4447d351 1793 ahci_start_engine(ap);
1da177e4 1794
9dadd45b 1795 if (online)
4bd00f6a 1796 *class = ahci_dev_classify(ap);
1da177e4 1797
4bd00f6a
TH		 1798 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1799 return rc;
1800}
1801
cc0680a5 1802static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1803 unsigned long deadline)
ad616ffb 1804{
cc0680a5 1805 struct ata_port *ap = link->ap;
9dadd45b 1806 bool online;
ad616ffb
TH		 1807 int rc;
1808
1809 DPRINTK("ENTER\n");
1810
4447d351 1811 ahci_stop_engine(ap);
ad616ffb 1812
cc0680a5 1813 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1814 deadline, &online, NULL);
ad616ffb 1815
4447d351 1816 ahci_start_engine(ap);
ad616ffb
TH		 1817
1818 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1819
1820 /* vt8251 doesn't clear BSY on signature FIS reception,
1821 * request follow-up softreset.
1822 */
9dadd45b 1823 return online ? -EAGAIN : rc;
ad616ffb
TH		 1824}
1825
edc93052
TH		 1826static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1827 unsigned long deadline)
1828{
1829 struct ata_port *ap = link->ap;
1830 struct ahci_port_priv *pp = ap->private_data;
1831 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1832 struct ata_taskfile tf;
9dadd45b 1833 bool online;
edc93052
TH		 1834 int rc;
1835
1836 ahci_stop_engine(ap);
1837
1838 /* clear D2H reception area to properly wait for D2H FIS */
1839 ata_tf_init(link->device, &tf);
1840 tf.command = 0x80;
1841 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1842
1843 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1844 deadline, &online, NULL);
edc93052
TH		 1845
1846 ahci_start_engine(ap);
1847
edc93052
TH		 1848 /* The pseudo configuration device on SIMG4726 attached to
1849 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1850 * hardreset if no device is attached to the first downstream
1851 * port && the pseudo device locks up on SRST w/ PMP==0. To
1852 * work around this, wait for !BSY only briefly. If BSY isn't
1853 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1854 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1855 *
1856 * Wait for two seconds. Devices attached to downstream port
1857 * which can't process the following IDENTIFY after this will
1858 * have to be reset again. For most cases, this should
1859 * suffice while making probing snappish enough.
1860 */
9dadd45b
TH		 1861 if (online) {
1862 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1863 ahci_check_ready);
1864 if (rc)
1865 ahci_kick_engine(ap, 0);
1866 }
9dadd45b 1867 return rc;
edc93052
TH		 1868}
1869
cc0680a5 1870static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1871{
cc0680a5 1872 struct ata_port *ap = link->ap;
4447d351 1873 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1874 u32 new_tmp, tmp;
1875
203c75b8 1876 ata_std_postreset(link, class);
02eaa666
JG		 1877
1878 /* Make sure port's ATAPI bit is set appropriately */
1879 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1880 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1881 new_tmp |= PORT_CMD_ATAPI;
1882 else
1883 new_tmp &= ~PORT_CMD_ATAPI;
1884 if (new_tmp != tmp) {
1885 writel(new_tmp, port_mmio + PORT_CMD);
1886 readl(port_mmio + PORT_CMD); /* flush */
1887 }
1da177e4
LT		 1888}
1889
12fad3f9 1890static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1891{
cedc9a47 1892 struct scatterlist *sg;
ff2aeb1e
TH		 1893 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1894 unsigned int si;
1da177e4
LT		 1895
1896 VPRINTK("ENTER\n");
1897
1898 /*
1899 * Next, the S/G list.
1900 */
ff2aeb1e 1901 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1902 dma_addr_t addr = sg_dma_address(sg);
1903 u32 sg_len = sg_dma_len(sg);
1904
ff2aeb1e
TH		 1905 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1906 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1907 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1908 }
828d09de 1909
ff2aeb1e 1910 return si;
1da177e4
LT		 1911}
1912
1913static void ahci_qc_prep(struct ata_queued_cmd *qc)
1914{
a0ea7328
JG		 1915 struct ata_port *ap = qc->ap;
1916 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1917 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1918 void *cmd_tbl;
1da177e4
LT		 1919 u32 opts;
1920 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1921 unsigned int n_elem;
1da177e4 1922
1da177e4
LT		 1923 /*
1924 * Fill in command table information. First, the header,
1925 * a SATA Register - Host to Device command FIS.
1926 */
12fad3f9
TH		 1927 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1928
7d50b60b 1929 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1930 if (is_atapi) {
12fad3f9
TH		 1931 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1932 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1933 }
1da177e4 1934
cc9278ed
TH		 1935 n_elem = 0;
1936 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1937 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1938
cc9278ed
TH		 1939 /*
1940 * Fill in command slot information.
1941 */
7d50b60b 1942 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1943 if (qc->tf.flags & ATA_TFLAG_WRITE)
1944 opts |= AHCI_CMD_WRITE;
1945 if (is_atapi)
4b10e559 1946 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1947
12fad3f9 1948 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1949}
1950
78cd52d0 1951static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1952{
417a1a6d 1953 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1954 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1955 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1956 struct ata_link *link = NULL;
1957 struct ata_queued_cmd *active_qc;
1958 struct ata_eh_info *active_ehi;
78cd52d0 1959 u32 serror;
1da177e4 1960
7d50b60b 1961 /* determine active link */
1eca4365 1962 ata_for_each_link(link, ap, EDGE)
7d50b60b
TH		 1963 if (ata_link_active(link))
1964 break;
1965 if (!link)
1966 link = &ap->link;
1967
1968 active_qc = ata_qc_from_tag(ap, link->active_tag);
1969 active_ehi = &link->eh_info;
1970
1971 /* record irq stat */
1972 ata_ehi_clear_desc(host_ehi);
1973 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1974
78cd52d0 1975 /* AHCI needs SError cleared; otherwise, it might lock up */
82ef04fb
TH		 1976 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1977 ahci_scr_write(&ap->link, SCR_ERROR, serror);
7d50b60b 1978 host_ehi->serror |= serror;
78cd52d0 1979
41669553 1980 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1981 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1982 irq_stat &= ~PORT_IRQ_IF_ERR;
1983
55a61604 1984 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1985 /* If qc is active, charge it; otherwise, the active
1986 * link. There's no active qc on NCQ errors. It will
1987 * be determined by EH by reading log page 10h.
1988 */
1989 if (active_qc)
1990 active_qc->err_mask |= AC_ERR_DEV;
1991 else
1992 active_ehi->err_mask |= AC_ERR_DEV;
1993
417a1a6d 1994 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1995 host_ehi->serror &= ~SERR_INTERNAL;
1996 }
1997
1998 if (irq_stat & PORT_IRQ_UNK_FIS) {
1999 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2000
2001 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2002 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 2003 ata_ehi_push_desc(active_ehi,
2004 "unknown FIS %08x %08x %08x %08x" ,
2005 unk[0], unk[1], unk[2], unk[3]);
2006 }
2007
071f44b1 2008 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 2009 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2010 active_ehi->action |= ATA_EH_RESET;
7d50b60b 2011 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 2012 }
78cd52d0
TH		 2013
2014 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 2015 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 2016 host_ehi->action |= ATA_EH_RESET;
7d50b60b 2017 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 2018 }
2019
78cd52d0 2020 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 2021 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 2022 host_ehi->action |= ATA_EH_RESET;
7d50b60b 2023 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 2024 }
1da177e4 2025
78cd52d0 2026 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 2027 ata_ehi_hotplugged(host_ehi);
2028 ata_ehi_push_desc(host_ehi, "%s",
2029 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 2030 "connection status changed" : "PHY RDY changed");
2031 }
2032
78cd52d0 2033 /* okay, let's hand over to EH */
a72ec4ce 2034
78cd52d0
TH		 2035 if (irq_stat & PORT_IRQ_FREEZE)
2036 ata_port_freeze(ap);
2037 else
2038 ata_port_abort(ap);
1da177e4
LT		 2039}
2040
df69c9c5 2041static void ahci_port_intr(struct ata_port *ap)
1da177e4 2042{
350756f6 2043 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 2044 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 2045 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 2046 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 2047 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 2048 u32 status, qc_active;
459ad688 2049 int rc;
1da177e4
LT		 2050
2051 status = readl(port_mmio + PORT_IRQ_STAT);
2052 writel(status, port_mmio + PORT_IRQ_STAT);
2053
b06ce3e5
TH		 2054 /* ignore BAD_PMP while resetting */
2055 if (unlikely(resetting))
2056 status &= ~PORT_IRQ_BAD_PMP;
2057
31556594
KCA		 2058 /* If we are getting PhyRdy, this is
2059 * just a power state change, we should
2060 * clear out this, plus the PhyRdy/Comm
2061 * Wake bits from Serror
2062 */
2063 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2064 (status & PORT_IRQ_PHYRDY)) {
2065 status &= ~PORT_IRQ_PHYRDY;
82ef04fb 2066 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 2067 }
2068
78cd52d0
TH		 2069 if (unlikely(status & PORT_IRQ_ERROR)) {
2070 ahci_error_intr(ap, status);
2071 return;
1da177e4
LT		 2072 }
2073
2f294968 2074 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2075 /* If SNotification is available, leave notification
2076 * handling to sata_async_notification(). If not,
2077 * emulate it by snooping SDB FIS RX area.
2078 *
2079 * Snooping FIS RX area is probably cheaper than
2080 * poking SNotification but some constrollers which
2081 * implement SNotification, ICH9 for example, don't
2082 * store AN SDB FIS into receive area.
2f294968 2083 */
5f226c6b 2084 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2085 sata_async_notification(ap);
5f226c6b
TH		 2086 else {
2087 /* If the 'N' bit in word 0 of the FIS is set,
2088 * we just received asynchronous notification.
2089 * Tell libata about it.
2090 */
2091 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2092 u32 f0 = le32_to_cpu(f[0]);
2093
2094 if (f0 & (1 << 15))
2095 sata_async_notification(ap);
2096 }
2f294968
KCA		 2097 }
2098
7d50b60b
TH		 2099 /* pp->active_link is valid iff any command is in flight */
2100 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2101 qc_active = readl(port_mmio + PORT_SCR_ACT);
2102 else
2103 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2104
79f97dad 2105 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2106
459ad688
TH		 2107 /* while resetting, invalid completions are expected */
2108 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2109 ehi->err_mask |= AC_ERR_HSM;
cf480626 2110 ehi->action |= ATA_EH_RESET;
12fad3f9 2111 ata_port_freeze(ap);
1da177e4 2112 }
1da177e4
LT		 2113}
2114
7d12e780 2115static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2116{
cca3974e 2117 struct ata_host *host = dev_instance;
1da177e4
LT		 2118 struct ahci_host_priv *hpriv;
2119 unsigned int i, handled = 0;
ea6ba10b 2120 void __iomem *mmio;
d28f87aa 2121 u32 irq_stat, irq_masked;
1da177e4
LT		 2122
2123 VPRINTK("ENTER\n");
2124
cca3974e 2125 hpriv = host->private_data;
0d5ff566 2126 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2127
2128 /* sigh. 0xffffffff is a valid return from h/w */
2129 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2130 if (!irq_stat)
2131 return IRQ_NONE;
2132
d28f87aa
TH		 2133 irq_masked = irq_stat & hpriv->port_map;
2134
2dcb407e 2135 spin_lock(&host->lock);
1da177e4 2136
2dcb407e 2137 for (i = 0; i < host->n_ports; i++) {
1da177e4 2138 struct ata_port *ap;
1da177e4 2139
d28f87aa 2140 if (!(irq_masked & (1 << i)))
67846b30
JG		 2141 continue;
2142
cca3974e 2143 ap = host->ports[i];
67846b30 2144 if (ap) {
df69c9c5 2145 ahci_port_intr(ap);
67846b30
JG		 2146 VPRINTK("port %u\n", i);
2147 } else {
2148 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2149 if (ata_ratelimit())
cca3974e 2150 dev_printk(KERN_WARNING, host->dev,
a9524a76 2151 "interrupt on disabled port %u\n", i);
1da177e4 2152 }
67846b30 2153
1da177e4
LT		 2154 handled = 1;
2155 }
2156
d28f87aa
TH		 2157 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2158 * it should be cleared after all the port events are cleared;
2159 * otherwise, it will raise a spurious interrupt after each
2160 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2161 * information.
2162 *
2163 * Also, use the unmasked value to clear interrupt as spurious
2164 * pending event on a dummy port might cause screaming IRQ.
2165 */
ea0c62f7
TH		 2166 writel(irq_stat, mmio + HOST_IRQ_STAT);
2167
cca3974e 2168 spin_unlock(&host->lock);
1da177e4
LT		 2169
2170 VPRINTK("EXIT\n");
2171
2172 return IRQ_RETVAL(handled);
2173}
2174
9a3d9eb0 2175static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2176{
2177 struct ata_port *ap = qc->ap;
4447d351 2178 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2179 struct ahci_port_priv *pp = ap->private_data;
2180
2181 /* Keep track of the currently active link. It will be used
2182 * in completion path to determine whether NCQ phase is in
2183 * progress.
2184 */
2185 pp->active_link = qc->dev->link;
1da177e4 2186
12fad3f9
TH		 2187 if (qc->tf.protocol == ATA_PROT_NCQ)
2188 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2189 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2190
18f7ba4c
KCA		 2191 ahci_sw_activity(qc->dev->link);
2192
1da177e4
LT		 2193 return 0;
2194}
2195
4c9bf4e7
TH		 2196static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2197{
2198 struct ahci_port_priv *pp = qc->ap->private_data;
2199 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2200
2201 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2202 return true;
2203}
2204
78cd52d0
TH		 2205static void ahci_freeze(struct ata_port *ap)
2206{
4447d351 2207 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2208
2209 /* turn IRQ off */
2210 writel(0, port_mmio + PORT_IRQ_MASK);
2211}
2212
2213static void ahci_thaw(struct ata_port *ap)
2214{
0d5ff566 2215 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2216 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2217 u32 tmp;
a7384925 2218 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2219
2220 /* clear IRQ */
2221 tmp = readl(port_mmio + PORT_IRQ_STAT);
2222 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2223 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2224
1c954a4d
TH		 2225 /* turn IRQ back on */
2226 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2227}
2228
2229static void ahci_error_handler(struct ata_port *ap)
2230{
b51e9e5d 2231 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2232 /* restart engine */
4447d351
TH		 2233 ahci_stop_engine(ap);
2234 ahci_start_engine(ap);
78cd52d0
TH		 2235 }
2236
a1efdaba 2237 sata_pmp_error_handler(ap);
edc93052
TH		 2238}
2239
78cd52d0
TH		 2240static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2241{
2242 struct ata_port *ap = qc->ap;
2243
d2e75dff
TH		 2244 /* make DMA engine forget about the failed command */
2245 if (qc->flags & ATA_QCFLAG_FAILED)
2246 ahci_kick_engine(ap, 1);
78cd52d0
TH		 2247}
2248
7d50b60b
TH		 2249static void ahci_pmp_attach(struct ata_port *ap)
2250{
2251 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2252 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2253 u32 cmd;
2254
2255 cmd = readl(port_mmio + PORT_CMD);
2256 cmd |= PORT_CMD_PMP;
2257 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2258
2259 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2260 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2261}
2262
2263static void ahci_pmp_detach(struct ata_port *ap)
2264{
2265 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2266 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2267 u32 cmd;
2268
2269 cmd = readl(port_mmio + PORT_CMD);
2270 cmd &= ~PORT_CMD_PMP;
2271 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2272
2273 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2274 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2275}
2276
028a2596
AD		 2277static int ahci_port_resume(struct ata_port *ap)
2278{
2279 ahci_power_up(ap);
2280 ahci_start_port(ap);
2281
071f44b1 2282 if (sata_pmp_attached(ap))
7d50b60b
TH		 2283 ahci_pmp_attach(ap);
2284 else
2285 ahci_pmp_detach(ap);
2286
028a2596
AD		 2287 return 0;
2288}
2289
438ac6d5 2290#ifdef CONFIG_PM
c1332875
TH		 2291static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2292{
c1332875
TH		 2293 const char *emsg = NULL;
2294 int rc;
2295
4447d351 2296 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2297 if (rc == 0)
4447d351 2298 ahci_power_down(ap);
8e16f941 2299 else {
c1332875 2300 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2301 ahci_start_port(ap);
c1332875
TH		 2302 }
2303
2304 return rc;
2305}
2306
c1332875
TH		 2307static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2308{
cca3974e 2309 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 2310 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2311 u32 ctl;
2312
3a2d5b70 2313 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2314 /* AHCI spec rev1.1 section 8.3.3:
2315 * Software must disable interrupts prior to requesting a
2316 * transition of the HBA to D3 state.
2317 */
2318 ctl = readl(mmio + HOST_CTL);
2319 ctl &= ~HOST_IRQ_EN;
2320 writel(ctl, mmio + HOST_CTL);
2321 readl(mmio + HOST_CTL); /* flush */
2322 }
2323
2324 return ata_pci_device_suspend(pdev, mesg);
2325}
2326
2327static int ahci_pci_device_resume(struct pci_dev *pdev)
2328{
cca3974e 2329 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2330 int rc;
2331
553c4aa6
TH		 2332 rc = ata_pci_device_do_resume(pdev);
2333 if (rc)
2334 return rc;
c1332875
TH		 2335
2336 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2337 rc = ahci_reset_controller(host);
c1332875
TH		 2338 if (rc)
2339 return rc;
2340
4447d351 2341 ahci_init_controller(host);
c1332875
TH		 2342 }
2343
cca3974e 2344 ata_host_resume(host);
c1332875
TH		 2345
2346 return 0;
2347}
438ac6d5 2348#endif
c1332875 2349
254950cd
TH		 2350static int ahci_port_start(struct ata_port *ap)
2351{
cca3974e 2352 struct device *dev = ap->host->dev;
254950cd 2353 struct ahci_port_priv *pp;
254950cd
TH		 2354 void *mem;
2355 dma_addr_t mem_dma;
254950cd 2356
24dc5f33 2357 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2358 if (!pp)
2359 return -ENOMEM;
254950cd 2360
24dc5f33
TH		 2361 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2362 GFP_KERNEL);
2363 if (!mem)
254950cd 2364 return -ENOMEM;
254950cd
TH		 2365 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2366
2367 /*
2368 * First item in chunk of DMA memory: 32-slot command table,
2369 * 32 bytes each in size
2370 */
2371 pp->cmd_slot = mem;
2372 pp->cmd_slot_dma = mem_dma;
2373
2374 mem += AHCI_CMD_SLOT_SZ;
2375 mem_dma += AHCI_CMD_SLOT_SZ;
2376
2377 /*
2378 * Second item: Received-FIS area
2379 */
2380 pp->rx_fis = mem;
2381 pp->rx_fis_dma = mem_dma;
2382
2383 mem += AHCI_RX_FIS_SZ;
2384 mem_dma += AHCI_RX_FIS_SZ;
2385
2386 /*
2387 * Third item: data area for storing a single command
2388 * and its scatter-gather table
2389 */
2390 pp->cmd_tbl = mem;
2391 pp->cmd_tbl_dma = mem_dma;
2392
a7384925 2393 /*
2dcb407e
JG		 2394 * Save off initial list of interrupts to be enabled.
2395 * This could be changed later
2396 */
a7384925
KCA		 2397 pp->intr_mask = DEF_PORT_IRQ;
2398
254950cd
TH		 2399 ap->private_data = pp;
2400
df69c9c5
JG		 2401 /* engage engines, captain */
2402 return ahci_port_resume(ap);
254950cd
TH		 2403}
2404
2405static void ahci_port_stop(struct ata_port *ap)
2406{
0be0aa98
TH		 2407 const char *emsg = NULL;
2408 int rc;
254950cd 2409
0be0aa98 2410 /* de-initialize port */
4447d351 2411 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2412 if (rc)
2413 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2414}
2415
4447d351 2416static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2417{
1da177e4 2418 int rc;
1da177e4 2419
1da177e4 2420 if (using_dac &&
6a35528a
YH		 2421 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2422 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 2423 if (rc) {
284901a9 2424 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2425 if (rc) {
a9524a76
JG		 2426 dev_printk(KERN_ERR, &pdev->dev,
2427 "64-bit DMA enable failed\n");
1da177e4
LT		 2428 return rc;
2429 }
2430 }
1da177e4 2431 } else {
284901a9 2432 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2433 if (rc) {
a9524a76
JG		 2434 dev_printk(KERN_ERR, &pdev->dev,
2435 "32-bit DMA enable failed\n");
1da177e4
LT		 2436 return rc;
2437 }
284901a9 2438 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2439 if (rc) {
a9524a76
JG		 2440 dev_printk(KERN_ERR, &pdev->dev,
2441 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2442 return rc;
2443 }
2444 }
1da177e4
LT		 2445 return 0;
2446}
2447
4447d351 2448static void ahci_print_info(struct ata_host *host)
1da177e4 2449{
4447d351
TH		 2450 struct ahci_host_priv *hpriv = host->private_data;
2451 struct pci_dev *pdev = to_pci_dev(host->dev);
2452 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2453 u32 vers, cap, impl, speed;
2454 const char *speed_s;
2455 u16 cc;
2456 const char *scc_s;
2457
2458 vers = readl(mmio + HOST_VERSION);
2459 cap = hpriv->cap;
2460 impl = hpriv->port_map;
2461
2462 speed = (cap >> 20) & 0xf;
2463 if (speed == 1)
2464 speed_s = "1.5";
2465 else if (speed == 2)
2466 speed_s = "3";
8522ee25
SH		 2467 else if (speed == 3)
2468 speed_s = "6";
1da177e4
LT		 2469 else
2470 speed_s = "?";
2471
2472 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2473 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2474 scc_s = "IDE";
c9f89475 2475 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2476 scc_s = "SATA";
c9f89475 2477 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2478 scc_s = "RAID";
2479 else
2480 scc_s = "unknown";
2481
a9524a76
JG		 2482 dev_printk(KERN_INFO, &pdev->dev,
2483 "AHCI %02x%02x.%02x%02x "
1da177e4 2484 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2485 ,
1da177e4 2486
2dcb407e
JG		 2487 (vers >> 24) & 0xff,
2488 (vers >> 16) & 0xff,
2489 (vers >> 8) & 0xff,
2490 vers & 0xff,
1da177e4
LT		 2491
2492 ((cap >> 8) & 0x1f) + 1,
2493 (cap & 0x1f) + 1,
2494 speed_s,
2495 impl,
2496 scc_s);
2497
a9524a76
JG		 2498 dev_printk(KERN_INFO, &pdev->dev,
2499 "flags: "
203ef6c4 2500 "%s%s%s%s%s%s%s"
18f7ba4c
KCA		 2501 "%s%s%s%s%s%s%s"
2502 "%s\n"
2dcb407e 2503 ,
1da177e4
LT		 2504
2505 cap & (1 << 31) ? "64bit " : "",
2506 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2507 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2508 cap & (1 << 28) ? "ilck " : "",
2509 cap & (1 << 27) ? "stag " : "",
2510 cap & (1 << 26) ? "pm " : "",
2511 cap & (1 << 25) ? "led " : "",
2512
2513 cap & (1 << 24) ? "clo " : "",
2514 cap & (1 << 19) ? "nz " : "",
2515 cap & (1 << 18) ? "only " : "",
2516 cap & (1 << 17) ? "pmp " : "",
2517 cap & (1 << 15) ? "pio " : "",
2518 cap & (1 << 14) ? "slum " : "",
18f7ba4c
KCA		 2519 cap & (1 << 13) ? "part " : "",
2520 cap & (1 << 6) ? "ems ": ""
1da177e4
LT		 2521 );
2522}
2523
edc93052
TH		 2524/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2525 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2526 * support PMP and the 4726 either directly exports the device
2527 * attached to the first downstream port or acts as a hardware storage
2528 * controller and emulate a single ATA device (can be RAID 0/1 or some
2529 * other configuration).
2530 *
2531 * When there's no device attached to the first downstream port of the
2532 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2533 * configure the 4726. However, ATA emulation of the device is very
2534 * lame. It doesn't send signature D2H Reg FIS after the initial
2535 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2536 *
2537 * The following function works around the problem by always using
2538 * hardreset on the port and not depending on receiving signature FIS
2539 * afterward. If signature FIS isn't received soon, ATA class is
2540 * assumed without follow-up softreset.
2541 */
2542static void ahci_p5wdh_workaround(struct ata_host *host)
2543{
2544 static struct dmi_system_id sysids[] = {
2545 {
2546 .ident = "P5W DH Deluxe",
2547 .matches = {
2548 DMI_MATCH(DMI_SYS_VENDOR,
2549 "ASUSTEK COMPUTER INC"),
2550 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2551 },
2552 },
2553 { }
2554 };
2555 struct pci_dev *pdev = to_pci_dev(host->dev);
2556
2557 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2558 dmi_check_system(sysids)) {
2559 struct ata_port *ap = host->ports[1];
2560
2561 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2562 "Deluxe on-board SIMG4726 workaround\n");
2563
2564 ap->ops = &ahci_p5wdh_ops;
2565 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2566 }
2567}
2568
1fd68434
RW		 2569static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2570{
2571 static const struct dmi_system_id broken_systems[] = {
2572 {
2573 .ident = "HP Compaq nx6310",
2574 .matches = {
2575 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2576 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2577 },
2578 /* PCI slot number of the controller */
2579 .driver_data = (void *)0x1FUL,
2580 },
d2f9c061
MR		 2581 {
2582 .ident = "HP Compaq 6720s",
2583 .matches = {
2584 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2585 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2586 },
2587 /* PCI slot number of the controller */
2588 .driver_data = (void *)0x1FUL,
2589 },
1fd68434
RW		 2590
2591 { } /* terminate list */
2592 };
2593 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2594
2595 if (dmi) {
2596 unsigned long slot = (unsigned long)dmi->driver_data;
2597 /* apply the quirk only to on-board controllers */
2598 return slot == PCI_SLOT(pdev->devfn);
2599 }
2600
2601 return false;
2602}
2603
24dc5f33 2604static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2605{
2606 static int printed_version;
e297d99e
TH		 2607 unsigned int board_id = ent->driver_data;
2608 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 2609 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2610 struct device *dev = &pdev->dev;
1da177e4 2611 struct ahci_host_priv *hpriv;
4447d351 2612 struct ata_host *host;
837f5f8f 2613 int n_ports, i, rc;
1da177e4
LT		 2614
2615 VPRINTK("ENTER\n");
2616
12fad3f9
TH		 2617 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2618
1da177e4 2619 if (!printed_version++)
a9524a76 2620 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2621
5b66c829
AC		 2622 /* The AHCI driver can only drive the SATA ports, the PATA driver
2623 can drive them all so if both drivers are selected make sure
2624 AHCI stays out of the way */
2625 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2626 return -ENODEV;
2627
4447d351 2628 /* acquire resources */
24dc5f33 2629 rc = pcim_enable_device(pdev);
1da177e4
LT		 2630 if (rc)
2631 return rc;
2632
dea55137
TH		 2633 /* AHCI controllers often implement SFF compatible interface.
2634 * Grab all PCI BARs just in case.
2635 */
2636 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2637 if (rc == -EBUSY)
24dc5f33 2638 pcim_pin_device(pdev);
0d5ff566 2639 if (rc)
24dc5f33 2640 return rc;
1da177e4 2641
c4f7792c
TH		 2642 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2643 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2644 u8 map;
2645
2646 /* ICH6s share the same PCI ID for both piix and ahci
2647 * modes. Enabling ahci mode while MAP indicates
2648 * combined mode is a bad idea. Yield to ata_piix.
2649 */
2650 pci_read_config_byte(pdev, ICH_MAP, &map);
2651 if (map & 0x3) {
2652 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2653 "combined mode, can't enable AHCI mode\n");
2654 return -ENODEV;
2655 }
2656 }
2657
24dc5f33
TH		 2658 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2659 if (!hpriv)
2660 return -ENOMEM;
417a1a6d
TH		 2661 hpriv->flags |= (unsigned long)pi.private_data;
2662
e297d99e
TH		 2663 /* MCP65 revision A1 and A2 can't do MSI */
2664 if (board_id == board_ahci_mcp65 &&
2665 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2666 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2667
e427fe04
SH		 2668 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2669 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2670 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2671
a5bfc471
TH		 2672 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2673 pci_enable_msi(pdev);
1da177e4 2674
4447d351 2675 /* save initial config */
417a1a6d 2676 ahci_save_initial_config(pdev, hpriv);
1da177e4 2677
4447d351 2678 /* prepare host */
274c1fde 2679 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2680 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2681
7d50b60b
TH		 2682 if (hpriv->cap & HOST_CAP_PMP)
2683 pi.flags |= ATA_FLAG_PMP;
2684
18f7ba4c
KCA		 2685 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2686 u8 messages;
2687 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2688 u32 em_loc = readl(mmio + HOST_EM_LOC);
2689 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2690
87943acf 2691 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
18f7ba4c
KCA		 2692
2693 /* we only support LED message type right now */
2694 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2695 /* store em_loc */
2696 hpriv->em_loc = ((em_loc >> 16) * 4);
2697 pi.flags |= ATA_FLAG_EM;
2698 if (!(em_ctl & EM_CTL_ALHD))
2699 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2700 }
2701 }
2702
1fd68434
RW		 2703 if (ahci_broken_system_poweroff(pdev)) {
2704 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2705 dev_info(&pdev->dev,
2706 "quirky BIOS, skipping spindown on poweroff\n");
2707 }
2708
837f5f8f
TH		 2709 /* CAP.NP sometimes indicate the index of the last enabled
2710 * port, at other times, that of the last possible port, so
2711 * determining the maximum port number requires looking at
2712 * both CAP.NP and port_map.
2713 */
2714 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2715
2716 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2717 if (!host)
2718 return -ENOMEM;
2719 host->iomap = pcim_iomap_table(pdev);
2720 host->private_data = hpriv;
2721
f3d7f23f 2722 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 2723 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 2724 else
2725 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 2726
18f7ba4c
KCA		 2727 if (pi.flags & ATA_FLAG_EM)
2728 ahci_reset_em(host);
2729
4447d351 2730 for (i = 0; i < host->n_ports; i++) {
dab632e8 2731 struct ata_port *ap = host->ports[i];
4447d351 2732
cbcdd875
TH		 2733 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2734 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2735 0x100 + ap->port_no * 0x80, "port");
2736
31556594
KCA		 2737 /* set initial link pm policy */
2738 ap->pm_policy = NOT_AVAILABLE;
2739
18f7ba4c
KCA		 2740 /* set enclosure management message type */
2741 if (ap->flags & ATA_FLAG_EM)
2742 ap->em_message_type = ahci_em_messages;
2743
2744
dab632e8 2745 /* disabled/not-implemented port */
350756f6 2746 if (!(hpriv->port_map & (1 << i)))
dab632e8 2747 ap->ops = &ata_dummy_port_ops;
4447d351 2748 }
d447df14 2749
edc93052
TH		 2750 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2751 ahci_p5wdh_workaround(host);
2752
4447d351
TH		 2753 /* initialize adapter */
2754 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2755 if (rc)
24dc5f33 2756 return rc;
1da177e4 2757
4447d351
TH		 2758 rc = ahci_reset_controller(host);
2759 if (rc)
2760 return rc;
1da177e4 2761
4447d351
TH		 2762 ahci_init_controller(host);
2763 ahci_print_info(host);
1da177e4 2764
4447d351
TH		 2765 pci_set_master(pdev);
2766 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2767 &ahci_sht);
907f4678 2768}
1da177e4
LT		 2769
2770static int __init ahci_init(void)
2771{
b7887196 2772 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2773}
2774
1da177e4
LT		 2775static void __exit ahci_exit(void)
2776{
2777 pci_unregister_driver(&ahci_pci_driver);
2778}
2779
2780
2781MODULE_AUTHOR("Jeff Garzik");
2782MODULE_DESCRIPTION("AHCI SATA low-level driver");
2783MODULE_LICENSE("GPL");
2784MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2785MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2786
2787module_init(ahci_init);
2788module_exit(ahci_exit);
Linux kernel - Deliverables
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