[deliverable/linux.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	/* Timer 1-ms Register */
	IMX_TIMER1MS				= 0x00e0,
	/* Port0 PHY Control Register */
	IMX_P0PHYCR				= 0x0178,
	IMX_P0PHYCR_TEST_PDDQ			= 1 << 20,
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_host_stop(struct ata_host *host);

static int imx_sata_enable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret;

	if (imxpriv->no_device)
		return 0;

	if (hpriv->target_pwr) {
		ret = regulator_enable(hpriv->target_pwr);
		if (ret)
			return ret;
	}

	ret = ahci_platform_enable_clks(hpriv);
	if (ret < 0)
		goto disable_regulator;

	if (imxpriv->type == AHCI_IMX6Q) {
		/*
		 * set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07ffffff, and the other one write for setting
		 * the mpll_clk_en.
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
				   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
				   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	usleep_range(1000, 2000);

	return 0;

disable_regulator:
	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);

	return ret;
}

static void imx_sata_disable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	if (imxpriv->no_device)
		return;

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	ahci_platform_disable_clks(hpriv);

	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + IMX_P0PHYCR);
	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
	imx_sata_disable(hpriv);
	imxpriv->no_device = true;
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= ahci_imx_host_stop,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct ahci_host_priv *hpriv;
	struct imx_ahci_priv *imxpriv;
	unsigned int reg_val;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv)
		return -ENOMEM;

	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = (enum ahci_imx_type)of_id->data;
	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		return PTR_ERR(imxpriv->ahb_clk);
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			return PTR_ERR(imxpriv->gpr);
		}
	}

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = imxpriv;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register IMX_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(hpriv->mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, hpriv->mmio + HOST_CAP);
	}
	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	if (ret)
		imx_sata_disable(hpriv);

	return ret;
}

static void ahci_imx_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	imx_sata_disable(hpriv);
}

#ifdef CONFIG_PM_SLEEP
static int imx_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = ahci_platform_suspend_host(dev);
	if (ret)
		return ret;

	imx_sata_disable(hpriv);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	return ahci_platform_resume_host(dev);
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
		.pm = &ahci_imx_pm_ops,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
24a9ad5b SG	32	/* Timer 1-ms Register */
	33	IMX_TIMER1MS = 0x00e0,
	34	/* Port0 PHY Control Register */
	35	IMX_P0PHYCR = 0x0178,
	36	IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
9e54eae2 RZ	37	};
9e54eae2 RZ	38
4a23d179 MV	39	enum ahci_imx_type {
	40	AHCI_IMX53,
	41	AHCI_IMX6Q,
	42	};
	43
9e54eae2 RZ	44	struct imx_ahci_priv {
9e54eae2 RZ	45	struct platform_device *ahci_pdev;
4a23d179	46	enum ahci_imx_type type;
9e54eae2 RZ	47	struct clk *ahb_clk;
9e54eae2 RZ	48	struct regmap *gpr;
8b789d89 RZ	49	bool no_device;
	50	bool first_time;
	51	};
	52
	53	static int ahci_imx_hotplug;
	54	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	55	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	56
90870d79 HG	57	static void ahci_imx_host_stop(struct ata_host *host);
	58
	59	static int imx_sata_enable(struct ahci_host_priv *hpriv)
8403e2ec	60	{
90870d79	61	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8403e2ec MV	62	int ret;
8403e2ec MV	63
90870d79 HG	64	if (imxpriv->no_device)
	65	return 0;
	66
	67	if (hpriv->target_pwr) {
	68	ret = regulator_enable(hpriv->target_pwr);
	69	if (ret)
4a23d179	70	return ret;
4a23d179 MV	71	}
4a23d179 MV	72
90870d79 HG	73	ret = ahci_platform_enable_clks(hpriv);
	74	if (ret < 0)
	75	goto disable_regulator;
8403e2ec	76
4a23d179	77	if (imxpriv->type == AHCI_IMX6Q) {
90870d79 HG	78	/*
	79	* set PHY Paremeters, two steps to configure the GPR13,
	80	* one write for rest of parameters, mask of first write
	81	* is 0x07ffffff, and the other one write for setting
	82	* the mpll_clk_en.
	83	*/
	84	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	85	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	86	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	87	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	88	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	89	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	90	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	91	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	92	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	93	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	94	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
	95	IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB \|
	96	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	97	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	98	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	99	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	100	IMX6Q_GPR13_SATA_TX_ATTEN_9_16 \|
	101	IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB \|
	102	IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
4a23d179 MV	103	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	104	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	105	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	106	}
8403e2ec MV	107
	108	usleep_range(1000, 2000);
	109
	110	return 0;
4a23d179	111
90870d79 HG	112	disable_regulator:
	113	if (hpriv->target_pwr)
	114	regulator_disable(hpriv->target_pwr);
	115
4a23d179	116	return ret;
8403e2ec MV	117	}
8403e2ec MV	118
90870d79	119	static void imx_sata_disable(struct ahci_host_priv *hpriv)
8403e2ec	120	{
90870d79 HG	121	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	122
	123	if (imxpriv->no_device)
	124	return;
8403e2ec	125
4a23d179 MV	126	if (imxpriv->type == AHCI_IMX6Q) {
	127	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	128	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	129	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	130	}
	131
90870d79	132	ahci_platform_disable_clks(hpriv);
4a23d179	133
90870d79 HG	134	if (hpriv->target_pwr)
90870d79 HG	135	regulator_disable(hpriv->target_pwr);
8403e2ec MV	136	}
8403e2ec MV	137
8b789d89 RZ	138	static void ahci_imx_error_handler(struct ata_port *ap)
	139	{
	140	u32 reg_val;
	141	struct ata_device *dev;
	142	struct ata_host *host = dev_get_drvdata(ap->dev);
	143	struct ahci_host_priv *hpriv = host->private_data;
	144	void __iomem *mmio = hpriv->mmio;
90870d79	145	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8b789d89 RZ	146
	147	ahci_error_handler(ap);
	148
	149	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	150	return;
	151
	152	imxpriv->first_time = false;
	153
	154	ata_for_each_dev(dev, &ap->link, ENABLED)
	155	return;
	156	/*
	157	* Disable link to save power. An imx ahci port can't be recovered
	158	* without full reset once the pddq mode is enabled making it
	159	* impossible to use as part of libata LPM.
	160	*/
24a9ad5b SG	161	reg_val = readl(mmio + IMX_P0PHYCR);
24a9ad5b SG	162	writel(reg_val \| IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
90870d79	163	imx_sata_disable(hpriv);
8b789d89 RZ	164	imxpriv->no_device = true;
	165	}
	166
ee4e5a9a	167	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	168	unsigned long deadline)
	169	{
	170	struct ata_port *ap = link->ap;
90870d79 HG	171	struct ata_host *host = dev_get_drvdata(ap->dev);
	172	struct ahci_host_priv *hpriv = host->private_data;
	173	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
4a23d179 MV	174	int ret = -EIO;
	175
	176	if (imxpriv->type == AHCI_IMX53)
	177	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	178	else if (imxpriv->type == AHCI_IMX6Q)
	179	ret = ahci_ops.softreset(link, class, deadline);
	180
	181	return ret;
	182	}
	183
8b789d89	184	static struct ata_port_operations ahci_imx_ops = {
90870d79 HG	185	.inherits = &ahci_ops,
90870d79 HG	186	.host_stop = ahci_imx_host_stop,
8b789d89	187	.error_handler = ahci_imx_error_handler,
4a23d179	188	.softreset = ahci_imx_softreset,
8b789d89 RZ	189	};
	190
	191	static const struct ata_port_info ahci_imx_port_info = {
	192	.flags = AHCI_FLAG_COMMON,
	193	.pio_mask = ATA_PIO4,
	194	.udma_mask = ATA_UDMA6,
	195	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	196	};
9e54eae2 RZ	197
9e54eae2	198	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	199	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	200	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	201	{},
	202	};
	203	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	204
	205	static int imx_ahci_probe(struct platform_device *pdev)
	206	{
	207	struct device *dev = &pdev->dev;
9e54eae2	208	const struct of_device_id *of_id;
90870d79	209	struct ahci_host_priv *hpriv;
9e54eae2	210	struct imx_ahci_priv *imxpriv;
90870d79	211	unsigned int reg_val;
9e54eae2 RZ	212	int ret;
9e54eae2 RZ	213
4a23d179 MV	214	of_id = of_match_device(imx_ahci_of_match, dev);
	215	if (!of_id)
	216	return -EINVAL;
	217
9e54eae2	218	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
90870d79	219	if (!imxpriv)
9e54eae2	220	return -ENOMEM;
9e54eae2	221
8b789d89 RZ	222	imxpriv->no_device = false;
8b789d89 RZ	223	imxpriv->first_time = true;
90870d79	224	imxpriv->type = (enum ahci_imx_type)of_id->data;
9e54eae2 RZ	225	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	226	if (IS_ERR(imxpriv->ahb_clk)) {
	227	dev_err(dev, "can't get ahb clock.\n");
90870d79	228	return PTR_ERR(imxpriv->ahb_clk);
9e54eae2 RZ	229	}
9e54eae2 RZ	230
90870d79 HG	231	if (imxpriv->type == AHCI_IMX6Q) {
	232	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	233	"fsl,imx6q-iomuxc-gpr");
	234	if (IS_ERR(imxpriv->gpr)) {
	235	dev_err(dev,
	236	"failed to find fsl,imx6q-iomux-gpr regmap\n");
	237	return PTR_ERR(imxpriv->gpr);
4a23d179 MV	238	}
	239	}
	240
90870d79 HG	241	hpriv = ahci_platform_get_resources(pdev);
	242	if (IS_ERR(hpriv))
	243	return PTR_ERR(hpriv);
	244
	245	hpriv->plat_data = imxpriv;
9e54eae2	246
90870d79 HG	247	ret = imx_sata_enable(hpriv);
	248	if (ret)
	249	return ret;
9e54eae2	250
90870d79 HG	251	/*
90870d79 HG	252	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
24a9ad5b	253	* and IP vendor specific register IMX_TIMER1MS.
90870d79 HG	254	* Configure CAP_SSS (support stagered spin up).
	255	* Implement the port0.
	256	* Get the ahb clock rate, and configure the TIMER1MS register.
	257	*/
	258	reg_val = readl(hpriv->mmio + HOST_CAP);
	259	if (!(reg_val & HOST_CAP_SSS)) {
	260	reg_val \|= HOST_CAP_SSS;
	261	writel(reg_val, hpriv->mmio + HOST_CAP);
	262	}
	263	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	264	if (!(reg_val & 0x1)) {
	265	reg_val \|= 0x1;
	266	writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
9e54eae2 RZ	267	}
9e54eae2 RZ	268
90870d79	269	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
24a9ad5b	270	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
9e54eae2	271
90870d79 HG	272	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	273	if (ret)
	274	imx_sata_disable(hpriv);
9e54eae2	275
90870d79 HG	276	return ret;
90870d79 HG	277	}
4a23d179	278
90870d79 HG	279	static void ahci_imx_host_stop(struct ata_host *host)
	280	{
	281	struct ahci_host_priv *hpriv = host->private_data;
8403e2ec	282
90870d79 HG	283	imx_sata_disable(hpriv);
90870d79 HG	284	}
9e54eae2	285
46ce6b74	286	#ifdef CONFIG_PM_SLEEP
90870d79 HG	287	static int imx_ahci_suspend(struct device *dev)
	288	{
	289	struct ata_host *host = dev_get_drvdata(dev);
	290	struct ahci_host_priv *hpriv = host->private_data;
	291	int ret;
9e54eae2	292
90870d79 HG	293	ret = ahci_platform_suspend_host(dev);
90870d79 HG	294	if (ret)
9e54eae2	295	return ret;
90870d79 HG	296
90870d79 HG	297	imx_sata_disable(hpriv);
9e54eae2 RZ	298
	299	return 0;
	300	}
	301
90870d79	302	static int imx_ahci_resume(struct device *dev)
9e54eae2	303	{
90870d79 HG	304	struct ata_host *host = dev_get_drvdata(dev);
	305	struct ahci_host_priv *hpriv = host->private_data;
	306	int ret;
9e54eae2	307
90870d79 HG	308	ret = imx_sata_enable(hpriv);
	309	if (ret)
	310	return ret;
	311
	312	return ahci_platform_resume_host(dev);
9e54eae2	313	}
46ce6b74	314	#endif
9e54eae2	315
90870d79 HG	316	static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
90870d79 HG	317
9e54eae2 RZ	318	static struct platform_driver imx_ahci_driver = {
9e54eae2 RZ	319	.probe = imx_ahci_probe,
90870d79	320	.remove = ata_platform_remove_one,
9e54eae2 RZ	321	.driver = {
	322	.name = "ahci-imx",
	323	.owner = THIS_MODULE,
	324	.of_match_table = imx_ahci_of_match,
90870d79	325	.pm = &ahci_imx_pm_ops,
9e54eae2 RZ	326	},
	327	};
	328	module_platform_driver(imx_ahci_driver);
	329
	330	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	331	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	332	MODULE_LICENSE("GPL");
	333	MODULE_ALIAS("ahci:imx");