[deliverable/linux.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	/* Timer 1-ms Register */
	IMX_TIMER1MS				= 0x00e0,
	/* Port0 PHY Control Register */
	IMX_P0PHYCR				= 0x0178,
	IMX_P0PHYCR_TEST_PDDQ			= 1 << 20,
	IMX_P0PHYCR_CR_READ			= 1 << 19,
	IMX_P0PHYCR_CR_WRITE			= 1 << 18,
	IMX_P0PHYCR_CR_CAP_DATA			= 1 << 17,
	IMX_P0PHYCR_CR_CAP_ADDR			= 1 << 16,
	/* Port0 PHY Status Register */
	IMX_P0PHYSR				= 0x017c,
	IMX_P0PHYSR_CR_ACK			= 1 << 18,
	IMX_P0PHYSR_CR_DATA_OUT			= 0xffff << 0,
	/* Lane0 Output Status Register */
	IMX_LANE0_OUT_STAT			= 0x2003,
	IMX_LANE0_OUT_STAT_RX_PLL_STATE		= 1 << 1,
	/* Clock Reset Register */
	IMX_CLOCK_RESET				= 0x7f3f,
	IMX_CLOCK_RESET_RESET			= 1 << 0,
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
	u32 phy_params;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_host_stop(struct ata_host *host);

static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
{
	int timeout = 10;
	u32 crval;
	u32 srval;

	/* Assert or deassert the bit */
	crval = readl(mmio + IMX_P0PHYCR);
	if (assert)
		crval |= bit;
	else
		crval &= ~bit;
	writel(crval, mmio + IMX_P0PHYCR);

	/* Wait for the cr_ack signal */
	do {
		srval = readl(mmio + IMX_P0PHYSR);
		if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
			break;
		usleep_range(100, 200);
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
{
	u32 crval = addr;
	int ret;

	/* Supply the address on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_addr signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_addr */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_phy_reg_write(u16 val, void __iomem *mmio)
{
	u32 crval = val;
	int ret;

	/* Supply the data on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_data signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_data */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	if (ret)
		return ret;

	if (val & IMX_CLOCK_RESET_RESET) {
		/*
		 * In case we're resetting the phy, it's unable to acknowledge,
		 * so we return immediately here.
		 */
		crval |= IMX_P0PHYCR_CR_WRITE;
		writel(crval, mmio + IMX_P0PHYCR);
		goto out;
	}

	/* Assert the cr_write signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
	if (ret)
		return ret;

	/* Deassert cr_write */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
	if (ret)
		return ret;

out:
	return 0;
}

static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
{
	int ret;

	/* Assert the cr_read signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
	if (ret)
		return ret;

	/* Capture the data from cr_data_out[] */
	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;

	/* Deassert cr_read */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
{
	void __iomem *mmio = hpriv->mmio;
	int timeout = 10;
	u16 val;
	int ret;

	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
	if (ret)
		return ret;
	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
	if (ret)
		return ret;

	/* Wait for PHY RX_PLL to be stable */
	do {
		usleep_range(100, 200);
		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
		if (ret)
			return ret;
		ret = imx_phy_reg_read(&val, mmio);
		if (ret)
			return ret;
		if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
			break;
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_sata_enable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	struct device *dev = &imxpriv->ahci_pdev->dev;
	int ret;

	if (imxpriv->no_device)
		return 0;

	if (hpriv->target_pwr) {
		ret = regulator_enable(hpriv->target_pwr);
		if (ret)
			return ret;
	}

	ret = ahci_platform_enable_clks(hpriv);
	if (ret < 0)
		goto disable_regulator;

	if (imxpriv->type == AHCI_IMX6Q) {
		/*
		 * set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07ffffff, and the other one write for setting
		 * the mpll_clk_en.
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   imxpriv->phy_params);
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);

		usleep_range(100, 200);

		ret = imx_sata_phy_reset(hpriv);
		if (ret) {
			dev_err(dev, "failed to reset phy: %d\n", ret);
			goto disable_regulator;
		}
	}

	usleep_range(1000, 2000);

	return 0;

disable_regulator:
	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);

	return ret;
}

static void imx_sata_disable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	if (imxpriv->no_device)
		return;

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	ahci_platform_disable_clks(hpriv);

	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + IMX_P0PHYCR);
	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
	imx_sata_disable(hpriv);
	imxpriv->no_device = true;
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= ahci_imx_host_stop,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

struct reg_value {
	u32 of_value;
	u32 reg_value;
};

struct reg_property {
	const char *name;
	const struct reg_value *values;
	size_t num_values;
	u32 def_value;
};

static const struct reg_value gpr13_tx_level[] = {
	{  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
	{  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
	{  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
	{  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
	{  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
	{  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
	{  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
	{ 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
	{ 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
	{ 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
	{ 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
	{ 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
	{ 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
	{ 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
	{ 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
	{ 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
	{ 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
	{ 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
	{ 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
	{ 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
	{ 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
	{ 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
	{ 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
	{ 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
	{ 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
	{ 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
	{ 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
	{ 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
	{ 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
	{ 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
	{ 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
	{ 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
};

static const struct reg_value gpr13_tx_boost[] = {
	{    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
	{  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
	{  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
	{ 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
	{ 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
	{ 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
	{ 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
	{ 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
	{ 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
	{ 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
	{ 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
	{ 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
	{ 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
	{ 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
	{ 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
	{ 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
};

static const struct reg_value gpr13_tx_atten[] = {
	{  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
	{  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
	{ 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
	{ 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
	{ 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
	{ 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
};

static const struct reg_value gpr13_rx_eq[] = {
	{  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
	{ 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
	{ 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
	{ 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
	{ 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
	{ 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
	{ 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
	{ 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
};

static const struct reg_property gpr13_props[] = {
	{
		.name = "fsl,transmit-level-mV",
		.values = gpr13_tx_level,
		.num_values = ARRAY_SIZE(gpr13_tx_level),
		.def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
	}, {
		.name = "fsl,transmit-boost-mdB",
		.values = gpr13_tx_boost,
		.num_values = ARRAY_SIZE(gpr13_tx_boost),
		.def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
	}, {
		.name = "fsl,transmit-atten-16ths",
		.values = gpr13_tx_atten,
		.num_values = ARRAY_SIZE(gpr13_tx_atten),
		.def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
	}, {
		.name = "fsl,receive-eq-mdB",
		.values = gpr13_rx_eq,
		.num_values = ARRAY_SIZE(gpr13_rx_eq),
		.def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
	},
};

static u32 imx_ahci_parse_props(struct device *dev,
				const struct reg_property *prop, size_t num)
{
	struct device_node *np = dev->of_node;
	u32 reg_value = 0;
	int i, j;

	for (i = 0; i < num; i++, prop++) {
		u32 of_val;

		if (of_property_read_u32(np, prop->name, &of_val)) {
			dev_info(dev, "%s not specified, using %08x\n",
				prop->name, prop->def_value);
			reg_value |= prop->def_value;
			continue;
		}

		for (j = 0; j < prop->num_values; j++) {
			if (prop->values[j].of_value == of_val) {
				dev_info(dev, "%s value %u, using %08x\n",
					prop->name, of_val, prop->values[j].reg_value);
				reg_value |= prop->values[j].reg_value;
				break;
			}
		}

		if (j == prop->num_values) {
			dev_err(dev, "DT property %s is not a valid value\n",
				prop->name);
			reg_value |= prop->def_value;
		}
	}

	return reg_value;
}

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct ahci_host_priv *hpriv;
	struct imx_ahci_priv *imxpriv;
	unsigned int reg_val;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv)
		return -ENOMEM;

	imxpriv->ahci_pdev = pdev;
	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = (enum ahci_imx_type)of_id->data;
	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		return PTR_ERR(imxpriv->ahb_clk);
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		u32 reg_value;

		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			return PTR_ERR(imxpriv->gpr);
		}

		reg_value = imx_ahci_parse_props(dev, gpr13_props,
						 ARRAY_SIZE(gpr13_props));

		imxpriv->phy_params =
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   reg_value;
	}

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = imxpriv;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register IMX_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(hpriv->mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, hpriv->mmio + HOST_CAP);
	}
	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
				      0, 0, 0);
	if (ret)
		imx_sata_disable(hpriv);

	return ret;
}

static void ahci_imx_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	imx_sata_disable(hpriv);
}

#ifdef CONFIG_PM_SLEEP
static int imx_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = ahci_platform_suspend_host(dev);
	if (ret)
		return ret;

	imx_sata_disable(hpriv);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	return ahci_platform_resume_host(dev);
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
		.pm = &ahci_imx_pm_ops,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
24a9ad5b SG	32	/* Timer 1-ms Register */
	33	IMX_TIMER1MS = 0x00e0,
	34	/* Port0 PHY Control Register */
	35	IMX_P0PHYCR = 0x0178,
	36	IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
e783c51c SG	37	IMX_P0PHYCR_CR_READ = 1 << 19,
	38	IMX_P0PHYCR_CR_WRITE = 1 << 18,
	39	IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
	40	IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
	41	/* Port0 PHY Status Register */
	42	IMX_P0PHYSR = 0x017c,
	43	IMX_P0PHYSR_CR_ACK = 1 << 18,
	44	IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
	45	/* Lane0 Output Status Register */
	46	IMX_LANE0_OUT_STAT = 0x2003,
	47	IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
	48	/* Clock Reset Register */
	49	IMX_CLOCK_RESET = 0x7f3f,
	50	IMX_CLOCK_RESET_RESET = 1 << 0,
9e54eae2 RZ	51	};
9e54eae2 RZ	52
4a23d179 MV	53	enum ahci_imx_type {
	54	AHCI_IMX53,
	55	AHCI_IMX6Q,
	56	};
	57
9e54eae2 RZ	58	struct imx_ahci_priv {
9e54eae2 RZ	59	struct platform_device *ahci_pdev;
4a23d179	60	enum ahci_imx_type type;
9e54eae2 RZ	61	struct clk *ahb_clk;
9e54eae2 RZ	62	struct regmap *gpr;
8b789d89 RZ	63	bool no_device;
8b789d89 RZ	64	bool first_time;
29e69413	65	u32 phy_params;
8b789d89 RZ	66	};
	67
	68	static int ahci_imx_hotplug;
	69	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	70	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	71
90870d79 HG	72	static void ahci_imx_host_stop(struct ata_host *host);
90870d79 HG	73
e783c51c SG	74	static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
	75	{
	76	int timeout = 10;
	77	u32 crval;
	78	u32 srval;
	79
	80	/* Assert or deassert the bit */
	81	crval = readl(mmio + IMX_P0PHYCR);
	82	if (assert)
	83	crval \|= bit;
	84	else
	85	crval &= ~bit;
	86	writel(crval, mmio + IMX_P0PHYCR);
	87
	88	/* Wait for the cr_ack signal */
	89	do {
	90	srval = readl(mmio + IMX_P0PHYSR);
	91	if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
	92	break;
	93	usleep_range(100, 200);
	94	} while (--timeout);
	95
	96	return timeout ? 0 : -ETIMEDOUT;
	97	}
	98
	99	static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
	100	{
	101	u32 crval = addr;
	102	int ret;
	103
	104	/* Supply the address on cr_data_in */
	105	writel(crval, mmio + IMX_P0PHYCR);
	106
	107	/* Assert the cr_cap_addr signal */
	108	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	109	if (ret)
	110	return ret;
	111
	112	/* Deassert cr_cap_addr */
	113	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	114	if (ret)
	115	return ret;
	116
	117	return 0;
	118	}
	119
	120	static int imx_phy_reg_write(u16 val, void __iomem *mmio)
	121	{
	122	u32 crval = val;
	123	int ret;
	124
	125	/* Supply the data on cr_data_in */
	126	writel(crval, mmio + IMX_P0PHYCR);
	127
	128	/* Assert the cr_cap_data signal */
	129	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	130	if (ret)
	131	return ret;
	132
	133	/* Deassert cr_cap_data */
	134	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	135	if (ret)
	136	return ret;
	137
138	if (val & IMX_CLOCK_RESET_RESET) {
139	/*
140	* In case we're resetting the phy, it's unable to acknowledge,
141	* so we return immediately here.
142	*/
143	crval \|= IMX_P0PHYCR_CR_WRITE;
144	writel(crval, mmio + IMX_P0PHYCR);
145	goto out;
146	}
147
148	/* Assert the cr_write signal */
149	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
150	if (ret)
151	return ret;
152
153	/* Deassert cr_write */
154	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
155	if (ret)
156	return ret;
157
158	out:
159	return 0;
160	}
161
162	static int imx_phy_reg_read(u16 val, void __iomem mmio)
163	{
164	int ret;
165
166	/* Assert the cr_read signal */
167	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
168	if (ret)
169	return ret;
170
171	/* Capture the data from cr_data_out[] */
172	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
173
174	/* Deassert cr_read */
175	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
176	if (ret)
177	return ret;
178
179	return 0;
180	}
181
182	static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
183	{
184	void __iomem *mmio = hpriv->mmio;
185	int timeout = 10;
186	u16 val;
187	int ret;
188
189	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
190	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
191	if (ret)
192	return ret;
193	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
194	if (ret)
195	return ret;
196
197	/* Wait for PHY RX_PLL to be stable */
198	do {
199	usleep_range(100, 200);
200	ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
201	if (ret)
202	return ret;
203	ret = imx_phy_reg_read(&val, mmio);
204	if (ret)
205	return ret;
206	if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
207	break;
208	} while (--timeout);
209
210	return timeout ? 0 : -ETIMEDOUT;
211	}
212
90870d79	213	static int imx_sata_enable(struct ahci_host_priv *hpriv)
8403e2ec	214	{
90870d79	215	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
e783c51c	216	struct device *dev = &imxpriv->ahci_pdev->dev;
8403e2ec MV	217	int ret;
8403e2ec MV	218
90870d79 HG	219	if (imxpriv->no_device)
	220	return 0;
	221
	222	if (hpriv->target_pwr) {
	223	ret = regulator_enable(hpriv->target_pwr);
	224	if (ret)
4a23d179	225	return ret;
4a23d179 MV	226	}
4a23d179 MV	227
90870d79 HG	228	ret = ahci_platform_enable_clks(hpriv);
	229	if (ret < 0)
	230	goto disable_regulator;
8403e2ec	231
4a23d179	232	if (imxpriv->type == AHCI_IMX6Q) {
90870d79 HG	233	/*
	234	* set PHY Paremeters, two steps to configure the GPR13,
	235	* one write for rest of parameters, mask of first write
	236	* is 0x07ffffff, and the other one write for setting
	237	* the mpll_clk_en.
	238	*/
	239	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	240	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	241	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	242	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	243	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	244	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	245	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	246	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	247	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	248	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	249	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
29e69413	250	imxpriv->phy_params);
4a23d179 MV	251	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	252	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	253	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
e783c51c	254
3685f251 SG	255	usleep_range(100, 200);
3685f251 SG	256
e783c51c SG	257	ret = imx_sata_phy_reset(hpriv);
	258	if (ret) {
	259	dev_err(dev, "failed to reset phy: %d\n", ret);
	260	goto disable_regulator;
	261	}
4a23d179	262	}
8403e2ec MV	263
	264	usleep_range(1000, 2000);
	265
	266	return 0;
4a23d179	267
90870d79 HG	268	disable_regulator:
	269	if (hpriv->target_pwr)
	270	regulator_disable(hpriv->target_pwr);
	271
4a23d179	272	return ret;
8403e2ec MV	273	}
8403e2ec MV	274
90870d79	275	static void imx_sata_disable(struct ahci_host_priv *hpriv)
8403e2ec	276	{
90870d79 HG	277	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	278
	279	if (imxpriv->no_device)
	280	return;
8403e2ec	281
4a23d179 MV	282	if (imxpriv->type == AHCI_IMX6Q) {
	283	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	284	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	285	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	286	}
	287
90870d79	288	ahci_platform_disable_clks(hpriv);
4a23d179	289
90870d79 HG	290	if (hpriv->target_pwr)
90870d79 HG	291	regulator_disable(hpriv->target_pwr);
8403e2ec MV	292	}
8403e2ec MV	293
8b789d89 RZ	294	static void ahci_imx_error_handler(struct ata_port *ap)
	295	{
	296	u32 reg_val;
	297	struct ata_device *dev;
	298	struct ata_host *host = dev_get_drvdata(ap->dev);
	299	struct ahci_host_priv *hpriv = host->private_data;
	300	void __iomem *mmio = hpriv->mmio;
90870d79	301	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8b789d89 RZ	302
	303	ahci_error_handler(ap);
	304
	305	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	306	return;
	307
	308	imxpriv->first_time = false;
	309
	310	ata_for_each_dev(dev, &ap->link, ENABLED)
	311	return;
	312	/*
	313	* Disable link to save power. An imx ahci port can't be recovered
	314	* without full reset once the pddq mode is enabled making it
	315	* impossible to use as part of libata LPM.
	316	*/
24a9ad5b SG	317	reg_val = readl(mmio + IMX_P0PHYCR);
24a9ad5b SG	318	writel(reg_val \| IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
90870d79	319	imx_sata_disable(hpriv);
8b789d89 RZ	320	imxpriv->no_device = true;
	321	}
	322
ee4e5a9a	323	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	324	unsigned long deadline)
	325	{
	326	struct ata_port *ap = link->ap;
90870d79 HG	327	struct ata_host *host = dev_get_drvdata(ap->dev);
	328	struct ahci_host_priv *hpriv = host->private_data;
	329	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
4a23d179 MV	330	int ret = -EIO;
	331
	332	if (imxpriv->type == AHCI_IMX53)
	333	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	334	else if (imxpriv->type == AHCI_IMX6Q)
	335	ret = ahci_ops.softreset(link, class, deadline);
	336
	337	return ret;
	338	}
	339
8b789d89	340	static struct ata_port_operations ahci_imx_ops = {
90870d79 HG	341	.inherits = &ahci_ops,
90870d79 HG	342	.host_stop = ahci_imx_host_stop,
8b789d89	343	.error_handler = ahci_imx_error_handler,
4a23d179	344	.softreset = ahci_imx_softreset,
8b789d89 RZ	345	};
	346
	347	static const struct ata_port_info ahci_imx_port_info = {
	348	.flags = AHCI_FLAG_COMMON,
	349	.pio_mask = ATA_PIO4,
	350	.udma_mask = ATA_UDMA6,
	351	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	352	};
9e54eae2 RZ	353
9e54eae2	354	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	355	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	356	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	357	{},
	358	};
	359	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	360
29e69413 RK	361	struct reg_value {
	362	u32 of_value;
	363	u32 reg_value;
	364	};
	365
	366	struct reg_property {
	367	const char *name;
	368	const struct reg_value *values;
	369	size_t num_values;
	370	u32 def_value;
	371	};
	372
	373	static const struct reg_value gpr13_tx_level[] = {
	374	{ 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
	375	{ 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
	376	{ 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
	377	{ 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
	378	{ 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
	379	{ 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
	380	{ 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
	381	{ 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
	382	{ 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
	383	{ 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
	384	{ 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
	385	{ 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
	386	{ 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
	387	{ 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
	388	{ 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
	389	{ 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
	390	{ 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
	391	{ 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
	392	{ 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
	393	{ 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
	394	{ 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
	395	{ 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
	396	{ 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
	397	{ 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
	398	{ 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
	399	{ 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
	400	{ 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
	401	{ 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
	402	{ 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
	403	{ 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
	404	{ 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
	405	{ 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
	406	};
	407
	408	static const struct reg_value gpr13_tx_boost[] = {
	409	{ 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
	410	{ 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
	411	{ 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
	412	{ 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
	413	{ 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
	414	{ 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
	415	{ 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
	416	{ 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
	417	{ 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
	418	{ 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
	419	{ 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
	420	{ 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
	421	{ 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
	422	{ 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
	423	{ 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
	424	{ 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
425	};
426
427	static const struct reg_value gpr13_tx_atten[] = {
428	{ 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
429	{ 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
430	{ 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
431	{ 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
432	{ 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
433	{ 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
434	};
435
436	static const struct reg_value gpr13_rx_eq[] = {
437	{ 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
438	{ 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
439	{ 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
440	{ 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
441	{ 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
442	{ 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
443	{ 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
444	{ 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
445	};
446
447	static const struct reg_property gpr13_props[] = {
448	{
449	.name = "fsl,transmit-level-mV",
450	.values = gpr13_tx_level,
451	.num_values = ARRAY_SIZE(gpr13_tx_level),
452	.def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
453	}, {
454	.name = "fsl,transmit-boost-mdB",
455	.values = gpr13_tx_boost,
456	.num_values = ARRAY_SIZE(gpr13_tx_boost),
457	.def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
458	}, {
459	.name = "fsl,transmit-atten-16ths",
460	.values = gpr13_tx_atten,
461	.num_values = ARRAY_SIZE(gpr13_tx_atten),
462	.def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
463	}, {
464	.name = "fsl,receive-eq-mdB",
465	.values = gpr13_rx_eq,
466	.num_values = ARRAY_SIZE(gpr13_rx_eq),
467	.def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
468	},
469	};
470
471	static u32 imx_ahci_parse_props(struct device *dev,
472	const struct reg_property *prop, size_t num)
473	{
474	struct device_node *np = dev->of_node;
475	u32 reg_value = 0;
476	int i, j;
477
478	for (i = 0; i < num; i++, prop++) {
479	u32 of_val;
480
481	if (of_property_read_u32(np, prop->name, &of_val)) {
482	dev_info(dev, "%s not specified, using %08x\n",
483	prop->name, prop->def_value);
484	reg_value \|= prop->def_value;
485	continue;
486	}
487
488	for (j = 0; j < prop->num_values; j++) {
489	if (prop->values[j].of_value == of_val) {
490	dev_info(dev, "%s value %u, using %08x\n",
491	prop->name, of_val, prop->values[j].reg_value);
492	reg_value \|= prop->values[j].reg_value;
493	break;
494	}
495	}
496
497	if (j == prop->num_values) {
498	dev_err(dev, "DT property %s is not a valid value\n",
499	prop->name);
500	reg_value \|= prop->def_value;
501	}
502	}
503
504	return reg_value;
505	}
506
9e54eae2 RZ	507	static int imx_ahci_probe(struct platform_device *pdev)
	508	{
	509	struct device *dev = &pdev->dev;
9e54eae2	510	const struct of_device_id *of_id;
90870d79	511	struct ahci_host_priv *hpriv;
9e54eae2	512	struct imx_ahci_priv *imxpriv;
90870d79	513	unsigned int reg_val;
9e54eae2 RZ	514	int ret;
9e54eae2 RZ	515
4a23d179 MV	516	of_id = of_match_device(imx_ahci_of_match, dev);
	517	if (!of_id)
	518	return -EINVAL;
	519
9e54eae2	520	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
90870d79	521	if (!imxpriv)
9e54eae2	522	return -ENOMEM;
9e54eae2	523
e783c51c	524	imxpriv->ahci_pdev = pdev;
8b789d89 RZ	525	imxpriv->no_device = false;
8b789d89 RZ	526	imxpriv->first_time = true;
90870d79	527	imxpriv->type = (enum ahci_imx_type)of_id->data;
9e54eae2 RZ	528	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	529	if (IS_ERR(imxpriv->ahb_clk)) {
	530	dev_err(dev, "can't get ahb clock.\n");
90870d79	531	return PTR_ERR(imxpriv->ahb_clk);
9e54eae2 RZ	532	}
9e54eae2 RZ	533
90870d79	534	if (imxpriv->type == AHCI_IMX6Q) {
29e69413 RK	535	u32 reg_value;
29e69413 RK	536
90870d79 HG	537	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	538	"fsl,imx6q-iomuxc-gpr");
	539	if (IS_ERR(imxpriv->gpr)) {
	540	dev_err(dev,
	541	"failed to find fsl,imx6q-iomux-gpr regmap\n");
	542	return PTR_ERR(imxpriv->gpr);
4a23d179	543	}
29e69413 RK	544
	545	reg_value = imx_ahci_parse_props(dev, gpr13_props,
	546	ARRAY_SIZE(gpr13_props));
	547
	548	imxpriv->phy_params =
	549	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	550	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	551	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	552	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	553	reg_value;
4a23d179 MV	554	}
4a23d179 MV	555
90870d79 HG	556	hpriv = ahci_platform_get_resources(pdev);
	557	if (IS_ERR(hpriv))
	558	return PTR_ERR(hpriv);
	559
	560	hpriv->plat_data = imxpriv;
9e54eae2	561
90870d79 HG	562	ret = imx_sata_enable(hpriv);
	563	if (ret)
	564	return ret;
9e54eae2	565
90870d79 HG	566	/*
90870d79 HG	567	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
24a9ad5b	568	* and IP vendor specific register IMX_TIMER1MS.
90870d79 HG	569	* Configure CAP_SSS (support stagered spin up).
	570	* Implement the port0.
	571	* Get the ahb clock rate, and configure the TIMER1MS register.
	572	*/
	573	reg_val = readl(hpriv->mmio + HOST_CAP);
	574	if (!(reg_val & HOST_CAP_SSS)) {
	575	reg_val \|= HOST_CAP_SSS;
	576	writel(reg_val, hpriv->mmio + HOST_CAP);
	577	}
	578	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	579	if (!(reg_val & 0x1)) {
	580	reg_val \|= 0x1;
	581	writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
9e54eae2 RZ	582	}
9e54eae2 RZ	583
90870d79	584	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
24a9ad5b	585	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
9e54eae2	586
f9f36917 KW	587	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
f9f36917 KW	588	0, 0, 0);
90870d79 HG	589	if (ret)
90870d79 HG	590	imx_sata_disable(hpriv);
9e54eae2	591
90870d79 HG	592	return ret;
90870d79 HG	593	}
4a23d179	594
90870d79 HG	595	static void ahci_imx_host_stop(struct ata_host *host)
	596	{
	597	struct ahci_host_priv *hpriv = host->private_data;
8403e2ec	598
90870d79 HG	599	imx_sata_disable(hpriv);
90870d79 HG	600	}
9e54eae2	601
46ce6b74	602	#ifdef CONFIG_PM_SLEEP
90870d79 HG	603	static int imx_ahci_suspend(struct device *dev)
	604	{
	605	struct ata_host *host = dev_get_drvdata(dev);
	606	struct ahci_host_priv *hpriv = host->private_data;
	607	int ret;
9e54eae2	608
90870d79 HG	609	ret = ahci_platform_suspend_host(dev);
90870d79 HG	610	if (ret)
9e54eae2	611	return ret;
90870d79 HG	612
90870d79 HG	613	imx_sata_disable(hpriv);
9e54eae2 RZ	614
	615	return 0;
	616	}
	617
90870d79	618	static int imx_ahci_resume(struct device *dev)
9e54eae2	619	{
90870d79 HG	620	struct ata_host *host = dev_get_drvdata(dev);
	621	struct ahci_host_priv *hpriv = host->private_data;
	622	int ret;
9e54eae2	623
90870d79 HG	624	ret = imx_sata_enable(hpriv);
	625	if (ret)
	626	return ret;
	627
	628	return ahci_platform_resume_host(dev);
9e54eae2	629	}
46ce6b74	630	#endif
9e54eae2	631
90870d79 HG	632	static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
90870d79 HG	633
9e54eae2 RZ	634	static struct platform_driver imx_ahci_driver = {
9e54eae2 RZ	635	.probe = imx_ahci_probe,
90870d79	636	.remove = ata_platform_remove_one,
9e54eae2 RZ	637	.driver = {
	638	.name = "ahci-imx",
	639	.owner = THIS_MODULE,
	640	.of_match_table = imx_ahci_of_match,
90870d79	641	.pm = &ahci_imx_pm_ops,
9e54eae2 RZ	642	},
	643	};
	644	module_platform_driver(imx_ahci_driver);
	645
	646	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	647	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	648	MODULE_LICENSE("GPL");
	649	MODULE_ALIAS("ahci:imx");