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c5754b52 OS |
1 | /* |
2 | * Allwinner sunxi AHCI SATA platform driver | |
3 | * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl> | |
4 | * Copyright 2014 Hans de Goede <hdegoede@redhat.com> | |
5 | * | |
6 | * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov | |
7 | * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>, | |
8 | * Daniel Wang <danielwang@allwinnertech.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms and conditions of the GNU General Public License, | |
12 | * version 2, as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | */ | |
19 | ||
20 | #include <linux/ahci_platform.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/regulator/consumer.h> | |
28 | #include "ahci.h" | |
29 | ||
018d5ef2 AM |
30 | #define DRV_NAME "ahci-sunxi" |
31 | ||
35c16a8f HG |
32 | /* Insmod parameters */ |
33 | static bool enable_pmp; | |
34 | module_param(enable_pmp, bool, 0); | |
35 | MODULE_PARM_DESC(enable_pmp, | |
36 | "Enable support for sata port multipliers, only use if you use a pmp!"); | |
37 | ||
cdf457a4 BZ |
38 | #define AHCI_BISTAFR 0x00a0 |
39 | #define AHCI_BISTCR 0x00a4 | |
40 | #define AHCI_BISTFCTR 0x00a8 | |
41 | #define AHCI_BISTSR 0x00ac | |
42 | #define AHCI_BISTDECR 0x00b0 | |
43 | #define AHCI_DIAGNR0 0x00b4 | |
44 | #define AHCI_DIAGNR1 0x00b8 | |
45 | #define AHCI_OOBR 0x00bc | |
46 | #define AHCI_PHYCS0R 0x00c0 | |
47 | #define AHCI_PHYCS1R 0x00c4 | |
48 | #define AHCI_PHYCS2R 0x00c8 | |
49 | #define AHCI_TIMER1MS 0x00e0 | |
50 | #define AHCI_GPARAM1R 0x00e8 | |
51 | #define AHCI_GPARAM2R 0x00ec | |
52 | #define AHCI_PPARAMR 0x00f0 | |
53 | #define AHCI_TESTR 0x00f4 | |
54 | #define AHCI_VERSIONR 0x00f8 | |
55 | #define AHCI_IDR 0x00fc | |
56 | #define AHCI_RWCR 0x00fc | |
57 | #define AHCI_P0DMACR 0x0170 | |
58 | #define AHCI_P0PHYCR 0x0178 | |
59 | #define AHCI_P0PHYSR 0x017c | |
c5754b52 OS |
60 | |
61 | static void sunxi_clrbits(void __iomem *reg, u32 clr_val) | |
62 | { | |
63 | u32 reg_val; | |
64 | ||
65 | reg_val = readl(reg); | |
66 | reg_val &= ~(clr_val); | |
67 | writel(reg_val, reg); | |
68 | } | |
69 | ||
70 | static void sunxi_setbits(void __iomem *reg, u32 set_val) | |
71 | { | |
72 | u32 reg_val; | |
73 | ||
74 | reg_val = readl(reg); | |
75 | reg_val |= set_val; | |
76 | writel(reg_val, reg); | |
77 | } | |
78 | ||
79 | static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) | |
80 | { | |
81 | u32 reg_val; | |
82 | ||
83 | reg_val = readl(reg); | |
84 | reg_val &= ~(clr_val); | |
85 | reg_val |= set_val; | |
86 | writel(reg_val, reg); | |
87 | } | |
88 | ||
89 | static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) | |
90 | { | |
91 | return (readl(reg) >> shift) & mask; | |
92 | } | |
93 | ||
94 | static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) | |
95 | { | |
96 | u32 reg_val; | |
97 | int timeout; | |
98 | ||
99 | /* This magic is from the original code */ | |
100 | writel(0, reg_base + AHCI_RWCR); | |
d2ec147a | 101 | msleep(5); |
c5754b52 OS |
102 | |
103 | sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); | |
104 | sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, | |
105 | (0x7 << 24), | |
106 | (0x5 << 24) | BIT(23) | BIT(18)); | |
107 | sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, | |
108 | (0x3 << 16) | (0x1f << 8) | (0x3 << 6), | |
109 | (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); | |
110 | sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); | |
111 | sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); | |
112 | sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, | |
113 | (0x7 << 20), (0x3 << 20)); | |
114 | sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, | |
115 | (0x1f << 5), (0x19 << 5)); | |
d2ec147a | 116 | msleep(5); |
c5754b52 OS |
117 | |
118 | sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); | |
119 | ||
120 | timeout = 250; /* Power up takes aprox 50 us */ | |
121 | do { | |
122 | reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28); | |
123 | if (reg_val == 0x02) | |
124 | break; | |
125 | ||
126 | if (--timeout == 0) { | |
127 | dev_err(dev, "PHY power up failed.\n"); | |
128 | return -EIO; | |
129 | } | |
130 | udelay(1); | |
131 | } while (1); | |
132 | ||
133 | sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); | |
134 | ||
135 | timeout = 100; /* Calibration takes aprox 10 us */ | |
136 | do { | |
137 | reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24); | |
138 | if (reg_val == 0x00) | |
139 | break; | |
140 | ||
141 | if (--timeout == 0) { | |
142 | dev_err(dev, "PHY calibration failed.\n"); | |
143 | return -EIO; | |
144 | } | |
145 | udelay(1); | |
146 | } while (1); | |
147 | ||
d2ec147a | 148 | msleep(15); |
c5754b52 OS |
149 | |
150 | writel(0x7, reg_base + AHCI_RWCR); | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | static void ahci_sunxi_start_engine(struct ata_port *ap) | |
156 | { | |
157 | void __iomem *port_mmio = ahci_port_base(ap); | |
158 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
159 | ||
160 | /* Setup DMA before DMA start */ | |
161 | sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); | |
162 | ||
163 | /* Start DMA */ | |
164 | sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); | |
165 | } | |
166 | ||
167 | static const struct ata_port_info ahci_sunxi_port_info = { | |
c5754b52 OS |
168 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, |
169 | .pio_mask = ATA_PIO4, | |
170 | .udma_mask = ATA_UDMA6, | |
171 | .port_ops = &ahci_platform_ops, | |
172 | }; | |
173 | ||
018d5ef2 AM |
174 | static struct scsi_host_template ahci_platform_sht = { |
175 | AHCI_SHT(DRV_NAME), | |
176 | }; | |
177 | ||
c5754b52 OS |
178 | static int ahci_sunxi_probe(struct platform_device *pdev) |
179 | { | |
180 | struct device *dev = &pdev->dev; | |
181 | struct ahci_host_priv *hpriv; | |
182 | int rc; | |
183 | ||
184 | hpriv = ahci_platform_get_resources(pdev); | |
185 | if (IS_ERR(hpriv)) | |
186 | return PTR_ERR(hpriv); | |
187 | ||
188 | hpriv->start_engine = ahci_sunxi_start_engine; | |
189 | ||
190 | rc = ahci_platform_enable_resources(hpriv); | |
191 | if (rc) | |
192 | return rc; | |
193 | ||
194 | rc = ahci_sunxi_phy_init(dev, hpriv->mmio); | |
195 | if (rc) | |
196 | goto disable_resources; | |
197 | ||
725c7b57 | 198 | hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | |
35c16a8f HG |
199 | AHCI_HFLAG_YES_NCQ; |
200 | ||
201 | /* | |
202 | * The sunxi sata controller seems to be unable to successfully do a | |
203 | * soft reset if no pmp is attached, so disable pmp use unless | |
204 | * requested, otherwise directly attached disks do not work. | |
205 | */ | |
206 | if (!enable_pmp) | |
207 | hpriv->flags |= AHCI_HFLAG_NO_PMP; | |
f9f36917 | 208 | |
018d5ef2 AM |
209 | rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, |
210 | &ahci_platform_sht); | |
c5754b52 OS |
211 | if (rc) |
212 | goto disable_resources; | |
213 | ||
214 | return 0; | |
215 | ||
216 | disable_resources: | |
217 | ahci_platform_disable_resources(hpriv); | |
218 | return rc; | |
219 | } | |
220 | ||
221 | #ifdef CONFIG_PM_SLEEP | |
1bf9d885 | 222 | static int ahci_sunxi_resume(struct device *dev) |
c5754b52 OS |
223 | { |
224 | struct ata_host *host = dev_get_drvdata(dev); | |
225 | struct ahci_host_priv *hpriv = host->private_data; | |
226 | int rc; | |
227 | ||
228 | rc = ahci_platform_enable_resources(hpriv); | |
229 | if (rc) | |
230 | return rc; | |
231 | ||
232 | rc = ahci_sunxi_phy_init(dev, hpriv->mmio); | |
233 | if (rc) | |
234 | goto disable_resources; | |
235 | ||
236 | rc = ahci_platform_resume_host(dev); | |
237 | if (rc) | |
238 | goto disable_resources; | |
239 | ||
240 | return 0; | |
241 | ||
242 | disable_resources: | |
243 | ahci_platform_disable_resources(hpriv); | |
244 | return rc; | |
245 | } | |
246 | #endif | |
247 | ||
248 | static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend, | |
249 | ahci_sunxi_resume); | |
250 | ||
251 | static const struct of_device_id ahci_sunxi_of_match[] = { | |
252 | { .compatible = "allwinner,sun4i-a10-ahci", }, | |
253 | { }, | |
254 | }; | |
255 | MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match); | |
256 | ||
257 | static struct platform_driver ahci_sunxi_driver = { | |
258 | .probe = ahci_sunxi_probe, | |
259 | .remove = ata_platform_remove_one, | |
260 | .driver = { | |
018d5ef2 | 261 | .name = DRV_NAME, |
c5754b52 OS |
262 | .of_match_table = ahci_sunxi_of_match, |
263 | .pm = &ahci_sunxi_pm_ops, | |
264 | }, | |
265 | }; | |
266 | module_platform_driver(ahci_sunxi_driver); | |
267 | ||
268 | MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver"); | |
269 | MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>"); | |
270 | MODULE_LICENSE("GPL"); |