Commit | Line | Data |
---|---|---|
81d01bfa LH |
1 | /* |
2 | * AppliedMicro X-Gene SoC SATA Host Controller Driver | |
3 | * | |
4 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
5 | * Author: Loc Ho <lho@apm.com> | |
6 | * Tuan Phan <tphan@apm.com> | |
7 | * Suman Tripathi <stripathi@apm.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | * | |
22 | * NOTE: PM support is not currently available. | |
23 | * | |
24 | */ | |
92b5bf98 | 25 | #include <linux/acpi.h> |
81d01bfa LH |
26 | #include <linux/module.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/ahci_platform.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/phy/phy.h> | |
32 | #include "ahci.h" | |
33 | ||
018d5ef2 AM |
34 | #define DRV_NAME "xgene-ahci" |
35 | ||
81d01bfa LH |
36 | /* Max # of disk per a controller */ |
37 | #define MAX_AHCI_CHN_PERCTR 2 | |
38 | ||
39 | /* MUX CSR */ | |
40 | #define SATA_ENET_CONFIG_REG 0x00000000 | |
41 | #define CFG_SATA_ENET_SELECT_MASK 0x00000001 | |
42 | ||
43 | /* SATA core host controller CSR */ | |
44 | #define SLVRDERRATTRIBUTES 0x00000000 | |
45 | #define SLVWRERRATTRIBUTES 0x00000004 | |
46 | #define MSTRDERRATTRIBUTES 0x00000008 | |
47 | #define MSTWRERRATTRIBUTES 0x0000000c | |
48 | #define BUSCTLREG 0x00000014 | |
49 | #define IOFMSTRWAUX 0x00000018 | |
50 | #define INTSTATUSMASK 0x0000002c | |
51 | #define ERRINTSTATUS 0x00000030 | |
52 | #define ERRINTSTATUSMASK 0x00000034 | |
53 | ||
54 | /* SATA host AHCI CSR */ | |
55 | #define PORTCFG 0x000000a4 | |
56 | #define PORTADDR_SET(dst, src) \ | |
57 | (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f)) | |
58 | #define PORTPHY1CFG 0x000000a8 | |
59 | #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \ | |
60 | (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000)) | |
61 | #define PORTPHY2CFG 0x000000ac | |
62 | #define PORTPHY3CFG 0x000000b0 | |
63 | #define PORTPHY4CFG 0x000000b4 | |
64 | #define PORTPHY5CFG 0x000000b8 | |
65 | #define SCTL0 0x0000012C | |
66 | #define PORTPHY5CFG_RTCHG_SET(dst, src) \ | |
67 | (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000)) | |
68 | #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \ | |
69 | (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000)) | |
70 | #define PORTAXICFG 0x000000bc | |
71 | #define PORTAXICFG_OUTTRANS_SET(dst, src) \ | |
72 | (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) | |
aeae4dca ST |
73 | #define PORTRANSCFG 0x000000c8 |
74 | #define PORTRANSCFG_RXWM_SET(dst, src) \ | |
75 | (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f)) | |
81d01bfa LH |
76 | |
77 | /* SATA host controller AXI CSR */ | |
78 | #define INT_SLV_TMOMASK 0x00000010 | |
79 | ||
80 | /* SATA diagnostic CSR */ | |
81 | #define CFG_MEM_RAM_SHUTDOWN 0x00000070 | |
82 | #define BLOCK_MEM_RDY 0x00000074 | |
83 | ||
0babe614 ST |
84 | /* Max retry for link down */ |
85 | #define MAX_LINK_DOWN_RETRY 3 | |
86 | ||
81d01bfa LH |
87 | struct xgene_ahci_context { |
88 | struct ahci_host_priv *hpriv; | |
89 | struct device *dev; | |
2a0bdff6 | 90 | u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/ |
a3a84bc7 | 91 | u32 class[MAX_AHCI_CHN_PERCTR]; /* tracking the class of device */ |
81d01bfa LH |
92 | void __iomem *csr_core; /* Core CSR address of IP */ |
93 | void __iomem *csr_diag; /* Diag CSR address of IP */ | |
94 | void __iomem *csr_axi; /* AXI CSR address of IP */ | |
95 | void __iomem *csr_mux; /* MUX CSR address of IP */ | |
96 | }; | |
97 | ||
98 | static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx) | |
99 | { | |
100 | dev_dbg(ctx->dev, "Release memory from shutdown\n"); | |
101 | writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); | |
102 | readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ | |
103 | msleep(1); /* reset may take up to 1ms */ | |
104 | if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { | |
105 | dev_err(ctx->dev, "failed to release memory from shutdown\n"); | |
106 | return -ENODEV; | |
107 | } | |
108 | return 0; | |
109 | } | |
110 | ||
1540035d ST |
111 | /** |
112 | * xgene_ahci_poll_reg_val- Poll a register on a specific value. | |
113 | * @ap : ATA port of interest. | |
114 | * @reg : Register of interest. | |
115 | * @val : Value to be attained. | |
116 | * @interval : waiting interval for polling. | |
117 | * @timeout : timeout for achieving the value. | |
118 | */ | |
119 | static int xgene_ahci_poll_reg_val(struct ata_port *ap, | |
120 | void __iomem *reg, unsigned | |
121 | int val, unsigned long interval, | |
122 | unsigned long timeout) | |
123 | { | |
124 | unsigned long deadline; | |
125 | unsigned int tmp; | |
126 | ||
127 | tmp = ioread32(reg); | |
128 | deadline = ata_deadline(jiffies, timeout); | |
129 | ||
130 | while (tmp != val && time_before(jiffies, deadline)) { | |
131 | ata_msleep(ap, interval); | |
132 | tmp = ioread32(reg); | |
133 | } | |
134 | ||
135 | return tmp; | |
136 | } | |
137 | ||
2a0bdff6 ST |
138 | /** |
139 | * xgene_ahci_restart_engine - Restart the dma engine. | |
140 | * @ap : ATA port of interest | |
141 | * | |
1540035d ST |
142 | * Waits for completion of multiple commands and restarts |
143 | * the DMA engine inside the controller. | |
2a0bdff6 ST |
144 | */ |
145 | static int xgene_ahci_restart_engine(struct ata_port *ap) | |
146 | { | |
147 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1540035d ST |
148 | struct ahci_port_priv *pp = ap->private_data; |
149 | void __iomem *port_mmio = ahci_port_base(ap); | |
150 | u32 fbs; | |
151 | ||
152 | /* | |
153 | * In case of PMP multiple IDENTIFY DEVICE commands can be | |
154 | * issued inside PxCI. So need to poll PxCI for the | |
155 | * completion of outstanding IDENTIFY DEVICE commands before | |
156 | * we restart the DMA engine. | |
157 | */ | |
158 | if (xgene_ahci_poll_reg_val(ap, port_mmio + | |
159 | PORT_CMD_ISSUE, 0x0, 1, 100)) | |
160 | return -EBUSY; | |
2a0bdff6 ST |
161 | |
162 | ahci_stop_engine(ap); | |
163 | ahci_start_fis_rx(ap); | |
1540035d ST |
164 | |
165 | /* | |
166 | * Enable the PxFBS.FBS_EN bit as it | |
167 | * gets cleared due to stopping the engine. | |
168 | */ | |
169 | if (pp->fbs_supported) { | |
170 | fbs = readl(port_mmio + PORT_FBS); | |
171 | writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); | |
172 | fbs = readl(port_mmio + PORT_FBS); | |
173 | } | |
174 | ||
2a0bdff6 ST |
175 | hpriv->start_engine(ap); |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | /** | |
181 | * xgene_ahci_qc_issue - Issue commands to the device | |
182 | * @qc: Command to issue | |
183 | * | |
a3a84bc7 ST |
184 | * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot |
185 | * clear the BSY bit after receiving the PIO setup FIS. This results in the dma | |
186 | * state machine goes into the CMFatalErrorUpdate state and locks up. By | |
187 | * restarting the dma engine, it removes the controller out of lock up state. | |
188 | * | |
189 | * Due to H/W errata, the controller is unable to save the PMP | |
190 | * field fetched from command header before sending the H2D FIS. | |
191 | * When the device returns the PMP port field in the D2H FIS, there is | |
192 | * a mismatch and results in command completion failure. The | |
193 | * workaround is to write the pmp value to PxFBS.DEV field before issuing | |
194 | * any command to PMP. | |
2a0bdff6 ST |
195 | */ |
196 | static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) | |
197 | { | |
198 | struct ata_port *ap = qc->ap; | |
199 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
200 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
201 | int rc = 0; | |
a3a84bc7 ST |
202 | u32 port_fbs; |
203 | void *port_mmio = ahci_port_base(ap); | |
204 | ||
205 | /* | |
206 | * Write the pmp value to PxFBS.DEV | |
207 | * for case of Port Mulitplier. | |
208 | */ | |
209 | if (ctx->class[ap->port_no] == ATA_DEV_PMP) { | |
210 | port_fbs = readl(port_mmio + PORT_FBS); | |
211 | port_fbs &= ~PORT_FBS_DEV_MASK; | |
212 | port_fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; | |
213 | writel(port_fbs, port_mmio + PORT_FBS); | |
214 | } | |
2a0bdff6 | 215 | |
1102407b | 216 | if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) || |
09c32aaa ST |
217 | (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) || |
218 | (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART))) | |
2a0bdff6 ST |
219 | xgene_ahci_restart_engine(ap); |
220 | ||
221 | rc = ahci_qc_issue(qc); | |
222 | ||
223 | /* Save the last command issued */ | |
224 | ctx->last_cmd[ap->port_no] = qc->tf.command; | |
225 | ||
226 | return rc; | |
227 | } | |
228 | ||
0bed13be ST |
229 | static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx) |
230 | { | |
231 | void __iomem *diagcsr = ctx->csr_diag; | |
232 | ||
233 | return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 && | |
234 | readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF); | |
235 | } | |
236 | ||
81d01bfa LH |
237 | /** |
238 | * xgene_ahci_read_id - Read ID data from the specified device | |
239 | * @dev: device | |
240 | * @tf: proposed taskfile | |
241 | * @id: data buffer | |
242 | * | |
243 | * This custom read ID function is required due to the fact that the HW | |
2a0bdff6 | 244 | * does not support DEVSLP. |
81d01bfa LH |
245 | */ |
246 | static unsigned int xgene_ahci_read_id(struct ata_device *dev, | |
247 | struct ata_taskfile *tf, u16 *id) | |
248 | { | |
249 | u32 err_mask; | |
81d01bfa LH |
250 | |
251 | err_mask = ata_do_dev_read_id(dev, tf, id); | |
252 | if (err_mask) | |
253 | return err_mask; | |
254 | ||
255 | /* | |
256 | * Mask reserved area. Word78 spec of Link Power Management | |
257 | * bit15-8: reserved | |
258 | * bit7: NCQ autosence | |
259 | * bit6: Software settings preservation supported | |
260 | * bit5: reserved | |
261 | * bit4: In-order sata delivery supported | |
262 | * bit3: DIPM requests supported | |
263 | * bit2: DMA Setup FIS Auto-Activate optimization supported | |
264 | * bit1: DMA Setup FIX non-Zero buffer offsets supported | |
265 | * bit0: Reserved | |
266 | * | |
267 | * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP | |
268 | */ | |
5c0b8e0d | 269 | id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8)); |
81d01bfa | 270 | |
81d01bfa LH |
271 | return 0; |
272 | } | |
273 | ||
274 | static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) | |
275 | { | |
276 | void __iomem *mmio = ctx->hpriv->mmio; | |
277 | u32 val; | |
278 | ||
279 | dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n", | |
280 | mmio, channel); | |
281 | val = readl(mmio + PORTCFG); | |
282 | val = PORTADDR_SET(val, channel == 0 ? 2 : 3); | |
283 | writel(val, mmio + PORTCFG); | |
284 | readl(mmio + PORTCFG); /* Force a barrier */ | |
285 | /* Disable fix rate */ | |
286 | writel(0x0001fffe, mmio + PORTPHY1CFG); | |
287 | readl(mmio + PORTPHY1CFG); /* Force a barrier */ | |
0185b1b7 | 288 | writel(0x28183219, mmio + PORTPHY2CFG); |
81d01bfa | 289 | readl(mmio + PORTPHY2CFG); /* Force a barrier */ |
0185b1b7 | 290 | writel(0x13081008, mmio + PORTPHY3CFG); |
81d01bfa | 291 | readl(mmio + PORTPHY3CFG); /* Force a barrier */ |
0185b1b7 | 292 | writel(0x00480815, mmio + PORTPHY4CFG); |
81d01bfa LH |
293 | readl(mmio + PORTPHY4CFG); /* Force a barrier */ |
294 | /* Set window negotiation */ | |
295 | val = readl(mmio + PORTPHY5CFG); | |
296 | val = PORTPHY5CFG_RTCHG_SET(val, 0x300); | |
297 | writel(val, mmio + PORTPHY5CFG); | |
298 | readl(mmio + PORTPHY5CFG); /* Force a barrier */ | |
299 | val = readl(mmio + PORTAXICFG); | |
300 | val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */ | |
301 | val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ | |
302 | writel(val, mmio + PORTAXICFG); | |
303 | readl(mmio + PORTAXICFG); /* Force a barrier */ | |
aeae4dca ST |
304 | /* Set the watermark threshold of the receive FIFO */ |
305 | val = readl(mmio + PORTRANSCFG); | |
306 | val = PORTRANSCFG_RXWM_SET(val, 0x30); | |
307 | writel(val, mmio + PORTRANSCFG); | |
81d01bfa LH |
308 | } |
309 | ||
310 | /** | |
311 | * xgene_ahci_do_hardreset - Issue the actual COMRESET | |
312 | * @link: link to reset | |
313 | * @deadline: deadline jiffies for the operation | |
314 | * @online: Return value to indicate if device online | |
315 | * | |
316 | * Due to the limitation of the hardware PHY, a difference set of setting is | |
317 | * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps), | |
318 | * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will | |
319 | * report disparity error and etc. In addition, during COMRESET, there can | |
320 | * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and | |
0babe614 ST |
321 | * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long |
322 | * reboot cycle regression, sometimes the PHY reports link down even if the | |
323 | * device is present because of speed negotiation failure. so need to retry | |
324 | * the COMRESET to get the link up. The following algorithm is followed to | |
325 | * proper configure the hardware PHY during COMRESET: | |
81d01bfa LH |
326 | * |
327 | * Alg Part 1: | |
328 | * 1. Start the PHY at Gen3 speed (default setting) | |
329 | * 2. Issue the COMRESET | |
330 | * 3. If no link, go to Alg Part 3 | |
331 | * 4. If link up, determine if the negotiated speed matches the PHY | |
332 | * configured speed | |
333 | * 5. If they matched, go to Alg Part 2 | |
334 | * 6. If they do not matched and first time, configure the PHY for the linked | |
335 | * up disk speed and repeat step 2 | |
336 | * 7. Go to Alg Part 2 | |
337 | * | |
338 | * Alg Part 2: | |
339 | * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error | |
340 | * reported in the register PORT_SCR_ERR, then reset the PHY receiver line | |
0babe614 | 341 | * 2. Go to Alg Part 4 |
81d01bfa LH |
342 | * |
343 | * Alg Part 3: | |
0babe614 ST |
344 | * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY |
345 | * communication establishment failed and maximum link down attempts are | |
346 | * less than Max attempts 3 then goto Alg Part 1. | |
347 | * 2. Go to Alg Part 4. | |
348 | * | |
349 | * Alg Part 4: | |
81d01bfa LH |
350 | * 1. Clear any pending from register PORT_SCR_ERR. |
351 | * | |
352 | * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition | |
353 | * and until the underlying PHY supports an method to reset the receiver | |
354 | * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors, | |
355 | * an warning message will be printed. | |
356 | */ | |
357 | static int xgene_ahci_do_hardreset(struct ata_link *link, | |
358 | unsigned long deadline, bool *online) | |
359 | { | |
360 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
361 | struct ata_port *ap = link->ap; | |
362 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
363 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
364 | struct ahci_port_priv *pp = ap->private_data; | |
365 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
366 | void __iomem *port_mmio = ahci_port_base(ap); | |
367 | struct ata_taskfile tf; | |
0babe614 | 368 | int link_down_retry = 0; |
81d01bfa | 369 | int rc; |
0babe614 | 370 | u32 val, sstatus; |
81d01bfa | 371 | |
0babe614 ST |
372 | do { |
373 | /* clear D2H reception area to properly wait for D2H FIS */ | |
374 | ata_tf_init(link->device, &tf); | |
375 | tf.command = ATA_BUSY; | |
376 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
377 | rc = sata_link_hardreset(link, timing, deadline, online, | |
81d01bfa | 378 | ahci_check_ready); |
0babe614 ST |
379 | if (*online) { |
380 | val = readl(port_mmio + PORT_SCR_ERR); | |
381 | if (val & (SERR_DISPARITY | SERR_10B_8B_ERR)) | |
382 | dev_warn(ctx->dev, "link has error\n"); | |
383 | break; | |
384 | } | |
81d01bfa | 385 | |
0babe614 ST |
386 | sata_scr_read(link, SCR_STATUS, &sstatus); |
387 | } while (link_down_retry++ < MAX_LINK_DOWN_RETRY && | |
388 | (sstatus & 0xff) == 0x1); | |
81d01bfa LH |
389 | |
390 | /* clear all errors if any pending */ | |
391 | val = readl(port_mmio + PORT_SCR_ERR); | |
392 | writel(val, port_mmio + PORT_SCR_ERR); | |
393 | ||
394 | return rc; | |
395 | } | |
396 | ||
397 | static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class, | |
398 | unsigned long deadline) | |
399 | { | |
400 | struct ata_port *ap = link->ap; | |
401 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
402 | void __iomem *port_mmio = ahci_port_base(ap); | |
403 | bool online; | |
404 | int rc; | |
405 | u32 portcmd_saved; | |
406 | u32 portclb_saved; | |
407 | u32 portclbhi_saved; | |
408 | u32 portrxfis_saved; | |
409 | u32 portrxfishi_saved; | |
410 | ||
411 | /* As hardreset resets these CSR, save it to restore later */ | |
412 | portcmd_saved = readl(port_mmio + PORT_CMD); | |
413 | portclb_saved = readl(port_mmio + PORT_LST_ADDR); | |
414 | portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI); | |
415 | portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR); | |
416 | portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI); | |
417 | ||
418 | ahci_stop_engine(ap); | |
419 | ||
420 | rc = xgene_ahci_do_hardreset(link, deadline, &online); | |
421 | ||
422 | /* As controller hardreset clears them, restore them */ | |
423 | writel(portcmd_saved, port_mmio + PORT_CMD); | |
424 | writel(portclb_saved, port_mmio + PORT_LST_ADDR); | |
425 | writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI); | |
426 | writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR); | |
427 | writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI); | |
428 | ||
429 | hpriv->start_engine(ap); | |
430 | ||
431 | if (online) | |
432 | *class = ahci_dev_classify(ap); | |
433 | ||
434 | return rc; | |
435 | } | |
436 | ||
437 | static void xgene_ahci_host_stop(struct ata_host *host) | |
438 | { | |
439 | struct ahci_host_priv *hpriv = host->private_data; | |
440 | ||
441 | ahci_platform_disable_resources(hpriv); | |
442 | } | |
443 | ||
a3a84bc7 ST |
444 | /** |
445 | * xgene_ahci_pmp_softreset - Issue the softreset to the drives connected | |
446 | * to Port Multiplier. | |
447 | * @link: link to reset | |
448 | * @class: Return value to indicate class of device | |
449 | * @deadline: deadline jiffies for the operation | |
450 | * | |
451 | * Due to H/W errata, the controller is unable to save the PMP | |
452 | * field fetched from command header before sending the H2D FIS. | |
453 | * When the device returns the PMP port field in the D2H FIS, there is | |
454 | * a mismatch and results in command completion failure. The workaround | |
455 | * is to write the pmp value to PxFBS.DEV field before issuing any command | |
456 | * to PMP. | |
457 | */ | |
458 | static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class, | |
459 | unsigned long deadline) | |
460 | { | |
461 | int pmp = sata_srst_pmp(link); | |
462 | struct ata_port *ap = link->ap; | |
463 | u32 rc; | |
464 | void *port_mmio = ahci_port_base(ap); | |
465 | u32 port_fbs; | |
466 | ||
467 | /* | |
468 | * Set PxFBS.DEV field with pmp | |
469 | * value. | |
470 | */ | |
471 | port_fbs = readl(port_mmio + PORT_FBS); | |
472 | port_fbs &= ~PORT_FBS_DEV_MASK; | |
473 | port_fbs |= pmp << PORT_FBS_DEV_OFFSET; | |
474 | writel(port_fbs, port_mmio + PORT_FBS); | |
475 | ||
476 | rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); | |
477 | ||
478 | return rc; | |
479 | } | |
480 | ||
481 | /** | |
482 | * xgene_ahci_softreset - Issue the softreset to the drive. | |
483 | * @link: link to reset | |
484 | * @class: Return value to indicate class of device | |
485 | * @deadline: deadline jiffies for the operation | |
486 | * | |
487 | * Due to H/W errata, the controller is unable to save the PMP | |
488 | * field fetched from command header before sending the H2D FIS. | |
489 | * When the device returns the PMP port field in the D2H FIS, there is | |
490 | * a mismatch and results in command completion failure. The workaround | |
491 | * is to write the pmp value to PxFBS.DEV field before issuing any command | |
492 | * to PMP. Here is the algorithm to detect PMP : | |
493 | * | |
494 | * 1. Save the PxFBS value | |
495 | * 2. Program PxFBS.DEV with pmp value send by framework. Framework sends | |
496 | * 0xF for both PMP/NON-PMP initially | |
497 | * 3. Issue softreset | |
498 | * 4. If signature class is PMP goto 6 | |
499 | * 5. restore the original PxFBS and goto 3 | |
500 | * 6. return | |
501 | */ | |
502 | static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class, | |
503 | unsigned long deadline) | |
504 | { | |
505 | int pmp = sata_srst_pmp(link); | |
506 | struct ata_port *ap = link->ap; | |
507 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
508 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
509 | void *port_mmio = ahci_port_base(ap); | |
510 | u32 port_fbs; | |
511 | u32 port_fbs_save; | |
512 | u32 retry = 1; | |
513 | u32 rc; | |
514 | ||
515 | port_fbs_save = readl(port_mmio + PORT_FBS); | |
516 | ||
517 | /* | |
518 | * Set PxFBS.DEV field with pmp | |
519 | * value. | |
520 | */ | |
521 | port_fbs = readl(port_mmio + PORT_FBS); | |
522 | port_fbs &= ~PORT_FBS_DEV_MASK; | |
523 | port_fbs |= pmp << PORT_FBS_DEV_OFFSET; | |
524 | writel(port_fbs, port_mmio + PORT_FBS); | |
525 | ||
526 | softreset_retry: | |
527 | rc = ahci_do_softreset(link, class, pmp, | |
528 | deadline, ahci_check_ready); | |
529 | ||
530 | ctx->class[ap->port_no] = *class; | |
531 | if (*class != ATA_DEV_PMP) { | |
532 | /* | |
533 | * Retry for normal drives without | |
534 | * setting PxFBS.DEV field with pmp value. | |
535 | */ | |
536 | if (retry--) { | |
537 | writel(port_fbs_save, port_mmio + PORT_FBS); | |
538 | goto softreset_retry; | |
539 | } | |
540 | } | |
541 | ||
542 | return rc; | |
543 | } | |
544 | ||
81d01bfa LH |
545 | static struct ata_port_operations xgene_ahci_ops = { |
546 | .inherits = &ahci_ops, | |
547 | .host_stop = xgene_ahci_host_stop, | |
548 | .hardreset = xgene_ahci_hardreset, | |
549 | .read_id = xgene_ahci_read_id, | |
2a0bdff6 | 550 | .qc_issue = xgene_ahci_qc_issue, |
a3a84bc7 ST |
551 | .softreset = xgene_ahci_softreset, |
552 | .pmp_softreset = xgene_ahci_pmp_softreset | |
81d01bfa LH |
553 | }; |
554 | ||
555 | static const struct ata_port_info xgene_ahci_port_info = { | |
1540035d | 556 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP, |
81d01bfa LH |
557 | .pio_mask = ATA_PIO4, |
558 | .udma_mask = ATA_UDMA6, | |
559 | .port_ops = &xgene_ahci_ops, | |
560 | }; | |
561 | ||
562 | static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv) | |
563 | { | |
564 | struct xgene_ahci_context *ctx = hpriv->plat_data; | |
565 | int i; | |
566 | int rc; | |
567 | u32 val; | |
568 | ||
569 | /* Remove IP RAM out of shutdown */ | |
570 | rc = xgene_ahci_init_memram(ctx); | |
571 | if (rc) | |
572 | return rc; | |
573 | ||
574 | for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++) | |
575 | xgene_ahci_set_phy_cfg(ctx, i); | |
576 | ||
577 | /* AXI disable Mask */ | |
578 | writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT); | |
579 | readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */ | |
580 | writel(0, ctx->csr_core + INTSTATUSMASK); | |
6a96918a | 581 | val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */ |
81d01bfa LH |
582 | dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n", |
583 | INTSTATUSMASK, val); | |
584 | ||
585 | writel(0x0, ctx->csr_core + ERRINTSTATUSMASK); | |
586 | readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */ | |
587 | writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK); | |
588 | readl(ctx->csr_axi + INT_SLV_TMOMASK); | |
589 | ||
590 | /* Enable AXI Interrupt */ | |
591 | writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES); | |
592 | writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES); | |
593 | writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES); | |
594 | writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES); | |
595 | ||
596 | /* Enable coherency */ | |
597 | val = readl(ctx->csr_core + BUSCTLREG); | |
598 | val &= ~0x00000002; /* Enable write coherency */ | |
599 | val &= ~0x00000001; /* Enable read coherency */ | |
600 | writel(val, ctx->csr_core + BUSCTLREG); | |
601 | ||
602 | val = readl(ctx->csr_core + IOFMSTRWAUX); | |
603 | val |= (1 << 3); /* Enable read coherency */ | |
604 | val |= (1 << 9); /* Enable write coherency */ | |
605 | writel(val, ctx->csr_core + IOFMSTRWAUX); | |
606 | val = readl(ctx->csr_core + IOFMSTRWAUX); | |
607 | dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n", | |
608 | IOFMSTRWAUX, val); | |
609 | ||
610 | return rc; | |
611 | } | |
612 | ||
613 | static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx) | |
614 | { | |
615 | u32 val; | |
616 | ||
617 | /* Check for optional MUX resource */ | |
a77b6ee9 | 618 | if (!ctx->csr_mux) |
81d01bfa LH |
619 | return 0; |
620 | ||
621 | val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
622 | val &= ~CFG_SATA_ENET_SELECT_MASK; | |
623 | writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
624 | val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); | |
625 | return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0; | |
626 | } | |
627 | ||
018d5ef2 AM |
628 | static struct scsi_host_template ahci_platform_sht = { |
629 | AHCI_SHT(DRV_NAME), | |
630 | }; | |
631 | ||
81d01bfa LH |
632 | static int xgene_ahci_probe(struct platform_device *pdev) |
633 | { | |
634 | struct device *dev = &pdev->dev; | |
635 | struct ahci_host_priv *hpriv; | |
636 | struct xgene_ahci_context *ctx; | |
637 | struct resource *res; | |
638 | int rc; | |
639 | ||
640 | hpriv = ahci_platform_get_resources(pdev); | |
641 | if (IS_ERR(hpriv)) | |
642 | return PTR_ERR(hpriv); | |
643 | ||
644 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
645 | if (!ctx) | |
646 | return -ENOMEM; | |
647 | ||
648 | hpriv->plat_data = ctx; | |
649 | ctx->hpriv = hpriv; | |
650 | ctx->dev = dev; | |
651 | ||
652 | /* Retrieve the IP core resource */ | |
653 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
654 | ctx->csr_core = devm_ioremap_resource(dev, res); | |
655 | if (IS_ERR(ctx->csr_core)) | |
656 | return PTR_ERR(ctx->csr_core); | |
657 | ||
658 | /* Retrieve the IP diagnostic resource */ | |
659 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
660 | ctx->csr_diag = devm_ioremap_resource(dev, res); | |
661 | if (IS_ERR(ctx->csr_diag)) | |
662 | return PTR_ERR(ctx->csr_diag); | |
663 | ||
664 | /* Retrieve the IP AXI resource */ | |
665 | res = platform_get_resource(pdev, IORESOURCE_MEM, 3); | |
666 | ctx->csr_axi = devm_ioremap_resource(dev, res); | |
667 | if (IS_ERR(ctx->csr_axi)) | |
668 | return PTR_ERR(ctx->csr_axi); | |
669 | ||
670 | /* Retrieve the optional IP mux resource */ | |
671 | res = platform_get_resource(pdev, IORESOURCE_MEM, 4); | |
a77b6ee9 ST |
672 | if (res) { |
673 | void __iomem *csr = devm_ioremap_resource(dev, res); | |
674 | if (IS_ERR(csr)) | |
675 | return PTR_ERR(csr); | |
676 | ||
677 | ctx->csr_mux = csr; | |
678 | } | |
81d01bfa LH |
679 | |
680 | dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core, | |
681 | hpriv->mmio); | |
682 | ||
683 | /* Select ATA */ | |
684 | if ((rc = xgene_ahci_mux_select(ctx))) { | |
685 | dev_err(dev, "SATA mux selection failed error %d\n", rc); | |
686 | return -ENODEV; | |
687 | } | |
688 | ||
0bed13be ST |
689 | if (xgene_ahci_is_memram_inited(ctx)) { |
690 | dev_info(dev, "skip clock and PHY initialization\n"); | |
691 | goto skip_clk_phy; | |
692 | } | |
693 | ||
81d01bfa LH |
694 | /* Due to errata, HW requires full toggle transition */ |
695 | rc = ahci_platform_enable_clks(hpriv); | |
696 | if (rc) | |
697 | goto disable_resources; | |
698 | ahci_platform_disable_clks(hpriv); | |
699 | ||
700 | rc = ahci_platform_enable_resources(hpriv); | |
701 | if (rc) | |
702 | goto disable_resources; | |
703 | ||
704 | /* Configure the host controller */ | |
705 | xgene_ahci_hw_init(hpriv); | |
0bed13be | 706 | skip_clk_phy: |
72f79f9e | 707 | hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ; |
f9f36917 | 708 | |
018d5ef2 AM |
709 | rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info, |
710 | &ahci_platform_sht); | |
81d01bfa LH |
711 | if (rc) |
712 | goto disable_resources; | |
713 | ||
714 | dev_dbg(dev, "X-Gene SATA host controller initialized\n"); | |
715 | return 0; | |
716 | ||
717 | disable_resources: | |
718 | ahci_platform_disable_resources(hpriv); | |
719 | return rc; | |
720 | } | |
721 | ||
92b5bf98 FK |
722 | #ifdef CONFIG_ACPI |
723 | static const struct acpi_device_id xgene_ahci_acpi_match[] = { | |
724 | { "APMC0D0D", }, | |
725 | { } | |
726 | }; | |
727 | MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match); | |
728 | #endif | |
729 | ||
81d01bfa LH |
730 | static const struct of_device_id xgene_ahci_of_match[] = { |
731 | {.compatible = "apm,xgene-ahci"}, | |
732 | {}, | |
733 | }; | |
734 | MODULE_DEVICE_TABLE(of, xgene_ahci_of_match); | |
735 | ||
736 | static struct platform_driver xgene_ahci_driver = { | |
737 | .probe = xgene_ahci_probe, | |
738 | .remove = ata_platform_remove_one, | |
739 | .driver = { | |
018d5ef2 | 740 | .name = DRV_NAME, |
81d01bfa | 741 | .of_match_table = xgene_ahci_of_match, |
92b5bf98 | 742 | .acpi_match_table = ACPI_PTR(xgene_ahci_acpi_match), |
81d01bfa LH |
743 | }, |
744 | }; | |
745 | ||
746 | module_platform_driver(xgene_ahci_driver); | |
747 | ||
748 | MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver"); | |
749 | MODULE_AUTHOR("Loc Ho <lho@apm.com>"); | |
750 | MODULE_LICENSE("GPL"); | |
751 | MODULE_VERSION("0.4"); |