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[libata] pata_cs5535: fix build
[deliverable/linux.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
fc085150 96#define DRV_VERSION "2.00ac7"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
228c1590
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS | ATA_FLAG_DETECT_POLLING,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
110 ATA_FLAG_DETECT_POLLING,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b 121 /* controller IDs */
669a5db4
JG		 122 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 ich_pata_133 = 4, /* ICH up to UDMA 133 */
127 ich5_sata = 5,
5e56a37c
TH		 128 ich6_sata = 6,
129 ich6_sata_ahci = 7,
130 ich6m_sata_ahci = 8,
131 ich8_sata_ahci = 9,
85cd7251 132
d33f58b8
TH		 133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
7b6dbd68 142 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 143};
144
d33f58b8
TH		 145struct piix_map_db {
146 const u32 mask;
73291a1c 147 const u16 port_enable;
d33f58b8
TH		 148 const int map[][4];
149};
150
d96715c1
TH		 151struct piix_host_priv {
152 const int *map;
153};
154
1da177e4
LT		 155static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
cca3974e 157static void piix_host_stop(struct ata_host *host);
ccc4672a 158static void piix_pata_error_handler(struct ata_port *ap);
669a5db4 159static void ich_pata_error_handler(struct ata_port *ap);
ccc4672a 160static void piix_sata_error_handler(struct ata_port *ap);
669a5db4
JG		 161static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
1da177e4
LT		 164
165static unsigned int in_module_init = 1;
166
3b7d697d 167static const struct pci_device_id piix_pci_tbl[] = {
1da177e4 168#ifdef ATA_ENABLE_PATA
669a5db4
JG		 169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
172 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX4 */
177 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX */
179 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel ICH (i810, i815, i840) UDMA 66*/
181 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
182 /* Intel ICH0 : UDMA 33*/
183 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
184 /* Intel ICH2M */
185 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
187 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3M */
189 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH3 (E7500/1) UDMA 100 */
191 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
193 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH5 */
196 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
197 /* C-ICH (i810E2) */
198 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 199 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 200 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH6 (and 6) (i915) UDMA 100 */
202 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH7/7-R (i945, i975) UDMA 100*/
204 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
205 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 206#endif
207
208 /* NOTE: The following PCI ids must be kept in sync with the
209 * list in drivers/pci/quirks.c.
210 */
211
1d076e5b 212 /* 82801EB (ICH5) */
1da177e4 213 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 214 /* 82801EB (ICH5) */
1da177e4 215 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 216 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 217 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 218 /* 6300ESB pretending RAID */
5e56a37c 219 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 220 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 221 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 222 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 223 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 224 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
225 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
226 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 227 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 228 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 229 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1d076e5b 230 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 231 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 232 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
08f12edc 233 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 234 /* SATA Controller 2 IDE (ICH8, ditto) */
08f12edc 235 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 236 /* Mobile SATA Controller IDE (ICH8M, ditto) */
08f12edc 237 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 238
239 { } /* terminate list */
240};
241
242static struct pci_driver piix_pci_driver = {
243 .name = DRV_NAME,
244 .id_table = piix_pci_tbl,
245 .probe = piix_init_one,
246 .remove = ata_pci_remove_one,
9b847548
JA		 247 .suspend = ata_pci_device_suspend,
248 .resume = ata_pci_device_resume,
1da177e4
LT		 249};
250
193515d5 251static struct scsi_host_template piix_sht = {
1da177e4
LT		 252 .module = THIS_MODULE,
253 .name = DRV_NAME,
254 .ioctl = ata_scsi_ioctl,
255 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 256 .can_queue = ATA_DEF_QUEUE,
257 .this_id = ATA_SHT_THIS_ID,
258 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 259 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
260 .emulated = ATA_SHT_EMULATED,
261 .use_clustering = ATA_SHT_USE_CLUSTERING,
262 .proc_name = DRV_NAME,
263 .dma_boundary = ATA_DMA_BOUNDARY,
264 .slave_configure = ata_scsi_slave_config,
ccf68c34 265 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 266 .bios_param = ata_std_bios_param,
9b847548
JA		 267 .resume = ata_scsi_device_resume,
268 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 269};
270
057ace5e 271static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 272 .port_disable = ata_port_disable,
273 .set_piomode = piix_set_piomode,
274 .set_dmamode = piix_set_dmamode,
89bad589 275 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 276
277 .tf_load = ata_tf_load,
278 .tf_read = ata_tf_read,
279 .check_status = ata_check_status,
280 .exec_command = ata_exec_command,
281 .dev_select = ata_std_dev_select,
282
1da177e4
LT		 283 .bmdma_setup = ata_bmdma_setup,
284 .bmdma_start = ata_bmdma_start,
285 .bmdma_stop = ata_bmdma_stop,
286 .bmdma_status = ata_bmdma_status,
287 .qc_prep = ata_qc_prep,
288 .qc_issue = ata_qc_issue_prot,
89bad589 289 .data_xfer = ata_pio_data_xfer,
1da177e4 290
3f037db0
TH		 291 .freeze = ata_bmdma_freeze,
292 .thaw = ata_bmdma_thaw,
ccc4672a 293 .error_handler = piix_pata_error_handler,
3f037db0 294 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 295
296 .irq_handler = ata_interrupt,
297 .irq_clear = ata_bmdma_irq_clear,
298
299 .port_start = ata_port_start,
300 .port_stop = ata_port_stop,
d96715c1 301 .host_stop = piix_host_stop,
1da177e4
LT		 302};
303
669a5db4
JG		 304static const struct ata_port_operations ich_pata_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = piix_set_piomode,
307 .set_dmamode = ich_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .bmdma_setup = ata_bmdma_setup,
317 .bmdma_start = ata_bmdma_start,
318 .bmdma_stop = ata_bmdma_stop,
319 .bmdma_status = ata_bmdma_status,
320 .qc_prep = ata_qc_prep,
321 .qc_issue = ata_qc_issue_prot,
322 .data_xfer = ata_pio_data_xfer,
323
324 .freeze = ata_bmdma_freeze,
325 .thaw = ata_bmdma_thaw,
326 .error_handler = ich_pata_error_handler,
327 .post_internal_cmd = ata_bmdma_post_internal_cmd,
328
329 .irq_handler = ata_interrupt,
330 .irq_clear = ata_bmdma_irq_clear,
331
332 .port_start = ata_port_start,
333 .port_stop = ata_port_stop,
334 .host_stop = ata_host_stop,
335};
336
057ace5e 337static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 338 .port_disable = ata_port_disable,
339
340 .tf_load = ata_tf_load,
341 .tf_read = ata_tf_read,
342 .check_status = ata_check_status,
343 .exec_command = ata_exec_command,
344 .dev_select = ata_std_dev_select,
345
1da177e4
LT		 346 .bmdma_setup = ata_bmdma_setup,
347 .bmdma_start = ata_bmdma_start,
348 .bmdma_stop = ata_bmdma_stop,
349 .bmdma_status = ata_bmdma_status,
350 .qc_prep = ata_qc_prep,
351 .qc_issue = ata_qc_issue_prot,
89bad589 352 .data_xfer = ata_pio_data_xfer,
1da177e4 353
3f037db0
TH		 354 .freeze = ata_bmdma_freeze,
355 .thaw = ata_bmdma_thaw,
ccc4672a 356 .error_handler = piix_sata_error_handler,
3f037db0 357 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 358
359 .irq_handler = ata_interrupt,
360 .irq_clear = ata_bmdma_irq_clear,
361
362 .port_start = ata_port_start,
363 .port_stop = ata_port_stop,
d96715c1 364 .host_stop = piix_host_stop,
1da177e4
LT		 365};
366
d96715c1 367static const struct piix_map_db ich5_map_db = {
d33f58b8 368 .mask = 0x7,
ea35d29e 369 .port_enable = 0x3,
d33f58b8
TH		 370 .map = {
371 /* PM PS SM SS MAP */
372 { P0, NA, P1, NA }, /* 000b */
373 { P1, NA, P0, NA }, /* 001b */
374 { RV, RV, RV, RV },
375 { RV, RV, RV, RV },
376 { P0, P1, IDE, IDE }, /* 100b */
377 { P1, P0, IDE, IDE }, /* 101b */
378 { IDE, IDE, P0, P1 }, /* 110b */
379 { IDE, IDE, P1, P0 }, /* 111b */
380 },
381};
382
d96715c1 383static const struct piix_map_db ich6_map_db = {
d33f58b8 384 .mask = 0x3,
ea35d29e 385 .port_enable = 0xf,
d33f58b8
TH		 386 .map = {
387 /* PM PS SM SS MAP */
79ea24e7 388 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 389 { IDE, IDE, P1, P3 }, /* 01b */
390 { P0, P2, IDE, IDE }, /* 10b */
391 { RV, RV, RV, RV },
392 },
393};
394
d96715c1 395static const struct piix_map_db ich6m_map_db = {
d33f58b8 396 .mask = 0x3,
ea35d29e 397 .port_enable = 0x5,
67083741
TH		 398
399 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 400 * it anyway. MAP 01b have been spotted on both ICH6M and
401 * ICH7M.
67083741
TH		 402 */
403 .map = {
404 /* PM PS SM SS MAP */
405 { P0, P2, RV, RV }, /* 00b */
406 { IDE, IDE, P1, P3 }, /* 01b */
407 { P0, P2, IDE, IDE }, /* 10b */
408 { RV, RV, RV, RV },
409 },
410};
411
08f12edc
JG		 412static const struct piix_map_db ich8_map_db = {
413 .mask = 0x3,
414 .port_enable = 0x3,
08f12edc
JG		 415 .map = {
416 /* PM PS SM SS MAP */
158f30c8 417 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 418 { RV, RV, RV, RV },
158f30c8 419 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
08f12edc
JG		 420 { RV, RV, RV, RV },
421 },
422};
423
d96715c1
TH		 424static const struct piix_map_db *piix_map_db_table[] = {
425 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 426 [ich6_sata] = &ich6_map_db,
427 [ich6_sata_ahci] = &ich6_map_db,
428 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 429 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 430};
431
1da177e4 432static struct ata_port_info piix_port_info[] = {
669a5db4 433 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
1d076e5b
TH		 434 {
435 .sht = &piix_sht,
b3362f88 436 .flags = PIIX_PATA_FLAGS,
1d076e5b 437 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 438 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 439 .udma_mask = ATA_UDMA_MASK_40C,
440 .port_ops = &piix_pata_ops,
441 },
442
669a5db4
JG		 443 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
444 {
445 .sht = &piix_sht,
b3362f88 446 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 447 .pio_mask = 0x1f, /* pio 0-4 */
448 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
449 .udma_mask = ATA_UDMA2, /* UDMA33 */
450 .port_ops = &ich_pata_ops,
451 },
452 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 453 {
454 .sht = &piix_sht,
b3362f88 455 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 456 .pio_mask = 0x1f, /* pio 0-4 */
457 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
458 .udma_mask = ATA_UDMA4,
459 .port_ops = &ich_pata_ops,
460 },
85cd7251 461
669a5db4
JG		 462 /* ich_pata_100: 3 */
463 {
464 .sht = &piix_sht,
b3362f88 465 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 466 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 467 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 468 .udma_mask = ATA_UDMA5, /* udma0-5 */
469 .port_ops = &ich_pata_ops,
1da177e4
LT		 470 },
471
669a5db4
JG		 472 /* ich_pata_133: 4 ICH with full UDMA6 */
473 {
474 .sht = &piix_sht,
b3362f88 475 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 476 .pio_mask = 0x1f, /* pio 0-4 */
477 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
478 .udma_mask = ATA_UDMA6, /* UDMA133 */
479 .port_ops = &ich_pata_ops,
480 },
481
482 /* ich5_sata: 5 */
1da177e4
LT		 483 {
484 .sht = &piix_sht,
228c1590 485 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 486 .pio_mask = 0x1f, /* pio0-4 */
487 .mwdma_mask = 0x07, /* mwdma0-2 */
488 .udma_mask = 0x7f, /* udma0-6 */
489 .port_ops = &piix_sata_ops,
490 },
491
5e56a37c 492 /* ich6_sata: 6 */
1da177e4
LT		 493 {
494 .sht = &piix_sht,
b3362f88 495 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 496 .pio_mask = 0x1f, /* pio0-4 */
497 .mwdma_mask = 0x07, /* mwdma0-2 */
498 .udma_mask = 0x7f, /* udma0-6 */
499 .port_ops = &piix_sata_ops,
500 },
501
5e56a37c 502 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 503 {
504 .sht = &piix_sht,
b3362f88 505 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 506 PIIX_FLAG_AHCI,
c368ca4e
JG		 507 .pio_mask = 0x1f, /* pio0-4 */
508 .mwdma_mask = 0x07, /* mwdma0-2 */
509 .udma_mask = 0x7f, /* udma0-6 */
510 .port_ops = &piix_sata_ops,
511 },
1d076e5b 512
5e56a37c 513 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 514 {
515 .sht = &piix_sht,
b3362f88 516 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 517 PIIX_FLAG_AHCI,
1d076e5b
TH		 518 .pio_mask = 0x1f, /* pio0-4 */
519 .mwdma_mask = 0x07, /* mwdma0-2 */
520 .udma_mask = 0x7f, /* udma0-6 */
521 .port_ops = &piix_sata_ops,
522 },
08f12edc 523
5e56a37c 524 /* ich8_sata_ahci: 9 */
08f12edc
JG		 525 {
526 .sht = &piix_sht,
b3362f88 527 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 528 PIIX_FLAG_AHCI,
529 .pio_mask = 0x1f, /* pio0-4 */
530 .mwdma_mask = 0x07, /* mwdma0-2 */
531 .udma_mask = 0x7f, /* udma0-6 */
532 .port_ops = &piix_sata_ops,
533 },
669a5db4 534
1da177e4
LT		 535};
536
537static struct pci_bits piix_enable_bits[] = {
538 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
539 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
540};
541
542MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
543MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
544MODULE_LICENSE("GPL");
545MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
546MODULE_VERSION(DRV_VERSION);
547
fc085150
AC		 548struct ich_laptop {
549 u16 device;
550 u16 subvendor;
551 u16 subdevice;
552};
553
554/*
555 * List of laptops that use short cables rather than 80 wire
556 */
557
558static const struct ich_laptop ich_laptop[] = {
559 /* devid, subvendor, subdev */
560 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
561 /* end marker */
562 { 0, }
563};
564
1da177e4
LT		 565/**
566 * piix_pata_cbl_detect - Probe host controller cable detect info
567 * @ap: Port for which cable detect info is desired
568 *
569 * Read 80c cable indicator from ATA PCI device's PCI config
570 * register. This register is normally set by firmware (BIOS).
571 *
572 * LOCKING:
573 * None (inherited from caller).
574 */
669a5db4
JG		 575
576static void ich_pata_cbl_detect(struct ata_port *ap)
1da177e4 577{
cca3974e 578 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 579 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 580 u8 tmp, mask;
581
582 /* no 80c support in host controller? */
583 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
584 goto cbl40;
585
fc085150
AC		 586 /* Check for specials - Acer Aspire 5602WLMi */
587 while (lap->device) {
588 if (lap->device == pdev->device &&
589 lap->subvendor == pdev->subsystem_vendor &&
590 lap->subdevice == pdev->subsystem_device) {
591 ap->cbl = ATA_CBL_PATA40_SHORT;
592 return;
593 }
594 lap++;
595 }
596
1da177e4 597 /* check BIOS cable detect results */
2a88d1ac 598 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 599 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
600 if ((tmp & mask) == 0)
601 goto cbl40;
602
603 ap->cbl = ATA_CBL_PATA80;
604 return;
605
606cbl40:
607 ap->cbl = ATA_CBL_PATA40;
1da177e4
LT		 608}
609
610/**
ccc4672a 611 * piix_pata_prereset - prereset for PATA host controller
573db6b8 612 * @ap: Target port
1da177e4 613 *
573db6b8
TH		 614 *
615 * LOCKING:
616 * None (inherited from caller).
617 */
ccc4672a 618static int piix_pata_prereset(struct ata_port *ap)
1da177e4 619{
cca3974e 620 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 621
c961922b
AC		 622 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
623 return -ENOENT;
624
669a5db4 625 ap->cbl = ATA_CBL_PATA40;
ccc4672a
TH		 626 return ata_std_prereset(ap);
627}
628
629static void piix_pata_error_handler(struct ata_port *ap)
630{
631 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
632 ata_std_postreset);
1da177e4
LT		 633}
634
669a5db4
JG		 635
636/**
637 * ich_pata_prereset - prereset for PATA host controller
638 * @ap: Target port
639 *
640 *
641 * LOCKING:
642 * None (inherited from caller).
643 */
644static int ich_pata_prereset(struct ata_port *ap)
645{
646 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
647
648 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
649 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
650 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
651 return 0;
652 }
653
654 ich_pata_cbl_detect(ap);
655
656 return ata_std_prereset(ap);
657}
658
659static void ich_pata_error_handler(struct ata_port *ap)
660{
661 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
662 ata_std_postreset);
663}
664
ccc4672a
TH		 665static void piix_sata_error_handler(struct ata_port *ap)
666{
228c1590 667 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
ccc4672a 668 ata_std_postreset);
1da177e4
LT		 669}
670
671/**
672 * piix_set_piomode - Initialize host controller PATA PIO timings
673 * @ap: Port whose timings we are configuring
674 * @adev: um
1da177e4
LT		 675 *
676 * Set PIO mode for device, in host controller PCI config space.
677 *
678 * LOCKING:
679 * None (inherited from caller).
680 */
681
682static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
683{
684 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 685 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 686 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 687 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 688 unsigned int slave_port = 0x44;
689 u16 master_data;
690 u8 slave_data;
669a5db4
JG		 691 u8 udma_enable;
692 int control = 0;
85cd7251 693
669a5db4
JG		 694 /*
695 * See Intel Document 298600-004 for the timing programing rules
696 * for ICH controllers.
697 */
1da177e4
LT		 698
699 static const /* ISP RTC */
700 u8 timings[][2] = { { 0, 0 },
701 { 0, 0 },
702 { 1, 0 },
703 { 2, 1 },
704 { 2, 3 }, };
705
669a5db4
JG		 706 if (pio >= 2)
707 control |= 1; /* TIME1 enable */
708 if (ata_pio_need_iordy(adev))
709 control |= 2; /* IE enable */
710
85cd7251 711 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 712 if (adev->class == ATA_DEV_ATA)
713 control |= 4; /* PPE enable */
714
1da177e4
LT		 715 pci_read_config_word(dev, master_port, &master_data);
716 if (is_slave) {
669a5db4 717 /* Enable SITRE (seperate slave timing register) */
1da177e4 718 master_data |= 0x4000;
669a5db4
JG		 719 /* enable PPE1, IE1 and TIME1 as needed */
720 master_data |= (control << 4);
1da177e4 721 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 722 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 723 /* Load the timing nibble for this slave */
724 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 725 } else {
669a5db4 726 /* Master keeps the bits in a different format */
1da177e4 727 master_data &= 0xccf8;
669a5db4
JG		 728 /* Enable PPE, IE and TIME as appropriate */
729 master_data |= control;
1da177e4
LT		 730 master_data |=
731 (timings[pio][0] << 12) |
732 (timings[pio][1] << 8);
733 }
734 pci_write_config_word(dev, master_port, master_data);
735 if (is_slave)
736 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 737
738 /* Ensure the UDMA bit is off - it will be turned back on if
739 UDMA is selected */
85cd7251 740
669a5db4
JG		 741 if (ap->udma_mask) {
742 pci_read_config_byte(dev, 0x48, &udma_enable);
743 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
744 pci_write_config_byte(dev, 0x48, udma_enable);
745 }
1da177e4
LT		 746}
747
748/**
669a5db4 749 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 750 * @ap: Port whose timings we are configuring
669a5db4 751 * @adev: Drive in question
1da177e4 752 * @udma: udma mode, 0 - 6
c32a8fd7 753 * @isich: set if the chip is an ICH device
1da177e4
LT		 754 *
755 * Set UDMA mode for device, in host controller PCI config space.
756 *
757 * LOCKING:
758 * None (inherited from caller).
759 */
760
669a5db4 761static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 762{
cca3974e 763 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 764 u8 master_port = ap->port_no ? 0x42 : 0x40;
765 u16 master_data;
766 u8 speed = adev->dma_mode;
767 int devid = adev->devno + 2 * ap->port_no;
768 u8 udma_enable;
85cd7251 769
669a5db4
JG		 770 static const /* ISP RTC */
771 u8 timings[][2] = { { 0, 0 },
772 { 0, 0 },
773 { 1, 0 },
774 { 2, 1 },
775 { 2, 3 }, };
776
777 pci_read_config_word(dev, master_port, &master_data);
778 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 779
780 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 781 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
782 u16 udma_timing;
783 u16 ideconf;
784 int u_clock, u_speed;
85cd7251 785
669a5db4
JG		 786 /*
787 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 788 * selection of dividers
789 *
669a5db4 790 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 791 * except UDMA0 which is 00
669a5db4
JG		 792 */
793 u_speed = min(2 - (udma & 1), udma);
794 if (udma == 5)
795 u_clock = 0x1000; /* 100Mhz */
796 else if (udma > 2)
797 u_clock = 1; /* 66Mhz */
798 else
799 u_clock = 0; /* 33Mhz */
85cd7251 800
669a5db4 801 udma_enable |= (1 << devid);
85cd7251 802
669a5db4
JG		 803 /* Load the CT/RP selection */
804 pci_read_config_word(dev, 0x4A, &udma_timing);
805 udma_timing &= ~(3 << (4 * devid));
806 udma_timing |= u_speed << (4 * devid);
807 pci_write_config_word(dev, 0x4A, udma_timing);
808
85cd7251 809 if (isich) {
669a5db4
JG		 810 /* Select a 33/66/100Mhz clock */
811 pci_read_config_word(dev, 0x54, &ideconf);
812 ideconf &= ~(0x1001 << devid);
813 ideconf |= u_clock << devid;
814 /* For ICH or later we should set bit 10 for better
815 performance (WR_PingPong_En) */
816 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 817 }
1da177e4 818 } else {
669a5db4
JG		 819 /*
820 * MWDMA is driven by the PIO timings. We must also enable
821 * IORDY unconditionally along with TIME1. PPE has already
822 * been set when the PIO timing was set.
823 */
824 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
825 unsigned int control;
826 u8 slave_data;
827 const unsigned int needed_pio[3] = {
828 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
829 };
830 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 831
669a5db4 832 control = 3; /* IORDY|TIME1 */
85cd7251 833
669a5db4
JG		 834 /* If the drive MWDMA is faster than it can do PIO then
835 we must force PIO into PIO0 */
85cd7251 836
669a5db4
JG		 837 if (adev->pio_mode < needed_pio[mwdma])
838 /* Enable DMA timing only */
839 control |= 8; /* PIO cycles in PIO0 */
840
841 if (adev->devno) { /* Slave */
842 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
843 master_data |= control << 4;
844 pci_read_config_byte(dev, 0x44, &slave_data);
845 slave_data &= (0x0F + 0xE1 * ap->port_no);
846 /* Load the matching timing */
847 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
848 pci_write_config_byte(dev, 0x44, slave_data);
849 } else { /* Master */
85cd7251 850 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 851 and master timing bits */
852 master_data |= control;
853 master_data |=
854 (timings[pio][0] << 12) |
855 (timings[pio][1] << 8);
856 }
857 udma_enable &= ~(1 << devid);
858 pci_write_config_word(dev, master_port, master_data);
1da177e4 859 }
669a5db4
JG		 860 /* Don't scribble on 0x48 if the controller does not support UDMA */
861 if (ap->udma_mask)
862 pci_write_config_byte(dev, 0x48, udma_enable);
863}
864
865/**
866 * piix_set_dmamode - Initialize host controller PATA DMA timings
867 * @ap: Port whose timings we are configuring
868 * @adev: um
869 *
870 * Set MW/UDMA mode for device, in host controller PCI config space.
871 *
872 * LOCKING:
873 * None (inherited from caller).
874 */
875
876static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
877{
878 do_pata_set_dmamode(ap, adev, 0);
879}
880
881/**
882 * ich_set_dmamode - Initialize host controller PATA DMA timings
883 * @ap: Port whose timings we are configuring
884 * @adev: um
885 *
886 * Set MW/UDMA mode for device, in host controller PCI config space.
887 *
888 * LOCKING:
889 * None (inherited from caller).
890 */
891
892static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
893{
894 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 895}
896
1da177e4
LT		 897#define AHCI_PCI_BAR 5
898#define AHCI_GLOBAL_CTL 0x04
899#define AHCI_ENABLE (1 << 31)
900static int piix_disable_ahci(struct pci_dev *pdev)
901{
ea6ba10b 902 void __iomem *mmio;
1da177e4
LT		 903 u32 tmp;
904 int rc = 0;
905
906 /* BUG: pci_enable_device has not yet been called. This
907 * works because this device is usually set up by BIOS.
908 */
909
374b1873
JG		 910 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
911 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 912 return 0;
7b6dbd68 913
374b1873 914 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 915 if (!mmio)
916 return -ENOMEM;
7b6dbd68 917
1da177e4
LT		 918 tmp = readl(mmio + AHCI_GLOBAL_CTL);
919 if (tmp & AHCI_ENABLE) {
920 tmp &= ~AHCI_ENABLE;
921 writel(tmp, mmio + AHCI_GLOBAL_CTL);
922
923 tmp = readl(mmio + AHCI_GLOBAL_CTL);
924 if (tmp & AHCI_ENABLE)
925 rc = -EIO;
926 }
7b6dbd68 927
374b1873 928 pci_iounmap(pdev, mmio);
1da177e4
LT		 929 return rc;
930}
931
c621b140
AC		 932/**
933 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 934 * @ata_dev: the PCI device to check
2e9edbf8 935 *
c621b140
AC		 936 * Check for the present of 450NX errata #19 and errata #25. If
937 * they are found return an error code so we can turn off DMA
938 */
939
940static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
941{
942 struct pci_dev *pdev = NULL;
943 u16 cfg;
944 u8 rev;
945 int no_piix_dma = 0;
2e9edbf8 946
c621b140
AC		 947 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
948 {
949 /* Look for 450NX PXB. Check for problem configurations
950 A PCI quirk checks bit 6 already */
951 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
952 pci_read_config_word(pdev, 0x41, &cfg);
953 /* Only on the original revision: IDE DMA can hang */
31a34fe7 954 if (rev == 0x00)
c621b140
AC		 955 no_piix_dma = 1;
956 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 957 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 958 no_piix_dma = 2;
959 }
31a34fe7 960 if (no_piix_dma)
c621b140 961 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 962 if (no_piix_dma == 2)
c621b140
AC		 963 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
964 return no_piix_dma;
2e9edbf8 965}
c621b140 966
ea35d29e 967static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 968 struct ata_port_info *pinfo,
ea35d29e
JG		 969 const struct piix_map_db *map_db)
970{
971 u16 pcs, new_pcs;
972
973 pci_read_config_word(pdev, ICH5_PCS, &pcs);
974
975 new_pcs = pcs | map_db->port_enable;
976
977 if (new_pcs != pcs) {
978 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
979 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
980 msleep(150);
981 }
982}
983
d33f58b8 984static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 985 struct ata_port_info *pinfo,
986 const struct piix_map_db *map_db)
d33f58b8 987{
d96715c1 988 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 989 const unsigned int *map;
990 int i, invalid_map = 0;
991 u8 map_value;
992
993 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
994
995 map = map_db->map[map_value & map_db->mask];
996
997 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
998 for (i = 0; i < 4; i++) {
999 switch (map[i]) {
1000 case RV:
1001 invalid_map = 1;
1002 printk(" XX");
1003 break;
1004
1005 case NA:
1006 printk(" --");
1007 break;
1008
1009 case IDE:
1010 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1011 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1012 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1013 i++;
1014 printk(" IDE IDE");
1015 break;
1016
1017 default:
1018 printk(" P%d", map[i]);
1019 if (i & 1)
cca3974e 1020 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1021 break;
1022 }
1023 }
1024 printk(" ]\n");
1025
1026 if (invalid_map)
1027 dev_printk(KERN_ERR, &pdev->dev,
1028 "invalid MAP value %u\n", map_value);
1029
d96715c1 1030 hpriv->map = map;
d33f58b8
TH		 1031}
1032
1da177e4
LT		 1033/**
1034 * piix_init_one - Register PIIX ATA PCI device with kernel services
1035 * @pdev: PCI device to register
1036 * @ent: Entry in piix_pci_tbl matching with @pdev
1037 *
1038 * Called from kernel PCI layer. We probe for combined mode (sigh),
1039 * and then hand over control to libata, for it to do the rest.
1040 *
1041 * LOCKING:
1042 * Inherited from PCI layer (may sleep).
1043 *
1044 * RETURNS:
1045 * Zero on success, or -ERRNO value.
1046 */
1047
1048static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1049{
1050 static int printed_version;
d33f58b8
TH		 1051 struct ata_port_info port_info[2];
1052 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 1053 struct piix_host_priv *hpriv;
cca3974e 1054 unsigned long port_flags;
1da177e4
LT		 1055
1056 if (!printed_version++)
6248e647
JG		 1057 dev_printk(KERN_DEBUG, &pdev->dev,
1058 "version " DRV_VERSION "\n");
1da177e4
LT		 1059
1060 /* no hotplugging support (FIXME) */
1061 if (!in_module_init)
1062 return -ENODEV;
1063
d96715c1
TH		 1064 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1065 if (!hpriv)
1066 return -ENOMEM;
1067
d33f58b8
TH		 1068 port_info[0] = piix_port_info[ent->driver_data];
1069 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1070 port_info[0].private_data = hpriv;
1071 port_info[1].private_data = hpriv;
1da177e4 1072
cca3974e 1073 port_flags = port_info[0].flags;
ff0fc146 1074
cca3974e 1075 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1076 u8 tmp;
1077 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1078 if (tmp == PIIX_AHCI_DEVICE) {
1079 int rc = piix_disable_ahci(pdev);
1080 if (rc)
1081 return rc;
1082 }
1da177e4
LT		 1083 }
1084
d33f58b8 1085 /* Initialize SATA map */
cca3974e 1086 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1087 piix_init_sata_map(pdev, port_info,
1088 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1089 piix_init_pcs(pdev, port_info,
1090 piix_map_db_table[ent->driver_data]);
ea35d29e 1091 }
1da177e4
LT		 1092
1093 /* On ICH5, some BIOSen disable the interrupt using the
1094 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1095 * On ICH6, this bit has the same effect, but only when
1096 * MSI is disabled (and it is disabled, as we don't use
1097 * message-signalled interrupts currently).
1098 */
cca3974e 1099 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1100 pci_intx(pdev, 1);
1da177e4 1101
c621b140
AC		 1102 if (piix_check_450nx_errata(pdev)) {
1103 /* This writes into the master table but it does not
1104 really matter for this errata as we will apply it to
1105 all the PIIX devices on the board */
d33f58b8
TH		 1106 port_info[0].mwdma_mask = 0;
1107 port_info[0].udma_mask = 0;
1108 port_info[1].mwdma_mask = 0;
1109 port_info[1].udma_mask = 0;
c621b140 1110 }
d33f58b8 1111 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 1112}
1113
cca3974e 1114static void piix_host_stop(struct ata_host *host)
d96715c1 1115{
cca3974e 1116 struct piix_host_priv *hpriv = host->private_data;
24dd01bf 1117
cca3974e 1118 ata_host_stop(host);
24dd01bf
JG		 1119
1120 kfree(hpriv);
d96715c1
TH		 1121}
1122
1da177e4
LT		 1123static int __init piix_init(void)
1124{
1125 int rc;
1126
b7887196
PR		 1127 DPRINTK("pci_register_driver\n");
1128 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1129 if (rc)
1130 return rc;
1131
1132 in_module_init = 0;
1133
1134 DPRINTK("done\n");
1135 return 0;
1136}
1137
1da177e4
LT		 1138static void __exit piix_exit(void)
1139{
1140 pci_unregister_driver(&piix_pci_driver);
1141}
1142
1143module_init(piix_init);
1144module_exit(piix_exit);
Linux kernel - Deliverables
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