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ahci: EM message type auto detect
[deliverable/linux.git] / drivers / ata / libahci.c
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365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59static int ahci_enable_alpm(struct ata_port *ap,
60 enum link_pm policy);
61static void ahci_disable_alpm(struct ata_port *ap);
62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88static void ahci_postreset(struct ata_link *link, unsigned int *class);
89static void ahci_error_handler(struct ata_port *ap);
90static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91static int ahci_port_resume(struct ata_port *ap);
92static void ahci_dev_config(struct ata_device *dev);
93static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
94 u32 opts);
95#ifdef CONFIG_PM
96static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97#endif
98static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101static void ahci_init_sw_activity(struct ata_link *link);
102
103static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
111
112static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
113static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
114static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
115static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
116
117static struct device_attribute *ahci_shost_attrs[] = {
118 &dev_attr_link_power_management_policy,
119 &dev_attr_em_message_type,
120 &dev_attr_em_message,
121 &dev_attr_ahci_host_caps,
122 &dev_attr_ahci_host_cap2,
123 &dev_attr_ahci_host_version,
124 &dev_attr_ahci_port_cmd,
125 NULL
126};
127
128static struct device_attribute *ahci_sdev_attrs[] = {
129 &dev_attr_sw_activity,
130 &dev_attr_unload_heads,
131 NULL
132};
133
134struct scsi_host_template ahci_sht = {
135 ATA_NCQ_SHT("ahci"),
136 .can_queue = AHCI_MAX_CMDS - 1,
137 .sg_tablesize = AHCI_MAX_SG,
138 .dma_boundary = AHCI_DMA_BOUNDARY,
139 .shost_attrs = ahci_shost_attrs,
140 .sdev_attrs = ahci_sdev_attrs,
141};
142EXPORT_SYMBOL_GPL(ahci_sht);
143
144struct ata_port_operations ahci_ops = {
145 .inherits = &sata_pmp_port_ops,
146
147 .qc_defer = ahci_pmp_qc_defer,
148 .qc_prep = ahci_qc_prep,
149 .qc_issue = ahci_qc_issue,
150 .qc_fill_rtf = ahci_qc_fill_rtf,
151
152 .freeze = ahci_freeze,
153 .thaw = ahci_thaw,
154 .softreset = ahci_softreset,
155 .hardreset = ahci_hardreset,
156 .postreset = ahci_postreset,
157 .pmp_softreset = ahci_softreset,
158 .error_handler = ahci_error_handler,
159 .post_internal_cmd = ahci_post_internal_cmd,
160 .dev_config = ahci_dev_config,
161
162 .scr_read = ahci_scr_read,
163 .scr_write = ahci_scr_write,
164 .pmp_attach = ahci_pmp_attach,
165 .pmp_detach = ahci_pmp_detach,
166
167 .enable_pm = ahci_enable_alpm,
168 .disable_pm = ahci_disable_alpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173#ifdef CONFIG_PM
174 .port_suspend = ahci_port_suspend,
175 .port_resume = ahci_port_resume,
176#endif
177 .port_start = ahci_port_start,
178 .port_stop = ahci_port_stop,
179};
180EXPORT_SYMBOL_GPL(ahci_ops);
181
182int ahci_em_messages = 1;
183EXPORT_SYMBOL_GPL(ahci_em_messages);
184module_param(ahci_em_messages, int, 0444);
185/* add other LED protocol types when they become supported */
186MODULE_PARM_DESC(ahci_em_messages,
008dbd61 187 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e
AV		 188
189static void ahci_enable_ahci(void __iomem *mmio)
190{
191 int i;
192 u32 tmp;
193
194 /* turn on AHCI_EN */
195 tmp = readl(mmio + HOST_CTL);
196 if (tmp & HOST_AHCI_EN)
197 return;
198
199 /* Some controllers need AHCI_EN to be written multiple times.
200 * Try a few times before giving up.
201 */
202 for (i = 0; i < 5; i++) {
203 tmp |= HOST_AHCI_EN;
204 writel(tmp, mmio + HOST_CTL);
205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
206 if (tmp & HOST_AHCI_EN)
207 return;
208 msleep(10);
209 }
210
211 WARN_ON(1);
212}
213
214static ssize_t ahci_show_host_caps(struct device *dev,
215 struct device_attribute *attr, char *buf)
216{
217 struct Scsi_Host *shost = class_to_shost(dev);
218 struct ata_port *ap = ata_shost_to_port(shost);
219 struct ahci_host_priv *hpriv = ap->host->private_data;
220
221 return sprintf(buf, "%x\n", hpriv->cap);
222}
223
224static ssize_t ahci_show_host_cap2(struct device *dev,
225 struct device_attribute *attr, char *buf)
226{
227 struct Scsi_Host *shost = class_to_shost(dev);
228 struct ata_port *ap = ata_shost_to_port(shost);
229 struct ahci_host_priv *hpriv = ap->host->private_data;
230
231 return sprintf(buf, "%x\n", hpriv->cap2);
232}
233
234static ssize_t ahci_show_host_version(struct device *dev,
235 struct device_attribute *attr, char *buf)
236{
237 struct Scsi_Host *shost = class_to_shost(dev);
238 struct ata_port *ap = ata_shost_to_port(shost);
239 struct ahci_host_priv *hpriv = ap->host->private_data;
240 void __iomem *mmio = hpriv->mmio;
241
242 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
243}
244
245static ssize_t ahci_show_port_cmd(struct device *dev,
246 struct device_attribute *attr, char *buf)
247{
248 struct Scsi_Host *shost = class_to_shost(dev);
249 struct ata_port *ap = ata_shost_to_port(shost);
250 void __iomem *port_mmio = ahci_port_base(ap);
251
252 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
253}
254
255/**
256 * ahci_save_initial_config - Save and fixup initial config values
257 * @dev: target AHCI device
258 * @hpriv: host private area to store config values
259 * @force_port_map: force port map to a specified value
260 * @mask_port_map: mask out particular bits from port map
261 *
262 * Some registers containing configuration info might be setup by
263 * BIOS and might be cleared on reset. This function saves the
264 * initial values of those registers into @hpriv such that they
265 * can be restored after controller reset.
266 *
267 * If inconsistent, config values are fixed up by this function.
268 *
269 * LOCKING:
270 * None.
271 */
272void ahci_save_initial_config(struct device *dev,
273 struct ahci_host_priv *hpriv,
274 unsigned int force_port_map,
275 unsigned int mask_port_map)
276{
277 void __iomem *mmio = hpriv->mmio;
278 u32 cap, cap2, vers, port_map;
279 int i;
280
281 /* make sure AHCI mode is enabled before accessing CAP */
282 ahci_enable_ahci(mmio);
283
284 /* Values prefixed with saved_ are written back to host after
285 * reset. Values without are used for driver operation.
286 */
287 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
288 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
289
290 /* CAP2 register is only defined for AHCI 1.2 and later */
291 vers = readl(mmio + HOST_VERSION);
292 if ((vers >> 16) > 1 ||
293 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
294 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
295 else
296 hpriv->saved_cap2 = cap2 = 0;
297
298 /* some chips have errata preventing 64bit use */
299 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
300 dev_printk(KERN_INFO, dev,
301 "controller can't do 64bit DMA, forcing 32bit\n");
302 cap &= ~HOST_CAP_64;
303 }
304
305 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
306 dev_printk(KERN_INFO, dev,
307 "controller can't do NCQ, turning off CAP_NCQ\n");
308 cap &= ~HOST_CAP_NCQ;
309 }
310
311 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
312 dev_printk(KERN_INFO, dev,
313 "controller can do NCQ, turning on CAP_NCQ\n");
314 cap |= HOST_CAP_NCQ;
315 }
316
317 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
318 dev_printk(KERN_INFO, dev,
319 "controller can't do PMP, turning off CAP_PMP\n");
320 cap &= ~HOST_CAP_PMP;
321 }
322
323 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
324 dev_printk(KERN_INFO, dev,
325 "controller can't do SNTF, turning off CAP_SNTF\n");
326 cap &= ~HOST_CAP_SNTF;
327 }
328
329 if (force_port_map && port_map != force_port_map) {
330 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
331 port_map, force_port_map);
332 port_map = force_port_map;
333 }
334
335 if (mask_port_map) {
336 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
337 port_map,
338 port_map & mask_port_map);
339 port_map &= mask_port_map;
340 }
341
342 /* cross check port_map and cap.n_ports */
343 if (port_map) {
344 int map_ports = 0;
345
346 for (i = 0; i < AHCI_MAX_PORTS; i++)
347 if (port_map & (1 << i))
348 map_ports++;
349
350 /* If PI has more ports than n_ports, whine, clear
351 * port_map and let it be generated from n_ports.
352 */
353 if (map_ports > ahci_nr_ports(cap)) {
354 dev_printk(KERN_WARNING, dev,
355 "implemented port map (0x%x) contains more "
356 "ports than nr_ports (%u), using nr_ports\n",
357 port_map, ahci_nr_ports(cap));
358 port_map = 0;
359 }
360 }
361
362 /* fabricate port_map from cap.nr_ports */
363 if (!port_map) {
364 port_map = (1 << ahci_nr_ports(cap)) - 1;
365 dev_printk(KERN_WARNING, dev,
366 "forcing PORTS_IMPL to 0x%x\n", port_map);
367
368 /* write the fixed up value to the PI register */
369 hpriv->saved_port_map = port_map;
370 }
371
372 /* record values to use during operation */
373 hpriv->cap = cap;
374 hpriv->cap2 = cap2;
375 hpriv->port_map = port_map;
376}
377EXPORT_SYMBOL_GPL(ahci_save_initial_config);
378
379/**
380 * ahci_restore_initial_config - Restore initial config
381 * @host: target ATA host
382 *
383 * Restore initial config stored by ahci_save_initial_config().
384 *
385 * LOCKING:
386 * None.
387 */
388static void ahci_restore_initial_config(struct ata_host *host)
389{
390 struct ahci_host_priv *hpriv = host->private_data;
391 void __iomem *mmio = hpriv->mmio;
392
393 writel(hpriv->saved_cap, mmio + HOST_CAP);
394 if (hpriv->saved_cap2)
395 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
396 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
397 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
398}
399
400static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
401{
402 static const int offset[] = {
403 [SCR_STATUS] = PORT_SCR_STAT,
404 [SCR_CONTROL] = PORT_SCR_CTL,
405 [SCR_ERROR] = PORT_SCR_ERR,
406 [SCR_ACTIVE] = PORT_SCR_ACT,
407 [SCR_NOTIFICATION] = PORT_SCR_NTF,
408 };
409 struct ahci_host_priv *hpriv = ap->host->private_data;
410
411 if (sc_reg < ARRAY_SIZE(offset) &&
412 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
413 return offset[sc_reg];
414 return 0;
415}
416
417static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
418{
419 void __iomem *port_mmio = ahci_port_base(link->ap);
420 int offset = ahci_scr_offset(link->ap, sc_reg);
421
422 if (offset) {
423 *val = readl(port_mmio + offset);
424 return 0;
425 }
426 return -EINVAL;
427}
428
429static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
430{
431 void __iomem *port_mmio = ahci_port_base(link->ap);
432 int offset = ahci_scr_offset(link->ap, sc_reg);
433
434 if (offset) {
435 writel(val, port_mmio + offset);
436 return 0;
437 }
438 return -EINVAL;
439}
440
96d60303
MG		 441static int ahci_is_device_present(void __iomem *port_mmio)
442{
443 u8 status = readl(port_mmio + PORT_TFDATA) & 0xff;
444
445 /* Make sure PxTFD.STS.BSY and PxTFD.STS.DRQ are 0 */
446 if (status & (ATA_BUSY | ATA_DRQ))
447 return 0;
448
449 /* Make sure PxSSTS.DET is 3h */
450 status = readl(port_mmio + PORT_SCR_STAT) & 0xf;
451 if (status != 3)
452 return 0;
453 return 1;
454}
455
365cfa1e
AV		 456void ahci_start_engine(struct ata_port *ap)
457{
458 void __iomem *port_mmio = ahci_port_base(ap);
459 u32 tmp;
460
96d60303
MG		 461 if (!ahci_is_device_present(port_mmio))
462 return;
463
365cfa1e
AV		 464 /* start DMA */
465 tmp = readl(port_mmio + PORT_CMD);
466 tmp |= PORT_CMD_START;
467 writel(tmp, port_mmio + PORT_CMD);
468 readl(port_mmio + PORT_CMD); /* flush */
469}
470EXPORT_SYMBOL_GPL(ahci_start_engine);
471
472int ahci_stop_engine(struct ata_port *ap)
473{
474 void __iomem *port_mmio = ahci_port_base(ap);
475 u32 tmp;
476
477 tmp = readl(port_mmio + PORT_CMD);
478
479 /* check if the HBA is idle */
480 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
481 return 0;
482
483 /* setting HBA to idle */
484 tmp &= ~PORT_CMD_START;
485 writel(tmp, port_mmio + PORT_CMD);
486
487 /* wait for engine to stop. This could be as long as 500 msec */
488 tmp = ata_wait_register(port_mmio + PORT_CMD,
489 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
490 if (tmp & PORT_CMD_LIST_ON)
491 return -EIO;
492
493 return 0;
494}
495EXPORT_SYMBOL_GPL(ahci_stop_engine);
496
497static void ahci_start_fis_rx(struct ata_port *ap)
498{
499 void __iomem *port_mmio = ahci_port_base(ap);
500 struct ahci_host_priv *hpriv = ap->host->private_data;
501 struct ahci_port_priv *pp = ap->private_data;
502 u32 tmp;
503
504 /* set FIS registers */
505 if (hpriv->cap & HOST_CAP_64)
506 writel((pp->cmd_slot_dma >> 16) >> 16,
507 port_mmio + PORT_LST_ADDR_HI);
508 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
509
510 if (hpriv->cap & HOST_CAP_64)
511 writel((pp->rx_fis_dma >> 16) >> 16,
512 port_mmio + PORT_FIS_ADDR_HI);
513 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
514
515 /* enable FIS reception */
516 tmp = readl(port_mmio + PORT_CMD);
517 tmp |= PORT_CMD_FIS_RX;
518 writel(tmp, port_mmio + PORT_CMD);
519
520 /* flush */
521 readl(port_mmio + PORT_CMD);
522}
523
524static int ahci_stop_fis_rx(struct ata_port *ap)
525{
526 void __iomem *port_mmio = ahci_port_base(ap);
527 u32 tmp;
528
529 /* disable FIS reception */
530 tmp = readl(port_mmio + PORT_CMD);
531 tmp &= ~PORT_CMD_FIS_RX;
532 writel(tmp, port_mmio + PORT_CMD);
533
534 /* wait for completion, spec says 500ms, give it 1000 */
535 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
536 PORT_CMD_FIS_ON, 10, 1000);
537 if (tmp & PORT_CMD_FIS_ON)
538 return -EBUSY;
539
540 return 0;
541}
542
543static void ahci_power_up(struct ata_port *ap)
544{
545 struct ahci_host_priv *hpriv = ap->host->private_data;
546 void __iomem *port_mmio = ahci_port_base(ap);
547 u32 cmd;
548
549 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
550
551 /* spin up device */
552 if (hpriv->cap & HOST_CAP_SSS) {
553 cmd |= PORT_CMD_SPIN_UP;
554 writel(cmd, port_mmio + PORT_CMD);
555 }
556
557 /* wake up link */
558 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
559}
560
561static void ahci_disable_alpm(struct ata_port *ap)
562{
563 struct ahci_host_priv *hpriv = ap->host->private_data;
564 void __iomem *port_mmio = ahci_port_base(ap);
565 u32 cmd;
566 struct ahci_port_priv *pp = ap->private_data;
567
568 /* IPM bits should be disabled by libata-core */
569 /* get the existing command bits */
570 cmd = readl(port_mmio + PORT_CMD);
571
572 /* disable ALPM and ASP */
573 cmd &= ~PORT_CMD_ASP;
574 cmd &= ~PORT_CMD_ALPE;
575
576 /* force the interface back to active */
577 cmd |= PORT_CMD_ICC_ACTIVE;
578
579 /* write out new cmd value */
580 writel(cmd, port_mmio + PORT_CMD);
581 cmd = readl(port_mmio + PORT_CMD);
582
583 /* wait 10ms to be sure we've come out of any low power state */
584 msleep(10);
585
586 /* clear out any PhyRdy stuff from interrupt status */
587 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
588
589 /* go ahead and clean out PhyRdy Change from Serror too */
590 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
591
592 /*
593 * Clear flag to indicate that we should ignore all PhyRdy
594 * state changes
595 */
596 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
597
598 /*
599 * Enable interrupts on Phy Ready.
600 */
601 pp->intr_mask |= PORT_IRQ_PHYRDY;
602 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
603
604 /*
605 * don't change the link pm policy - we can be called
606 * just to turn of link pm temporarily
607 */
608}
609
610static int ahci_enable_alpm(struct ata_port *ap,
611 enum link_pm policy)
612{
613 struct ahci_host_priv *hpriv = ap->host->private_data;
614 void __iomem *port_mmio = ahci_port_base(ap);
615 u32 cmd;
616 struct ahci_port_priv *pp = ap->private_data;
617 u32 asp;
618
619 /* Make sure the host is capable of link power management */
620 if (!(hpriv->cap & HOST_CAP_ALPM))
621 return -EINVAL;
622
623 switch (policy) {
624 case MAX_PERFORMANCE:
625 case NOT_AVAILABLE:
626 /*
627 * if we came here with NOT_AVAILABLE,
628 * it just means this is the first time we
629 * have tried to enable - default to max performance,
630 * and let the user go to lower power modes on request.
631 */
632 ahci_disable_alpm(ap);
633 return 0;
634 case MIN_POWER:
635 /* configure HBA to enter SLUMBER */
636 asp = PORT_CMD_ASP;
637 break;
638 case MEDIUM_POWER:
639 /* configure HBA to enter PARTIAL */
640 asp = 0;
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 /*
647 * Disable interrupts on Phy Ready. This keeps us from
648 * getting woken up due to spurious phy ready interrupts
649 * TBD - Hot plug should be done via polling now, is
650 * that even supported?
651 */
652 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
653 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
654
655 /*
656 * Set a flag to indicate that we should ignore all PhyRdy
657 * state changes since these can happen now whenever we
658 * change link state
659 */
660 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
661
662 /* get the existing command bits */
663 cmd = readl(port_mmio + PORT_CMD);
664
665 /*
666 * Set ASP based on Policy
667 */
668 cmd |= asp;
669
670 /*
671 * Setting this bit will instruct the HBA to aggressively
672 * enter a lower power link state when it's appropriate and
673 * based on the value set above for ASP
674 */
675 cmd |= PORT_CMD_ALPE;
676
677 /* write out new cmd value */
678 writel(cmd, port_mmio + PORT_CMD);
679 cmd = readl(port_mmio + PORT_CMD);
680
681 /* IPM bits should be set by libata-core */
682 return 0;
683}
684
685#ifdef CONFIG_PM
686static void ahci_power_down(struct ata_port *ap)
687{
688 struct ahci_host_priv *hpriv = ap->host->private_data;
689 void __iomem *port_mmio = ahci_port_base(ap);
690 u32 cmd, scontrol;
691
692 if (!(hpriv->cap & HOST_CAP_SSS))
693 return;
694
695 /* put device into listen mode, first set PxSCTL.DET to 0 */
696 scontrol = readl(port_mmio + PORT_SCR_CTL);
697 scontrol &= ~0xf;
698 writel(scontrol, port_mmio + PORT_SCR_CTL);
699
700 /* then set PxCMD.SUD to 0 */
701 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
702 cmd &= ~PORT_CMD_SPIN_UP;
703 writel(cmd, port_mmio + PORT_CMD);
704}
705#endif
706
707static void ahci_start_port(struct ata_port *ap)
708{
709 struct ahci_port_priv *pp = ap->private_data;
710 struct ata_link *link;
711 struct ahci_em_priv *emp;
712 ssize_t rc;
713 int i;
714
715 /* enable FIS reception */
716 ahci_start_fis_rx(ap);
717
718 /* enable DMA */
719 ahci_start_engine(ap);
720
721 /* turn on LEDs */
722 if (ap->flags & ATA_FLAG_EM) {
723 ata_for_each_link(link, ap, EDGE) {
724 emp = &pp->em_priv[link->pmp];
725
726 /* EM Transmit bit maybe busy during init */
727 for (i = 0; i < EM_MAX_RETRY; i++) {
728 rc = ahci_transmit_led_message(ap,
729 emp->led_state,
730 4);
731 if (rc == -EBUSY)
732 msleep(1);
733 else
734 break;
735 }
736 }
737 }
738
739 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
740 ata_for_each_link(link, ap, EDGE)
741 ahci_init_sw_activity(link);
742
743}
744
745static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
746{
747 int rc;
748
749 /* disable DMA */
750 rc = ahci_stop_engine(ap);
751 if (rc) {
752 *emsg = "failed to stop engine";
753 return rc;
754 }
755
756 /* disable FIS reception */
757 rc = ahci_stop_fis_rx(ap);
758 if (rc) {
759 *emsg = "failed stop FIS RX";
760 return rc;
761 }
762
763 return 0;
764}
765
766int ahci_reset_controller(struct ata_host *host)
767{
768 struct ahci_host_priv *hpriv = host->private_data;
769 void __iomem *mmio = hpriv->mmio;
770 u32 tmp;
771
772 /* we must be in AHCI mode, before using anything
773 * AHCI-specific, such as HOST_RESET.
774 */
775 ahci_enable_ahci(mmio);
776
777 /* global controller reset */
778 if (!ahci_skip_host_reset) {
779 tmp = readl(mmio + HOST_CTL);
780 if ((tmp & HOST_RESET) == 0) {
781 writel(tmp | HOST_RESET, mmio + HOST_CTL);
782 readl(mmio + HOST_CTL); /* flush */
783 }
784
785 /*
786 * to perform host reset, OS should set HOST_RESET
787 * and poll until this bit is read to be "0".
788 * reset must complete within 1 second, or
789 * the hardware should be considered fried.
790 */
791 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
792 HOST_RESET, 10, 1000);
793
794 if (tmp & HOST_RESET) {
795 dev_printk(KERN_ERR, host->dev,
796 "controller reset failed (0x%x)\n", tmp);
797 return -EIO;
798 }
799
800 /* turn on AHCI mode */
801 ahci_enable_ahci(mmio);
802
803 /* Some registers might be cleared on reset. Restore
804 * initial values.
805 */
806 ahci_restore_initial_config(host);
807 } else
808 dev_printk(KERN_INFO, host->dev,
809 "skipping global host reset\n");
810
811 return 0;
812}
813EXPORT_SYMBOL_GPL(ahci_reset_controller);
814
815static void ahci_sw_activity(struct ata_link *link)
816{
817 struct ata_port *ap = link->ap;
818 struct ahci_port_priv *pp = ap->private_data;
819 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
820
821 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
822 return;
823
824 emp->activity++;
825 if (!timer_pending(&emp->timer))
826 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
827}
828
829static void ahci_sw_activity_blink(unsigned long arg)
830{
831 struct ata_link *link = (struct ata_link *)arg;
832 struct ata_port *ap = link->ap;
833 struct ahci_port_priv *pp = ap->private_data;
834 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
835 unsigned long led_message = emp->led_state;
836 u32 activity_led_state;
837 unsigned long flags;
838
839 led_message &= EM_MSG_LED_VALUE;
840 led_message |= ap->port_no | (link->pmp << 8);
841
842 /* check to see if we've had activity. If so,
843 * toggle state of LED and reset timer. If not,
844 * turn LED to desired idle state.
845 */
846 spin_lock_irqsave(ap->lock, flags);
847 if (emp->saved_activity != emp->activity) {
848 emp->saved_activity = emp->activity;
849 /* get the current LED state */
850 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
851
852 if (activity_led_state)
853 activity_led_state = 0;
854 else
855 activity_led_state = 1;
856
857 /* clear old state */
858 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
859
860 /* toggle state */
861 led_message |= (activity_led_state << 16);
862 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
863 } else {
864 /* switch to idle */
865 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
866 if (emp->blink_policy == BLINK_OFF)
867 led_message |= (1 << 16);
868 }
869 spin_unlock_irqrestore(ap->lock, flags);
870 ahci_transmit_led_message(ap, led_message, 4);
871}
872
873static void ahci_init_sw_activity(struct ata_link *link)
874{
875 struct ata_port *ap = link->ap;
876 struct ahci_port_priv *pp = ap->private_data;
877 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
878
879 /* init activity stats, setup timer */
880 emp->saved_activity = emp->activity = 0;
881 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
882
883 /* check our blink policy and set flag for link if it's enabled */
884 if (emp->blink_policy)
885 link->flags |= ATA_LFLAG_SW_ACTIVITY;
886}
887
888int ahci_reset_em(struct ata_host *host)
889{
890 struct ahci_host_priv *hpriv = host->private_data;
891 void __iomem *mmio = hpriv->mmio;
892 u32 em_ctl;
893
894 em_ctl = readl(mmio + HOST_EM_CTL);
895 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
896 return -EINVAL;
897
898 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
899 return 0;
900}
901EXPORT_SYMBOL_GPL(ahci_reset_em);
902
903static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
904 ssize_t size)
905{
906 struct ahci_host_priv *hpriv = ap->host->private_data;
907 struct ahci_port_priv *pp = ap->private_data;
908 void __iomem *mmio = hpriv->mmio;
909 u32 em_ctl;
910 u32 message[] = {0, 0};
911 unsigned long flags;
912 int pmp;
913 struct ahci_em_priv *emp;
914
915 /* get the slot number from the message */
916 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
917 if (pmp < EM_MAX_SLOTS)
918 emp = &pp->em_priv[pmp];
919 else
920 return -EINVAL;
921
922 spin_lock_irqsave(ap->lock, flags);
923
924 /*
925 * if we are still busy transmitting a previous message,
926 * do not allow
927 */
928 em_ctl = readl(mmio + HOST_EM_CTL);
929 if (em_ctl & EM_CTL_TM) {
930 spin_unlock_irqrestore(ap->lock, flags);
931 return -EBUSY;
932 }
933
008dbd61
HZ		 934 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
935 /*
936 * create message header - this is all zero except for
937 * the message size, which is 4 bytes.
938 */
939 message[0] |= (4 << 8);
365cfa1e 940
008dbd61
HZ		 941 /* ignore 0:4 of byte zero, fill in port info yourself */
942 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 943
008dbd61
HZ		 944 /* write message to EM_LOC */
945 writel(message[0], mmio + hpriv->em_loc);
946 writel(message[1], mmio + hpriv->em_loc+4);
947
948 /*
949 * tell hardware to transmit the message
950 */
951 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
952 }
365cfa1e
AV		 953
954 /* save off new led state for port/slot */
955 emp->led_state = state;
956
365cfa1e
AV		 957 spin_unlock_irqrestore(ap->lock, flags);
958 return size;
959}
960
961static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
962{
963 struct ahci_port_priv *pp = ap->private_data;
964 struct ata_link *link;
965 struct ahci_em_priv *emp;
966 int rc = 0;
967
968 ata_for_each_link(link, ap, EDGE) {
969 emp = &pp->em_priv[link->pmp];
970 rc += sprintf(buf, "%lx\n", emp->led_state);
971 }
972 return rc;
973}
974
975static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
976 size_t size)
977{
978 int state;
979 int pmp;
980 struct ahci_port_priv *pp = ap->private_data;
981 struct ahci_em_priv *emp;
982
983 state = simple_strtoul(buf, NULL, 0);
984
985 /* get the slot number from the message */
986 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
987 if (pmp < EM_MAX_SLOTS)
988 emp = &pp->em_priv[pmp];
989 else
990 return -EINVAL;
991
992 /* mask off the activity bits if we are in sw_activity
993 * mode, user should turn off sw_activity before setting
994 * activity led through em_message
995 */
996 if (emp->blink_policy)
997 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
998
999 return ahci_transmit_led_message(ap, state, size);
1000}
1001
1002static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1003{
1004 struct ata_link *link = dev->link;
1005 struct ata_port *ap = link->ap;
1006 struct ahci_port_priv *pp = ap->private_data;
1007 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1008 u32 port_led_state = emp->led_state;
1009
1010 /* save the desired Activity LED behavior */
1011 if (val == OFF) {
1012 /* clear LFLAG */
1013 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1014
1015 /* set the LED to OFF */
1016 port_led_state &= EM_MSG_LED_VALUE_OFF;
1017 port_led_state |= (ap->port_no | (link->pmp << 8));
1018 ahci_transmit_led_message(ap, port_led_state, 4);
1019 } else {
1020 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1021 if (val == BLINK_OFF) {
1022 /* set LED to ON for idle */
1023 port_led_state &= EM_MSG_LED_VALUE_OFF;
1024 port_led_state |= (ap->port_no | (link->pmp << 8));
1025 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1026 ahci_transmit_led_message(ap, port_led_state, 4);
1027 }
1028 }
1029 emp->blink_policy = val;
1030 return 0;
1031}
1032
1033static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1034{
1035 struct ata_link *link = dev->link;
1036 struct ata_port *ap = link->ap;
1037 struct ahci_port_priv *pp = ap->private_data;
1038 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1039
1040 /* display the saved value of activity behavior for this
1041 * disk.
1042 */
1043 return sprintf(buf, "%d\n", emp->blink_policy);
1044}
1045
1046static void ahci_port_init(struct device *dev, struct ata_port *ap,
1047 int port_no, void __iomem *mmio,
1048 void __iomem *port_mmio)
1049{
1050 const char *emsg = NULL;
1051 int rc;
1052 u32 tmp;
1053
1054 /* make sure port is not active */
1055 rc = ahci_deinit_port(ap, &emsg);
1056 if (rc)
1057 dev_warn(dev, "%s (%d)\n", emsg, rc);
1058
1059 /* clear SError */
1060 tmp = readl(port_mmio + PORT_SCR_ERR);
1061 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1062 writel(tmp, port_mmio + PORT_SCR_ERR);
1063
1064 /* clear port IRQ */
1065 tmp = readl(port_mmio + PORT_IRQ_STAT);
1066 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1067 if (tmp)
1068 writel(tmp, port_mmio + PORT_IRQ_STAT);
1069
1070 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1071}
1072
1073void ahci_init_controller(struct ata_host *host)
1074{
1075 struct ahci_host_priv *hpriv = host->private_data;
1076 void __iomem *mmio = hpriv->mmio;
1077 int i;
1078 void __iomem *port_mmio;
1079 u32 tmp;
1080
1081 for (i = 0; i < host->n_ports; i++) {
1082 struct ata_port *ap = host->ports[i];
1083
1084 port_mmio = ahci_port_base(ap);
1085 if (ata_port_is_dummy(ap))
1086 continue;
1087
1088 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1089 }
1090
1091 tmp = readl(mmio + HOST_CTL);
1092 VPRINTK("HOST_CTL 0x%x\n", tmp);
1093 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1094 tmp = readl(mmio + HOST_CTL);
1095 VPRINTK("HOST_CTL 0x%x\n", tmp);
1096}
1097EXPORT_SYMBOL_GPL(ahci_init_controller);
1098
1099static void ahci_dev_config(struct ata_device *dev)
1100{
1101 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1102
1103 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1104 dev->max_sectors = 255;
1105 ata_dev_printk(dev, KERN_INFO,
1106 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1107 }
1108}
1109
1110static unsigned int ahci_dev_classify(struct ata_port *ap)
1111{
1112 void __iomem *port_mmio = ahci_port_base(ap);
1113 struct ata_taskfile tf;
1114 u32 tmp;
1115
1116 tmp = readl(port_mmio + PORT_SIG);
1117 tf.lbah = (tmp >> 24) & 0xff;
1118 tf.lbam = (tmp >> 16) & 0xff;
1119 tf.lbal = (tmp >> 8) & 0xff;
1120 tf.nsect = (tmp) & 0xff;
1121
1122 return ata_dev_classify(&tf);
1123}
1124
1125static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1126 u32 opts)
1127{
1128 dma_addr_t cmd_tbl_dma;
1129
1130 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1131
1132 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1133 pp->cmd_slot[tag].status = 0;
1134 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1135 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1136}
1137
1138int ahci_kick_engine(struct ata_port *ap)
1139{
1140 void __iomem *port_mmio = ahci_port_base(ap);
1141 struct ahci_host_priv *hpriv = ap->host->private_data;
1142 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1143 u32 tmp;
1144 int busy, rc;
1145
1146 /* stop engine */
1147 rc = ahci_stop_engine(ap);
1148 if (rc)
1149 goto out_restart;
1150
1151 /* need to do CLO?
1152 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1153 */
1154 busy = status & (ATA_BUSY | ATA_DRQ);
1155 if (!busy && !sata_pmp_attached(ap)) {
1156 rc = 0;
1157 goto out_restart;
1158 }
1159
1160 if (!(hpriv->cap & HOST_CAP_CLO)) {
1161 rc = -EOPNOTSUPP;
1162 goto out_restart;
1163 }
1164
1165 /* perform CLO */
1166 tmp = readl(port_mmio + PORT_CMD);
1167 tmp |= PORT_CMD_CLO;
1168 writel(tmp, port_mmio + PORT_CMD);
1169
1170 rc = 0;
1171 tmp = ata_wait_register(port_mmio + PORT_CMD,
1172 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1173 if (tmp & PORT_CMD_CLO)
1174 rc = -EIO;
1175
1176 /* restart engine */
1177 out_restart:
1178 ahci_start_engine(ap);
1179 return rc;
1180}
1181EXPORT_SYMBOL_GPL(ahci_kick_engine);
1182
1183static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1184 struct ata_taskfile *tf, int is_cmd, u16 flags,
1185 unsigned long timeout_msec)
1186{
1187 const u32 cmd_fis_len = 5; /* five dwords */
1188 struct ahci_port_priv *pp = ap->private_data;
1189 void __iomem *port_mmio = ahci_port_base(ap);
1190 u8 *fis = pp->cmd_tbl;
1191 u32 tmp;
1192
1193 /* prep the command */
1194 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1195 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1196
1197 /* issue & wait */
1198 writel(1, port_mmio + PORT_CMD_ISSUE);
1199
1200 if (timeout_msec) {
1201 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1202 1, timeout_msec);
1203 if (tmp & 0x1) {
1204 ahci_kick_engine(ap);
1205 return -EBUSY;
1206 }
1207 } else
1208 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1209
1210 return 0;
1211}
1212
1213int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1214 int pmp, unsigned long deadline,
1215 int (*check_ready)(struct ata_link *link))
1216{
1217 struct ata_port *ap = link->ap;
1218 struct ahci_host_priv *hpriv = ap->host->private_data;
1219 const char *reason = NULL;
1220 unsigned long now, msecs;
1221 struct ata_taskfile tf;
1222 int rc;
1223
1224 DPRINTK("ENTER\n");
1225
1226 /* prepare for SRST (AHCI-1.1 10.4.1) */
1227 rc = ahci_kick_engine(ap);
1228 if (rc && rc != -EOPNOTSUPP)
1229 ata_link_printk(link, KERN_WARNING,
1230 "failed to reset engine (errno=%d)\n", rc);
1231
1232 ata_tf_init(link->device, &tf);
1233
1234 /* issue the first D2H Register FIS */
1235 msecs = 0;
1236 now = jiffies;
1237 if (time_after(now, deadline))
1238 msecs = jiffies_to_msecs(deadline - now);
1239
1240 tf.ctl |= ATA_SRST;
1241 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1242 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1243 rc = -EIO;
1244 reason = "1st FIS failed";
1245 goto fail;
1246 }
1247
1248 /* spec says at least 5us, but be generous and sleep for 1ms */
1249 msleep(1);
1250
1251 /* issue the second D2H Register FIS */
1252 tf.ctl &= ~ATA_SRST;
1253 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1254
1255 /* wait for link to become ready */
1256 rc = ata_wait_after_reset(link, deadline, check_ready);
1257 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1258 /*
1259 * Workaround for cases where link online status can't
1260 * be trusted. Treat device readiness timeout as link
1261 * offline.
1262 */
1263 ata_link_printk(link, KERN_INFO,
1264 "device not ready, treating as offline\n");
1265 *class = ATA_DEV_NONE;
1266 } else if (rc) {
1267 /* link occupied, -ENODEV too is an error */
1268 reason = "device not ready";
1269 goto fail;
1270 } else
1271 *class = ahci_dev_classify(ap);
1272
1273 DPRINTK("EXIT, class=%u\n", *class);
1274 return 0;
1275
1276 fail:
1277 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1278 return rc;
1279}
1280
1281int ahci_check_ready(struct ata_link *link)
1282{
1283 void __iomem *port_mmio = ahci_port_base(link->ap);
1284 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1285
1286 return ata_check_ready(status);
1287}
1288EXPORT_SYMBOL_GPL(ahci_check_ready);
1289
1290static int ahci_softreset(struct ata_link *link, unsigned int *class,
1291 unsigned long deadline)
1292{
1293 int pmp = sata_srst_pmp(link);
1294
1295 DPRINTK("ENTER\n");
1296
1297 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1298}
1299EXPORT_SYMBOL_GPL(ahci_do_softreset);
1300
1301static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1302 unsigned long deadline)
1303{
1304 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1305 struct ata_port *ap = link->ap;
1306 struct ahci_port_priv *pp = ap->private_data;
1307 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1308 struct ata_taskfile tf;
1309 bool online;
1310 int rc;
1311
1312 DPRINTK("ENTER\n");
1313
1314 ahci_stop_engine(ap);
1315
1316 /* clear D2H reception area to properly wait for D2H FIS */
1317 ata_tf_init(link->device, &tf);
1318 tf.command = 0x80;
1319 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1320
1321 rc = sata_link_hardreset(link, timing, deadline, &online,
1322 ahci_check_ready);
1323
1324 ahci_start_engine(ap);
1325
1326 if (online)
1327 *class = ahci_dev_classify(ap);
1328
1329 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1330 return rc;
1331}
1332
1333static void ahci_postreset(struct ata_link *link, unsigned int *class)
1334{
1335 struct ata_port *ap = link->ap;
1336 void __iomem *port_mmio = ahci_port_base(ap);
1337 u32 new_tmp, tmp;
1338
1339 ata_std_postreset(link, class);
1340
1341 /* Make sure port's ATAPI bit is set appropriately */
1342 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1343 if (*class == ATA_DEV_ATAPI)
1344 new_tmp |= PORT_CMD_ATAPI;
1345 else
1346 new_tmp &= ~PORT_CMD_ATAPI;
1347 if (new_tmp != tmp) {
1348 writel(new_tmp, port_mmio + PORT_CMD);
1349 readl(port_mmio + PORT_CMD); /* flush */
1350 }
1351}
1352
1353static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1354{
1355 struct scatterlist *sg;
1356 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1357 unsigned int si;
1358
1359 VPRINTK("ENTER\n");
1360
1361 /*
1362 * Next, the S/G list.
1363 */
1364 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1365 dma_addr_t addr = sg_dma_address(sg);
1366 u32 sg_len = sg_dma_len(sg);
1367
1368 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1369 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1370 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1371 }
1372
1373 return si;
1374}
1375
1376static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1377{
1378 struct ata_port *ap = qc->ap;
1379 struct ahci_port_priv *pp = ap->private_data;
1380
1381 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1382 return ata_std_qc_defer(qc);
1383 else
1384 return sata_pmp_qc_defer_cmd_switch(qc);
1385}
1386
1387static void ahci_qc_prep(struct ata_queued_cmd *qc)
1388{
1389 struct ata_port *ap = qc->ap;
1390 struct ahci_port_priv *pp = ap->private_data;
1391 int is_atapi = ata_is_atapi(qc->tf.protocol);
1392 void *cmd_tbl;
1393 u32 opts;
1394 const u32 cmd_fis_len = 5; /* five dwords */
1395 unsigned int n_elem;
1396
1397 /*
1398 * Fill in command table information. First, the header,
1399 * a SATA Register - Host to Device command FIS.
1400 */
1401 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1402
1403 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1404 if (is_atapi) {
1405 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1406 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1407 }
1408
1409 n_elem = 0;
1410 if (qc->flags & ATA_QCFLAG_DMAMAP)
1411 n_elem = ahci_fill_sg(qc, cmd_tbl);
1412
1413 /*
1414 * Fill in command slot information.
1415 */
1416 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1417 if (qc->tf.flags & ATA_TFLAG_WRITE)
1418 opts |= AHCI_CMD_WRITE;
1419 if (is_atapi)
1420 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1421
1422 ahci_fill_cmd_slot(pp, qc->tag, opts);
1423}
1424
1425static void ahci_fbs_dec_intr(struct ata_port *ap)
1426{
1427 struct ahci_port_priv *pp = ap->private_data;
1428 void __iomem *port_mmio = ahci_port_base(ap);
1429 u32 fbs = readl(port_mmio + PORT_FBS);
1430 int retries = 3;
1431
1432 DPRINTK("ENTER\n");
1433 BUG_ON(!pp->fbs_enabled);
1434
1435 /* time to wait for DEC is not specified by AHCI spec,
1436 * add a retry loop for safety.
1437 */
1438 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1439 fbs = readl(port_mmio + PORT_FBS);
1440 while ((fbs & PORT_FBS_DEC) && retries--) {
1441 udelay(1);
1442 fbs = readl(port_mmio + PORT_FBS);
1443 }
1444
1445 if (fbs & PORT_FBS_DEC)
1446 dev_printk(KERN_ERR, ap->host->dev,
1447 "failed to clear device error\n");
1448}
1449
1450static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1451{
1452 struct ahci_host_priv *hpriv = ap->host->private_data;
1453 struct ahci_port_priv *pp = ap->private_data;
1454 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1455 struct ata_link *link = NULL;
1456 struct ata_queued_cmd *active_qc;
1457 struct ata_eh_info *active_ehi;
1458 bool fbs_need_dec = false;
1459 u32 serror;
1460
1461 /* determine active link with error */
1462 if (pp->fbs_enabled) {
1463 void __iomem *port_mmio = ahci_port_base(ap);
1464 u32 fbs = readl(port_mmio + PORT_FBS);
1465 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1466
1467 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1468 ata_link_online(&ap->pmp_link[pmp])) {
1469 link = &ap->pmp_link[pmp];
1470 fbs_need_dec = true;
1471 }
1472
1473 } else
1474 ata_for_each_link(link, ap, EDGE)
1475 if (ata_link_active(link))
1476 break;
1477
1478 if (!link)
1479 link = &ap->link;
1480
1481 active_qc = ata_qc_from_tag(ap, link->active_tag);
1482 active_ehi = &link->eh_info;
1483
1484 /* record irq stat */
1485 ata_ehi_clear_desc(host_ehi);
1486 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1487
1488 /* AHCI needs SError cleared; otherwise, it might lock up */
1489 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1490 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1491 host_ehi->serror |= serror;
1492
1493 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1494 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1495 irq_stat &= ~PORT_IRQ_IF_ERR;
1496
1497 if (irq_stat & PORT_IRQ_TF_ERR) {
1498 /* If qc is active, charge it; otherwise, the active
1499 * link. There's no active qc on NCQ errors. It will
1500 * be determined by EH by reading log page 10h.
1501 */
1502 if (active_qc)
1503 active_qc->err_mask |= AC_ERR_DEV;
1504 else
1505 active_ehi->err_mask |= AC_ERR_DEV;
1506
1507 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1508 host_ehi->serror &= ~SERR_INTERNAL;
1509 }
1510
1511 if (irq_stat & PORT_IRQ_UNK_FIS) {
1512 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1513
1514 active_ehi->err_mask |= AC_ERR_HSM;
1515 active_ehi->action |= ATA_EH_RESET;
1516 ata_ehi_push_desc(active_ehi,
1517 "unknown FIS %08x %08x %08x %08x" ,
1518 unk[0], unk[1], unk[2], unk[3]);
1519 }
1520
1521 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1522 active_ehi->err_mask |= AC_ERR_HSM;
1523 active_ehi->action |= ATA_EH_RESET;
1524 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1525 }
1526
1527 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1528 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1529 host_ehi->action |= ATA_EH_RESET;
1530 ata_ehi_push_desc(host_ehi, "host bus error");
1531 }
1532
1533 if (irq_stat & PORT_IRQ_IF_ERR) {
1534 if (fbs_need_dec)
1535 active_ehi->err_mask |= AC_ERR_DEV;
1536 else {
1537 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1538 host_ehi->action |= ATA_EH_RESET;
1539 }
1540
1541 ata_ehi_push_desc(host_ehi, "interface fatal error");
1542 }
1543
1544 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1545 ata_ehi_hotplugged(host_ehi);
1546 ata_ehi_push_desc(host_ehi, "%s",
1547 irq_stat & PORT_IRQ_CONNECT ?
1548 "connection status changed" : "PHY RDY changed");
1549 }
1550
1551 /* okay, let's hand over to EH */
1552
1553 if (irq_stat & PORT_IRQ_FREEZE)
1554 ata_port_freeze(ap);
1555 else if (fbs_need_dec) {
1556 ata_link_abort(link);
1557 ahci_fbs_dec_intr(ap);
1558 } else
1559 ata_port_abort(ap);
1560}
1561
1562static void ahci_port_intr(struct ata_port *ap)
1563{
1564 void __iomem *port_mmio = ahci_port_base(ap);
1565 struct ata_eh_info *ehi = &ap->link.eh_info;
1566 struct ahci_port_priv *pp = ap->private_data;
1567 struct ahci_host_priv *hpriv = ap->host->private_data;
1568 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1569 u32 status, qc_active = 0;
1570 int rc;
1571
1572 status = readl(port_mmio + PORT_IRQ_STAT);
1573 writel(status, port_mmio + PORT_IRQ_STAT);
1574
1575 /* ignore BAD_PMP while resetting */
1576 if (unlikely(resetting))
1577 status &= ~PORT_IRQ_BAD_PMP;
1578
1579 /* If we are getting PhyRdy, this is
1580 * just a power state change, we should
1581 * clear out this, plus the PhyRdy/Comm
1582 * Wake bits from Serror
1583 */
1584 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1585 (status & PORT_IRQ_PHYRDY)) {
1586 status &= ~PORT_IRQ_PHYRDY;
1587 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1588 }
1589
1590 if (unlikely(status & PORT_IRQ_ERROR)) {
1591 ahci_error_intr(ap, status);
1592 return;
1593 }
1594
1595 if (status & PORT_IRQ_SDB_FIS) {
1596 /* If SNotification is available, leave notification
1597 * handling to sata_async_notification(). If not,
1598 * emulate it by snooping SDB FIS RX area.
1599 *
1600 * Snooping FIS RX area is probably cheaper than
1601 * poking SNotification but some constrollers which
1602 * implement SNotification, ICH9 for example, don't
1603 * store AN SDB FIS into receive area.
1604 */
1605 if (hpriv->cap & HOST_CAP_SNTF)
1606 sata_async_notification(ap);
1607 else {
1608 /* If the 'N' bit in word 0 of the FIS is set,
1609 * we just received asynchronous notification.
1610 * Tell libata about it.
1611 *
1612 * Lack of SNotification should not appear in
1613 * ahci 1.2, so the workaround is unnecessary
1614 * when FBS is enabled.
1615 */
1616 if (pp->fbs_enabled)
1617 WARN_ON_ONCE(1);
1618 else {
1619 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1620 u32 f0 = le32_to_cpu(f[0]);
1621 if (f0 & (1 << 15))
1622 sata_async_notification(ap);
1623 }
1624 }
1625 }
1626
1627 /* pp->active_link is not reliable once FBS is enabled, both
1628 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1629 * NCQ and non-NCQ commands may be in flight at the same time.
1630 */
1631 if (pp->fbs_enabled) {
1632 if (ap->qc_active) {
1633 qc_active = readl(port_mmio + PORT_SCR_ACT);
1634 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1635 }
1636 } else {
1637 /* pp->active_link is valid iff any command is in flight */
1638 if (ap->qc_active && pp->active_link->sactive)
1639 qc_active = readl(port_mmio + PORT_SCR_ACT);
1640 else
1641 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1642 }
1643
1644
1645 rc = ata_qc_complete_multiple(ap, qc_active);
1646
1647 /* while resetting, invalid completions are expected */
1648 if (unlikely(rc < 0 && !resetting)) {
1649 ehi->err_mask |= AC_ERR_HSM;
1650 ehi->action |= ATA_EH_RESET;
1651 ata_port_freeze(ap);
1652 }
1653}
1654
1655irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1656{
1657 struct ata_host *host = dev_instance;
1658 struct ahci_host_priv *hpriv;
1659 unsigned int i, handled = 0;
1660 void __iomem *mmio;
1661 u32 irq_stat, irq_masked;
1662
1663 VPRINTK("ENTER\n");
1664
1665 hpriv = host->private_data;
1666 mmio = hpriv->mmio;
1667
1668 /* sigh. 0xffffffff is a valid return from h/w */
1669 irq_stat = readl(mmio + HOST_IRQ_STAT);
1670 if (!irq_stat)
1671 return IRQ_NONE;
1672
1673 irq_masked = irq_stat & hpriv->port_map;
1674
1675 spin_lock(&host->lock);
1676
1677 for (i = 0; i < host->n_ports; i++) {
1678 struct ata_port *ap;
1679
1680 if (!(irq_masked & (1 << i)))
1681 continue;
1682
1683 ap = host->ports[i];
1684 if (ap) {
1685 ahci_port_intr(ap);
1686 VPRINTK("port %u\n", i);
1687 } else {
1688 VPRINTK("port %u (no irq)\n", i);
1689 if (ata_ratelimit())
1690 dev_printk(KERN_WARNING, host->dev,
1691 "interrupt on disabled port %u\n", i);
1692 }
1693
1694 handled = 1;
1695 }
1696
1697 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1698 * it should be cleared after all the port events are cleared;
1699 * otherwise, it will raise a spurious interrupt after each
1700 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1701 * information.
1702 *
1703 * Also, use the unmasked value to clear interrupt as spurious
1704 * pending event on a dummy port might cause screaming IRQ.
1705 */
1706 writel(irq_stat, mmio + HOST_IRQ_STAT);
1707
1708 spin_unlock(&host->lock);
1709
1710 VPRINTK("EXIT\n");
1711
1712 return IRQ_RETVAL(handled);
1713}
1714EXPORT_SYMBOL_GPL(ahci_interrupt);
1715
1716static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1717{
1718 struct ata_port *ap = qc->ap;
1719 void __iomem *port_mmio = ahci_port_base(ap);
1720 struct ahci_port_priv *pp = ap->private_data;
1721
1722 /* Keep track of the currently active link. It will be used
1723 * in completion path to determine whether NCQ phase is in
1724 * progress.
1725 */
1726 pp->active_link = qc->dev->link;
1727
1728 if (qc->tf.protocol == ATA_PROT_NCQ)
1729 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1730
1731 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1732 u32 fbs = readl(port_mmio + PORT_FBS);
1733 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1734 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1735 writel(fbs, port_mmio + PORT_FBS);
1736 pp->fbs_last_dev = qc->dev->link->pmp;
1737 }
1738
1739 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1740
1741 ahci_sw_activity(qc->dev->link);
1742
1743 return 0;
1744}
1745
1746static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1747{
1748 struct ahci_port_priv *pp = qc->ap->private_data;
1749 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1750
1751 if (pp->fbs_enabled)
1752 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1753
1754 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1755 return true;
1756}
1757
1758static void ahci_freeze(struct ata_port *ap)
1759{
1760 void __iomem *port_mmio = ahci_port_base(ap);
1761
1762 /* turn IRQ off */
1763 writel(0, port_mmio + PORT_IRQ_MASK);
1764}
1765
1766static void ahci_thaw(struct ata_port *ap)
1767{
1768 struct ahci_host_priv *hpriv = ap->host->private_data;
1769 void __iomem *mmio = hpriv->mmio;
1770 void __iomem *port_mmio = ahci_port_base(ap);
1771 u32 tmp;
1772 struct ahci_port_priv *pp = ap->private_data;
1773
1774 /* clear IRQ */
1775 tmp = readl(port_mmio + PORT_IRQ_STAT);
1776 writel(tmp, port_mmio + PORT_IRQ_STAT);
1777 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1778
1779 /* turn IRQ back on */
1780 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1781}
1782
1783static void ahci_error_handler(struct ata_port *ap)
1784{
1785 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1786 /* restart engine */
1787 ahci_stop_engine(ap);
1788 ahci_start_engine(ap);
1789 }
1790
1791 sata_pmp_error_handler(ap);
1792}
1793
1794static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1795{
1796 struct ata_port *ap = qc->ap;
1797
1798 /* make DMA engine forget about the failed command */
1799 if (qc->flags & ATA_QCFLAG_FAILED)
1800 ahci_kick_engine(ap);
1801}
1802
1803static void ahci_enable_fbs(struct ata_port *ap)
1804{
1805 struct ahci_port_priv *pp = ap->private_data;
1806 void __iomem *port_mmio = ahci_port_base(ap);
1807 u32 fbs;
1808 int rc;
1809
1810 if (!pp->fbs_supported)
1811 return;
1812
1813 fbs = readl(port_mmio + PORT_FBS);
1814 if (fbs & PORT_FBS_EN) {
1815 pp->fbs_enabled = true;
1816 pp->fbs_last_dev = -1; /* initialization */
1817 return;
1818 }
1819
1820 rc = ahci_stop_engine(ap);
1821 if (rc)
1822 return;
1823
1824 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1825 fbs = readl(port_mmio + PORT_FBS);
1826 if (fbs & PORT_FBS_EN) {
1827 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1828 pp->fbs_enabled = true;
1829 pp->fbs_last_dev = -1; /* initialization */
1830 } else
1831 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1832
1833 ahci_start_engine(ap);
1834}
1835
1836static void ahci_disable_fbs(struct ata_port *ap)
1837{
1838 struct ahci_port_priv *pp = ap->private_data;
1839 void __iomem *port_mmio = ahci_port_base(ap);
1840 u32 fbs;
1841 int rc;
1842
1843 if (!pp->fbs_supported)
1844 return;
1845
1846 fbs = readl(port_mmio + PORT_FBS);
1847 if ((fbs & PORT_FBS_EN) == 0) {
1848 pp->fbs_enabled = false;
1849 return;
1850 }
1851
1852 rc = ahci_stop_engine(ap);
1853 if (rc)
1854 return;
1855
1856 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1857 fbs = readl(port_mmio + PORT_FBS);
1858 if (fbs & PORT_FBS_EN)
1859 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1860 else {
1861 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1862 pp->fbs_enabled = false;
1863 }
1864
1865 ahci_start_engine(ap);
1866}
1867
1868static void ahci_pmp_attach(struct ata_port *ap)
1869{
1870 void __iomem *port_mmio = ahci_port_base(ap);
1871 struct ahci_port_priv *pp = ap->private_data;
1872 u32 cmd;
1873
1874 cmd = readl(port_mmio + PORT_CMD);
1875 cmd |= PORT_CMD_PMP;
1876 writel(cmd, port_mmio + PORT_CMD);
1877
1878 ahci_enable_fbs(ap);
1879
1880 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1881 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1882}
1883
1884static void ahci_pmp_detach(struct ata_port *ap)
1885{
1886 void __iomem *port_mmio = ahci_port_base(ap);
1887 struct ahci_port_priv *pp = ap->private_data;
1888 u32 cmd;
1889
1890 ahci_disable_fbs(ap);
1891
1892 cmd = readl(port_mmio + PORT_CMD);
1893 cmd &= ~PORT_CMD_PMP;
1894 writel(cmd, port_mmio + PORT_CMD);
1895
1896 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1897 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1898}
1899
1900static int ahci_port_resume(struct ata_port *ap)
1901{
1902 ahci_power_up(ap);
1903 ahci_start_port(ap);
1904
1905 if (sata_pmp_attached(ap))
1906 ahci_pmp_attach(ap);
1907 else
1908 ahci_pmp_detach(ap);
1909
1910 return 0;
1911}
1912
1913#ifdef CONFIG_PM
1914static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1915{
1916 const char *emsg = NULL;
1917 int rc;
1918
1919 rc = ahci_deinit_port(ap, &emsg);
1920 if (rc == 0)
1921 ahci_power_down(ap);
1922 else {
1923 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1924 ahci_start_port(ap);
1925 }
1926
1927 return rc;
1928}
1929#endif
1930
1931static int ahci_port_start(struct ata_port *ap)
1932{
1933 struct ahci_host_priv *hpriv = ap->host->private_data;
1934 struct device *dev = ap->host->dev;
1935 struct ahci_port_priv *pp;
1936 void *mem;
1937 dma_addr_t mem_dma;
1938 size_t dma_sz, rx_fis_sz;
1939
1940 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1941 if (!pp)
1942 return -ENOMEM;
1943
1944 /* check FBS capability */
1945 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
1946 void __iomem *port_mmio = ahci_port_base(ap);
1947 u32 cmd = readl(port_mmio + PORT_CMD);
1948 if (cmd & PORT_CMD_FBSCP)
1949 pp->fbs_supported = true;
1950 else
1951 dev_printk(KERN_WARNING, dev,
1952 "The port is not capable of FBS\n");
1953 }
1954
1955 if (pp->fbs_supported) {
1956 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
1957 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
1958 } else {
1959 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
1960 rx_fis_sz = AHCI_RX_FIS_SZ;
1961 }
1962
1963 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
1964 if (!mem)
1965 return -ENOMEM;
1966 memset(mem, 0, dma_sz);
1967
1968 /*
1969 * First item in chunk of DMA memory: 32-slot command table,
1970 * 32 bytes each in size
1971 */
1972 pp->cmd_slot = mem;
1973 pp->cmd_slot_dma = mem_dma;
1974
1975 mem += AHCI_CMD_SLOT_SZ;
1976 mem_dma += AHCI_CMD_SLOT_SZ;
1977
1978 /*
1979 * Second item: Received-FIS area
1980 */
1981 pp->rx_fis = mem;
1982 pp->rx_fis_dma = mem_dma;
1983
1984 mem += rx_fis_sz;
1985 mem_dma += rx_fis_sz;
1986
1987 /*
1988 * Third item: data area for storing a single command
1989 * and its scatter-gather table
1990 */
1991 pp->cmd_tbl = mem;
1992 pp->cmd_tbl_dma = mem_dma;
1993
1994 /*
1995 * Save off initial list of interrupts to be enabled.
1996 * This could be changed later
1997 */
1998 pp->intr_mask = DEF_PORT_IRQ;
1999
2000 ap->private_data = pp;
2001
2002 /* engage engines, captain */
2003 return ahci_port_resume(ap);
2004}
2005
2006static void ahci_port_stop(struct ata_port *ap)
2007{
2008 const char *emsg = NULL;
2009 int rc;
2010
2011 /* de-initialize port */
2012 rc = ahci_deinit_port(ap, &emsg);
2013 if (rc)
2014 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2015}
2016
2017void ahci_print_info(struct ata_host *host, const char *scc_s)
2018{
2019 struct ahci_host_priv *hpriv = host->private_data;
2020 void __iomem *mmio = hpriv->mmio;
2021 u32 vers, cap, cap2, impl, speed;
2022 const char *speed_s;
2023
2024 vers = readl(mmio + HOST_VERSION);
2025 cap = hpriv->cap;
2026 cap2 = hpriv->cap2;
2027 impl = hpriv->port_map;
2028
2029 speed = (cap >> 20) & 0xf;
2030 if (speed == 1)
2031 speed_s = "1.5";
2032 else if (speed == 2)
2033 speed_s = "3";
2034 else if (speed == 3)
2035 speed_s = "6";
2036 else
2037 speed_s = "?";
2038
2039 dev_info(host->dev,
2040 "AHCI %02x%02x.%02x%02x "
2041 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2042 ,
2043
2044 (vers >> 24) & 0xff,
2045 (vers >> 16) & 0xff,
2046 (vers >> 8) & 0xff,
2047 vers & 0xff,
2048
2049 ((cap >> 8) & 0x1f) + 1,
2050 (cap & 0x1f) + 1,
2051 speed_s,
2052 impl,
2053 scc_s);
2054
2055 dev_info(host->dev,
2056 "flags: "
2057 "%s%s%s%s%s%s%s"
2058 "%s%s%s%s%s%s%s"
2059 "%s%s%s%s%s%s\n"
2060 ,
2061
2062 cap & HOST_CAP_64 ? "64bit " : "",
2063 cap & HOST_CAP_NCQ ? "ncq " : "",
2064 cap & HOST_CAP_SNTF ? "sntf " : "",
2065 cap & HOST_CAP_MPS ? "ilck " : "",
2066 cap & HOST_CAP_SSS ? "stag " : "",
2067 cap & HOST_CAP_ALPM ? "pm " : "",
2068 cap & HOST_CAP_LED ? "led " : "",
2069 cap & HOST_CAP_CLO ? "clo " : "",
2070 cap & HOST_CAP_ONLY ? "only " : "",
2071 cap & HOST_CAP_PMP ? "pmp " : "",
2072 cap & HOST_CAP_FBS ? "fbs " : "",
2073 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2074 cap & HOST_CAP_SSC ? "slum " : "",
2075 cap & HOST_CAP_PART ? "part " : "",
2076 cap & HOST_CAP_CCC ? "ccc " : "",
2077 cap & HOST_CAP_EMS ? "ems " : "",
2078 cap & HOST_CAP_SXS ? "sxs " : "",
2079 cap2 & HOST_CAP2_APST ? "apst " : "",
2080 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2081 cap2 & HOST_CAP2_BOH ? "boh " : ""
2082 );
2083}
2084EXPORT_SYMBOL_GPL(ahci_print_info);
2085
2086void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2087 struct ata_port_info *pi)
2088{
2089 u8 messages;
2090 void __iomem *mmio = hpriv->mmio;
2091 u32 em_loc = readl(mmio + HOST_EM_LOC);
2092 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2093
2094 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2095 return;
2096
2097 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2098
008dbd61 2099 if (messages) {
365cfa1e
AV		 2100 /* store em_loc */
2101 hpriv->em_loc = ((em_loc >> 16) * 4);
008dbd61 2102 hpriv->em_msg_type = messages;
365cfa1e
AV		 2103 pi->flags |= ATA_FLAG_EM;
2104 if (!(em_ctl & EM_CTL_ALHD))
2105 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2106 }
2107}
2108EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2109
2110MODULE_AUTHOR("Jeff Garzik");
2111MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2112MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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