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libata: implement sata_link_scr_lpm() and make ata_dev_set_feature() global
[deliverable/linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
c93b263e 59static int ahci_enable_alpm(struct ata_port *ap, enum ata_lpm_policy policy);
365cfa1e
AV		 60static void ahci_disable_alpm(struct ata_port *ap);
61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static void ahci_postreset(struct ata_link *link, unsigned int *class);
88static void ahci_error_handler(struct ata_port *ap);
89static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
90static int ahci_port_resume(struct ata_port *ap);
91static void ahci_dev_config(struct ata_device *dev);
92static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
93 u32 opts);
94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
c0623166
HZ		 110static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
365cfa1e
AV		 115
116static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 120static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
365cfa1e 122
fad16e7a 123struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 124 &dev_attr_link_power_management_policy,
125 &dev_attr_em_message_type,
126 &dev_attr_em_message,
127 &dev_attr_ahci_host_caps,
128 &dev_attr_ahci_host_cap2,
129 &dev_attr_ahci_host_version,
130 &dev_attr_ahci_port_cmd,
c0623166 131 &dev_attr_em_buffer,
365cfa1e
AV		 132 NULL
133};
fad16e7a 134EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 135
fad16e7a 136struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 137 &dev_attr_sw_activity,
138 &dev_attr_unload_heads,
139 NULL
140};
fad16e7a 141EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 142
143struct ata_port_operations ahci_ops = {
144 .inherits = &sata_pmp_port_ops,
145
146 .qc_defer = ahci_pmp_qc_defer,
147 .qc_prep = ahci_qc_prep,
148 .qc_issue = ahci_qc_issue,
149 .qc_fill_rtf = ahci_qc_fill_rtf,
150
151 .freeze = ahci_freeze,
152 .thaw = ahci_thaw,
153 .softreset = ahci_softreset,
154 .hardreset = ahci_hardreset,
155 .postreset = ahci_postreset,
156 .pmp_softreset = ahci_softreset,
157 .error_handler = ahci_error_handler,
158 .post_internal_cmd = ahci_post_internal_cmd,
159 .dev_config = ahci_dev_config,
160
161 .scr_read = ahci_scr_read,
162 .scr_write = ahci_scr_write,
163 .pmp_attach = ahci_pmp_attach,
164 .pmp_detach = ahci_pmp_detach,
165
166 .enable_pm = ahci_enable_alpm,
167 .disable_pm = ahci_disable_alpm,
168 .em_show = ahci_led_show,
169 .em_store = ahci_led_store,
170 .sw_activity_show = ahci_activity_show,
171 .sw_activity_store = ahci_activity_store,
172#ifdef CONFIG_PM
173 .port_suspend = ahci_port_suspend,
174 .port_resume = ahci_port_resume,
175#endif
176 .port_start = ahci_port_start,
177 .port_stop = ahci_port_stop,
178};
179EXPORT_SYMBOL_GPL(ahci_ops);
180
181int ahci_em_messages = 1;
182EXPORT_SYMBOL_GPL(ahci_em_messages);
183module_param(ahci_em_messages, int, 0444);
184/* add other LED protocol types when they become supported */
185MODULE_PARM_DESC(ahci_em_messages,
008dbd61 186 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e
AV		 187
188static void ahci_enable_ahci(void __iomem *mmio)
189{
190 int i;
191 u32 tmp;
192
193 /* turn on AHCI_EN */
194 tmp = readl(mmio + HOST_CTL);
195 if (tmp & HOST_AHCI_EN)
196 return;
197
198 /* Some controllers need AHCI_EN to be written multiple times.
199 * Try a few times before giving up.
200 */
201 for (i = 0; i < 5; i++) {
202 tmp |= HOST_AHCI_EN;
203 writel(tmp, mmio + HOST_CTL);
204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
205 if (tmp & HOST_AHCI_EN)
206 return;
207 msleep(10);
208 }
209
210 WARN_ON(1);
211}
212
213static ssize_t ahci_show_host_caps(struct device *dev,
214 struct device_attribute *attr, char *buf)
215{
216 struct Scsi_Host *shost = class_to_shost(dev);
217 struct ata_port *ap = ata_shost_to_port(shost);
218 struct ahci_host_priv *hpriv = ap->host->private_data;
219
220 return sprintf(buf, "%x\n", hpriv->cap);
221}
222
223static ssize_t ahci_show_host_cap2(struct device *dev,
224 struct device_attribute *attr, char *buf)
225{
226 struct Scsi_Host *shost = class_to_shost(dev);
227 struct ata_port *ap = ata_shost_to_port(shost);
228 struct ahci_host_priv *hpriv = ap->host->private_data;
229
230 return sprintf(buf, "%x\n", hpriv->cap2);
231}
232
233static ssize_t ahci_show_host_version(struct device *dev,
234 struct device_attribute *attr, char *buf)
235{
236 struct Scsi_Host *shost = class_to_shost(dev);
237 struct ata_port *ap = ata_shost_to_port(shost);
238 struct ahci_host_priv *hpriv = ap->host->private_data;
239 void __iomem *mmio = hpriv->mmio;
240
241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
242}
243
244static ssize_t ahci_show_port_cmd(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct Scsi_Host *shost = class_to_shost(dev);
248 struct ata_port *ap = ata_shost_to_port(shost);
249 void __iomem *port_mmio = ahci_port_base(ap);
250
251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
252}
253
c0623166
HZ		 254static ssize_t ahci_read_em_buffer(struct device *dev,
255 struct device_attribute *attr, char *buf)
256{
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260 void __iomem *mmio = hpriv->mmio;
261 void __iomem *em_mmio = mmio + hpriv->em_loc;
262 u32 em_ctl, msg;
263 unsigned long flags;
264 size_t count;
265 int i;
266
267 spin_lock_irqsave(ap->lock, flags);
268
269 em_ctl = readl(mmio + HOST_EM_CTL);
270 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
271 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
272 spin_unlock_irqrestore(ap->lock, flags);
273 return -EINVAL;
274 }
275
276 if (!(em_ctl & EM_CTL_MR)) {
277 spin_unlock_irqrestore(ap->lock, flags);
278 return -EAGAIN;
279 }
280
281 if (!(em_ctl & EM_CTL_SMB))
282 em_mmio += hpriv->em_buf_sz;
283
284 count = hpriv->em_buf_sz;
285
286 /* the count should not be larger than PAGE_SIZE */
287 if (count > PAGE_SIZE) {
288 if (printk_ratelimit())
289 ata_port_printk(ap, KERN_WARNING,
290 "EM read buffer size too large: "
291 "buffer size %u, page size %lu\n",
292 hpriv->em_buf_sz, PAGE_SIZE);
293 count = PAGE_SIZE;
294 }
295
296 for (i = 0; i < count; i += 4) {
297 msg = readl(em_mmio + i);
298 buf[i] = msg & 0xff;
299 buf[i + 1] = (msg >> 8) & 0xff;
300 buf[i + 2] = (msg >> 16) & 0xff;
301 buf[i + 3] = (msg >> 24) & 0xff;
302 }
303
304 spin_unlock_irqrestore(ap->lock, flags);
305
306 return i;
307}
308
309static ssize_t ahci_store_em_buffer(struct device *dev,
310 struct device_attribute *attr,
311 const char *buf, size_t size)
312{
313 struct Scsi_Host *shost = class_to_shost(dev);
314 struct ata_port *ap = ata_shost_to_port(shost);
315 struct ahci_host_priv *hpriv = ap->host->private_data;
316 void __iomem *mmio = hpriv->mmio;
317 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 318 const unsigned char *msg_buf = buf;
c0623166
HZ		 319 u32 em_ctl, msg;
320 unsigned long flags;
321 int i;
322
323 /* check size validity */
324 if (!(ap->flags & ATA_FLAG_EM) ||
325 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
326 size % 4 || size > hpriv->em_buf_sz)
327 return -EINVAL;
328
329 spin_lock_irqsave(ap->lock, flags);
330
331 em_ctl = readl(mmio + HOST_EM_CTL);
332 if (em_ctl & EM_CTL_TM) {
333 spin_unlock_irqrestore(ap->lock, flags);
334 return -EBUSY;
335 }
336
337 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 338 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
339 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 340 writel(msg, em_mmio + i);
341 }
342
343 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
344
345 spin_unlock_irqrestore(ap->lock, flags);
346
347 return size;
348}
349
365cfa1e
AV		 350/**
351 * ahci_save_initial_config - Save and fixup initial config values
352 * @dev: target AHCI device
353 * @hpriv: host private area to store config values
354 * @force_port_map: force port map to a specified value
355 * @mask_port_map: mask out particular bits from port map
356 *
357 * Some registers containing configuration info might be setup by
358 * BIOS and might be cleared on reset. This function saves the
359 * initial values of those registers into @hpriv such that they
360 * can be restored after controller reset.
361 *
362 * If inconsistent, config values are fixed up by this function.
363 *
364 * LOCKING:
365 * None.
366 */
367void ahci_save_initial_config(struct device *dev,
368 struct ahci_host_priv *hpriv,
369 unsigned int force_port_map,
370 unsigned int mask_port_map)
371{
372 void __iomem *mmio = hpriv->mmio;
373 u32 cap, cap2, vers, port_map;
374 int i;
375
376 /* make sure AHCI mode is enabled before accessing CAP */
377 ahci_enable_ahci(mmio);
378
379 /* Values prefixed with saved_ are written back to host after
380 * reset. Values without are used for driver operation.
381 */
382 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
383 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
384
385 /* CAP2 register is only defined for AHCI 1.2 and later */
386 vers = readl(mmio + HOST_VERSION);
387 if ((vers >> 16) > 1 ||
388 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
389 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
390 else
391 hpriv->saved_cap2 = cap2 = 0;
392
393 /* some chips have errata preventing 64bit use */
394 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
395 dev_printk(KERN_INFO, dev,
396 "controller can't do 64bit DMA, forcing 32bit\n");
397 cap &= ~HOST_CAP_64;
398 }
399
400 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
401 dev_printk(KERN_INFO, dev,
402 "controller can't do NCQ, turning off CAP_NCQ\n");
403 cap &= ~HOST_CAP_NCQ;
404 }
405
406 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
407 dev_printk(KERN_INFO, dev,
408 "controller can do NCQ, turning on CAP_NCQ\n");
409 cap |= HOST_CAP_NCQ;
410 }
411
412 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
413 dev_printk(KERN_INFO, dev,
414 "controller can't do PMP, turning off CAP_PMP\n");
415 cap &= ~HOST_CAP_PMP;
416 }
417
418 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
419 dev_printk(KERN_INFO, dev,
420 "controller can't do SNTF, turning off CAP_SNTF\n");
421 cap &= ~HOST_CAP_SNTF;
422 }
423
5f173107
TH		 424 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
425 dev_printk(KERN_INFO, dev,
426 "controller can do FBS, turning on CAP_FBS\n");
427 cap |= HOST_CAP_FBS;
428 }
429
365cfa1e
AV		 430 if (force_port_map && port_map != force_port_map) {
431 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
432 port_map, force_port_map);
433 port_map = force_port_map;
434 }
435
436 if (mask_port_map) {
437 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
438 port_map,
439 port_map & mask_port_map);
440 port_map &= mask_port_map;
441 }
442
443 /* cross check port_map and cap.n_ports */
444 if (port_map) {
445 int map_ports = 0;
446
447 for (i = 0; i < AHCI_MAX_PORTS; i++)
448 if (port_map & (1 << i))
449 map_ports++;
450
451 /* If PI has more ports than n_ports, whine, clear
452 * port_map and let it be generated from n_ports.
453 */
454 if (map_ports > ahci_nr_ports(cap)) {
455 dev_printk(KERN_WARNING, dev,
456 "implemented port map (0x%x) contains more "
457 "ports than nr_ports (%u), using nr_ports\n",
458 port_map, ahci_nr_ports(cap));
459 port_map = 0;
460 }
461 }
462
463 /* fabricate port_map from cap.nr_ports */
464 if (!port_map) {
465 port_map = (1 << ahci_nr_ports(cap)) - 1;
466 dev_printk(KERN_WARNING, dev,
467 "forcing PORTS_IMPL to 0x%x\n", port_map);
468
469 /* write the fixed up value to the PI register */
470 hpriv->saved_port_map = port_map;
471 }
472
473 /* record values to use during operation */
474 hpriv->cap = cap;
475 hpriv->cap2 = cap2;
476 hpriv->port_map = port_map;
477}
478EXPORT_SYMBOL_GPL(ahci_save_initial_config);
479
480/**
481 * ahci_restore_initial_config - Restore initial config
482 * @host: target ATA host
483 *
484 * Restore initial config stored by ahci_save_initial_config().
485 *
486 * LOCKING:
487 * None.
488 */
489static void ahci_restore_initial_config(struct ata_host *host)
490{
491 struct ahci_host_priv *hpriv = host->private_data;
492 void __iomem *mmio = hpriv->mmio;
493
494 writel(hpriv->saved_cap, mmio + HOST_CAP);
495 if (hpriv->saved_cap2)
496 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
497 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
498 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
499}
500
501static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
502{
503 static const int offset[] = {
504 [SCR_STATUS] = PORT_SCR_STAT,
505 [SCR_CONTROL] = PORT_SCR_CTL,
506 [SCR_ERROR] = PORT_SCR_ERR,
507 [SCR_ACTIVE] = PORT_SCR_ACT,
508 [SCR_NOTIFICATION] = PORT_SCR_NTF,
509 };
510 struct ahci_host_priv *hpriv = ap->host->private_data;
511
512 if (sc_reg < ARRAY_SIZE(offset) &&
513 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
514 return offset[sc_reg];
515 return 0;
516}
517
518static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
519{
520 void __iomem *port_mmio = ahci_port_base(link->ap);
521 int offset = ahci_scr_offset(link->ap, sc_reg);
522
523 if (offset) {
524 *val = readl(port_mmio + offset);
525 return 0;
526 }
527 return -EINVAL;
528}
529
530static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
531{
532 void __iomem *port_mmio = ahci_port_base(link->ap);
533 int offset = ahci_scr_offset(link->ap, sc_reg);
534
535 if (offset) {
536 writel(val, port_mmio + offset);
537 return 0;
538 }
539 return -EINVAL;
540}
541
542void ahci_start_engine(struct ata_port *ap)
543{
544 void __iomem *port_mmio = ahci_port_base(ap);
545 u32 tmp;
546
547 /* start DMA */
548 tmp = readl(port_mmio + PORT_CMD);
549 tmp |= PORT_CMD_START;
550 writel(tmp, port_mmio + PORT_CMD);
551 readl(port_mmio + PORT_CMD); /* flush */
552}
553EXPORT_SYMBOL_GPL(ahci_start_engine);
554
555int ahci_stop_engine(struct ata_port *ap)
556{
557 void __iomem *port_mmio = ahci_port_base(ap);
558 u32 tmp;
559
560 tmp = readl(port_mmio + PORT_CMD);
561
562 /* check if the HBA is idle */
563 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
564 return 0;
565
566 /* setting HBA to idle */
567 tmp &= ~PORT_CMD_START;
568 writel(tmp, port_mmio + PORT_CMD);
569
570 /* wait for engine to stop. This could be as long as 500 msec */
571 tmp = ata_wait_register(port_mmio + PORT_CMD,
572 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
573 if (tmp & PORT_CMD_LIST_ON)
574 return -EIO;
575
576 return 0;
577}
578EXPORT_SYMBOL_GPL(ahci_stop_engine);
579
580static void ahci_start_fis_rx(struct ata_port *ap)
581{
582 void __iomem *port_mmio = ahci_port_base(ap);
583 struct ahci_host_priv *hpriv = ap->host->private_data;
584 struct ahci_port_priv *pp = ap->private_data;
585 u32 tmp;
586
587 /* set FIS registers */
588 if (hpriv->cap & HOST_CAP_64)
589 writel((pp->cmd_slot_dma >> 16) >> 16,
590 port_mmio + PORT_LST_ADDR_HI);
591 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
592
593 if (hpriv->cap & HOST_CAP_64)
594 writel((pp->rx_fis_dma >> 16) >> 16,
595 port_mmio + PORT_FIS_ADDR_HI);
596 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
597
598 /* enable FIS reception */
599 tmp = readl(port_mmio + PORT_CMD);
600 tmp |= PORT_CMD_FIS_RX;
601 writel(tmp, port_mmio + PORT_CMD);
602
603 /* flush */
604 readl(port_mmio + PORT_CMD);
605}
606
607static int ahci_stop_fis_rx(struct ata_port *ap)
608{
609 void __iomem *port_mmio = ahci_port_base(ap);
610 u32 tmp;
611
612 /* disable FIS reception */
613 tmp = readl(port_mmio + PORT_CMD);
614 tmp &= ~PORT_CMD_FIS_RX;
615 writel(tmp, port_mmio + PORT_CMD);
616
617 /* wait for completion, spec says 500ms, give it 1000 */
618 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
619 PORT_CMD_FIS_ON, 10, 1000);
620 if (tmp & PORT_CMD_FIS_ON)
621 return -EBUSY;
622
623 return 0;
624}
625
626static void ahci_power_up(struct ata_port *ap)
627{
628 struct ahci_host_priv *hpriv = ap->host->private_data;
629 void __iomem *port_mmio = ahci_port_base(ap);
630 u32 cmd;
631
632 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
633
634 /* spin up device */
635 if (hpriv->cap & HOST_CAP_SSS) {
636 cmd |= PORT_CMD_SPIN_UP;
637 writel(cmd, port_mmio + PORT_CMD);
638 }
639
640 /* wake up link */
641 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
642}
643
644static void ahci_disable_alpm(struct ata_port *ap)
645{
646 struct ahci_host_priv *hpriv = ap->host->private_data;
647 void __iomem *port_mmio = ahci_port_base(ap);
648 u32 cmd;
649 struct ahci_port_priv *pp = ap->private_data;
650
c93b263e 651 /* LPM bits should be disabled by libata-core */
365cfa1e
AV		 652 /* get the existing command bits */
653 cmd = readl(port_mmio + PORT_CMD);
654
655 /* disable ALPM and ASP */
656 cmd &= ~PORT_CMD_ASP;
657 cmd &= ~PORT_CMD_ALPE;
658
659 /* force the interface back to active */
660 cmd |= PORT_CMD_ICC_ACTIVE;
661
662 /* write out new cmd value */
663 writel(cmd, port_mmio + PORT_CMD);
664 cmd = readl(port_mmio + PORT_CMD);
665
666 /* wait 10ms to be sure we've come out of any low power state */
667 msleep(10);
668
669 /* clear out any PhyRdy stuff from interrupt status */
670 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
671
672 /* go ahead and clean out PhyRdy Change from Serror too */
673 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
674
675 /*
676 * Clear flag to indicate that we should ignore all PhyRdy
677 * state changes
678 */
679 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
680
681 /*
682 * Enable interrupts on Phy Ready.
683 */
684 pp->intr_mask |= PORT_IRQ_PHYRDY;
685 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
686
687 /*
688 * don't change the link pm policy - we can be called
689 * just to turn of link pm temporarily
690 */
691}
692
c93b263e 693static int ahci_enable_alpm(struct ata_port *ap, enum ata_lpm_policy policy)
365cfa1e
AV		 694{
695 struct ahci_host_priv *hpriv = ap->host->private_data;
696 void __iomem *port_mmio = ahci_port_base(ap);
697 u32 cmd;
698 struct ahci_port_priv *pp = ap->private_data;
699 u32 asp;
700
701 /* Make sure the host is capable of link power management */
702 if (!(hpriv->cap & HOST_CAP_ALPM))
703 return -EINVAL;
704
705 switch (policy) {
c93b263e
TH		 706 case ATA_LPM_MAX_POWER:
707 case ATA_LPM_UNKNOWN:
365cfa1e 708 /*
c93b263e 709 * if we came here with ATA_LPM_UNKNOWN,
365cfa1e
AV		 710 * it just means this is the first time we
711 * have tried to enable - default to max performance,
712 * and let the user go to lower power modes on request.
713 */
714 ahci_disable_alpm(ap);
715 return 0;
c93b263e 716 case ATA_LPM_MIN_POWER:
365cfa1e
AV		 717 /* configure HBA to enter SLUMBER */
718 asp = PORT_CMD_ASP;
719 break;
c93b263e 720 case ATA_LPM_MED_POWER:
365cfa1e
AV		 721 /* configure HBA to enter PARTIAL */
722 asp = 0;
723 break;
724 default:
725 return -EINVAL;
726 }
727
728 /*
729 * Disable interrupts on Phy Ready. This keeps us from
730 * getting woken up due to spurious phy ready interrupts
731 * TBD - Hot plug should be done via polling now, is
732 * that even supported?
733 */
734 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
735 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
736
737 /*
738 * Set a flag to indicate that we should ignore all PhyRdy
739 * state changes since these can happen now whenever we
740 * change link state
741 */
742 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
743
744 /* get the existing command bits */
745 cmd = readl(port_mmio + PORT_CMD);
746
747 /*
748 * Set ASP based on Policy
749 */
750 cmd |= asp;
751
752 /*
753 * Setting this bit will instruct the HBA to aggressively
754 * enter a lower power link state when it's appropriate and
755 * based on the value set above for ASP
756 */
757 cmd |= PORT_CMD_ALPE;
758
759 /* write out new cmd value */
760 writel(cmd, port_mmio + PORT_CMD);
761 cmd = readl(port_mmio + PORT_CMD);
762
c93b263e 763 /* LPM bits should be set by libata-core */
365cfa1e
AV		 764 return 0;
765}
766
767#ifdef CONFIG_PM
768static void ahci_power_down(struct ata_port *ap)
769{
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 void __iomem *port_mmio = ahci_port_base(ap);
772 u32 cmd, scontrol;
773
774 if (!(hpriv->cap & HOST_CAP_SSS))
775 return;
776
777 /* put device into listen mode, first set PxSCTL.DET to 0 */
778 scontrol = readl(port_mmio + PORT_SCR_CTL);
779 scontrol &= ~0xf;
780 writel(scontrol, port_mmio + PORT_SCR_CTL);
781
782 /* then set PxCMD.SUD to 0 */
783 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
784 cmd &= ~PORT_CMD_SPIN_UP;
785 writel(cmd, port_mmio + PORT_CMD);
786}
787#endif
788
789static void ahci_start_port(struct ata_port *ap)
790{
791 struct ahci_port_priv *pp = ap->private_data;
792 struct ata_link *link;
793 struct ahci_em_priv *emp;
794 ssize_t rc;
795 int i;
796
797 /* enable FIS reception */
798 ahci_start_fis_rx(ap);
799
800 /* enable DMA */
801 ahci_start_engine(ap);
802
803 /* turn on LEDs */
804 if (ap->flags & ATA_FLAG_EM) {
805 ata_for_each_link(link, ap, EDGE) {
806 emp = &pp->em_priv[link->pmp];
807
808 /* EM Transmit bit maybe busy during init */
809 for (i = 0; i < EM_MAX_RETRY; i++) {
810 rc = ahci_transmit_led_message(ap,
811 emp->led_state,
812 4);
813 if (rc == -EBUSY)
814 msleep(1);
815 else
816 break;
817 }
818 }
819 }
820
821 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
822 ata_for_each_link(link, ap, EDGE)
823 ahci_init_sw_activity(link);
824
825}
826
827static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
828{
829 int rc;
830
831 /* disable DMA */
832 rc = ahci_stop_engine(ap);
833 if (rc) {
834 *emsg = "failed to stop engine";
835 return rc;
836 }
837
838 /* disable FIS reception */
839 rc = ahci_stop_fis_rx(ap);
840 if (rc) {
841 *emsg = "failed stop FIS RX";
842 return rc;
843 }
844
845 return 0;
846}
847
848int ahci_reset_controller(struct ata_host *host)
849{
850 struct ahci_host_priv *hpriv = host->private_data;
851 void __iomem *mmio = hpriv->mmio;
852 u32 tmp;
853
854 /* we must be in AHCI mode, before using anything
855 * AHCI-specific, such as HOST_RESET.
856 */
857 ahci_enable_ahci(mmio);
858
859 /* global controller reset */
860 if (!ahci_skip_host_reset) {
861 tmp = readl(mmio + HOST_CTL);
862 if ((tmp & HOST_RESET) == 0) {
863 writel(tmp | HOST_RESET, mmio + HOST_CTL);
864 readl(mmio + HOST_CTL); /* flush */
865 }
866
867 /*
868 * to perform host reset, OS should set HOST_RESET
869 * and poll until this bit is read to be "0".
870 * reset must complete within 1 second, or
871 * the hardware should be considered fried.
872 */
873 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
874 HOST_RESET, 10, 1000);
875
876 if (tmp & HOST_RESET) {
877 dev_printk(KERN_ERR, host->dev,
878 "controller reset failed (0x%x)\n", tmp);
879 return -EIO;
880 }
881
882 /* turn on AHCI mode */
883 ahci_enable_ahci(mmio);
884
885 /* Some registers might be cleared on reset. Restore
886 * initial values.
887 */
888 ahci_restore_initial_config(host);
889 } else
890 dev_printk(KERN_INFO, host->dev,
891 "skipping global host reset\n");
892
893 return 0;
894}
895EXPORT_SYMBOL_GPL(ahci_reset_controller);
896
897static void ahci_sw_activity(struct ata_link *link)
898{
899 struct ata_port *ap = link->ap;
900 struct ahci_port_priv *pp = ap->private_data;
901 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
902
903 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
904 return;
905
906 emp->activity++;
907 if (!timer_pending(&emp->timer))
908 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
909}
910
911static void ahci_sw_activity_blink(unsigned long arg)
912{
913 struct ata_link *link = (struct ata_link *)arg;
914 struct ata_port *ap = link->ap;
915 struct ahci_port_priv *pp = ap->private_data;
916 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
917 unsigned long led_message = emp->led_state;
918 u32 activity_led_state;
919 unsigned long flags;
920
921 led_message &= EM_MSG_LED_VALUE;
922 led_message |= ap->port_no | (link->pmp << 8);
923
924 /* check to see if we've had activity. If so,
925 * toggle state of LED and reset timer. If not,
926 * turn LED to desired idle state.
927 */
928 spin_lock_irqsave(ap->lock, flags);
929 if (emp->saved_activity != emp->activity) {
930 emp->saved_activity = emp->activity;
931 /* get the current LED state */
932 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
933
934 if (activity_led_state)
935 activity_led_state = 0;
936 else
937 activity_led_state = 1;
938
939 /* clear old state */
940 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
941
942 /* toggle state */
943 led_message |= (activity_led_state << 16);
944 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
945 } else {
946 /* switch to idle */
947 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
948 if (emp->blink_policy == BLINK_OFF)
949 led_message |= (1 << 16);
950 }
951 spin_unlock_irqrestore(ap->lock, flags);
952 ahci_transmit_led_message(ap, led_message, 4);
953}
954
955static void ahci_init_sw_activity(struct ata_link *link)
956{
957 struct ata_port *ap = link->ap;
958 struct ahci_port_priv *pp = ap->private_data;
959 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
960
961 /* init activity stats, setup timer */
962 emp->saved_activity = emp->activity = 0;
963 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
964
965 /* check our blink policy and set flag for link if it's enabled */
966 if (emp->blink_policy)
967 link->flags |= ATA_LFLAG_SW_ACTIVITY;
968}
969
970int ahci_reset_em(struct ata_host *host)
971{
972 struct ahci_host_priv *hpriv = host->private_data;
973 void __iomem *mmio = hpriv->mmio;
974 u32 em_ctl;
975
976 em_ctl = readl(mmio + HOST_EM_CTL);
977 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
978 return -EINVAL;
979
980 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
981 return 0;
982}
983EXPORT_SYMBOL_GPL(ahci_reset_em);
984
985static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
986 ssize_t size)
987{
988 struct ahci_host_priv *hpriv = ap->host->private_data;
989 struct ahci_port_priv *pp = ap->private_data;
990 void __iomem *mmio = hpriv->mmio;
991 u32 em_ctl;
992 u32 message[] = {0, 0};
993 unsigned long flags;
994 int pmp;
995 struct ahci_em_priv *emp;
996
997 /* get the slot number from the message */
998 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
999 if (pmp < EM_MAX_SLOTS)
1000 emp = &pp->em_priv[pmp];
1001 else
1002 return -EINVAL;
1003
1004 spin_lock_irqsave(ap->lock, flags);
1005
1006 /*
1007 * if we are still busy transmitting a previous message,
1008 * do not allow
1009 */
1010 em_ctl = readl(mmio + HOST_EM_CTL);
1011 if (em_ctl & EM_CTL_TM) {
1012 spin_unlock_irqrestore(ap->lock, flags);
1013 return -EBUSY;
1014 }
1015
008dbd61
HZ		 1016 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1017 /*
1018 * create message header - this is all zero except for
1019 * the message size, which is 4 bytes.
1020 */
1021 message[0] |= (4 << 8);
365cfa1e 1022
008dbd61
HZ		 1023 /* ignore 0:4 of byte zero, fill in port info yourself */
1024 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1025
008dbd61
HZ		 1026 /* write message to EM_LOC */
1027 writel(message[0], mmio + hpriv->em_loc);
1028 writel(message[1], mmio + hpriv->em_loc+4);
1029
1030 /*
1031 * tell hardware to transmit the message
1032 */
1033 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1034 }
365cfa1e
AV		 1035
1036 /* save off new led state for port/slot */
1037 emp->led_state = state;
1038
365cfa1e
AV		 1039 spin_unlock_irqrestore(ap->lock, flags);
1040 return size;
1041}
1042
1043static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1044{
1045 struct ahci_port_priv *pp = ap->private_data;
1046 struct ata_link *link;
1047 struct ahci_em_priv *emp;
1048 int rc = 0;
1049
1050 ata_for_each_link(link, ap, EDGE) {
1051 emp = &pp->em_priv[link->pmp];
1052 rc += sprintf(buf, "%lx\n", emp->led_state);
1053 }
1054 return rc;
1055}
1056
1057static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1058 size_t size)
1059{
1060 int state;
1061 int pmp;
1062 struct ahci_port_priv *pp = ap->private_data;
1063 struct ahci_em_priv *emp;
1064
1065 state = simple_strtoul(buf, NULL, 0);
1066
1067 /* get the slot number from the message */
1068 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1069 if (pmp < EM_MAX_SLOTS)
1070 emp = &pp->em_priv[pmp];
1071 else
1072 return -EINVAL;
1073
1074 /* mask off the activity bits if we are in sw_activity
1075 * mode, user should turn off sw_activity before setting
1076 * activity led through em_message
1077 */
1078 if (emp->blink_policy)
1079 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1080
1081 return ahci_transmit_led_message(ap, state, size);
1082}
1083
1084static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1085{
1086 struct ata_link *link = dev->link;
1087 struct ata_port *ap = link->ap;
1088 struct ahci_port_priv *pp = ap->private_data;
1089 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1090 u32 port_led_state = emp->led_state;
1091
1092 /* save the desired Activity LED behavior */
1093 if (val == OFF) {
1094 /* clear LFLAG */
1095 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1096
1097 /* set the LED to OFF */
1098 port_led_state &= EM_MSG_LED_VALUE_OFF;
1099 port_led_state |= (ap->port_no | (link->pmp << 8));
1100 ahci_transmit_led_message(ap, port_led_state, 4);
1101 } else {
1102 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1103 if (val == BLINK_OFF) {
1104 /* set LED to ON for idle */
1105 port_led_state &= EM_MSG_LED_VALUE_OFF;
1106 port_led_state |= (ap->port_no | (link->pmp << 8));
1107 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1108 ahci_transmit_led_message(ap, port_led_state, 4);
1109 }
1110 }
1111 emp->blink_policy = val;
1112 return 0;
1113}
1114
1115static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1116{
1117 struct ata_link *link = dev->link;
1118 struct ata_port *ap = link->ap;
1119 struct ahci_port_priv *pp = ap->private_data;
1120 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1121
1122 /* display the saved value of activity behavior for this
1123 * disk.
1124 */
1125 return sprintf(buf, "%d\n", emp->blink_policy);
1126}
1127
1128static void ahci_port_init(struct device *dev, struct ata_port *ap,
1129 int port_no, void __iomem *mmio,
1130 void __iomem *port_mmio)
1131{
1132 const char *emsg = NULL;
1133 int rc;
1134 u32 tmp;
1135
1136 /* make sure port is not active */
1137 rc = ahci_deinit_port(ap, &emsg);
1138 if (rc)
1139 dev_warn(dev, "%s (%d)\n", emsg, rc);
1140
1141 /* clear SError */
1142 tmp = readl(port_mmio + PORT_SCR_ERR);
1143 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1144 writel(tmp, port_mmio + PORT_SCR_ERR);
1145
1146 /* clear port IRQ */
1147 tmp = readl(port_mmio + PORT_IRQ_STAT);
1148 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1149 if (tmp)
1150 writel(tmp, port_mmio + PORT_IRQ_STAT);
1151
1152 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1153}
1154
1155void ahci_init_controller(struct ata_host *host)
1156{
1157 struct ahci_host_priv *hpriv = host->private_data;
1158 void __iomem *mmio = hpriv->mmio;
1159 int i;
1160 void __iomem *port_mmio;
1161 u32 tmp;
1162
1163 for (i = 0; i < host->n_ports; i++) {
1164 struct ata_port *ap = host->ports[i];
1165
1166 port_mmio = ahci_port_base(ap);
1167 if (ata_port_is_dummy(ap))
1168 continue;
1169
1170 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1171 }
1172
1173 tmp = readl(mmio + HOST_CTL);
1174 VPRINTK("HOST_CTL 0x%x\n", tmp);
1175 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1176 tmp = readl(mmio + HOST_CTL);
1177 VPRINTK("HOST_CTL 0x%x\n", tmp);
1178}
1179EXPORT_SYMBOL_GPL(ahci_init_controller);
1180
1181static void ahci_dev_config(struct ata_device *dev)
1182{
1183 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1184
1185 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1186 dev->max_sectors = 255;
1187 ata_dev_printk(dev, KERN_INFO,
1188 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1189 }
1190}
1191
1192static unsigned int ahci_dev_classify(struct ata_port *ap)
1193{
1194 void __iomem *port_mmio = ahci_port_base(ap);
1195 struct ata_taskfile tf;
1196 u32 tmp;
1197
1198 tmp = readl(port_mmio + PORT_SIG);
1199 tf.lbah = (tmp >> 24) & 0xff;
1200 tf.lbam = (tmp >> 16) & 0xff;
1201 tf.lbal = (tmp >> 8) & 0xff;
1202 tf.nsect = (tmp) & 0xff;
1203
1204 return ata_dev_classify(&tf);
1205}
1206
1207static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1208 u32 opts)
1209{
1210 dma_addr_t cmd_tbl_dma;
1211
1212 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1213
1214 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1215 pp->cmd_slot[tag].status = 0;
1216 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1217 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1218}
1219
1220int ahci_kick_engine(struct ata_port *ap)
1221{
1222 void __iomem *port_mmio = ahci_port_base(ap);
1223 struct ahci_host_priv *hpriv = ap->host->private_data;
1224 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1225 u32 tmp;
1226 int busy, rc;
1227
1228 /* stop engine */
1229 rc = ahci_stop_engine(ap);
1230 if (rc)
1231 goto out_restart;
1232
1233 /* need to do CLO?
1234 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1235 */
1236 busy = status & (ATA_BUSY | ATA_DRQ);
1237 if (!busy && !sata_pmp_attached(ap)) {
1238 rc = 0;
1239 goto out_restart;
1240 }
1241
1242 if (!(hpriv->cap & HOST_CAP_CLO)) {
1243 rc = -EOPNOTSUPP;
1244 goto out_restart;
1245 }
1246
1247 /* perform CLO */
1248 tmp = readl(port_mmio + PORT_CMD);
1249 tmp |= PORT_CMD_CLO;
1250 writel(tmp, port_mmio + PORT_CMD);
1251
1252 rc = 0;
1253 tmp = ata_wait_register(port_mmio + PORT_CMD,
1254 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1255 if (tmp & PORT_CMD_CLO)
1256 rc = -EIO;
1257
1258 /* restart engine */
1259 out_restart:
1260 ahci_start_engine(ap);
1261 return rc;
1262}
1263EXPORT_SYMBOL_GPL(ahci_kick_engine);
1264
1265static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1266 struct ata_taskfile *tf, int is_cmd, u16 flags,
1267 unsigned long timeout_msec)
1268{
1269 const u32 cmd_fis_len = 5; /* five dwords */
1270 struct ahci_port_priv *pp = ap->private_data;
1271 void __iomem *port_mmio = ahci_port_base(ap);
1272 u8 *fis = pp->cmd_tbl;
1273 u32 tmp;
1274
1275 /* prep the command */
1276 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1277 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1278
1279 /* issue & wait */
1280 writel(1, port_mmio + PORT_CMD_ISSUE);
1281
1282 if (timeout_msec) {
1283 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1284 1, timeout_msec);
1285 if (tmp & 0x1) {
1286 ahci_kick_engine(ap);
1287 return -EBUSY;
1288 }
1289 } else
1290 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1291
1292 return 0;
1293}
1294
1295int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1296 int pmp, unsigned long deadline,
1297 int (*check_ready)(struct ata_link *link))
1298{
1299 struct ata_port *ap = link->ap;
1300 struct ahci_host_priv *hpriv = ap->host->private_data;
1301 const char *reason = NULL;
1302 unsigned long now, msecs;
1303 struct ata_taskfile tf;
1304 int rc;
1305
1306 DPRINTK("ENTER\n");
1307
1308 /* prepare for SRST (AHCI-1.1 10.4.1) */
1309 rc = ahci_kick_engine(ap);
1310 if (rc && rc != -EOPNOTSUPP)
1311 ata_link_printk(link, KERN_WARNING,
1312 "failed to reset engine (errno=%d)\n", rc);
1313
1314 ata_tf_init(link->device, &tf);
1315
1316 /* issue the first D2H Register FIS */
1317 msecs = 0;
1318 now = jiffies;
f1f5a807 1319 if (time_after(deadline, now))
365cfa1e
AV		 1320 msecs = jiffies_to_msecs(deadline - now);
1321
1322 tf.ctl |= ATA_SRST;
1323 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1324 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1325 rc = -EIO;
1326 reason = "1st FIS failed";
1327 goto fail;
1328 }
1329
1330 /* spec says at least 5us, but be generous and sleep for 1ms */
1331 msleep(1);
1332
1333 /* issue the second D2H Register FIS */
1334 tf.ctl &= ~ATA_SRST;
1335 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1336
1337 /* wait for link to become ready */
1338 rc = ata_wait_after_reset(link, deadline, check_ready);
1339 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1340 /*
1341 * Workaround for cases where link online status can't
1342 * be trusted. Treat device readiness timeout as link
1343 * offline.
1344 */
1345 ata_link_printk(link, KERN_INFO,
1346 "device not ready, treating as offline\n");
1347 *class = ATA_DEV_NONE;
1348 } else if (rc) {
1349 /* link occupied, -ENODEV too is an error */
1350 reason = "device not ready";
1351 goto fail;
1352 } else
1353 *class = ahci_dev_classify(ap);
1354
1355 DPRINTK("EXIT, class=%u\n", *class);
1356 return 0;
1357
1358 fail:
1359 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1360 return rc;
1361}
1362
1363int ahci_check_ready(struct ata_link *link)
1364{
1365 void __iomem *port_mmio = ahci_port_base(link->ap);
1366 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1367
1368 return ata_check_ready(status);
1369}
1370EXPORT_SYMBOL_GPL(ahci_check_ready);
1371
1372static int ahci_softreset(struct ata_link *link, unsigned int *class,
1373 unsigned long deadline)
1374{
1375 int pmp = sata_srst_pmp(link);
1376
1377 DPRINTK("ENTER\n");
1378
1379 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1380}
1381EXPORT_SYMBOL_GPL(ahci_do_softreset);
1382
1383static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1384 unsigned long deadline)
1385{
1386 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1387 struct ata_port *ap = link->ap;
1388 struct ahci_port_priv *pp = ap->private_data;
1389 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1390 struct ata_taskfile tf;
1391 bool online;
1392 int rc;
1393
1394 DPRINTK("ENTER\n");
1395
1396 ahci_stop_engine(ap);
1397
1398 /* clear D2H reception area to properly wait for D2H FIS */
1399 ata_tf_init(link->device, &tf);
1400 tf.command = 0x80;
1401 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1402
1403 rc = sata_link_hardreset(link, timing, deadline, &online,
1404 ahci_check_ready);
1405
1406 ahci_start_engine(ap);
1407
1408 if (online)
1409 *class = ahci_dev_classify(ap);
1410
1411 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1412 return rc;
1413}
1414
1415static void ahci_postreset(struct ata_link *link, unsigned int *class)
1416{
1417 struct ata_port *ap = link->ap;
1418 void __iomem *port_mmio = ahci_port_base(ap);
1419 u32 new_tmp, tmp;
1420
1421 ata_std_postreset(link, class);
1422
1423 /* Make sure port's ATAPI bit is set appropriately */
1424 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1425 if (*class == ATA_DEV_ATAPI)
1426 new_tmp |= PORT_CMD_ATAPI;
1427 else
1428 new_tmp &= ~PORT_CMD_ATAPI;
1429 if (new_tmp != tmp) {
1430 writel(new_tmp, port_mmio + PORT_CMD);
1431 readl(port_mmio + PORT_CMD); /* flush */
1432 }
1433}
1434
1435static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1436{
1437 struct scatterlist *sg;
1438 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1439 unsigned int si;
1440
1441 VPRINTK("ENTER\n");
1442
1443 /*
1444 * Next, the S/G list.
1445 */
1446 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1447 dma_addr_t addr = sg_dma_address(sg);
1448 u32 sg_len = sg_dma_len(sg);
1449
1450 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1451 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1452 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1453 }
1454
1455 return si;
1456}
1457
1458static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1459{
1460 struct ata_port *ap = qc->ap;
1461 struct ahci_port_priv *pp = ap->private_data;
1462
1463 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1464 return ata_std_qc_defer(qc);
1465 else
1466 return sata_pmp_qc_defer_cmd_switch(qc);
1467}
1468
1469static void ahci_qc_prep(struct ata_queued_cmd *qc)
1470{
1471 struct ata_port *ap = qc->ap;
1472 struct ahci_port_priv *pp = ap->private_data;
1473 int is_atapi = ata_is_atapi(qc->tf.protocol);
1474 void *cmd_tbl;
1475 u32 opts;
1476 const u32 cmd_fis_len = 5; /* five dwords */
1477 unsigned int n_elem;
1478
1479 /*
1480 * Fill in command table information. First, the header,
1481 * a SATA Register - Host to Device command FIS.
1482 */
1483 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1484
1485 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1486 if (is_atapi) {
1487 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1488 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1489 }
1490
1491 n_elem = 0;
1492 if (qc->flags & ATA_QCFLAG_DMAMAP)
1493 n_elem = ahci_fill_sg(qc, cmd_tbl);
1494
1495 /*
1496 * Fill in command slot information.
1497 */
1498 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1499 if (qc->tf.flags & ATA_TFLAG_WRITE)
1500 opts |= AHCI_CMD_WRITE;
1501 if (is_atapi)
1502 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1503
1504 ahci_fill_cmd_slot(pp, qc->tag, opts);
1505}
1506
1507static void ahci_fbs_dec_intr(struct ata_port *ap)
1508{
1509 struct ahci_port_priv *pp = ap->private_data;
1510 void __iomem *port_mmio = ahci_port_base(ap);
1511 u32 fbs = readl(port_mmio + PORT_FBS);
1512 int retries = 3;
1513
1514 DPRINTK("ENTER\n");
1515 BUG_ON(!pp->fbs_enabled);
1516
1517 /* time to wait for DEC is not specified by AHCI spec,
1518 * add a retry loop for safety.
1519 */
1520 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1521 fbs = readl(port_mmio + PORT_FBS);
1522 while ((fbs & PORT_FBS_DEC) && retries--) {
1523 udelay(1);
1524 fbs = readl(port_mmio + PORT_FBS);
1525 }
1526
1527 if (fbs & PORT_FBS_DEC)
1528 dev_printk(KERN_ERR, ap->host->dev,
1529 "failed to clear device error\n");
1530}
1531
1532static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1533{
1534 struct ahci_host_priv *hpriv = ap->host->private_data;
1535 struct ahci_port_priv *pp = ap->private_data;
1536 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1537 struct ata_link *link = NULL;
1538 struct ata_queued_cmd *active_qc;
1539 struct ata_eh_info *active_ehi;
1540 bool fbs_need_dec = false;
1541 u32 serror;
1542
1543 /* determine active link with error */
1544 if (pp->fbs_enabled) {
1545 void __iomem *port_mmio = ahci_port_base(ap);
1546 u32 fbs = readl(port_mmio + PORT_FBS);
1547 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1548
1549 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1550 ata_link_online(&ap->pmp_link[pmp])) {
1551 link = &ap->pmp_link[pmp];
1552 fbs_need_dec = true;
1553 }
1554
1555 } else
1556 ata_for_each_link(link, ap, EDGE)
1557 if (ata_link_active(link))
1558 break;
1559
1560 if (!link)
1561 link = &ap->link;
1562
1563 active_qc = ata_qc_from_tag(ap, link->active_tag);
1564 active_ehi = &link->eh_info;
1565
1566 /* record irq stat */
1567 ata_ehi_clear_desc(host_ehi);
1568 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1569
1570 /* AHCI needs SError cleared; otherwise, it might lock up */
1571 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1572 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1573 host_ehi->serror |= serror;
1574
1575 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1576 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1577 irq_stat &= ~PORT_IRQ_IF_ERR;
1578
1579 if (irq_stat & PORT_IRQ_TF_ERR) {
1580 /* If qc is active, charge it; otherwise, the active
1581 * link. There's no active qc on NCQ errors. It will
1582 * be determined by EH by reading log page 10h.
1583 */
1584 if (active_qc)
1585 active_qc->err_mask |= AC_ERR_DEV;
1586 else
1587 active_ehi->err_mask |= AC_ERR_DEV;
1588
1589 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1590 host_ehi->serror &= ~SERR_INTERNAL;
1591 }
1592
1593 if (irq_stat & PORT_IRQ_UNK_FIS) {
1594 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1595
1596 active_ehi->err_mask |= AC_ERR_HSM;
1597 active_ehi->action |= ATA_EH_RESET;
1598 ata_ehi_push_desc(active_ehi,
1599 "unknown FIS %08x %08x %08x %08x" ,
1600 unk[0], unk[1], unk[2], unk[3]);
1601 }
1602
1603 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1604 active_ehi->err_mask |= AC_ERR_HSM;
1605 active_ehi->action |= ATA_EH_RESET;
1606 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1607 }
1608
1609 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1610 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1611 host_ehi->action |= ATA_EH_RESET;
1612 ata_ehi_push_desc(host_ehi, "host bus error");
1613 }
1614
1615 if (irq_stat & PORT_IRQ_IF_ERR) {
1616 if (fbs_need_dec)
1617 active_ehi->err_mask |= AC_ERR_DEV;
1618 else {
1619 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1620 host_ehi->action |= ATA_EH_RESET;
1621 }
1622
1623 ata_ehi_push_desc(host_ehi, "interface fatal error");
1624 }
1625
1626 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1627 ata_ehi_hotplugged(host_ehi);
1628 ata_ehi_push_desc(host_ehi, "%s",
1629 irq_stat & PORT_IRQ_CONNECT ?
1630 "connection status changed" : "PHY RDY changed");
1631 }
1632
1633 /* okay, let's hand over to EH */
1634
1635 if (irq_stat & PORT_IRQ_FREEZE)
1636 ata_port_freeze(ap);
1637 else if (fbs_need_dec) {
1638 ata_link_abort(link);
1639 ahci_fbs_dec_intr(ap);
1640 } else
1641 ata_port_abort(ap);
1642}
1643
1644static void ahci_port_intr(struct ata_port *ap)
1645{
1646 void __iomem *port_mmio = ahci_port_base(ap);
1647 struct ata_eh_info *ehi = &ap->link.eh_info;
1648 struct ahci_port_priv *pp = ap->private_data;
1649 struct ahci_host_priv *hpriv = ap->host->private_data;
1650 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1651 u32 status, qc_active = 0;
1652 int rc;
1653
1654 status = readl(port_mmio + PORT_IRQ_STAT);
1655 writel(status, port_mmio + PORT_IRQ_STAT);
1656
1657 /* ignore BAD_PMP while resetting */
1658 if (unlikely(resetting))
1659 status &= ~PORT_IRQ_BAD_PMP;
1660
1661 /* If we are getting PhyRdy, this is
1662 * just a power state change, we should
1663 * clear out this, plus the PhyRdy/Comm
1664 * Wake bits from Serror
1665 */
1666 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1667 (status & PORT_IRQ_PHYRDY)) {
1668 status &= ~PORT_IRQ_PHYRDY;
1669 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1670 }
1671
1672 if (unlikely(status & PORT_IRQ_ERROR)) {
1673 ahci_error_intr(ap, status);
1674 return;
1675 }
1676
1677 if (status & PORT_IRQ_SDB_FIS) {
1678 /* If SNotification is available, leave notification
1679 * handling to sata_async_notification(). If not,
1680 * emulate it by snooping SDB FIS RX area.
1681 *
1682 * Snooping FIS RX area is probably cheaper than
1683 * poking SNotification but some constrollers which
1684 * implement SNotification, ICH9 for example, don't
1685 * store AN SDB FIS into receive area.
1686 */
1687 if (hpriv->cap & HOST_CAP_SNTF)
1688 sata_async_notification(ap);
1689 else {
1690 /* If the 'N' bit in word 0 of the FIS is set,
1691 * we just received asynchronous notification.
1692 * Tell libata about it.
1693 *
1694 * Lack of SNotification should not appear in
1695 * ahci 1.2, so the workaround is unnecessary
1696 * when FBS is enabled.
1697 */
1698 if (pp->fbs_enabled)
1699 WARN_ON_ONCE(1);
1700 else {
1701 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1702 u32 f0 = le32_to_cpu(f[0]);
1703 if (f0 & (1 << 15))
1704 sata_async_notification(ap);
1705 }
1706 }
1707 }
1708
1709 /* pp->active_link is not reliable once FBS is enabled, both
1710 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1711 * NCQ and non-NCQ commands may be in flight at the same time.
1712 */
1713 if (pp->fbs_enabled) {
1714 if (ap->qc_active) {
1715 qc_active = readl(port_mmio + PORT_SCR_ACT);
1716 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1717 }
1718 } else {
1719 /* pp->active_link is valid iff any command is in flight */
1720 if (ap->qc_active && pp->active_link->sactive)
1721 qc_active = readl(port_mmio + PORT_SCR_ACT);
1722 else
1723 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1724 }
1725
1726
1727 rc = ata_qc_complete_multiple(ap, qc_active);
1728
1729 /* while resetting, invalid completions are expected */
1730 if (unlikely(rc < 0 && !resetting)) {
1731 ehi->err_mask |= AC_ERR_HSM;
1732 ehi->action |= ATA_EH_RESET;
1733 ata_port_freeze(ap);
1734 }
1735}
1736
1737irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1738{
1739 struct ata_host *host = dev_instance;
1740 struct ahci_host_priv *hpriv;
1741 unsigned int i, handled = 0;
1742 void __iomem *mmio;
1743 u32 irq_stat, irq_masked;
1744
1745 VPRINTK("ENTER\n");
1746
1747 hpriv = host->private_data;
1748 mmio = hpriv->mmio;
1749
1750 /* sigh. 0xffffffff is a valid return from h/w */
1751 irq_stat = readl(mmio + HOST_IRQ_STAT);
1752 if (!irq_stat)
1753 return IRQ_NONE;
1754
1755 irq_masked = irq_stat & hpriv->port_map;
1756
1757 spin_lock(&host->lock);
1758
1759 for (i = 0; i < host->n_ports; i++) {
1760 struct ata_port *ap;
1761
1762 if (!(irq_masked & (1 << i)))
1763 continue;
1764
1765 ap = host->ports[i];
1766 if (ap) {
1767 ahci_port_intr(ap);
1768 VPRINTK("port %u\n", i);
1769 } else {
1770 VPRINTK("port %u (no irq)\n", i);
1771 if (ata_ratelimit())
1772 dev_printk(KERN_WARNING, host->dev,
1773 "interrupt on disabled port %u\n", i);
1774 }
1775
1776 handled = 1;
1777 }
1778
1779 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1780 * it should be cleared after all the port events are cleared;
1781 * otherwise, it will raise a spurious interrupt after each
1782 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1783 * information.
1784 *
1785 * Also, use the unmasked value to clear interrupt as spurious
1786 * pending event on a dummy port might cause screaming IRQ.
1787 */
1788 writel(irq_stat, mmio + HOST_IRQ_STAT);
1789
1790 spin_unlock(&host->lock);
1791
1792 VPRINTK("EXIT\n");
1793
1794 return IRQ_RETVAL(handled);
1795}
1796EXPORT_SYMBOL_GPL(ahci_interrupt);
1797
1798static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1799{
1800 struct ata_port *ap = qc->ap;
1801 void __iomem *port_mmio = ahci_port_base(ap);
1802 struct ahci_port_priv *pp = ap->private_data;
1803
1804 /* Keep track of the currently active link. It will be used
1805 * in completion path to determine whether NCQ phase is in
1806 * progress.
1807 */
1808 pp->active_link = qc->dev->link;
1809
1810 if (qc->tf.protocol == ATA_PROT_NCQ)
1811 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1812
1813 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1814 u32 fbs = readl(port_mmio + PORT_FBS);
1815 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1816 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1817 writel(fbs, port_mmio + PORT_FBS);
1818 pp->fbs_last_dev = qc->dev->link->pmp;
1819 }
1820
1821 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1822
1823 ahci_sw_activity(qc->dev->link);
1824
1825 return 0;
1826}
1827
1828static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1829{
1830 struct ahci_port_priv *pp = qc->ap->private_data;
1831 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1832
1833 if (pp->fbs_enabled)
1834 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1835
1836 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1837 return true;
1838}
1839
1840static void ahci_freeze(struct ata_port *ap)
1841{
1842 void __iomem *port_mmio = ahci_port_base(ap);
1843
1844 /* turn IRQ off */
1845 writel(0, port_mmio + PORT_IRQ_MASK);
1846}
1847
1848static void ahci_thaw(struct ata_port *ap)
1849{
1850 struct ahci_host_priv *hpriv = ap->host->private_data;
1851 void __iomem *mmio = hpriv->mmio;
1852 void __iomem *port_mmio = ahci_port_base(ap);
1853 u32 tmp;
1854 struct ahci_port_priv *pp = ap->private_data;
1855
1856 /* clear IRQ */
1857 tmp = readl(port_mmio + PORT_IRQ_STAT);
1858 writel(tmp, port_mmio + PORT_IRQ_STAT);
1859 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1860
1861 /* turn IRQ back on */
1862 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1863}
1864
1865static void ahci_error_handler(struct ata_port *ap)
1866{
1867 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1868 /* restart engine */
1869 ahci_stop_engine(ap);
1870 ahci_start_engine(ap);
1871 }
1872
1873 sata_pmp_error_handler(ap);
0ee71952
TH		 1874
1875 if (!ata_dev_enabled(ap->link.device))
1876 ahci_stop_engine(ap);
365cfa1e
AV		 1877}
1878
1879static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1880{
1881 struct ata_port *ap = qc->ap;
1882
1883 /* make DMA engine forget about the failed command */
1884 if (qc->flags & ATA_QCFLAG_FAILED)
1885 ahci_kick_engine(ap);
1886}
1887
1888static void ahci_enable_fbs(struct ata_port *ap)
1889{
1890 struct ahci_port_priv *pp = ap->private_data;
1891 void __iomem *port_mmio = ahci_port_base(ap);
1892 u32 fbs;
1893 int rc;
1894
1895 if (!pp->fbs_supported)
1896 return;
1897
1898 fbs = readl(port_mmio + PORT_FBS);
1899 if (fbs & PORT_FBS_EN) {
1900 pp->fbs_enabled = true;
1901 pp->fbs_last_dev = -1; /* initialization */
1902 return;
1903 }
1904
1905 rc = ahci_stop_engine(ap);
1906 if (rc)
1907 return;
1908
1909 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1910 fbs = readl(port_mmio + PORT_FBS);
1911 if (fbs & PORT_FBS_EN) {
1912 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1913 pp->fbs_enabled = true;
1914 pp->fbs_last_dev = -1; /* initialization */
1915 } else
1916 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1917
1918 ahci_start_engine(ap);
1919}
1920
1921static void ahci_disable_fbs(struct ata_port *ap)
1922{
1923 struct ahci_port_priv *pp = ap->private_data;
1924 void __iomem *port_mmio = ahci_port_base(ap);
1925 u32 fbs;
1926 int rc;
1927
1928 if (!pp->fbs_supported)
1929 return;
1930
1931 fbs = readl(port_mmio + PORT_FBS);
1932 if ((fbs & PORT_FBS_EN) == 0) {
1933 pp->fbs_enabled = false;
1934 return;
1935 }
1936
1937 rc = ahci_stop_engine(ap);
1938 if (rc)
1939 return;
1940
1941 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1942 fbs = readl(port_mmio + PORT_FBS);
1943 if (fbs & PORT_FBS_EN)
1944 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1945 else {
1946 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1947 pp->fbs_enabled = false;
1948 }
1949
1950 ahci_start_engine(ap);
1951}
1952
1953static void ahci_pmp_attach(struct ata_port *ap)
1954{
1955 void __iomem *port_mmio = ahci_port_base(ap);
1956 struct ahci_port_priv *pp = ap->private_data;
1957 u32 cmd;
1958
1959 cmd = readl(port_mmio + PORT_CMD);
1960 cmd |= PORT_CMD_PMP;
1961 writel(cmd, port_mmio + PORT_CMD);
1962
1963 ahci_enable_fbs(ap);
1964
1965 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1966 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1967}
1968
1969static void ahci_pmp_detach(struct ata_port *ap)
1970{
1971 void __iomem *port_mmio = ahci_port_base(ap);
1972 struct ahci_port_priv *pp = ap->private_data;
1973 u32 cmd;
1974
1975 ahci_disable_fbs(ap);
1976
1977 cmd = readl(port_mmio + PORT_CMD);
1978 cmd &= ~PORT_CMD_PMP;
1979 writel(cmd, port_mmio + PORT_CMD);
1980
1981 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1982 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1983}
1984
1985static int ahci_port_resume(struct ata_port *ap)
1986{
1987 ahci_power_up(ap);
1988 ahci_start_port(ap);
1989
1990 if (sata_pmp_attached(ap))
1991 ahci_pmp_attach(ap);
1992 else
1993 ahci_pmp_detach(ap);
1994
1995 return 0;
1996}
1997
1998#ifdef CONFIG_PM
1999static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2000{
2001 const char *emsg = NULL;
2002 int rc;
2003
2004 rc = ahci_deinit_port(ap, &emsg);
2005 if (rc == 0)
2006 ahci_power_down(ap);
2007 else {
2008 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2009 ahci_start_port(ap);
2010 }
2011
2012 return rc;
2013}
2014#endif
2015
2016static int ahci_port_start(struct ata_port *ap)
2017{
2018 struct ahci_host_priv *hpriv = ap->host->private_data;
2019 struct device *dev = ap->host->dev;
2020 struct ahci_port_priv *pp;
2021 void *mem;
2022 dma_addr_t mem_dma;
2023 size_t dma_sz, rx_fis_sz;
2024
2025 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2026 if (!pp)
2027 return -ENOMEM;
2028
2029 /* check FBS capability */
2030 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2031 void __iomem *port_mmio = ahci_port_base(ap);
2032 u32 cmd = readl(port_mmio + PORT_CMD);
2033 if (cmd & PORT_CMD_FBSCP)
2034 pp->fbs_supported = true;
5f173107
TH		 2035 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2036 dev_printk(KERN_INFO, dev,
2037 "port %d can do FBS, forcing FBSCP\n",
2038 ap->port_no);
2039 pp->fbs_supported = true;
2040 } else
365cfa1e 2041 dev_printk(KERN_WARNING, dev,
5f173107
TH		 2042 "port %d is not capable of FBS\n",
2043 ap->port_no);
365cfa1e
AV		 2044 }
2045
2046 if (pp->fbs_supported) {
2047 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2048 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2049 } else {
2050 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2051 rx_fis_sz = AHCI_RX_FIS_SZ;
2052 }
2053
2054 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2055 if (!mem)
2056 return -ENOMEM;
2057 memset(mem, 0, dma_sz);
2058
2059 /*
2060 * First item in chunk of DMA memory: 32-slot command table,
2061 * 32 bytes each in size
2062 */
2063 pp->cmd_slot = mem;
2064 pp->cmd_slot_dma = mem_dma;
2065
2066 mem += AHCI_CMD_SLOT_SZ;
2067 mem_dma += AHCI_CMD_SLOT_SZ;
2068
2069 /*
2070 * Second item: Received-FIS area
2071 */
2072 pp->rx_fis = mem;
2073 pp->rx_fis_dma = mem_dma;
2074
2075 mem += rx_fis_sz;
2076 mem_dma += rx_fis_sz;
2077
2078 /*
2079 * Third item: data area for storing a single command
2080 * and its scatter-gather table
2081 */
2082 pp->cmd_tbl = mem;
2083 pp->cmd_tbl_dma = mem_dma;
2084
2085 /*
2086 * Save off initial list of interrupts to be enabled.
2087 * This could be changed later
2088 */
2089 pp->intr_mask = DEF_PORT_IRQ;
2090
2091 ap->private_data = pp;
2092
2093 /* engage engines, captain */
2094 return ahci_port_resume(ap);
2095}
2096
2097static void ahci_port_stop(struct ata_port *ap)
2098{
2099 const char *emsg = NULL;
2100 int rc;
2101
2102 /* de-initialize port */
2103 rc = ahci_deinit_port(ap, &emsg);
2104 if (rc)
2105 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2106}
2107
2108void ahci_print_info(struct ata_host *host, const char *scc_s)
2109{
2110 struct ahci_host_priv *hpriv = host->private_data;
2111 void __iomem *mmio = hpriv->mmio;
2112 u32 vers, cap, cap2, impl, speed;
2113 const char *speed_s;
2114
2115 vers = readl(mmio + HOST_VERSION);
2116 cap = hpriv->cap;
2117 cap2 = hpriv->cap2;
2118 impl = hpriv->port_map;
2119
2120 speed = (cap >> 20) & 0xf;
2121 if (speed == 1)
2122 speed_s = "1.5";
2123 else if (speed == 2)
2124 speed_s = "3";
2125 else if (speed == 3)
2126 speed_s = "6";
2127 else
2128 speed_s = "?";
2129
2130 dev_info(host->dev,
2131 "AHCI %02x%02x.%02x%02x "
2132 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2133 ,
2134
2135 (vers >> 24) & 0xff,
2136 (vers >> 16) & 0xff,
2137 (vers >> 8) & 0xff,
2138 vers & 0xff,
2139
2140 ((cap >> 8) & 0x1f) + 1,
2141 (cap & 0x1f) + 1,
2142 speed_s,
2143 impl,
2144 scc_s);
2145
2146 dev_info(host->dev,
2147 "flags: "
2148 "%s%s%s%s%s%s%s"
2149 "%s%s%s%s%s%s%s"
2150 "%s%s%s%s%s%s\n"
2151 ,
2152
2153 cap & HOST_CAP_64 ? "64bit " : "",
2154 cap & HOST_CAP_NCQ ? "ncq " : "",
2155 cap & HOST_CAP_SNTF ? "sntf " : "",
2156 cap & HOST_CAP_MPS ? "ilck " : "",
2157 cap & HOST_CAP_SSS ? "stag " : "",
2158 cap & HOST_CAP_ALPM ? "pm " : "",
2159 cap & HOST_CAP_LED ? "led " : "",
2160 cap & HOST_CAP_CLO ? "clo " : "",
2161 cap & HOST_CAP_ONLY ? "only " : "",
2162 cap & HOST_CAP_PMP ? "pmp " : "",
2163 cap & HOST_CAP_FBS ? "fbs " : "",
2164 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2165 cap & HOST_CAP_SSC ? "slum " : "",
2166 cap & HOST_CAP_PART ? "part " : "",
2167 cap & HOST_CAP_CCC ? "ccc " : "",
2168 cap & HOST_CAP_EMS ? "ems " : "",
2169 cap & HOST_CAP_SXS ? "sxs " : "",
2170 cap2 & HOST_CAP2_APST ? "apst " : "",
2171 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2172 cap2 & HOST_CAP2_BOH ? "boh " : ""
2173 );
2174}
2175EXPORT_SYMBOL_GPL(ahci_print_info);
2176
2177void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2178 struct ata_port_info *pi)
2179{
2180 u8 messages;
2181 void __iomem *mmio = hpriv->mmio;
2182 u32 em_loc = readl(mmio + HOST_EM_LOC);
2183 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2184
2185 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2186 return;
2187
2188 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2189
008dbd61 2190 if (messages) {
365cfa1e
AV		 2191 /* store em_loc */
2192 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2193 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2194 hpriv->em_msg_type = messages;
365cfa1e
AV		 2195 pi->flags |= ATA_FLAG_EM;
2196 if (!(em_ctl & EM_CTL_ALHD))
2197 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2198 }
2199}
2200EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2201
2202MODULE_AUTHOR("Jeff Garzik");
2203MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2204MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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