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ahci: Intel DNV device IDs SATA
[deliverable/linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
d684a90d 46#include <linux/pci.h>
365cfa1e 47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
65fe1f0f 79static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
345347c5
YHC		 86static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
365cfa1e
AV		 88static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
365cfa1e
AV		 116
117static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 121static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 123static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 124
fad16e7a 125struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 126 &dev_attr_link_power_management_policy,
127 &dev_attr_em_message_type,
128 &dev_attr_em_message,
129 &dev_attr_ahci_host_caps,
130 &dev_attr_ahci_host_cap2,
131 &dev_attr_ahci_host_version,
132 &dev_attr_ahci_port_cmd,
c0623166 133 &dev_attr_em_buffer,
6e5fe5b1 134 &dev_attr_em_message_supported,
365cfa1e
AV		 135 NULL
136};
fad16e7a 137EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 138
fad16e7a 139struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 140 &dev_attr_sw_activity,
141 &dev_attr_unload_heads,
142 NULL
143};
fad16e7a 144EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 145
146struct ata_port_operations ahci_ops = {
147 .inherits = &sata_pmp_port_ops,
148
149 .qc_defer = ahci_pmp_qc_defer,
150 .qc_prep = ahci_qc_prep,
151 .qc_issue = ahci_qc_issue,
152 .qc_fill_rtf = ahci_qc_fill_rtf,
153
154 .freeze = ahci_freeze,
155 .thaw = ahci_thaw,
156 .softreset = ahci_softreset,
157 .hardreset = ahci_hardreset,
158 .postreset = ahci_postreset,
159 .pmp_softreset = ahci_softreset,
160 .error_handler = ahci_error_handler,
161 .post_internal_cmd = ahci_post_internal_cmd,
162 .dev_config = ahci_dev_config,
163
164 .scr_read = ahci_scr_read,
165 .scr_write = ahci_scr_write,
166 .pmp_attach = ahci_pmp_attach,
167 .pmp_detach = ahci_pmp_detach,
168
6b7ae954 169 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 170 .em_show = ahci_led_show,
171 .em_store = ahci_led_store,
172 .sw_activity_show = ahci_activity_show,
173 .sw_activity_store = ahci_activity_store,
439d7a35 174 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 175#ifdef CONFIG_PM
176 .port_suspend = ahci_port_suspend,
177 .port_resume = ahci_port_resume,
178#endif
179 .port_start = ahci_port_start,
180 .port_stop = ahci_port_stop,
181};
182EXPORT_SYMBOL_GPL(ahci_ops);
183
345347c5
YHC		 184struct ata_port_operations ahci_pmp_retry_srst_ops = {
185 .inherits = &ahci_ops,
186 .softreset = ahci_pmp_retry_softreset,
187};
188EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189
ed08d40c 190static bool ahci_em_messages __read_mostly = true;
365cfa1e 191EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 192module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 193/* add other LED protocol types when they become supported */
194MODULE_PARM_DESC(ahci_em_messages,
008dbd61 195 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 196
ed08d40c
CL		 197/* device sleep idle timeout in ms */
198static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 199module_param(devslp_idle_timeout, int, 0644);
200MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
201
365cfa1e
AV		 202static void ahci_enable_ahci(void __iomem *mmio)
203{
204 int i;
205 u32 tmp;
206
207 /* turn on AHCI_EN */
208 tmp = readl(mmio + HOST_CTL);
209 if (tmp & HOST_AHCI_EN)
210 return;
211
212 /* Some controllers need AHCI_EN to be written multiple times.
213 * Try a few times before giving up.
214 */
215 for (i = 0; i < 5; i++) {
216 tmp |= HOST_AHCI_EN;
217 writel(tmp, mmio + HOST_CTL);
218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
219 if (tmp & HOST_AHCI_EN)
220 return;
221 msleep(10);
222 }
223
224 WARN_ON(1);
225}
226
227static ssize_t ahci_show_host_caps(struct device *dev,
228 struct device_attribute *attr, char *buf)
229{
230 struct Scsi_Host *shost = class_to_shost(dev);
231 struct ata_port *ap = ata_shost_to_port(shost);
232 struct ahci_host_priv *hpriv = ap->host->private_data;
233
234 return sprintf(buf, "%x\n", hpriv->cap);
235}
236
237static ssize_t ahci_show_host_cap2(struct device *dev,
238 struct device_attribute *attr, char *buf)
239{
240 struct Scsi_Host *shost = class_to_shost(dev);
241 struct ata_port *ap = ata_shost_to_port(shost);
242 struct ahci_host_priv *hpriv = ap->host->private_data;
243
244 return sprintf(buf, "%x\n", hpriv->cap2);
245}
246
247static ssize_t ahci_show_host_version(struct device *dev,
248 struct device_attribute *attr, char *buf)
249{
250 struct Scsi_Host *shost = class_to_shost(dev);
251 struct ata_port *ap = ata_shost_to_port(shost);
252 struct ahci_host_priv *hpriv = ap->host->private_data;
253 void __iomem *mmio = hpriv->mmio;
254
255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
256}
257
258static ssize_t ahci_show_port_cmd(struct device *dev,
259 struct device_attribute *attr, char *buf)
260{
261 struct Scsi_Host *shost = class_to_shost(dev);
262 struct ata_port *ap = ata_shost_to_port(shost);
263 void __iomem *port_mmio = ahci_port_base(ap);
264
265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
266}
267
c0623166
HZ		 268static ssize_t ahci_read_em_buffer(struct device *dev,
269 struct device_attribute *attr, char *buf)
270{
271 struct Scsi_Host *shost = class_to_shost(dev);
272 struct ata_port *ap = ata_shost_to_port(shost);
273 struct ahci_host_priv *hpriv = ap->host->private_data;
274 void __iomem *mmio = hpriv->mmio;
275 void __iomem *em_mmio = mmio + hpriv->em_loc;
276 u32 em_ctl, msg;
277 unsigned long flags;
278 size_t count;
279 int i;
280
281 spin_lock_irqsave(ap->lock, flags);
282
283 em_ctl = readl(mmio + HOST_EM_CTL);
284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
286 spin_unlock_irqrestore(ap->lock, flags);
287 return -EINVAL;
288 }
289
290 if (!(em_ctl & EM_CTL_MR)) {
291 spin_unlock_irqrestore(ap->lock, flags);
292 return -EAGAIN;
293 }
294
295 if (!(em_ctl & EM_CTL_SMB))
296 em_mmio += hpriv->em_buf_sz;
297
298 count = hpriv->em_buf_sz;
299
300 /* the count should not be larger than PAGE_SIZE */
301 if (count > PAGE_SIZE) {
302 if (printk_ratelimit())
a9a79dfe
JP		 303 ata_port_warn(ap,
304 "EM read buffer size too large: "
305 "buffer size %u, page size %lu\n",
306 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 307 count = PAGE_SIZE;
308 }
309
310 for (i = 0; i < count; i += 4) {
311 msg = readl(em_mmio + i);
312 buf[i] = msg & 0xff;
313 buf[i + 1] = (msg >> 8) & 0xff;
314 buf[i + 2] = (msg >> 16) & 0xff;
315 buf[i + 3] = (msg >> 24) & 0xff;
316 }
317
318 spin_unlock_irqrestore(ap->lock, flags);
319
320 return i;
321}
322
323static ssize_t ahci_store_em_buffer(struct device *dev,
324 struct device_attribute *attr,
325 const char *buf, size_t size)
326{
327 struct Scsi_Host *shost = class_to_shost(dev);
328 struct ata_port *ap = ata_shost_to_port(shost);
329 struct ahci_host_priv *hpriv = ap->host->private_data;
330 void __iomem *mmio = hpriv->mmio;
331 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 332 const unsigned char *msg_buf = buf;
c0623166
HZ		 333 u32 em_ctl, msg;
334 unsigned long flags;
335 int i;
336
337 /* check size validity */
338 if (!(ap->flags & ATA_FLAG_EM) ||
339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
340 size % 4 || size > hpriv->em_buf_sz)
341 return -EINVAL;
342
343 spin_lock_irqsave(ap->lock, flags);
344
345 em_ctl = readl(mmio + HOST_EM_CTL);
346 if (em_ctl & EM_CTL_TM) {
347 spin_unlock_irqrestore(ap->lock, flags);
348 return -EBUSY;
349 }
350
351 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 352 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 354 writel(msg, em_mmio + i);
355 }
356
357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
358
359 spin_unlock_irqrestore(ap->lock, flags);
360
361 return size;
362}
363
6e5fe5b1
HR		 364static ssize_t ahci_show_em_supported(struct device *dev,
365 struct device_attribute *attr, char *buf)
366{
367 struct Scsi_Host *shost = class_to_shost(dev);
368 struct ata_port *ap = ata_shost_to_port(shost);
369 struct ahci_host_priv *hpriv = ap->host->private_data;
370 void __iomem *mmio = hpriv->mmio;
371 u32 em_ctl;
372
373 em_ctl = readl(mmio + HOST_EM_CTL);
374
375 return sprintf(buf, "%s%s%s%s\n",
376 em_ctl & EM_CTL_LED ? "led " : "",
377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
378 em_ctl & EM_CTL_SES ? "ses-2 " : "",
379 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
380}
381
365cfa1e
AV		 382/**
383 * ahci_save_initial_config - Save and fixup initial config values
384 * @dev: target AHCI device
385 * @hpriv: host private area to store config values
365cfa1e
AV		 386 *
387 * Some registers containing configuration info might be setup by
388 * BIOS and might be cleared on reset. This function saves the
389 * initial values of those registers into @hpriv such that they
390 * can be restored after controller reset.
391 *
392 * If inconsistent, config values are fixed up by this function.
393 *
039ece38
HG		 394 * If it is not set already this function sets hpriv->start_engine to
395 * ahci_start_engine.
396 *
365cfa1e
AV		 397 * LOCKING:
398 * None.
399 */
725c7b57 400void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 401{
402 void __iomem *mmio = hpriv->mmio;
403 u32 cap, cap2, vers, port_map;
404 int i;
405
406 /* make sure AHCI mode is enabled before accessing CAP */
407 ahci_enable_ahci(mmio);
408
409 /* Values prefixed with saved_ are written back to host after
410 * reset. Values without are used for driver operation.
411 */
412 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
413 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
414
415 /* CAP2 register is only defined for AHCI 1.2 and later */
416 vers = readl(mmio + HOST_VERSION);
417 if ((vers >> 16) > 1 ||
418 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
419 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
420 else
421 hpriv->saved_cap2 = cap2 = 0;
422
423 /* some chips have errata preventing 64bit use */
424 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 425 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 426 cap &= ~HOST_CAP_64;
427 }
428
429 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 430 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 431 cap &= ~HOST_CAP_NCQ;
432 }
433
434 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 435 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 436 cap |= HOST_CAP_NCQ;
437 }
438
439 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 440 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 441 cap &= ~HOST_CAP_PMP;
442 }
443
444 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 445 dev_info(dev,
446 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 447 cap &= ~HOST_CAP_SNTF;
448 }
449
0cf4a7d6
JP		 450 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
451 dev_info(dev,
452 "controller can't do DEVSLP, turning off\n");
453 cap2 &= ~HOST_CAP2_SDS;
454 cap2 &= ~HOST_CAP2_SADM;
455 }
456
5f173107 457 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 458 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 459 cap |= HOST_CAP_FBS;
460 }
461
888d91a0
KW		 462 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
463 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
464 cap &= ~HOST_CAP_FBS;
465 }
466
725c7b57 467 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 468 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 469 port_map, hpriv->force_port_map);
470 port_map = hpriv->force_port_map;
365cfa1e
AV		 471 }
472
725c7b57 473 if (hpriv->mask_port_map) {
a44fec1f
JP		 474 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
475 port_map,
725c7b57
AT		 476 port_map & hpriv->mask_port_map);
477 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 478 }
479
480 /* cross check port_map and cap.n_ports */
481 if (port_map) {
482 int map_ports = 0;
483
484 for (i = 0; i < AHCI_MAX_PORTS; i++)
485 if (port_map & (1 << i))
486 map_ports++;
487
488 /* If PI has more ports than n_ports, whine, clear
489 * port_map and let it be generated from n_ports.
490 */
491 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 492 dev_warn(dev,
493 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
494 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 495 port_map = 0;
496 }
497 }
498
566d1827
TH		 499 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
500 if (!port_map && vers < 0x10300) {
365cfa1e 501 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 502 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 503
504 /* write the fixed up value to the PI register */
505 hpriv->saved_port_map = port_map;
506 }
507
508 /* record values to use during operation */
509 hpriv->cap = cap;
510 hpriv->cap2 = cap2;
511 hpriv->port_map = port_map;
039ece38
HG		 512
513 if (!hpriv->start_engine)
514 hpriv->start_engine = ahci_start_engine;
365cfa1e
AV		 515}
516EXPORT_SYMBOL_GPL(ahci_save_initial_config);
517
518/**
519 * ahci_restore_initial_config - Restore initial config
520 * @host: target ATA host
521 *
522 * Restore initial config stored by ahci_save_initial_config().
523 *
524 * LOCKING:
525 * None.
526 */
527static void ahci_restore_initial_config(struct ata_host *host)
528{
529 struct ahci_host_priv *hpriv = host->private_data;
530 void __iomem *mmio = hpriv->mmio;
531
532 writel(hpriv->saved_cap, mmio + HOST_CAP);
533 if (hpriv->saved_cap2)
534 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
535 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
536 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
537}
538
539static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
540{
541 static const int offset[] = {
542 [SCR_STATUS] = PORT_SCR_STAT,
543 [SCR_CONTROL] = PORT_SCR_CTL,
544 [SCR_ERROR] = PORT_SCR_ERR,
545 [SCR_ACTIVE] = PORT_SCR_ACT,
546 [SCR_NOTIFICATION] = PORT_SCR_NTF,
547 };
548 struct ahci_host_priv *hpriv = ap->host->private_data;
549
550 if (sc_reg < ARRAY_SIZE(offset) &&
551 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
552 return offset[sc_reg];
553 return 0;
554}
555
556static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
557{
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
560
561 if (offset) {
562 *val = readl(port_mmio + offset);
563 return 0;
564 }
565 return -EINVAL;
566}
567
568static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
569{
570 void __iomem *port_mmio = ahci_port_base(link->ap);
571 int offset = ahci_scr_offset(link->ap, sc_reg);
572
573 if (offset) {
574 writel(val, port_mmio + offset);
575 return 0;
576 }
577 return -EINVAL;
578}
579
580void ahci_start_engine(struct ata_port *ap)
581{
582 void __iomem *port_mmio = ahci_port_base(ap);
583 u32 tmp;
584
585 /* start DMA */
586 tmp = readl(port_mmio + PORT_CMD);
587 tmp |= PORT_CMD_START;
588 writel(tmp, port_mmio + PORT_CMD);
589 readl(port_mmio + PORT_CMD); /* flush */
590}
591EXPORT_SYMBOL_GPL(ahci_start_engine);
592
593int ahci_stop_engine(struct ata_port *ap)
594{
595 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 596 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 597 u32 tmp;
598
fb329633
DP		 599 /*
600 * On some controllers, stopping a port's DMA engine while the port
601 * is in ALPM state (partial or slumber) results in failures on
602 * subsequent DMA engine starts. For those controllers, put the
603 * port back in active state before stopping its DMA engine.
604 */
605 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
606 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
607 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
608 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
609 return -EIO;
610 }
611
365cfa1e
AV		 612 tmp = readl(port_mmio + PORT_CMD);
613
614 /* check if the HBA is idle */
615 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
616 return 0;
617
618 /* setting HBA to idle */
619 tmp &= ~PORT_CMD_START;
620 writel(tmp, port_mmio + PORT_CMD);
621
622 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 623 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 624 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
625 if (tmp & PORT_CMD_LIST_ON)
626 return -EIO;
627
628 return 0;
629}
630EXPORT_SYMBOL_GPL(ahci_stop_engine);
631
39e0ee99 632void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 633{
634 void __iomem *port_mmio = ahci_port_base(ap);
635 struct ahci_host_priv *hpriv = ap->host->private_data;
636 struct ahci_port_priv *pp = ap->private_data;
637 u32 tmp;
638
639 /* set FIS registers */
640 if (hpriv->cap & HOST_CAP_64)
641 writel((pp->cmd_slot_dma >> 16) >> 16,
642 port_mmio + PORT_LST_ADDR_HI);
643 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
644
645 if (hpriv->cap & HOST_CAP_64)
646 writel((pp->rx_fis_dma >> 16) >> 16,
647 port_mmio + PORT_FIS_ADDR_HI);
648 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
649
650 /* enable FIS reception */
651 tmp = readl(port_mmio + PORT_CMD);
652 tmp |= PORT_CMD_FIS_RX;
653 writel(tmp, port_mmio + PORT_CMD);
654
655 /* flush */
656 readl(port_mmio + PORT_CMD);
657}
39e0ee99 658EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 659
660static int ahci_stop_fis_rx(struct ata_port *ap)
661{
662 void __iomem *port_mmio = ahci_port_base(ap);
663 u32 tmp;
664
665 /* disable FIS reception */
666 tmp = readl(port_mmio + PORT_CMD);
667 tmp &= ~PORT_CMD_FIS_RX;
668 writel(tmp, port_mmio + PORT_CMD);
669
670 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 671 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 672 PORT_CMD_FIS_ON, 10, 1000);
673 if (tmp & PORT_CMD_FIS_ON)
674 return -EBUSY;
675
676 return 0;
677}
678
679static void ahci_power_up(struct ata_port *ap)
680{
681 struct ahci_host_priv *hpriv = ap->host->private_data;
682 void __iomem *port_mmio = ahci_port_base(ap);
683 u32 cmd;
684
685 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
686
687 /* spin up device */
688 if (hpriv->cap & HOST_CAP_SSS) {
689 cmd |= PORT_CMD_SPIN_UP;
690 writel(cmd, port_mmio + PORT_CMD);
691 }
692
693 /* wake up link */
694 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
695}
696
6b7ae954
TH		 697static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
698 unsigned int hints)
365cfa1e 699{
6b7ae954 700 struct ata_port *ap = link->ap;
365cfa1e 701 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 702 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 703 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 704
6b7ae954 705 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 706 /* wakeup flag only applies to the max power policy */
707 hints &= ~ATA_LPM_WAKE_ONLY;
708
365cfa1e 709 /*
6b7ae954
TH		 710 * Disable interrupts on Phy Ready. This keeps us from
711 * getting woken up due to spurious phy ready
712 * interrupts.
365cfa1e 713 */
6b7ae954
TH		 714 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
715 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
716
717 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 718 }
719
6b7ae954
TH		 720 if (hpriv->cap & HOST_CAP_ALPM) {
721 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 722
6b7ae954 723 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 724 if (!(hints & ATA_LPM_WAKE_ONLY))
725 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 726 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 727
6b7ae954
TH		 728 writel(cmd, port_mmio + PORT_CMD);
729 readl(port_mmio + PORT_CMD);
365cfa1e 730
6b7ae954 731 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 732 ata_msleep(ap, 10);
fb329633
DP		 733
734 if (hints & ATA_LPM_WAKE_ONLY)
735 return 0;
6b7ae954
TH		 736 } else {
737 cmd |= PORT_CMD_ALPE;
738 if (policy == ATA_LPM_MIN_POWER)
739 cmd |= PORT_CMD_ASP;
365cfa1e 740
6b7ae954
TH		 741 /* write out new cmd value */
742 writel(cmd, port_mmio + PORT_CMD);
743 }
744 }
365cfa1e 745
65fe1f0f
SH		 746 /* set aggressive device sleep */
747 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
748 (hpriv->cap2 & HOST_CAP2_SADM) &&
749 (link->device->flags & ATA_DFLAG_DEVSLP)) {
750 if (policy == ATA_LPM_MIN_POWER)
751 ahci_set_aggressive_devslp(ap, true);
752 else
753 ahci_set_aggressive_devslp(ap, false);
754 }
755
6b7ae954
TH		 756 if (policy == ATA_LPM_MAX_POWER) {
757 sata_link_scr_lpm(link, policy, false);
758
759 /* turn PHYRDY IRQ back on */
760 pp->intr_mask |= PORT_IRQ_PHYRDY;
761 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
762 }
365cfa1e 763
365cfa1e
AV		 764 return 0;
765}
766
767#ifdef CONFIG_PM
768static void ahci_power_down(struct ata_port *ap)
769{
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 void __iomem *port_mmio = ahci_port_base(ap);
772 u32 cmd, scontrol;
773
774 if (!(hpriv->cap & HOST_CAP_SSS))
775 return;
776
777 /* put device into listen mode, first set PxSCTL.DET to 0 */
778 scontrol = readl(port_mmio + PORT_SCR_CTL);
779 scontrol &= ~0xf;
780 writel(scontrol, port_mmio + PORT_SCR_CTL);
781
782 /* then set PxCMD.SUD to 0 */
783 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
784 cmd &= ~PORT_CMD_SPIN_UP;
785 writel(cmd, port_mmio + PORT_CMD);
786}
787#endif
788
789static void ahci_start_port(struct ata_port *ap)
790{
66583c9f 791 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 792 struct ahci_port_priv *pp = ap->private_data;
793 struct ata_link *link;
794 struct ahci_em_priv *emp;
795 ssize_t rc;
796 int i;
797
798 /* enable FIS reception */
799 ahci_start_fis_rx(ap);
800
66583c9f
BN		 801 /* enable DMA */
802 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 803 hpriv->start_engine(ap);
66583c9f 804
365cfa1e
AV		 805 /* turn on LEDs */
806 if (ap->flags & ATA_FLAG_EM) {
807 ata_for_each_link(link, ap, EDGE) {
808 emp = &pp->em_priv[link->pmp];
809
810 /* EM Transmit bit maybe busy during init */
811 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 812 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 813 emp->led_state,
814 4);
fa070ee6
LD		 815 /*
816 * If busy, give a breather but do not
817 * release EH ownership by using msleep()
818 * instead of ata_msleep(). EM Transmit
819 * bit is busy for the whole host and
820 * releasing ownership will cause other
821 * ports to fail the same way.
822 */
365cfa1e 823 if (rc == -EBUSY)
fa070ee6 824 msleep(1);
365cfa1e
AV		 825 else
826 break;
827 }
828 }
829 }
830
831 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
832 ata_for_each_link(link, ap, EDGE)
833 ahci_init_sw_activity(link);
834
835}
836
837static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
838{
839 int rc;
840
841 /* disable DMA */
842 rc = ahci_stop_engine(ap);
843 if (rc) {
844 *emsg = "failed to stop engine";
845 return rc;
846 }
847
848 /* disable FIS reception */
849 rc = ahci_stop_fis_rx(ap);
850 if (rc) {
851 *emsg = "failed stop FIS RX";
852 return rc;
853 }
854
855 return 0;
856}
857
858int ahci_reset_controller(struct ata_host *host)
859{
860 struct ahci_host_priv *hpriv = host->private_data;
861 void __iomem *mmio = hpriv->mmio;
862 u32 tmp;
863
864 /* we must be in AHCI mode, before using anything
865 * AHCI-specific, such as HOST_RESET.
866 */
867 ahci_enable_ahci(mmio);
868
869 /* global controller reset */
870 if (!ahci_skip_host_reset) {
871 tmp = readl(mmio + HOST_CTL);
872 if ((tmp & HOST_RESET) == 0) {
873 writel(tmp | HOST_RESET, mmio + HOST_CTL);
874 readl(mmio + HOST_CTL); /* flush */
875 }
876
877 /*
878 * to perform host reset, OS should set HOST_RESET
879 * and poll until this bit is read to be "0".
880 * reset must complete within 1 second, or
881 * the hardware should be considered fried.
882 */
97750ceb 883 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 884 HOST_RESET, 10, 1000);
885
886 if (tmp & HOST_RESET) {
a44fec1f
JP		 887 dev_err(host->dev, "controller reset failed (0x%x)\n",
888 tmp);
365cfa1e
AV		 889 return -EIO;
890 }
891
892 /* turn on AHCI mode */
893 ahci_enable_ahci(mmio);
894
895 /* Some registers might be cleared on reset. Restore
896 * initial values.
897 */
898 ahci_restore_initial_config(host);
899 } else
a44fec1f 900 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 901
902 return 0;
903}
904EXPORT_SYMBOL_GPL(ahci_reset_controller);
905
906static void ahci_sw_activity(struct ata_link *link)
907{
908 struct ata_port *ap = link->ap;
909 struct ahci_port_priv *pp = ap->private_data;
910 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
911
912 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
913 return;
914
915 emp->activity++;
916 if (!timer_pending(&emp->timer))
917 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
918}
919
920static void ahci_sw_activity_blink(unsigned long arg)
921{
922 struct ata_link *link = (struct ata_link *)arg;
923 struct ata_port *ap = link->ap;
924 struct ahci_port_priv *pp = ap->private_data;
925 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
926 unsigned long led_message = emp->led_state;
927 u32 activity_led_state;
928 unsigned long flags;
929
930 led_message &= EM_MSG_LED_VALUE;
931 led_message |= ap->port_no | (link->pmp << 8);
932
933 /* check to see if we've had activity. If so,
934 * toggle state of LED and reset timer. If not,
935 * turn LED to desired idle state.
936 */
937 spin_lock_irqsave(ap->lock, flags);
938 if (emp->saved_activity != emp->activity) {
939 emp->saved_activity = emp->activity;
940 /* get the current LED state */
941 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
942
943 if (activity_led_state)
944 activity_led_state = 0;
945 else
946 activity_led_state = 1;
947
948 /* clear old state */
949 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
950
951 /* toggle state */
952 led_message |= (activity_led_state << 16);
953 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
954 } else {
955 /* switch to idle */
956 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
957 if (emp->blink_policy == BLINK_OFF)
958 led_message |= (1 << 16);
959 }
960 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 961 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 962}
963
964static void ahci_init_sw_activity(struct ata_link *link)
965{
966 struct ata_port *ap = link->ap;
967 struct ahci_port_priv *pp = ap->private_data;
968 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
969
970 /* init activity stats, setup timer */
971 emp->saved_activity = emp->activity = 0;
972 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
973
974 /* check our blink policy and set flag for link if it's enabled */
975 if (emp->blink_policy)
976 link->flags |= ATA_LFLAG_SW_ACTIVITY;
977}
978
979int ahci_reset_em(struct ata_host *host)
980{
981 struct ahci_host_priv *hpriv = host->private_data;
982 void __iomem *mmio = hpriv->mmio;
983 u32 em_ctl;
984
985 em_ctl = readl(mmio + HOST_EM_CTL);
986 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
987 return -EINVAL;
988
989 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
990 return 0;
991}
992EXPORT_SYMBOL_GPL(ahci_reset_em);
993
994static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
995 ssize_t size)
996{
997 struct ahci_host_priv *hpriv = ap->host->private_data;
998 struct ahci_port_priv *pp = ap->private_data;
999 void __iomem *mmio = hpriv->mmio;
1000 u32 em_ctl;
1001 u32 message[] = {0, 0};
1002 unsigned long flags;
1003 int pmp;
1004 struct ahci_em_priv *emp;
1005
1006 /* get the slot number from the message */
1007 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1008 if (pmp < EM_MAX_SLOTS)
1009 emp = &pp->em_priv[pmp];
1010 else
1011 return -EINVAL;
1012
1013 spin_lock_irqsave(ap->lock, flags);
1014
1015 /*
1016 * if we are still busy transmitting a previous message,
1017 * do not allow
1018 */
1019 em_ctl = readl(mmio + HOST_EM_CTL);
1020 if (em_ctl & EM_CTL_TM) {
1021 spin_unlock_irqrestore(ap->lock, flags);
1022 return -EBUSY;
1023 }
1024
008dbd61
HZ		 1025 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1026 /*
1027 * create message header - this is all zero except for
1028 * the message size, which is 4 bytes.
1029 */
1030 message[0] |= (4 << 8);
365cfa1e 1031
008dbd61
HZ		 1032 /* ignore 0:4 of byte zero, fill in port info yourself */
1033 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1034
008dbd61
HZ		 1035 /* write message to EM_LOC */
1036 writel(message[0], mmio + hpriv->em_loc);
1037 writel(message[1], mmio + hpriv->em_loc+4);
1038
1039 /*
1040 * tell hardware to transmit the message
1041 */
1042 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1043 }
365cfa1e
AV		 1044
1045 /* save off new led state for port/slot */
1046 emp->led_state = state;
1047
365cfa1e
AV		 1048 spin_unlock_irqrestore(ap->lock, flags);
1049 return size;
1050}
1051
1052static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1053{
1054 struct ahci_port_priv *pp = ap->private_data;
1055 struct ata_link *link;
1056 struct ahci_em_priv *emp;
1057 int rc = 0;
1058
1059 ata_for_each_link(link, ap, EDGE) {
1060 emp = &pp->em_priv[link->pmp];
1061 rc += sprintf(buf, "%lx\n", emp->led_state);
1062 }
1063 return rc;
1064}
1065
1066static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1067 size_t size)
1068{
b2a52b6a 1069 unsigned int state;
365cfa1e
AV		 1070 int pmp;
1071 struct ahci_port_priv *pp = ap->private_data;
1072 struct ahci_em_priv *emp;
1073
b2a52b6a
DY		 1074 if (kstrtouint(buf, 0, &state) < 0)
1075 return -EINVAL;
365cfa1e
AV		 1076
1077 /* get the slot number from the message */
1078 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1079 if (pmp < EM_MAX_SLOTS)
1080 emp = &pp->em_priv[pmp];
1081 else
1082 return -EINVAL;
1083
1084 /* mask off the activity bits if we are in sw_activity
1085 * mode, user should turn off sw_activity before setting
1086 * activity led through em_message
1087 */
1088 if (emp->blink_policy)
1089 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1090
439d7a35 1091 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1092}
1093
1094static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1095{
1096 struct ata_link *link = dev->link;
1097 struct ata_port *ap = link->ap;
1098 struct ahci_port_priv *pp = ap->private_data;
1099 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1100 u32 port_led_state = emp->led_state;
1101
1102 /* save the desired Activity LED behavior */
1103 if (val == OFF) {
1104 /* clear LFLAG */
1105 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1106
1107 /* set the LED to OFF */
1108 port_led_state &= EM_MSG_LED_VALUE_OFF;
1109 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1110 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1111 } else {
1112 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1113 if (val == BLINK_OFF) {
1114 /* set LED to ON for idle */
1115 port_led_state &= EM_MSG_LED_VALUE_OFF;
1116 port_led_state |= (ap->port_no | (link->pmp << 8));
1117 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1118 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1119 }
1120 }
1121 emp->blink_policy = val;
1122 return 0;
1123}
1124
1125static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1126{
1127 struct ata_link *link = dev->link;
1128 struct ata_port *ap = link->ap;
1129 struct ahci_port_priv *pp = ap->private_data;
1130 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1131
1132 /* display the saved value of activity behavior for this
1133 * disk.
1134 */
1135 return sprintf(buf, "%d\n", emp->blink_policy);
1136}
1137
1138static void ahci_port_init(struct device *dev, struct ata_port *ap,
1139 int port_no, void __iomem *mmio,
1140 void __iomem *port_mmio)
1141{
8a3e33cf 1142 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1143 const char *emsg = NULL;
1144 int rc;
1145 u32 tmp;
1146
1147 /* make sure port is not active */
1148 rc = ahci_deinit_port(ap, &emsg);
1149 if (rc)
1150 dev_warn(dev, "%s (%d)\n", emsg, rc);
1151
1152 /* clear SError */
1153 tmp = readl(port_mmio + PORT_SCR_ERR);
1154 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1155 writel(tmp, port_mmio + PORT_SCR_ERR);
1156
1157 /* clear port IRQ */
1158 tmp = readl(port_mmio + PORT_IRQ_STAT);
1159 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1160 if (tmp)
1161 writel(tmp, port_mmio + PORT_IRQ_STAT);
1162
1163 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1164
1165 /* mark esata ports */
1166 tmp = readl(port_mmio + PORT_CMD);
1167 if ((tmp & PORT_CMD_HPCP) ||
1168 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
1169 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1170}
1171
1172void ahci_init_controller(struct ata_host *host)
1173{
1174 struct ahci_host_priv *hpriv = host->private_data;
1175 void __iomem *mmio = hpriv->mmio;
1176 int i;
1177 void __iomem *port_mmio;
1178 u32 tmp;
1179
1180 for (i = 0; i < host->n_ports; i++) {
1181 struct ata_port *ap = host->ports[i];
1182
1183 port_mmio = ahci_port_base(ap);
1184 if (ata_port_is_dummy(ap))
1185 continue;
1186
1187 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1188 }
1189
1190 tmp = readl(mmio + HOST_CTL);
1191 VPRINTK("HOST_CTL 0x%x\n", tmp);
1192 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1193 tmp = readl(mmio + HOST_CTL);
1194 VPRINTK("HOST_CTL 0x%x\n", tmp);
1195}
1196EXPORT_SYMBOL_GPL(ahci_init_controller);
1197
1198static void ahci_dev_config(struct ata_device *dev)
1199{
1200 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1201
1202 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1203 dev->max_sectors = 255;
a9a79dfe
JP		 1204 ata_dev_info(dev,
1205 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1206 }
1207}
1208
bbb4ab43 1209unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1210{
1211 void __iomem *port_mmio = ahci_port_base(ap);
1212 struct ata_taskfile tf;
1213 u32 tmp;
1214
1215 tmp = readl(port_mmio + PORT_SIG);
1216 tf.lbah = (tmp >> 24) & 0xff;
1217 tf.lbam = (tmp >> 16) & 0xff;
1218 tf.lbal = (tmp >> 8) & 0xff;
1219 tf.nsect = (tmp) & 0xff;
1220
1221 return ata_dev_classify(&tf);
1222}
bbb4ab43 1223EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1224
02cdfcf0
DM		 1225void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1226 u32 opts)
365cfa1e
AV		 1227{
1228 dma_addr_t cmd_tbl_dma;
1229
1230 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1231
1232 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1233 pp->cmd_slot[tag].status = 0;
1234 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1235 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1236}
02cdfcf0 1237EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1238
1239int ahci_kick_engine(struct ata_port *ap)
1240{
1241 void __iomem *port_mmio = ahci_port_base(ap);
1242 struct ahci_host_priv *hpriv = ap->host->private_data;
1243 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1244 u32 tmp;
1245 int busy, rc;
1246
1247 /* stop engine */
1248 rc = ahci_stop_engine(ap);
1249 if (rc)
1250 goto out_restart;
1251
1252 /* need to do CLO?
1253 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1254 */
1255 busy = status & (ATA_BUSY | ATA_DRQ);
1256 if (!busy && !sata_pmp_attached(ap)) {
1257 rc = 0;
1258 goto out_restart;
1259 }
1260
1261 if (!(hpriv->cap & HOST_CAP_CLO)) {
1262 rc = -EOPNOTSUPP;
1263 goto out_restart;
1264 }
1265
1266 /* perform CLO */
1267 tmp = readl(port_mmio + PORT_CMD);
1268 tmp |= PORT_CMD_CLO;
1269 writel(tmp, port_mmio + PORT_CMD);
1270
1271 rc = 0;
97750ceb 1272 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1273 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1274 if (tmp & PORT_CMD_CLO)
1275 rc = -EIO;
1276
1277 /* restart engine */
1278 out_restart:
039ece38 1279 hpriv->start_engine(ap);
365cfa1e
AV		 1280 return rc;
1281}
1282EXPORT_SYMBOL_GPL(ahci_kick_engine);
1283
1284static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1285 struct ata_taskfile *tf, int is_cmd, u16 flags,
1286 unsigned long timeout_msec)
1287{
1288 const u32 cmd_fis_len = 5; /* five dwords */
1289 struct ahci_port_priv *pp = ap->private_data;
1290 void __iomem *port_mmio = ahci_port_base(ap);
1291 u8 *fis = pp->cmd_tbl;
1292 u32 tmp;
1293
1294 /* prep the command */
1295 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1296 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1297
023113d2
XY		 1298 /* set port value for softreset of Port Multiplier */
1299 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1300 tmp = readl(port_mmio + PORT_FBS);
1301 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1302 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1303 writel(tmp, port_mmio + PORT_FBS);
1304 pp->fbs_last_dev = pmp;
1305 }
1306
365cfa1e
AV		 1307 /* issue & wait */
1308 writel(1, port_mmio + PORT_CMD_ISSUE);
1309
1310 if (timeout_msec) {
97750ceb
TH		 1311 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1312 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1313 if (tmp & 0x1) {
1314 ahci_kick_engine(ap);
1315 return -EBUSY;
1316 }
1317 } else
1318 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1319
1320 return 0;
1321}
1322
1323int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1324 int pmp, unsigned long deadline,
1325 int (*check_ready)(struct ata_link *link))
1326{
1327 struct ata_port *ap = link->ap;
1328 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1329 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1330 const char *reason = NULL;
1331 unsigned long now, msecs;
1332 struct ata_taskfile tf;
89dafa20 1333 bool fbs_disabled = false;
365cfa1e
AV		 1334 int rc;
1335
1336 DPRINTK("ENTER\n");
1337
1338 /* prepare for SRST (AHCI-1.1 10.4.1) */
1339 rc = ahci_kick_engine(ap);
1340 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1341 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1342
89dafa20 1343 /*
1344 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1345 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1346 * that is attached to port multiplier.
1347 */
1348 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1349 ahci_disable_fbs(ap);
1350 fbs_disabled = true;
1351 }
1352
365cfa1e
AV		 1353 ata_tf_init(link->device, &tf);
1354
1355 /* issue the first D2H Register FIS */
1356 msecs = 0;
1357 now = jiffies;
f1f5a807 1358 if (time_after(deadline, now))
365cfa1e
AV		 1359 msecs = jiffies_to_msecs(deadline - now);
1360
1361 tf.ctl |= ATA_SRST;
1362 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1363 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1364 rc = -EIO;
1365 reason = "1st FIS failed";
1366 goto fail;
1367 }
1368
1369 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1370 ata_msleep(ap, 1);
365cfa1e
AV		 1371
1372 /* issue the second D2H Register FIS */
1373 tf.ctl &= ~ATA_SRST;
1374 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1375
1376 /* wait for link to become ready */
1377 rc = ata_wait_after_reset(link, deadline, check_ready);
1378 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1379 /*
1380 * Workaround for cases where link online status can't
1381 * be trusted. Treat device readiness timeout as link
1382 * offline.
1383 */
a9a79dfe 1384 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1385 *class = ATA_DEV_NONE;
1386 } else if (rc) {
1387 /* link occupied, -ENODEV too is an error */
1388 reason = "device not ready";
1389 goto fail;
1390 } else
1391 *class = ahci_dev_classify(ap);
1392
89dafa20 1393 /* re-enable FBS if disabled before */
1394 if (fbs_disabled)
1395 ahci_enable_fbs(ap);
1396
365cfa1e
AV		 1397 DPRINTK("EXIT, class=%u\n", *class);
1398 return 0;
1399
1400 fail:
a9a79dfe 1401 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1402 return rc;
1403}
1404
1405int ahci_check_ready(struct ata_link *link)
1406{
1407 void __iomem *port_mmio = ahci_port_base(link->ap);
1408 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1409
1410 return ata_check_ready(status);
1411}
1412EXPORT_SYMBOL_GPL(ahci_check_ready);
1413
1414static int ahci_softreset(struct ata_link *link, unsigned int *class,
1415 unsigned long deadline)
1416{
1417 int pmp = sata_srst_pmp(link);
1418
1419 DPRINTK("ENTER\n");
1420
1421 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1422}
1423EXPORT_SYMBOL_GPL(ahci_do_softreset);
1424
345347c5
YHC		 1425static int ahci_bad_pmp_check_ready(struct ata_link *link)
1426{
1427 void __iomem *port_mmio = ahci_port_base(link->ap);
1428 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1429 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1430
1431 /*
1432 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1433 * which can save timeout delay.
1434 */
1435 if (irq_status & PORT_IRQ_BAD_PMP)
1436 return -EIO;
1437
1438 return ata_check_ready(status);
1439}
1440
35186d05
DY		 1441static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1442 unsigned long deadline)
345347c5
YHC		 1443{
1444 struct ata_port *ap = link->ap;
1445 void __iomem *port_mmio = ahci_port_base(ap);
1446 int pmp = sata_srst_pmp(link);
1447 int rc;
1448 u32 irq_sts;
1449
1450 DPRINTK("ENTER\n");
1451
1452 rc = ahci_do_softreset(link, class, pmp, deadline,
1453 ahci_bad_pmp_check_ready);
1454
1455 /*
1456 * Soft reset fails with IPMS set when PMP is enabled but
1457 * SATA HDD/ODD is connected to SATA port, do soft reset
1458 * again to port 0.
1459 */
1460 if (rc == -EIO) {
1461 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1462 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1463 ata_link_warn(link,
345347c5
YHC		 1464 "applying PMP SRST workaround "
1465 "and retrying\n");
1466 rc = ahci_do_softreset(link, class, 0, deadline,
1467 ahci_check_ready);
1468 }
1469 }
1470
1471 return rc;
1472}
1473
365cfa1e
AV		 1474static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1475 unsigned long deadline)
1476{
1477 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1478 struct ata_port *ap = link->ap;
1479 struct ahci_port_priv *pp = ap->private_data;
039ece38 1480 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1481 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1482 struct ata_taskfile tf;
1483 bool online;
1484 int rc;
1485
1486 DPRINTK("ENTER\n");
1487
1488 ahci_stop_engine(ap);
1489
1490 /* clear D2H reception area to properly wait for D2H FIS */
1491 ata_tf_init(link->device, &tf);
9bbb1b0e 1492 tf.command = ATA_BUSY;
365cfa1e
AV		 1493 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1494
1495 rc = sata_link_hardreset(link, timing, deadline, &online,
1496 ahci_check_ready);
1497
039ece38 1498 hpriv->start_engine(ap);
365cfa1e
AV		 1499
1500 if (online)
1501 *class = ahci_dev_classify(ap);
1502
1503 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1504 return rc;
1505}
1506
1507static void ahci_postreset(struct ata_link *link, unsigned int *class)
1508{
1509 struct ata_port *ap = link->ap;
1510 void __iomem *port_mmio = ahci_port_base(ap);
1511 u32 new_tmp, tmp;
1512
1513 ata_std_postreset(link, class);
1514
1515 /* Make sure port's ATAPI bit is set appropriately */
1516 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1517 if (*class == ATA_DEV_ATAPI)
1518 new_tmp |= PORT_CMD_ATAPI;
1519 else
1520 new_tmp &= ~PORT_CMD_ATAPI;
1521 if (new_tmp != tmp) {
1522 writel(new_tmp, port_mmio + PORT_CMD);
1523 readl(port_mmio + PORT_CMD); /* flush */
1524 }
1525}
1526
1527static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1528{
1529 struct scatterlist *sg;
1530 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1531 unsigned int si;
1532
1533 VPRINTK("ENTER\n");
1534
1535 /*
1536 * Next, the S/G list.
1537 */
1538 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1539 dma_addr_t addr = sg_dma_address(sg);
1540 u32 sg_len = sg_dma_len(sg);
1541
1542 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1543 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1544 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1545 }
1546
1547 return si;
1548}
1549
1550static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1551{
1552 struct ata_port *ap = qc->ap;
1553 struct ahci_port_priv *pp = ap->private_data;
1554
1555 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1556 return ata_std_qc_defer(qc);
1557 else
1558 return sata_pmp_qc_defer_cmd_switch(qc);
1559}
1560
1561static void ahci_qc_prep(struct ata_queued_cmd *qc)
1562{
1563 struct ata_port *ap = qc->ap;
1564 struct ahci_port_priv *pp = ap->private_data;
1565 int is_atapi = ata_is_atapi(qc->tf.protocol);
1566 void *cmd_tbl;
1567 u32 opts;
1568 const u32 cmd_fis_len = 5; /* five dwords */
1569 unsigned int n_elem;
1570
1571 /*
1572 * Fill in command table information. First, the header,
1573 * a SATA Register - Host to Device command FIS.
1574 */
1575 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1576
1577 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1578 if (is_atapi) {
1579 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1580 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1581 }
1582
1583 n_elem = 0;
1584 if (qc->flags & ATA_QCFLAG_DMAMAP)
1585 n_elem = ahci_fill_sg(qc, cmd_tbl);
1586
1587 /*
1588 * Fill in command slot information.
1589 */
1590 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1591 if (qc->tf.flags & ATA_TFLAG_WRITE)
1592 opts |= AHCI_CMD_WRITE;
1593 if (is_atapi)
1594 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1595
1596 ahci_fill_cmd_slot(pp, qc->tag, opts);
1597}
1598
1599static void ahci_fbs_dec_intr(struct ata_port *ap)
1600{
1601 struct ahci_port_priv *pp = ap->private_data;
1602 void __iomem *port_mmio = ahci_port_base(ap);
1603 u32 fbs = readl(port_mmio + PORT_FBS);
1604 int retries = 3;
1605
1606 DPRINTK("ENTER\n");
1607 BUG_ON(!pp->fbs_enabled);
1608
1609 /* time to wait for DEC is not specified by AHCI spec,
1610 * add a retry loop for safety.
1611 */
1612 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1613 fbs = readl(port_mmio + PORT_FBS);
1614 while ((fbs & PORT_FBS_DEC) && retries--) {
1615 udelay(1);
1616 fbs = readl(port_mmio + PORT_FBS);
1617 }
1618
1619 if (fbs & PORT_FBS_DEC)
a44fec1f 1620 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1621}
1622
1623static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1624{
1625 struct ahci_host_priv *hpriv = ap->host->private_data;
1626 struct ahci_port_priv *pp = ap->private_data;
1627 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1628 struct ata_link *link = NULL;
1629 struct ata_queued_cmd *active_qc;
1630 struct ata_eh_info *active_ehi;
1631 bool fbs_need_dec = false;
1632 u32 serror;
1633
1634 /* determine active link with error */
1635 if (pp->fbs_enabled) {
1636 void __iomem *port_mmio = ahci_port_base(ap);
1637 u32 fbs = readl(port_mmio + PORT_FBS);
1638 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1639
912b9ac6 1640 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1641 link = &ap->pmp_link[pmp];
1642 fbs_need_dec = true;
1643 }
1644
1645 } else
1646 ata_for_each_link(link, ap, EDGE)
1647 if (ata_link_active(link))
1648 break;
1649
1650 if (!link)
1651 link = &ap->link;
1652
1653 active_qc = ata_qc_from_tag(ap, link->active_tag);
1654 active_ehi = &link->eh_info;
1655
1656 /* record irq stat */
1657 ata_ehi_clear_desc(host_ehi);
1658 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1659
1660 /* AHCI needs SError cleared; otherwise, it might lock up */
1661 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1662 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1663 host_ehi->serror |= serror;
1664
1665 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1666 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1667 irq_stat &= ~PORT_IRQ_IF_ERR;
1668
1669 if (irq_stat & PORT_IRQ_TF_ERR) {
1670 /* If qc is active, charge it; otherwise, the active
1671 * link. There's no active qc on NCQ errors. It will
1672 * be determined by EH by reading log page 10h.
1673 */
1674 if (active_qc)
1675 active_qc->err_mask |= AC_ERR_DEV;
1676 else
1677 active_ehi->err_mask |= AC_ERR_DEV;
1678
1679 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1680 host_ehi->serror &= ~SERR_INTERNAL;
1681 }
1682
1683 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1684 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1685
1686 active_ehi->err_mask |= AC_ERR_HSM;
1687 active_ehi->action |= ATA_EH_RESET;
1688 ata_ehi_push_desc(active_ehi,
1689 "unknown FIS %08x %08x %08x %08x" ,
1690 unk[0], unk[1], unk[2], unk[3]);
1691 }
1692
1693 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1694 active_ehi->err_mask |= AC_ERR_HSM;
1695 active_ehi->action |= ATA_EH_RESET;
1696 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1697 }
1698
1699 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1700 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1701 host_ehi->action |= ATA_EH_RESET;
1702 ata_ehi_push_desc(host_ehi, "host bus error");
1703 }
1704
1705 if (irq_stat & PORT_IRQ_IF_ERR) {
1706 if (fbs_need_dec)
1707 active_ehi->err_mask |= AC_ERR_DEV;
1708 else {
1709 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1710 host_ehi->action |= ATA_EH_RESET;
1711 }
1712
1713 ata_ehi_push_desc(host_ehi, "interface fatal error");
1714 }
1715
1716 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1717 ata_ehi_hotplugged(host_ehi);
1718 ata_ehi_push_desc(host_ehi, "%s",
1719 irq_stat & PORT_IRQ_CONNECT ?
1720 "connection status changed" : "PHY RDY changed");
1721 }
1722
1723 /* okay, let's hand over to EH */
1724
1725 if (irq_stat & PORT_IRQ_FREEZE)
1726 ata_port_freeze(ap);
1727 else if (fbs_need_dec) {
1728 ata_link_abort(link);
1729 ahci_fbs_dec_intr(ap);
1730 } else
1731 ata_port_abort(ap);
1732}
1733
5ca72c4f
AG		 1734static void ahci_handle_port_interrupt(struct ata_port *ap,
1735 void __iomem *port_mmio, u32 status)
365cfa1e 1736{
365cfa1e
AV		 1737 struct ata_eh_info *ehi = &ap->link.eh_info;
1738 struct ahci_port_priv *pp = ap->private_data;
1739 struct ahci_host_priv *hpriv = ap->host->private_data;
1740 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1741 u32 qc_active = 0;
365cfa1e
AV		 1742 int rc;
1743
365cfa1e
AV		 1744 /* ignore BAD_PMP while resetting */
1745 if (unlikely(resetting))
1746 status &= ~PORT_IRQ_BAD_PMP;
1747
8393b811 1748 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1749 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1750 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1751 }
1752
1753 if (unlikely(status & PORT_IRQ_ERROR)) {
1754 ahci_error_intr(ap, status);
1755 return;
1756 }
1757
1758 if (status & PORT_IRQ_SDB_FIS) {
1759 /* If SNotification is available, leave notification
1760 * handling to sata_async_notification(). If not,
1761 * emulate it by snooping SDB FIS RX area.
1762 *
1763 * Snooping FIS RX area is probably cheaper than
1764 * poking SNotification but some constrollers which
1765 * implement SNotification, ICH9 for example, don't
1766 * store AN SDB FIS into receive area.
1767 */
1768 if (hpriv->cap & HOST_CAP_SNTF)
1769 sata_async_notification(ap);
1770 else {
1771 /* If the 'N' bit in word 0 of the FIS is set,
1772 * we just received asynchronous notification.
1773 * Tell libata about it.
1774 *
1775 * Lack of SNotification should not appear in
1776 * ahci 1.2, so the workaround is unnecessary
1777 * when FBS is enabled.
1778 */
1779 if (pp->fbs_enabled)
1780 WARN_ON_ONCE(1);
1781 else {
1782 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1783 u32 f0 = le32_to_cpu(f[0]);
1784 if (f0 & (1 << 15))
1785 sata_async_notification(ap);
1786 }
1787 }
1788 }
1789
1790 /* pp->active_link is not reliable once FBS is enabled, both
1791 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1792 * NCQ and non-NCQ commands may be in flight at the same time.
1793 */
1794 if (pp->fbs_enabled) {
1795 if (ap->qc_active) {
1796 qc_active = readl(port_mmio + PORT_SCR_ACT);
1797 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1798 }
1799 } else {
1800 /* pp->active_link is valid iff any command is in flight */
1801 if (ap->qc_active && pp->active_link->sactive)
1802 qc_active = readl(port_mmio + PORT_SCR_ACT);
1803 else
1804 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1805 }
1806
1807
1808 rc = ata_qc_complete_multiple(ap, qc_active);
1809
1810 /* while resetting, invalid completions are expected */
1811 if (unlikely(rc < 0 && !resetting)) {
1812 ehi->err_mask |= AC_ERR_HSM;
1813 ehi->action |= ATA_EH_RESET;
1814 ata_port_freeze(ap);
1815 }
1816}
1817
7865f83f 1818static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1819{
1820 void __iomem *port_mmio = ahci_port_base(ap);
1821 u32 status;
1822
1823 status = readl(port_mmio + PORT_IRQ_STAT);
1824 writel(status, port_mmio + PORT_IRQ_STAT);
1825
7865f83f 1826 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1827}
1828
a6b7fb76 1829static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1830{
1831 struct ata_port *ap = dev_instance;
5ca72c4f 1832 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1833 u32 status;
1834
5ca72c4f
AG		 1835 VPRINTK("ENTER\n");
1836
227dfb4d
AG		 1837 status = readl(port_mmio + PORT_IRQ_STAT);
1838 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1839
a6b7fb76
DW		 1840 spin_lock(ap->lock);
1841 ahci_handle_port_interrupt(ap, port_mmio, status);
1842 spin_unlock(ap->lock);
5ca72c4f
AG		 1843
1844 VPRINTK("EXIT\n");
1845
a6b7fb76 1846 return IRQ_HANDLED;
5ca72c4f 1847}
5ca72c4f 1848
a129db89 1849static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1850{
365cfa1e 1851 unsigned int i, handled = 0;
03e83cbd 1852
365cfa1e
AV		 1853 for (i = 0; i < host->n_ports; i++) {
1854 struct ata_port *ap;
1855
1856 if (!(irq_masked & (1 << i)))
1857 continue;
1858
1859 ap = host->ports[i];
1860 if (ap) {
7865f83f 1861 ahci_port_intr(ap);
365cfa1e
AV		 1862 VPRINTK("port %u\n", i);
1863 } else {
1864 VPRINTK("port %u (no irq)\n", i);
1865 if (ata_ratelimit())
a44fec1f
JP		 1866 dev_warn(host->dev,
1867 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1868 }
1869
1870 handled = 1;
1871 }
1872
a129db89
ST		 1873 return handled;
1874}
1875
5903b164 1876static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
365cfa1e
AV		 1877{
1878 struct ata_host *host = dev_instance;
1879 struct ahci_host_priv *hpriv;
5903b164 1880 unsigned int rc = 0;
365cfa1e
AV		 1881 void __iomem *mmio;
1882 u32 irq_stat, irq_masked;
1883
1884 VPRINTK("ENTER\n");
1885
1886 hpriv = host->private_data;
1887 mmio = hpriv->mmio;
1888
1889 /* sigh. 0xffffffff is a valid return from h/w */
1890 irq_stat = readl(mmio + HOST_IRQ_STAT);
1891 if (!irq_stat)
1892 return IRQ_NONE;
1893
1894 irq_masked = irq_stat & hpriv->port_map;
1895
03e83cbd
TH		 1896 spin_lock(&host->lock);
1897
5903b164
ST		 1898 /*
1899 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1900 * it should be cleared before all the port events are cleared.
1901 */
1902 writel(irq_stat, mmio + HOST_IRQ_STAT);
365cfa1e 1903
5903b164 1904 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e 1905
5903b164 1906 spin_unlock(&host->lock);
365cfa1e 1907
5903b164
ST		 1908 VPRINTK("EXIT\n");
1909
1910 return IRQ_RETVAL(rc);
1911}
1912
a129db89
ST		 1913static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1914{
1915 struct ata_host *host = dev_instance;
1916 struct ahci_host_priv *hpriv;
1917 unsigned int rc = 0;
1918 void __iomem *mmio;
1919 u32 irq_stat, irq_masked;
1920
1921 VPRINTK("ENTER\n");
1922
1923 hpriv = host->private_data;
1924 mmio = hpriv->mmio;
1925
1926 /* sigh. 0xffffffff is a valid return from h/w */
1927 irq_stat = readl(mmio + HOST_IRQ_STAT);
1928 if (!irq_stat)
1929 return IRQ_NONE;
1930
1931 irq_masked = irq_stat & hpriv->port_map;
1932
1933 spin_lock(&host->lock);
1934
1935 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1936
1937 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1938 * it should be cleared after all the port events are cleared;
1939 * otherwise, it will raise a spurious interrupt after each
1940 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1941 * information.
1942 *
1943 * Also, use the unmasked value to clear interrupt as spurious
1944 * pending event on a dummy port might cause screaming IRQ.
1945 */
1946 writel(irq_stat, mmio + HOST_IRQ_STAT);
1947
03e83cbd
TH		 1948 spin_unlock(&host->lock);
1949
365cfa1e
AV		 1950 VPRINTK("EXIT\n");
1951
a129db89 1952 return IRQ_RETVAL(rc);
365cfa1e 1953}
365cfa1e 1954
39e0ee99 1955unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1956{
1957 struct ata_port *ap = qc->ap;
1958 void __iomem *port_mmio = ahci_port_base(ap);
1959 struct ahci_port_priv *pp = ap->private_data;
1960
1961 /* Keep track of the currently active link. It will be used
1962 * in completion path to determine whether NCQ phase is in
1963 * progress.
1964 */
1965 pp->active_link = qc->dev->link;
1966
1967 if (qc->tf.protocol == ATA_PROT_NCQ)
1968 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1969
1970 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1971 u32 fbs = readl(port_mmio + PORT_FBS);
1972 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1973 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1974 writel(fbs, port_mmio + PORT_FBS);
1975 pp->fbs_last_dev = qc->dev->link->pmp;
1976 }
1977
1978 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1979
1980 ahci_sw_activity(qc->dev->link);
1981
1982 return 0;
1983}
39e0ee99 1984EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1985
1986static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1987{
1988 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1989 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1990
1991 if (pp->fbs_enabled)
6ad60195
TH		 1992 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1993
1994 /*
1995 * After a successful execution of an ATA PIO data-in command,
1996 * the device doesn't send D2H Reg FIS to update the TF and
1997 * the host should take TF and E_Status from the preceding PIO
1998 * Setup FIS.
1999 */
2000 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2001 !(qc->flags & ATA_QCFLAG_FAILED)) {
2002 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2003 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2004 } else
2005 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2006
365cfa1e
AV		 2007 return true;
2008}
2009
2010static void ahci_freeze(struct ata_port *ap)
2011{
2012 void __iomem *port_mmio = ahci_port_base(ap);
2013
2014 /* turn IRQ off */
2015 writel(0, port_mmio + PORT_IRQ_MASK);
2016}
2017
2018static void ahci_thaw(struct ata_port *ap)
2019{
2020 struct ahci_host_priv *hpriv = ap->host->private_data;
2021 void __iomem *mmio = hpriv->mmio;
2022 void __iomem *port_mmio = ahci_port_base(ap);
2023 u32 tmp;
2024 struct ahci_port_priv *pp = ap->private_data;
2025
2026 /* clear IRQ */
2027 tmp = readl(port_mmio + PORT_IRQ_STAT);
2028 writel(tmp, port_mmio + PORT_IRQ_STAT);
2029 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2030
2031 /* turn IRQ back on */
2032 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2033}
2034
8b789d89 2035void ahci_error_handler(struct ata_port *ap)
365cfa1e 2036{
039ece38
HG		 2037 struct ahci_host_priv *hpriv = ap->host->private_data;
2038
365cfa1e
AV		 2039 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2040 /* restart engine */
2041 ahci_stop_engine(ap);
039ece38 2042 hpriv->start_engine(ap);
365cfa1e
AV		 2043 }
2044
2045 sata_pmp_error_handler(ap);
0ee71952
TH		 2046
2047 if (!ata_dev_enabled(ap->link.device))
2048 ahci_stop_engine(ap);
365cfa1e 2049}
8b789d89 2050EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2051
2052static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2053{
2054 struct ata_port *ap = qc->ap;
2055
2056 /* make DMA engine forget about the failed command */
2057 if (qc->flags & ATA_QCFLAG_FAILED)
2058 ahci_kick_engine(ap);
2059}
2060
65fe1f0f
SH		 2061static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2062{
039ece38 2063 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2064 void __iomem *port_mmio = ahci_port_base(ap);
2065 struct ata_device *dev = ap->link.device;
2066 u32 devslp, dm, dito, mdat, deto;
2067 int rc;
2068 unsigned int err_mask;
2069
2070 devslp = readl(port_mmio + PORT_DEVSLP);
2071 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2072 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2073 return;
2074 }
2075
2076 /* disable device sleep */
2077 if (!sleep) {
2078 if (devslp & PORT_DEVSLP_ADSE) {
2079 writel(devslp & ~PORT_DEVSLP_ADSE,
2080 port_mmio + PORT_DEVSLP);
2081 err_mask = ata_dev_set_feature(dev,
2082 SETFEATURES_SATA_DISABLE,
2083 SATA_DEVSLP);
2084 if (err_mask && err_mask != AC_ERR_DEV)
2085 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2086 }
2087 return;
2088 }
2089
2090 /* device sleep was already enabled */
2091 if (devslp & PORT_DEVSLP_ADSE)
2092 return;
2093
2094 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2095 rc = ahci_stop_engine(ap);
2096 if (rc)
2097 return;
2098
2099 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2100 dito = devslp_idle_timeout / (dm + 1);
2101 if (dito > 0x3ff)
2102 dito = 0x3ff;
2103
2104 /* Use the nominal value 10 ms if the read MDAT is zero,
2105 * the nominal value of DETO is 20 ms.
2106 */
803739d2 2107 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2108 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2109 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2110 ATA_LOG_DEVSLP_MDAT_MASK;
2111 if (!mdat)
2112 mdat = 10;
803739d2 2113 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2114 if (!deto)
2115 deto = 20;
2116 } else {
2117 mdat = 10;
2118 deto = 20;
2119 }
2120
2121 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2122 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2123 (deto << PORT_DEVSLP_DETO_OFFSET) |
2124 PORT_DEVSLP_ADSE);
2125 writel(devslp, port_mmio + PORT_DEVSLP);
2126
039ece38 2127 hpriv->start_engine(ap);
65fe1f0f
SH		 2128
2129 /* enable device sleep feature for the drive */
2130 err_mask = ata_dev_set_feature(dev,
2131 SETFEATURES_SATA_ENABLE,
2132 SATA_DEVSLP);
2133 if (err_mask && err_mask != AC_ERR_DEV)
2134 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2135}
2136
365cfa1e
AV		 2137static void ahci_enable_fbs(struct ata_port *ap)
2138{
039ece38 2139 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2140 struct ahci_port_priv *pp = ap->private_data;
2141 void __iomem *port_mmio = ahci_port_base(ap);
2142 u32 fbs;
2143 int rc;
2144
2145 if (!pp->fbs_supported)
2146 return;
2147
2148 fbs = readl(port_mmio + PORT_FBS);
2149 if (fbs & PORT_FBS_EN) {
2150 pp->fbs_enabled = true;
2151 pp->fbs_last_dev = -1; /* initialization */
2152 return;
2153 }
2154
2155 rc = ahci_stop_engine(ap);
2156 if (rc)
2157 return;
2158
2159 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2160 fbs = readl(port_mmio + PORT_FBS);
2161 if (fbs & PORT_FBS_EN) {
a44fec1f 2162 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2163 pp->fbs_enabled = true;
2164 pp->fbs_last_dev = -1; /* initialization */
2165 } else
a44fec1f 2166 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2167
039ece38 2168 hpriv->start_engine(ap);
365cfa1e
AV		 2169}
2170
2171static void ahci_disable_fbs(struct ata_port *ap)
2172{
039ece38 2173 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2174 struct ahci_port_priv *pp = ap->private_data;
2175 void __iomem *port_mmio = ahci_port_base(ap);
2176 u32 fbs;
2177 int rc;
2178
2179 if (!pp->fbs_supported)
2180 return;
2181
2182 fbs = readl(port_mmio + PORT_FBS);
2183 if ((fbs & PORT_FBS_EN) == 0) {
2184 pp->fbs_enabled = false;
2185 return;
2186 }
2187
2188 rc = ahci_stop_engine(ap);
2189 if (rc)
2190 return;
2191
2192 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2193 fbs = readl(port_mmio + PORT_FBS);
2194 if (fbs & PORT_FBS_EN)
a44fec1f 2195 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2196 else {
a44fec1f 2197 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2198 pp->fbs_enabled = false;
2199 }
2200
039ece38 2201 hpriv->start_engine(ap);
365cfa1e
AV		 2202}
2203
2204static void ahci_pmp_attach(struct ata_port *ap)
2205{
2206 void __iomem *port_mmio = ahci_port_base(ap);
2207 struct ahci_port_priv *pp = ap->private_data;
2208 u32 cmd;
2209
2210 cmd = readl(port_mmio + PORT_CMD);
2211 cmd |= PORT_CMD_PMP;
2212 writel(cmd, port_mmio + PORT_CMD);
2213
2214 ahci_enable_fbs(ap);
2215
2216 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2217
2218 /*
2219 * We must not change the port interrupt mask register if the
2220 * port is marked frozen, the value in pp->intr_mask will be
2221 * restored later when the port is thawed.
2222 *
2223 * Note that during initialization, the port is marked as
2224 * frozen since the irq handler is not yet registered.
2225 */
2226 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2227 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2228}
2229
2230static void ahci_pmp_detach(struct ata_port *ap)
2231{
2232 void __iomem *port_mmio = ahci_port_base(ap);
2233 struct ahci_port_priv *pp = ap->private_data;
2234 u32 cmd;
2235
2236 ahci_disable_fbs(ap);
2237
2238 cmd = readl(port_mmio + PORT_CMD);
2239 cmd &= ~PORT_CMD_PMP;
2240 writel(cmd, port_mmio + PORT_CMD);
2241
2242 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2243
2244 /* see comment above in ahci_pmp_attach() */
2245 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2246 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2247}
2248
02cdfcf0 2249int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2250{
2251 ahci_power_up(ap);
2252 ahci_start_port(ap);
2253
2254 if (sata_pmp_attached(ap))
2255 ahci_pmp_attach(ap);
2256 else
2257 ahci_pmp_detach(ap);
2258
2259 return 0;
2260}
02cdfcf0 2261EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2262
2263#ifdef CONFIG_PM
2264static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2265{
2266 const char *emsg = NULL;
2267 int rc;
2268
2269 rc = ahci_deinit_port(ap, &emsg);
2270 if (rc == 0)
2271 ahci_power_down(ap);
2272 else {
a9a79dfe 2273 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2274 ata_port_freeze(ap);
365cfa1e
AV		 2275 }
2276
2277 return rc;
2278}
2279#endif
2280
2281static int ahci_port_start(struct ata_port *ap)
2282{
2283 struct ahci_host_priv *hpriv = ap->host->private_data;
2284 struct device *dev = ap->host->dev;
2285 struct ahci_port_priv *pp;
2286 void *mem;
2287 dma_addr_t mem_dma;
2288 size_t dma_sz, rx_fis_sz;
2289
2290 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2291 if (!pp)
2292 return -ENOMEM;
2293
b29900e6
AG		 2294 if (ap->host->n_ports > 1) {
2295 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2296 if (!pp->irq_desc) {
2297 devm_kfree(dev, pp);
2298 return -ENOMEM;
2299 }
2300 snprintf(pp->irq_desc, 8,
2301 "%s%d", dev_driver_string(dev), ap->port_no);
2302 }
2303
365cfa1e
AV		 2304 /* check FBS capability */
2305 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2306 void __iomem *port_mmio = ahci_port_base(ap);
2307 u32 cmd = readl(port_mmio + PORT_CMD);
2308 if (cmd & PORT_CMD_FBSCP)
2309 pp->fbs_supported = true;
5f173107 2310 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2311 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2312 ap->port_no);
5f173107
TH		 2313 pp->fbs_supported = true;
2314 } else
a44fec1f
JP		 2315 dev_warn(dev, "port %d is not capable of FBS\n",
2316 ap->port_no);
365cfa1e
AV		 2317 }
2318
2319 if (pp->fbs_supported) {
2320 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2321 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2322 } else {
2323 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2324 rx_fis_sz = AHCI_RX_FIS_SZ;
2325 }
2326
2327 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2328 if (!mem)
2329 return -ENOMEM;
2330 memset(mem, 0, dma_sz);
2331
2332 /*
2333 * First item in chunk of DMA memory: 32-slot command table,
2334 * 32 bytes each in size
2335 */
2336 pp->cmd_slot = mem;
2337 pp->cmd_slot_dma = mem_dma;
2338
2339 mem += AHCI_CMD_SLOT_SZ;
2340 mem_dma += AHCI_CMD_SLOT_SZ;
2341
2342 /*
2343 * Second item: Received-FIS area
2344 */
2345 pp->rx_fis = mem;
2346 pp->rx_fis_dma = mem_dma;
2347
2348 mem += rx_fis_sz;
2349 mem_dma += rx_fis_sz;
2350
2351 /*
2352 * Third item: data area for storing a single command
2353 * and its scatter-gather table
2354 */
2355 pp->cmd_tbl = mem;
2356 pp->cmd_tbl_dma = mem_dma;
2357
2358 /*
2359 * Save off initial list of interrupts to be enabled.
2360 * This could be changed later
2361 */
2362 pp->intr_mask = DEF_PORT_IRQ;
2363
7865f83f
TH		 2364 /*
2365 * Switch to per-port locking in case each port has its own MSI vector.
2366 */
21bfd1aa 2367 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2368 spin_lock_init(&pp->lock);
2369 ap->lock = &pp->lock;
2370 }
5ca72c4f 2371
365cfa1e
AV		 2372 ap->private_data = pp;
2373
2374 /* engage engines, captain */
2375 return ahci_port_resume(ap);
2376}
2377
2378static void ahci_port_stop(struct ata_port *ap)
2379{
2380 const char *emsg = NULL;
2381 int rc;
2382
2383 /* de-initialize port */
2384 rc = ahci_deinit_port(ap, &emsg);
2385 if (rc)
a9a79dfe 2386 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2387}
2388
2389void ahci_print_info(struct ata_host *host, const char *scc_s)
2390{
2391 struct ahci_host_priv *hpriv = host->private_data;
2392 void __iomem *mmio = hpriv->mmio;
2393 u32 vers, cap, cap2, impl, speed;
2394 const char *speed_s;
2395
2396 vers = readl(mmio + HOST_VERSION);
2397 cap = hpriv->cap;
2398 cap2 = hpriv->cap2;
2399 impl = hpriv->port_map;
2400
2401 speed = (cap >> 20) & 0xf;
2402 if (speed == 1)
2403 speed_s = "1.5";
2404 else if (speed == 2)
2405 speed_s = "3";
2406 else if (speed == 3)
2407 speed_s = "6";
2408 else
2409 speed_s = "?";
2410
2411 dev_info(host->dev,
2412 "AHCI %02x%02x.%02x%02x "
2413 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2414 ,
2415
2416 (vers >> 24) & 0xff,
2417 (vers >> 16) & 0xff,
2418 (vers >> 8) & 0xff,
2419 vers & 0xff,
2420
2421 ((cap >> 8) & 0x1f) + 1,
2422 (cap & 0x1f) + 1,
2423 speed_s,
2424 impl,
2425 scc_s);
2426
2427 dev_info(host->dev,
2428 "flags: "
2429 "%s%s%s%s%s%s%s"
2430 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2431 "%s%s%s%s%s%s%s"
2432 "%s%s\n"
365cfa1e
AV		 2433 ,
2434
2435 cap & HOST_CAP_64 ? "64bit " : "",
2436 cap & HOST_CAP_NCQ ? "ncq " : "",
2437 cap & HOST_CAP_SNTF ? "sntf " : "",
2438 cap & HOST_CAP_MPS ? "ilck " : "",
2439 cap & HOST_CAP_SSS ? "stag " : "",
2440 cap & HOST_CAP_ALPM ? "pm " : "",
2441 cap & HOST_CAP_LED ? "led " : "",
2442 cap & HOST_CAP_CLO ? "clo " : "",
2443 cap & HOST_CAP_ONLY ? "only " : "",
2444 cap & HOST_CAP_PMP ? "pmp " : "",
2445 cap & HOST_CAP_FBS ? "fbs " : "",
2446 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2447 cap & HOST_CAP_SSC ? "slum " : "",
2448 cap & HOST_CAP_PART ? "part " : "",
2449 cap & HOST_CAP_CCC ? "ccc " : "",
2450 cap & HOST_CAP_EMS ? "ems " : "",
2451 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2452 cap2 & HOST_CAP2_DESO ? "deso " : "",
2453 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2454 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2455 cap2 & HOST_CAP2_APST ? "apst " : "",
2456 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2457 cap2 & HOST_CAP2_BOH ? "boh " : ""
2458 );
2459}
2460EXPORT_SYMBOL_GPL(ahci_print_info);
2461
2462void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2463 struct ata_port_info *pi)
2464{
2465 u8 messages;
2466 void __iomem *mmio = hpriv->mmio;
2467 u32 em_loc = readl(mmio + HOST_EM_LOC);
2468 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2469
2470 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2471 return;
2472
2473 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2474
008dbd61 2475 if (messages) {
365cfa1e
AV		 2476 /* store em_loc */
2477 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2478 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2479 hpriv->em_msg_type = messages;
365cfa1e
AV		 2480 pi->flags |= ATA_FLAG_EM;
2481 if (!(em_ctl & EM_CTL_ALHD))
2482 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2483 }
2484}
2485EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2486
d684a90d 2487static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2488 struct scsi_host_template *sht)
1c62854f 2489{
d684a90d 2490 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2491 int i, rc;
2492
2493 rc = ata_host_start(host);
2494 if (rc)
2495 return rc;
21bfd1aa
RR		 2496 /*
2497 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2498 * allocated. That is one MSI per port, starting from @irq.
2499 */
1c62854f
AG		 2500 for (i = 0; i < host->n_ports; i++) {
2501 struct ahci_port_priv *pp = host->ports[i]->private_data;
f893180b 2502 int irq = ahci_irq_vector(hpriv, i);
1c62854f
AG		 2503
2504 /* Do not receive interrupts sent by dummy ports */
2505 if (!pp) {
2506 disable_irq(irq + i);
2507 continue;
2508 }
2509
a6b7fb76
DW		 2510 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2511 0, pp->irq_desc, host->ports[i]);
2512
1c62854f 2513 if (rc)
0a142b26 2514 return rc;
d684a90d 2515 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2516 }
d684a90d 2517
0a142b26 2518 return ata_host_register(host, sht);
1c62854f 2519}
d1028e2f
AG		 2520
2521/**
2522 * ahci_host_activate - start AHCI host, request IRQs and register it
2523 * @host: target ATA host
d1028e2f
AG		 2524 * @sht: scsi_host_template to use when registering the host
2525 *
d1028e2f
AG		 2526 * LOCKING:
2527 * Inherited from calling layer (may sleep).
2528 *
2529 * RETURNS:
2530 * 0 on success, -errno otherwise.
2531 */
21bfd1aa 2532int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2533{
2534 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2535 int irq = hpriv->irq;
d1028e2f
AG		 2536 int rc;
2537
d684a90d
DW		 2538 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX))
2539 rc = ahci_host_activate_multi_irqs(host, sht);
5903b164
ST		 2540 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2541 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2542 IRQF_SHARED, sht);
d1028e2f 2543 else
a129db89 2544 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
7865f83f 2545 IRQF_SHARED, sht);
d1028e2f
AG		 2546 return rc;
2547}
1c62854f
AG		 2548EXPORT_SYMBOL_GPL(ahci_host_activate);
2549
365cfa1e
AV		 2550MODULE_AUTHOR("Jeff Garzik");
2551MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2552MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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