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ahci: Workaround for ThunderX Errata#22536
[deliverable/linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
d684a90d 46#include <linux/pci.h>
365cfa1e 47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
65fe1f0f 79static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
345347c5
YHC		 86static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
365cfa1e
AV		 88static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
f070d671 116static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 117
118static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 122static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 124static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 125
fad16e7a 126struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
c0623166 134 &dev_attr_em_buffer,
6e5fe5b1 135 &dev_attr_em_message_supported,
365cfa1e
AV		 136 NULL
137};
fad16e7a 138EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 139
fad16e7a 140struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 NULL
144};
fad16e7a 145EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 146
147struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
149
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
154
155 .freeze = ahci_freeze,
156 .thaw = ahci_thaw,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
164
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
169
6b7ae954 170 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
439d7a35 175 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 176#ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179#endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182};
183EXPORT_SYMBOL_GPL(ahci_ops);
184
345347c5
YHC		 185struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188};
189EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
ed08d40c 191static bool ahci_em_messages __read_mostly = true;
365cfa1e 192EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 193module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 194/* add other LED protocol types when they become supported */
195MODULE_PARM_DESC(ahci_em_messages,
008dbd61 196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 197
ed08d40c
CL		 198/* device sleep idle timeout in ms */
199static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 200module_param(devslp_idle_timeout, int, 0644);
201MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
202
365cfa1e
AV		 203static void ahci_enable_ahci(void __iomem *mmio)
204{
205 int i;
206 u32 tmp;
207
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
211 return;
212
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
215 */
216 for (i = 0; i < 5; i++) {
217 tmp |= HOST_AHCI_EN;
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
221 return;
222 msleep(10);
223 }
224
225 WARN_ON(1);
226}
227
228static ssize_t ahci_show_host_caps(struct device *dev,
229 struct device_attribute *attr, char *buf)
230{
231 struct Scsi_Host *shost = class_to_shost(dev);
232 struct ata_port *ap = ata_shost_to_port(shost);
233 struct ahci_host_priv *hpriv = ap->host->private_data;
234
235 return sprintf(buf, "%x\n", hpriv->cap);
236}
237
238static ssize_t ahci_show_host_cap2(struct device *dev,
239 struct device_attribute *attr, char *buf)
240{
241 struct Scsi_Host *shost = class_to_shost(dev);
242 struct ata_port *ap = ata_shost_to_port(shost);
243 struct ahci_host_priv *hpriv = ap->host->private_data;
244
245 return sprintf(buf, "%x\n", hpriv->cap2);
246}
247
248static ssize_t ahci_show_host_version(struct device *dev,
249 struct device_attribute *attr, char *buf)
250{
251 struct Scsi_Host *shost = class_to_shost(dev);
252 struct ata_port *ap = ata_shost_to_port(shost);
253 struct ahci_host_priv *hpriv = ap->host->private_data;
254 void __iomem *mmio = hpriv->mmio;
255
256 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257}
258
259static ssize_t ahci_show_port_cmd(struct device *dev,
260 struct device_attribute *attr, char *buf)
261{
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 void __iomem *port_mmio = ahci_port_base(ap);
265
266 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267}
268
c0623166
HZ		 269static ssize_t ahci_read_em_buffer(struct device *dev,
270 struct device_attribute *attr, char *buf)
271{
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 struct ahci_host_priv *hpriv = ap->host->private_data;
275 void __iomem *mmio = hpriv->mmio;
276 void __iomem *em_mmio = mmio + hpriv->em_loc;
277 u32 em_ctl, msg;
278 unsigned long flags;
279 size_t count;
280 int i;
281
282 spin_lock_irqsave(ap->lock, flags);
283
284 em_ctl = readl(mmio + HOST_EM_CTL);
285 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
286 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
287 spin_unlock_irqrestore(ap->lock, flags);
288 return -EINVAL;
289 }
290
291 if (!(em_ctl & EM_CTL_MR)) {
292 spin_unlock_irqrestore(ap->lock, flags);
293 return -EAGAIN;
294 }
295
296 if (!(em_ctl & EM_CTL_SMB))
297 em_mmio += hpriv->em_buf_sz;
298
299 count = hpriv->em_buf_sz;
300
301 /* the count should not be larger than PAGE_SIZE */
302 if (count > PAGE_SIZE) {
303 if (printk_ratelimit())
a9a79dfe
JP		 304 ata_port_warn(ap,
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 308 count = PAGE_SIZE;
309 }
310
311 for (i = 0; i < count; i += 4) {
312 msg = readl(em_mmio + i);
313 buf[i] = msg & 0xff;
314 buf[i + 1] = (msg >> 8) & 0xff;
315 buf[i + 2] = (msg >> 16) & 0xff;
316 buf[i + 3] = (msg >> 24) & 0xff;
317 }
318
319 spin_unlock_irqrestore(ap->lock, flags);
320
321 return i;
322}
323
324static ssize_t ahci_store_em_buffer(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t size)
327{
328 struct Scsi_Host *shost = class_to_shost(dev);
329 struct ata_port *ap = ata_shost_to_port(shost);
330 struct ahci_host_priv *hpriv = ap->host->private_data;
331 void __iomem *mmio = hpriv->mmio;
332 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 333 const unsigned char *msg_buf = buf;
c0623166
HZ		 334 u32 em_ctl, msg;
335 unsigned long flags;
336 int i;
337
338 /* check size validity */
339 if (!(ap->flags & ATA_FLAG_EM) ||
340 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
341 size % 4 || size > hpriv->em_buf_sz)
342 return -EINVAL;
343
344 spin_lock_irqsave(ap->lock, flags);
345
346 em_ctl = readl(mmio + HOST_EM_CTL);
347 if (em_ctl & EM_CTL_TM) {
348 spin_unlock_irqrestore(ap->lock, flags);
349 return -EBUSY;
350 }
351
352 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 353 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
354 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 355 writel(msg, em_mmio + i);
356 }
357
358 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
359
360 spin_unlock_irqrestore(ap->lock, flags);
361
362 return size;
363}
364
6e5fe5b1
HR		 365static ssize_t ahci_show_em_supported(struct device *dev,
366 struct device_attribute *attr, char *buf)
367{
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 u32 em_ctl;
373
374 em_ctl = readl(mmio + HOST_EM_CTL);
375
376 return sprintf(buf, "%s%s%s%s\n",
377 em_ctl & EM_CTL_LED ? "led " : "",
378 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
379 em_ctl & EM_CTL_SES ? "ses-2 " : "",
380 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
381}
382
365cfa1e
AV		 383/**
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
365cfa1e
AV		 387 *
388 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the
390 * initial values of those registers into @hpriv such that they
391 * can be restored after controller reset.
392 *
393 * If inconsistent, config values are fixed up by this function.
394 *
039ece38
HG		 395 * If it is not set already this function sets hpriv->start_engine to
396 * ahci_start_engine.
397 *
365cfa1e
AV		 398 * LOCKING:
399 * None.
400 */
725c7b57 401void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 402{
403 void __iomem *mmio = hpriv->mmio;
404 u32 cap, cap2, vers, port_map;
405 int i;
406
407 /* make sure AHCI mode is enabled before accessing CAP */
408 ahci_enable_ahci(mmio);
409
410 /* Values prefixed with saved_ are written back to host after
411 * reset. Values without are used for driver operation.
412 */
413 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
414 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
415
416 /* CAP2 register is only defined for AHCI 1.2 and later */
417 vers = readl(mmio + HOST_VERSION);
418 if ((vers >> 16) > 1 ||
419 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
420 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
421 else
422 hpriv->saved_cap2 = cap2 = 0;
423
424 /* some chips have errata preventing 64bit use */
425 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 426 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 427 cap &= ~HOST_CAP_64;
428 }
429
430 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 431 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 432 cap &= ~HOST_CAP_NCQ;
433 }
434
435 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 436 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 437 cap |= HOST_CAP_NCQ;
438 }
439
440 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 441 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 442 cap &= ~HOST_CAP_PMP;
443 }
444
445 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 446 dev_info(dev,
447 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 448 cap &= ~HOST_CAP_SNTF;
449 }
450
0cf4a7d6
JP		 451 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
452 dev_info(dev,
453 "controller can't do DEVSLP, turning off\n");
454 cap2 &= ~HOST_CAP2_SDS;
455 cap2 &= ~HOST_CAP2_SADM;
456 }
457
5f173107 458 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 459 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 460 cap |= HOST_CAP_FBS;
461 }
462
888d91a0
KW		 463 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
464 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
465 cap &= ~HOST_CAP_FBS;
466 }
467
725c7b57 468 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 469 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 470 port_map, hpriv->force_port_map);
471 port_map = hpriv->force_port_map;
365cfa1e
AV		 472 }
473
725c7b57 474 if (hpriv->mask_port_map) {
a44fec1f
JP		 475 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
476 port_map,
725c7b57
AT		 477 port_map & hpriv->mask_port_map);
478 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 479 }
480
481 /* cross check port_map and cap.n_ports */
482 if (port_map) {
483 int map_ports = 0;
484
485 for (i = 0; i < AHCI_MAX_PORTS; i++)
486 if (port_map & (1 << i))
487 map_ports++;
488
489 /* If PI has more ports than n_ports, whine, clear
490 * port_map and let it be generated from n_ports.
491 */
492 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 493 dev_warn(dev,
494 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
495 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 496 port_map = 0;
497 }
498 }
499
566d1827
TH		 500 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
501 if (!port_map && vers < 0x10300) {
365cfa1e 502 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 503 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 504
505 /* write the fixed up value to the PI register */
506 hpriv->saved_port_map = port_map;
507 }
508
509 /* record values to use during operation */
510 hpriv->cap = cap;
511 hpriv->cap2 = cap2;
512 hpriv->port_map = port_map;
039ece38
HG		 513
514 if (!hpriv->start_engine)
515 hpriv->start_engine = ahci_start_engine;
f070d671
ST		 516
517 if (!hpriv->irq_handler)
d867b95f 518 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 519}
520EXPORT_SYMBOL_GPL(ahci_save_initial_config);
521
522/**
523 * ahci_restore_initial_config - Restore initial config
524 * @host: target ATA host
525 *
526 * Restore initial config stored by ahci_save_initial_config().
527 *
528 * LOCKING:
529 * None.
530 */
531static void ahci_restore_initial_config(struct ata_host *host)
532{
533 struct ahci_host_priv *hpriv = host->private_data;
534 void __iomem *mmio = hpriv->mmio;
535
536 writel(hpriv->saved_cap, mmio + HOST_CAP);
537 if (hpriv->saved_cap2)
538 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
539 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
540 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
541}
542
543static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
544{
545 static const int offset[] = {
546 [SCR_STATUS] = PORT_SCR_STAT,
547 [SCR_CONTROL] = PORT_SCR_CTL,
548 [SCR_ERROR] = PORT_SCR_ERR,
549 [SCR_ACTIVE] = PORT_SCR_ACT,
550 [SCR_NOTIFICATION] = PORT_SCR_NTF,
551 };
552 struct ahci_host_priv *hpriv = ap->host->private_data;
553
554 if (sc_reg < ARRAY_SIZE(offset) &&
555 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
556 return offset[sc_reg];
557 return 0;
558}
559
560static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
561{
562 void __iomem *port_mmio = ahci_port_base(link->ap);
563 int offset = ahci_scr_offset(link->ap, sc_reg);
564
565 if (offset) {
566 *val = readl(port_mmio + offset);
567 return 0;
568 }
569 return -EINVAL;
570}
571
572static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
573{
574 void __iomem *port_mmio = ahci_port_base(link->ap);
575 int offset = ahci_scr_offset(link->ap, sc_reg);
576
577 if (offset) {
578 writel(val, port_mmio + offset);
579 return 0;
580 }
581 return -EINVAL;
582}
583
584void ahci_start_engine(struct ata_port *ap)
585{
586 void __iomem *port_mmio = ahci_port_base(ap);
587 u32 tmp;
588
589 /* start DMA */
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
594}
595EXPORT_SYMBOL_GPL(ahci_start_engine);
596
597int ahci_stop_engine(struct ata_port *ap)
598{
599 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 600 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 601 u32 tmp;
602
fb329633
DP		 603 /*
604 * On some controllers, stopping a port's DMA engine while the port
605 * is in ALPM state (partial or slumber) results in failures on
606 * subsequent DMA engine starts. For those controllers, put the
607 * port back in active state before stopping its DMA engine.
608 */
609 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
610 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
611 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
612 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
613 return -EIO;
614 }
615
365cfa1e
AV		 616 tmp = readl(port_mmio + PORT_CMD);
617
618 /* check if the HBA is idle */
619 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
620 return 0;
621
622 /* setting HBA to idle */
623 tmp &= ~PORT_CMD_START;
624 writel(tmp, port_mmio + PORT_CMD);
625
626 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 627 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 628 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
629 if (tmp & PORT_CMD_LIST_ON)
630 return -EIO;
631
632 return 0;
633}
634EXPORT_SYMBOL_GPL(ahci_stop_engine);
635
39e0ee99 636void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 637{
638 void __iomem *port_mmio = ahci_port_base(ap);
639 struct ahci_host_priv *hpriv = ap->host->private_data;
640 struct ahci_port_priv *pp = ap->private_data;
641 u32 tmp;
642
643 /* set FIS registers */
644 if (hpriv->cap & HOST_CAP_64)
645 writel((pp->cmd_slot_dma >> 16) >> 16,
646 port_mmio + PORT_LST_ADDR_HI);
647 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
648
649 if (hpriv->cap & HOST_CAP_64)
650 writel((pp->rx_fis_dma >> 16) >> 16,
651 port_mmio + PORT_FIS_ADDR_HI);
652 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
653
654 /* enable FIS reception */
655 tmp = readl(port_mmio + PORT_CMD);
656 tmp |= PORT_CMD_FIS_RX;
657 writel(tmp, port_mmio + PORT_CMD);
658
659 /* flush */
660 readl(port_mmio + PORT_CMD);
661}
39e0ee99 662EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 663
664static int ahci_stop_fis_rx(struct ata_port *ap)
665{
666 void __iomem *port_mmio = ahci_port_base(ap);
667 u32 tmp;
668
669 /* disable FIS reception */
670 tmp = readl(port_mmio + PORT_CMD);
671 tmp &= ~PORT_CMD_FIS_RX;
672 writel(tmp, port_mmio + PORT_CMD);
673
674 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 675 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 676 PORT_CMD_FIS_ON, 10, 1000);
677 if (tmp & PORT_CMD_FIS_ON)
678 return -EBUSY;
679
680 return 0;
681}
682
683static void ahci_power_up(struct ata_port *ap)
684{
685 struct ahci_host_priv *hpriv = ap->host->private_data;
686 void __iomem *port_mmio = ahci_port_base(ap);
687 u32 cmd;
688
689 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
690
691 /* spin up device */
692 if (hpriv->cap & HOST_CAP_SSS) {
693 cmd |= PORT_CMD_SPIN_UP;
694 writel(cmd, port_mmio + PORT_CMD);
695 }
696
697 /* wake up link */
698 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
699}
700
6b7ae954
TH		 701static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
702 unsigned int hints)
365cfa1e 703{
6b7ae954 704 struct ata_port *ap = link->ap;
365cfa1e 705 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 706 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 707 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 708
6b7ae954 709 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 710 /* wakeup flag only applies to the max power policy */
711 hints &= ~ATA_LPM_WAKE_ONLY;
712
365cfa1e 713 /*
6b7ae954
TH		 714 * Disable interrupts on Phy Ready. This keeps us from
715 * getting woken up due to spurious phy ready
716 * interrupts.
365cfa1e 717 */
6b7ae954
TH		 718 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
719 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
720
721 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 722 }
723
6b7ae954
TH		 724 if (hpriv->cap & HOST_CAP_ALPM) {
725 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 726
6b7ae954 727 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 728 if (!(hints & ATA_LPM_WAKE_ONLY))
729 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 730 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 731
6b7ae954
TH		 732 writel(cmd, port_mmio + PORT_CMD);
733 readl(port_mmio + PORT_CMD);
365cfa1e 734
6b7ae954 735 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 736 ata_msleep(ap, 10);
fb329633
DP		 737
738 if (hints & ATA_LPM_WAKE_ONLY)
739 return 0;
6b7ae954
TH		 740 } else {
741 cmd |= PORT_CMD_ALPE;
742 if (policy == ATA_LPM_MIN_POWER)
743 cmd |= PORT_CMD_ASP;
365cfa1e 744
6b7ae954
TH		 745 /* write out new cmd value */
746 writel(cmd, port_mmio + PORT_CMD);
747 }
748 }
365cfa1e 749
65fe1f0f
SH		 750 /* set aggressive device sleep */
751 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
752 (hpriv->cap2 & HOST_CAP2_SADM) &&
753 (link->device->flags & ATA_DFLAG_DEVSLP)) {
754 if (policy == ATA_LPM_MIN_POWER)
755 ahci_set_aggressive_devslp(ap, true);
756 else
757 ahci_set_aggressive_devslp(ap, false);
758 }
759
6b7ae954
TH		 760 if (policy == ATA_LPM_MAX_POWER) {
761 sata_link_scr_lpm(link, policy, false);
762
763 /* turn PHYRDY IRQ back on */
764 pp->intr_mask |= PORT_IRQ_PHYRDY;
765 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
766 }
365cfa1e 767
365cfa1e
AV		 768 return 0;
769}
770
771#ifdef CONFIG_PM
772static void ahci_power_down(struct ata_port *ap)
773{
774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 void __iomem *port_mmio = ahci_port_base(ap);
776 u32 cmd, scontrol;
777
778 if (!(hpriv->cap & HOST_CAP_SSS))
779 return;
780
781 /* put device into listen mode, first set PxSCTL.DET to 0 */
782 scontrol = readl(port_mmio + PORT_SCR_CTL);
783 scontrol &= ~0xf;
784 writel(scontrol, port_mmio + PORT_SCR_CTL);
785
786 /* then set PxCMD.SUD to 0 */
787 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
788 cmd &= ~PORT_CMD_SPIN_UP;
789 writel(cmd, port_mmio + PORT_CMD);
790}
791#endif
792
793static void ahci_start_port(struct ata_port *ap)
794{
66583c9f 795 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 796 struct ahci_port_priv *pp = ap->private_data;
797 struct ata_link *link;
798 struct ahci_em_priv *emp;
799 ssize_t rc;
800 int i;
801
802 /* enable FIS reception */
803 ahci_start_fis_rx(ap);
804
66583c9f
BN		 805 /* enable DMA */
806 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 807 hpriv->start_engine(ap);
66583c9f 808
365cfa1e
AV		 809 /* turn on LEDs */
810 if (ap->flags & ATA_FLAG_EM) {
811 ata_for_each_link(link, ap, EDGE) {
812 emp = &pp->em_priv[link->pmp];
813
814 /* EM Transmit bit maybe busy during init */
815 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 816 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 817 emp->led_state,
818 4);
fa070ee6
LD		 819 /*
820 * If busy, give a breather but do not
821 * release EH ownership by using msleep()
822 * instead of ata_msleep(). EM Transmit
823 * bit is busy for the whole host and
824 * releasing ownership will cause other
825 * ports to fail the same way.
826 */
365cfa1e 827 if (rc == -EBUSY)
fa070ee6 828 msleep(1);
365cfa1e
AV		 829 else
830 break;
831 }
832 }
833 }
834
835 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
836 ata_for_each_link(link, ap, EDGE)
837 ahci_init_sw_activity(link);
838
839}
840
841static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
842{
843 int rc;
844
845 /* disable DMA */
846 rc = ahci_stop_engine(ap);
847 if (rc) {
848 *emsg = "failed to stop engine";
849 return rc;
850 }
851
852 /* disable FIS reception */
853 rc = ahci_stop_fis_rx(ap);
854 if (rc) {
855 *emsg = "failed stop FIS RX";
856 return rc;
857 }
858
859 return 0;
860}
861
862int ahci_reset_controller(struct ata_host *host)
863{
864 struct ahci_host_priv *hpriv = host->private_data;
865 void __iomem *mmio = hpriv->mmio;
866 u32 tmp;
867
868 /* we must be in AHCI mode, before using anything
869 * AHCI-specific, such as HOST_RESET.
870 */
871 ahci_enable_ahci(mmio);
872
873 /* global controller reset */
874 if (!ahci_skip_host_reset) {
875 tmp = readl(mmio + HOST_CTL);
876 if ((tmp & HOST_RESET) == 0) {
877 writel(tmp | HOST_RESET, mmio + HOST_CTL);
878 readl(mmio + HOST_CTL); /* flush */
879 }
880
881 /*
882 * to perform host reset, OS should set HOST_RESET
883 * and poll until this bit is read to be "0".
884 * reset must complete within 1 second, or
885 * the hardware should be considered fried.
886 */
97750ceb 887 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 888 HOST_RESET, 10, 1000);
889
890 if (tmp & HOST_RESET) {
a44fec1f
JP		 891 dev_err(host->dev, "controller reset failed (0x%x)\n",
892 tmp);
365cfa1e
AV		 893 return -EIO;
894 }
895
896 /* turn on AHCI mode */
897 ahci_enable_ahci(mmio);
898
899 /* Some registers might be cleared on reset. Restore
900 * initial values.
901 */
902 ahci_restore_initial_config(host);
903 } else
a44fec1f 904 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 905
906 return 0;
907}
908EXPORT_SYMBOL_GPL(ahci_reset_controller);
909
910static void ahci_sw_activity(struct ata_link *link)
911{
912 struct ata_port *ap = link->ap;
913 struct ahci_port_priv *pp = ap->private_data;
914 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
915
916 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
917 return;
918
919 emp->activity++;
920 if (!timer_pending(&emp->timer))
921 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
922}
923
924static void ahci_sw_activity_blink(unsigned long arg)
925{
926 struct ata_link *link = (struct ata_link *)arg;
927 struct ata_port *ap = link->ap;
928 struct ahci_port_priv *pp = ap->private_data;
929 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
930 unsigned long led_message = emp->led_state;
931 u32 activity_led_state;
932 unsigned long flags;
933
934 led_message &= EM_MSG_LED_VALUE;
935 led_message |= ap->port_no | (link->pmp << 8);
936
937 /* check to see if we've had activity. If so,
938 * toggle state of LED and reset timer. If not,
939 * turn LED to desired idle state.
940 */
941 spin_lock_irqsave(ap->lock, flags);
942 if (emp->saved_activity != emp->activity) {
943 emp->saved_activity = emp->activity;
944 /* get the current LED state */
945 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
946
947 if (activity_led_state)
948 activity_led_state = 0;
949 else
950 activity_led_state = 1;
951
952 /* clear old state */
953 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
954
955 /* toggle state */
956 led_message |= (activity_led_state << 16);
957 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
958 } else {
959 /* switch to idle */
960 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
961 if (emp->blink_policy == BLINK_OFF)
962 led_message |= (1 << 16);
963 }
964 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 965 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 966}
967
968static void ahci_init_sw_activity(struct ata_link *link)
969{
970 struct ata_port *ap = link->ap;
971 struct ahci_port_priv *pp = ap->private_data;
972 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
973
974 /* init activity stats, setup timer */
975 emp->saved_activity = emp->activity = 0;
976 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
977
978 /* check our blink policy and set flag for link if it's enabled */
979 if (emp->blink_policy)
980 link->flags |= ATA_LFLAG_SW_ACTIVITY;
981}
982
983int ahci_reset_em(struct ata_host *host)
984{
985 struct ahci_host_priv *hpriv = host->private_data;
986 void __iomem *mmio = hpriv->mmio;
987 u32 em_ctl;
988
989 em_ctl = readl(mmio + HOST_EM_CTL);
990 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
991 return -EINVAL;
992
993 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
994 return 0;
995}
996EXPORT_SYMBOL_GPL(ahci_reset_em);
997
998static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
999 ssize_t size)
1000{
1001 struct ahci_host_priv *hpriv = ap->host->private_data;
1002 struct ahci_port_priv *pp = ap->private_data;
1003 void __iomem *mmio = hpriv->mmio;
1004 u32 em_ctl;
1005 u32 message[] = {0, 0};
1006 unsigned long flags;
1007 int pmp;
1008 struct ahci_em_priv *emp;
1009
1010 /* get the slot number from the message */
1011 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1012 if (pmp < EM_MAX_SLOTS)
1013 emp = &pp->em_priv[pmp];
1014 else
1015 return -EINVAL;
1016
1017 spin_lock_irqsave(ap->lock, flags);
1018
1019 /*
1020 * if we are still busy transmitting a previous message,
1021 * do not allow
1022 */
1023 em_ctl = readl(mmio + HOST_EM_CTL);
1024 if (em_ctl & EM_CTL_TM) {
1025 spin_unlock_irqrestore(ap->lock, flags);
1026 return -EBUSY;
1027 }
1028
008dbd61
HZ		 1029 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1030 /*
1031 * create message header - this is all zero except for
1032 * the message size, which is 4 bytes.
1033 */
1034 message[0] |= (4 << 8);
365cfa1e 1035
008dbd61
HZ		 1036 /* ignore 0:4 of byte zero, fill in port info yourself */
1037 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1038
008dbd61
HZ		 1039 /* write message to EM_LOC */
1040 writel(message[0], mmio + hpriv->em_loc);
1041 writel(message[1], mmio + hpriv->em_loc+4);
1042
1043 /*
1044 * tell hardware to transmit the message
1045 */
1046 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1047 }
365cfa1e
AV		 1048
1049 /* save off new led state for port/slot */
1050 emp->led_state = state;
1051
365cfa1e
AV		 1052 spin_unlock_irqrestore(ap->lock, flags);
1053 return size;
1054}
1055
1056static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1057{
1058 struct ahci_port_priv *pp = ap->private_data;
1059 struct ata_link *link;
1060 struct ahci_em_priv *emp;
1061 int rc = 0;
1062
1063 ata_for_each_link(link, ap, EDGE) {
1064 emp = &pp->em_priv[link->pmp];
1065 rc += sprintf(buf, "%lx\n", emp->led_state);
1066 }
1067 return rc;
1068}
1069
1070static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1071 size_t size)
1072{
b2a52b6a 1073 unsigned int state;
365cfa1e
AV		 1074 int pmp;
1075 struct ahci_port_priv *pp = ap->private_data;
1076 struct ahci_em_priv *emp;
1077
b2a52b6a
DY		 1078 if (kstrtouint(buf, 0, &state) < 0)
1079 return -EINVAL;
365cfa1e
AV		 1080
1081 /* get the slot number from the message */
1082 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1083 if (pmp < EM_MAX_SLOTS)
1084 emp = &pp->em_priv[pmp];
1085 else
1086 return -EINVAL;
1087
1088 /* mask off the activity bits if we are in sw_activity
1089 * mode, user should turn off sw_activity before setting
1090 * activity led through em_message
1091 */
1092 if (emp->blink_policy)
1093 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1094
439d7a35 1095 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1096}
1097
1098static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1099{
1100 struct ata_link *link = dev->link;
1101 struct ata_port *ap = link->ap;
1102 struct ahci_port_priv *pp = ap->private_data;
1103 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1104 u32 port_led_state = emp->led_state;
1105
1106 /* save the desired Activity LED behavior */
1107 if (val == OFF) {
1108 /* clear LFLAG */
1109 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1110
1111 /* set the LED to OFF */
1112 port_led_state &= EM_MSG_LED_VALUE_OFF;
1113 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1114 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1115 } else {
1116 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1117 if (val == BLINK_OFF) {
1118 /* set LED to ON for idle */
1119 port_led_state &= EM_MSG_LED_VALUE_OFF;
1120 port_led_state |= (ap->port_no | (link->pmp << 8));
1121 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1122 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1123 }
1124 }
1125 emp->blink_policy = val;
1126 return 0;
1127}
1128
1129static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1130{
1131 struct ata_link *link = dev->link;
1132 struct ata_port *ap = link->ap;
1133 struct ahci_port_priv *pp = ap->private_data;
1134 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1135
1136 /* display the saved value of activity behavior for this
1137 * disk.
1138 */
1139 return sprintf(buf, "%d\n", emp->blink_policy);
1140}
1141
1142static void ahci_port_init(struct device *dev, struct ata_port *ap,
1143 int port_no, void __iomem *mmio,
1144 void __iomem *port_mmio)
1145{
8a3e33cf 1146 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1147 const char *emsg = NULL;
1148 int rc;
1149 u32 tmp;
1150
1151 /* make sure port is not active */
1152 rc = ahci_deinit_port(ap, &emsg);
1153 if (rc)
1154 dev_warn(dev, "%s (%d)\n", emsg, rc);
1155
1156 /* clear SError */
1157 tmp = readl(port_mmio + PORT_SCR_ERR);
1158 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1159 writel(tmp, port_mmio + PORT_SCR_ERR);
1160
1161 /* clear port IRQ */
1162 tmp = readl(port_mmio + PORT_IRQ_STAT);
1163 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1164 if (tmp)
1165 writel(tmp, port_mmio + PORT_IRQ_STAT);
1166
1167 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1168
1169 /* mark esata ports */
1170 tmp = readl(port_mmio + PORT_CMD);
1171 if ((tmp & PORT_CMD_HPCP) ||
1172 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
1173 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1174}
1175
1176void ahci_init_controller(struct ata_host *host)
1177{
1178 struct ahci_host_priv *hpriv = host->private_data;
1179 void __iomem *mmio = hpriv->mmio;
1180 int i;
1181 void __iomem *port_mmio;
1182 u32 tmp;
1183
1184 for (i = 0; i < host->n_ports; i++) {
1185 struct ata_port *ap = host->ports[i];
1186
1187 port_mmio = ahci_port_base(ap);
1188 if (ata_port_is_dummy(ap))
1189 continue;
1190
1191 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1192 }
1193
1194 tmp = readl(mmio + HOST_CTL);
1195 VPRINTK("HOST_CTL 0x%x\n", tmp);
1196 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1197 tmp = readl(mmio + HOST_CTL);
1198 VPRINTK("HOST_CTL 0x%x\n", tmp);
1199}
1200EXPORT_SYMBOL_GPL(ahci_init_controller);
1201
1202static void ahci_dev_config(struct ata_device *dev)
1203{
1204 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1205
1206 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1207 dev->max_sectors = 255;
a9a79dfe
JP		 1208 ata_dev_info(dev,
1209 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1210 }
1211}
1212
bbb4ab43 1213unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1214{
1215 void __iomem *port_mmio = ahci_port_base(ap);
1216 struct ata_taskfile tf;
1217 u32 tmp;
1218
1219 tmp = readl(port_mmio + PORT_SIG);
1220 tf.lbah = (tmp >> 24) & 0xff;
1221 tf.lbam = (tmp >> 16) & 0xff;
1222 tf.lbal = (tmp >> 8) & 0xff;
1223 tf.nsect = (tmp) & 0xff;
1224
1225 return ata_dev_classify(&tf);
1226}
bbb4ab43 1227EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1228
02cdfcf0
DM		 1229void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1230 u32 opts)
365cfa1e
AV		 1231{
1232 dma_addr_t cmd_tbl_dma;
1233
1234 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1235
1236 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1237 pp->cmd_slot[tag].status = 0;
1238 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1239 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1240}
02cdfcf0 1241EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1242
1243int ahci_kick_engine(struct ata_port *ap)
1244{
1245 void __iomem *port_mmio = ahci_port_base(ap);
1246 struct ahci_host_priv *hpriv = ap->host->private_data;
1247 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1248 u32 tmp;
1249 int busy, rc;
1250
1251 /* stop engine */
1252 rc = ahci_stop_engine(ap);
1253 if (rc)
1254 goto out_restart;
1255
1256 /* need to do CLO?
1257 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1258 */
1259 busy = status & (ATA_BUSY | ATA_DRQ);
1260 if (!busy && !sata_pmp_attached(ap)) {
1261 rc = 0;
1262 goto out_restart;
1263 }
1264
1265 if (!(hpriv->cap & HOST_CAP_CLO)) {
1266 rc = -EOPNOTSUPP;
1267 goto out_restart;
1268 }
1269
1270 /* perform CLO */
1271 tmp = readl(port_mmio + PORT_CMD);
1272 tmp |= PORT_CMD_CLO;
1273 writel(tmp, port_mmio + PORT_CMD);
1274
1275 rc = 0;
97750ceb 1276 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1277 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1278 if (tmp & PORT_CMD_CLO)
1279 rc = -EIO;
1280
1281 /* restart engine */
1282 out_restart:
039ece38 1283 hpriv->start_engine(ap);
365cfa1e
AV		 1284 return rc;
1285}
1286EXPORT_SYMBOL_GPL(ahci_kick_engine);
1287
1288static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1289 struct ata_taskfile *tf, int is_cmd, u16 flags,
1290 unsigned long timeout_msec)
1291{
1292 const u32 cmd_fis_len = 5; /* five dwords */
1293 struct ahci_port_priv *pp = ap->private_data;
1294 void __iomem *port_mmio = ahci_port_base(ap);
1295 u8 *fis = pp->cmd_tbl;
1296 u32 tmp;
1297
1298 /* prep the command */
1299 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1300 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1301
023113d2
XY		 1302 /* set port value for softreset of Port Multiplier */
1303 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1304 tmp = readl(port_mmio + PORT_FBS);
1305 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1306 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1307 writel(tmp, port_mmio + PORT_FBS);
1308 pp->fbs_last_dev = pmp;
1309 }
1310
365cfa1e
AV		 1311 /* issue & wait */
1312 writel(1, port_mmio + PORT_CMD_ISSUE);
1313
1314 if (timeout_msec) {
97750ceb
TH		 1315 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1316 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1317 if (tmp & 0x1) {
1318 ahci_kick_engine(ap);
1319 return -EBUSY;
1320 }
1321 } else
1322 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1323
1324 return 0;
1325}
1326
1327int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1328 int pmp, unsigned long deadline,
1329 int (*check_ready)(struct ata_link *link))
1330{
1331 struct ata_port *ap = link->ap;
1332 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1333 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1334 const char *reason = NULL;
1335 unsigned long now, msecs;
1336 struct ata_taskfile tf;
89dafa20 1337 bool fbs_disabled = false;
365cfa1e
AV		 1338 int rc;
1339
1340 DPRINTK("ENTER\n");
1341
1342 /* prepare for SRST (AHCI-1.1 10.4.1) */
1343 rc = ahci_kick_engine(ap);
1344 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1345 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1346
89dafa20 1347 /*
1348 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1349 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1350 * that is attached to port multiplier.
1351 */
1352 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1353 ahci_disable_fbs(ap);
1354 fbs_disabled = true;
1355 }
1356
365cfa1e
AV		 1357 ata_tf_init(link->device, &tf);
1358
1359 /* issue the first D2H Register FIS */
1360 msecs = 0;
1361 now = jiffies;
f1f5a807 1362 if (time_after(deadline, now))
365cfa1e
AV		 1363 msecs = jiffies_to_msecs(deadline - now);
1364
1365 tf.ctl |= ATA_SRST;
1366 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1367 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1368 rc = -EIO;
1369 reason = "1st FIS failed";
1370 goto fail;
1371 }
1372
1373 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1374 ata_msleep(ap, 1);
365cfa1e
AV		 1375
1376 /* issue the second D2H Register FIS */
1377 tf.ctl &= ~ATA_SRST;
1378 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1379
1380 /* wait for link to become ready */
1381 rc = ata_wait_after_reset(link, deadline, check_ready);
1382 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1383 /*
1384 * Workaround for cases where link online status can't
1385 * be trusted. Treat device readiness timeout as link
1386 * offline.
1387 */
a9a79dfe 1388 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1389 *class = ATA_DEV_NONE;
1390 } else if (rc) {
1391 /* link occupied, -ENODEV too is an error */
1392 reason = "device not ready";
1393 goto fail;
1394 } else
1395 *class = ahci_dev_classify(ap);
1396
89dafa20 1397 /* re-enable FBS if disabled before */
1398 if (fbs_disabled)
1399 ahci_enable_fbs(ap);
1400
365cfa1e
AV		 1401 DPRINTK("EXIT, class=%u\n", *class);
1402 return 0;
1403
1404 fail:
a9a79dfe 1405 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1406 return rc;
1407}
1408
1409int ahci_check_ready(struct ata_link *link)
1410{
1411 void __iomem *port_mmio = ahci_port_base(link->ap);
1412 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1413
1414 return ata_check_ready(status);
1415}
1416EXPORT_SYMBOL_GPL(ahci_check_ready);
1417
1418static int ahci_softreset(struct ata_link *link, unsigned int *class,
1419 unsigned long deadline)
1420{
1421 int pmp = sata_srst_pmp(link);
1422
1423 DPRINTK("ENTER\n");
1424
1425 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1426}
1427EXPORT_SYMBOL_GPL(ahci_do_softreset);
1428
345347c5
YHC		 1429static int ahci_bad_pmp_check_ready(struct ata_link *link)
1430{
1431 void __iomem *port_mmio = ahci_port_base(link->ap);
1432 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1433 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1434
1435 /*
1436 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1437 * which can save timeout delay.
1438 */
1439 if (irq_status & PORT_IRQ_BAD_PMP)
1440 return -EIO;
1441
1442 return ata_check_ready(status);
1443}
1444
35186d05
DY		 1445static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1446 unsigned long deadline)
345347c5
YHC		 1447{
1448 struct ata_port *ap = link->ap;
1449 void __iomem *port_mmio = ahci_port_base(ap);
1450 int pmp = sata_srst_pmp(link);
1451 int rc;
1452 u32 irq_sts;
1453
1454 DPRINTK("ENTER\n");
1455
1456 rc = ahci_do_softreset(link, class, pmp, deadline,
1457 ahci_bad_pmp_check_ready);
1458
1459 /*
1460 * Soft reset fails with IPMS set when PMP is enabled but
1461 * SATA HDD/ODD is connected to SATA port, do soft reset
1462 * again to port 0.
1463 */
1464 if (rc == -EIO) {
1465 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1466 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1467 ata_link_warn(link,
345347c5
YHC		 1468 "applying PMP SRST workaround "
1469 "and retrying\n");
1470 rc = ahci_do_softreset(link, class, 0, deadline,
1471 ahci_check_ready);
1472 }
1473 }
1474
1475 return rc;
1476}
1477
365cfa1e
AV		 1478static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1479 unsigned long deadline)
1480{
1481 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1482 struct ata_port *ap = link->ap;
1483 struct ahci_port_priv *pp = ap->private_data;
039ece38 1484 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1485 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1486 struct ata_taskfile tf;
1487 bool online;
1488 int rc;
1489
1490 DPRINTK("ENTER\n");
1491
1492 ahci_stop_engine(ap);
1493
1494 /* clear D2H reception area to properly wait for D2H FIS */
1495 ata_tf_init(link->device, &tf);
9bbb1b0e 1496 tf.command = ATA_BUSY;
365cfa1e
AV		 1497 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1498
1499 rc = sata_link_hardreset(link, timing, deadline, &online,
1500 ahci_check_ready);
1501
039ece38 1502 hpriv->start_engine(ap);
365cfa1e
AV		 1503
1504 if (online)
1505 *class = ahci_dev_classify(ap);
1506
1507 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1508 return rc;
1509}
1510
1511static void ahci_postreset(struct ata_link *link, unsigned int *class)
1512{
1513 struct ata_port *ap = link->ap;
1514 void __iomem *port_mmio = ahci_port_base(ap);
1515 u32 new_tmp, tmp;
1516
1517 ata_std_postreset(link, class);
1518
1519 /* Make sure port's ATAPI bit is set appropriately */
1520 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1521 if (*class == ATA_DEV_ATAPI)
1522 new_tmp |= PORT_CMD_ATAPI;
1523 else
1524 new_tmp &= ~PORT_CMD_ATAPI;
1525 if (new_tmp != tmp) {
1526 writel(new_tmp, port_mmio + PORT_CMD);
1527 readl(port_mmio + PORT_CMD); /* flush */
1528 }
1529}
1530
1531static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1532{
1533 struct scatterlist *sg;
1534 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1535 unsigned int si;
1536
1537 VPRINTK("ENTER\n");
1538
1539 /*
1540 * Next, the S/G list.
1541 */
1542 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1543 dma_addr_t addr = sg_dma_address(sg);
1544 u32 sg_len = sg_dma_len(sg);
1545
1546 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1547 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1548 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1549 }
1550
1551 return si;
1552}
1553
1554static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1555{
1556 struct ata_port *ap = qc->ap;
1557 struct ahci_port_priv *pp = ap->private_data;
1558
1559 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1560 return ata_std_qc_defer(qc);
1561 else
1562 return sata_pmp_qc_defer_cmd_switch(qc);
1563}
1564
1565static void ahci_qc_prep(struct ata_queued_cmd *qc)
1566{
1567 struct ata_port *ap = qc->ap;
1568 struct ahci_port_priv *pp = ap->private_data;
1569 int is_atapi = ata_is_atapi(qc->tf.protocol);
1570 void *cmd_tbl;
1571 u32 opts;
1572 const u32 cmd_fis_len = 5; /* five dwords */
1573 unsigned int n_elem;
1574
1575 /*
1576 * Fill in command table information. First, the header,
1577 * a SATA Register - Host to Device command FIS.
1578 */
1579 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1580
1581 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1582 if (is_atapi) {
1583 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1584 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1585 }
1586
1587 n_elem = 0;
1588 if (qc->flags & ATA_QCFLAG_DMAMAP)
1589 n_elem = ahci_fill_sg(qc, cmd_tbl);
1590
1591 /*
1592 * Fill in command slot information.
1593 */
1594 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1595 if (qc->tf.flags & ATA_TFLAG_WRITE)
1596 opts |= AHCI_CMD_WRITE;
1597 if (is_atapi)
1598 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1599
1600 ahci_fill_cmd_slot(pp, qc->tag, opts);
1601}
1602
1603static void ahci_fbs_dec_intr(struct ata_port *ap)
1604{
1605 struct ahci_port_priv *pp = ap->private_data;
1606 void __iomem *port_mmio = ahci_port_base(ap);
1607 u32 fbs = readl(port_mmio + PORT_FBS);
1608 int retries = 3;
1609
1610 DPRINTK("ENTER\n");
1611 BUG_ON(!pp->fbs_enabled);
1612
1613 /* time to wait for DEC is not specified by AHCI spec,
1614 * add a retry loop for safety.
1615 */
1616 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1617 fbs = readl(port_mmio + PORT_FBS);
1618 while ((fbs & PORT_FBS_DEC) && retries--) {
1619 udelay(1);
1620 fbs = readl(port_mmio + PORT_FBS);
1621 }
1622
1623 if (fbs & PORT_FBS_DEC)
a44fec1f 1624 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1625}
1626
1627static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1628{
1629 struct ahci_host_priv *hpriv = ap->host->private_data;
1630 struct ahci_port_priv *pp = ap->private_data;
1631 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1632 struct ata_link *link = NULL;
1633 struct ata_queued_cmd *active_qc;
1634 struct ata_eh_info *active_ehi;
1635 bool fbs_need_dec = false;
1636 u32 serror;
1637
1638 /* determine active link with error */
1639 if (pp->fbs_enabled) {
1640 void __iomem *port_mmio = ahci_port_base(ap);
1641 u32 fbs = readl(port_mmio + PORT_FBS);
1642 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1643
912b9ac6 1644 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1645 link = &ap->pmp_link[pmp];
1646 fbs_need_dec = true;
1647 }
1648
1649 } else
1650 ata_for_each_link(link, ap, EDGE)
1651 if (ata_link_active(link))
1652 break;
1653
1654 if (!link)
1655 link = &ap->link;
1656
1657 active_qc = ata_qc_from_tag(ap, link->active_tag);
1658 active_ehi = &link->eh_info;
1659
1660 /* record irq stat */
1661 ata_ehi_clear_desc(host_ehi);
1662 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1663
1664 /* AHCI needs SError cleared; otherwise, it might lock up */
1665 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1666 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1667 host_ehi->serror |= serror;
1668
1669 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1670 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1671 irq_stat &= ~PORT_IRQ_IF_ERR;
1672
1673 if (irq_stat & PORT_IRQ_TF_ERR) {
1674 /* If qc is active, charge it; otherwise, the active
1675 * link. There's no active qc on NCQ errors. It will
1676 * be determined by EH by reading log page 10h.
1677 */
1678 if (active_qc)
1679 active_qc->err_mask |= AC_ERR_DEV;
1680 else
1681 active_ehi->err_mask |= AC_ERR_DEV;
1682
1683 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1684 host_ehi->serror &= ~SERR_INTERNAL;
1685 }
1686
1687 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1688 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1689
1690 active_ehi->err_mask |= AC_ERR_HSM;
1691 active_ehi->action |= ATA_EH_RESET;
1692 ata_ehi_push_desc(active_ehi,
1693 "unknown FIS %08x %08x %08x %08x" ,
1694 unk[0], unk[1], unk[2], unk[3]);
1695 }
1696
1697 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1698 active_ehi->err_mask |= AC_ERR_HSM;
1699 active_ehi->action |= ATA_EH_RESET;
1700 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1701 }
1702
1703 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1704 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1705 host_ehi->action |= ATA_EH_RESET;
1706 ata_ehi_push_desc(host_ehi, "host bus error");
1707 }
1708
1709 if (irq_stat & PORT_IRQ_IF_ERR) {
1710 if (fbs_need_dec)
1711 active_ehi->err_mask |= AC_ERR_DEV;
1712 else {
1713 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1714 host_ehi->action |= ATA_EH_RESET;
1715 }
1716
1717 ata_ehi_push_desc(host_ehi, "interface fatal error");
1718 }
1719
1720 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1721 ata_ehi_hotplugged(host_ehi);
1722 ata_ehi_push_desc(host_ehi, "%s",
1723 irq_stat & PORT_IRQ_CONNECT ?
1724 "connection status changed" : "PHY RDY changed");
1725 }
1726
1727 /* okay, let's hand over to EH */
1728
1729 if (irq_stat & PORT_IRQ_FREEZE)
1730 ata_port_freeze(ap);
1731 else if (fbs_need_dec) {
1732 ata_link_abort(link);
1733 ahci_fbs_dec_intr(ap);
1734 } else
1735 ata_port_abort(ap);
1736}
1737
5ca72c4f
AG		 1738static void ahci_handle_port_interrupt(struct ata_port *ap,
1739 void __iomem *port_mmio, u32 status)
365cfa1e 1740{
365cfa1e
AV		 1741 struct ata_eh_info *ehi = &ap->link.eh_info;
1742 struct ahci_port_priv *pp = ap->private_data;
1743 struct ahci_host_priv *hpriv = ap->host->private_data;
1744 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1745 u32 qc_active = 0;
365cfa1e
AV		 1746 int rc;
1747
365cfa1e
AV		 1748 /* ignore BAD_PMP while resetting */
1749 if (unlikely(resetting))
1750 status &= ~PORT_IRQ_BAD_PMP;
1751
8393b811 1752 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1753 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1754 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1755 }
1756
1757 if (unlikely(status & PORT_IRQ_ERROR)) {
1758 ahci_error_intr(ap, status);
1759 return;
1760 }
1761
1762 if (status & PORT_IRQ_SDB_FIS) {
1763 /* If SNotification is available, leave notification
1764 * handling to sata_async_notification(). If not,
1765 * emulate it by snooping SDB FIS RX area.
1766 *
1767 * Snooping FIS RX area is probably cheaper than
1768 * poking SNotification but some constrollers which
1769 * implement SNotification, ICH9 for example, don't
1770 * store AN SDB FIS into receive area.
1771 */
1772 if (hpriv->cap & HOST_CAP_SNTF)
1773 sata_async_notification(ap);
1774 else {
1775 /* If the 'N' bit in word 0 of the FIS is set,
1776 * we just received asynchronous notification.
1777 * Tell libata about it.
1778 *
1779 * Lack of SNotification should not appear in
1780 * ahci 1.2, so the workaround is unnecessary
1781 * when FBS is enabled.
1782 */
1783 if (pp->fbs_enabled)
1784 WARN_ON_ONCE(1);
1785 else {
1786 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1787 u32 f0 = le32_to_cpu(f[0]);
1788 if (f0 & (1 << 15))
1789 sata_async_notification(ap);
1790 }
1791 }
1792 }
1793
1794 /* pp->active_link is not reliable once FBS is enabled, both
1795 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1796 * NCQ and non-NCQ commands may be in flight at the same time.
1797 */
1798 if (pp->fbs_enabled) {
1799 if (ap->qc_active) {
1800 qc_active = readl(port_mmio + PORT_SCR_ACT);
1801 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1802 }
1803 } else {
1804 /* pp->active_link is valid iff any command is in flight */
1805 if (ap->qc_active && pp->active_link->sactive)
1806 qc_active = readl(port_mmio + PORT_SCR_ACT);
1807 else
1808 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1809 }
1810
1811
1812 rc = ata_qc_complete_multiple(ap, qc_active);
1813
1814 /* while resetting, invalid completions are expected */
1815 if (unlikely(rc < 0 && !resetting)) {
1816 ehi->err_mask |= AC_ERR_HSM;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1819 }
1820}
1821
7865f83f 1822static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1823{
1824 void __iomem *port_mmio = ahci_port_base(ap);
1825 u32 status;
1826
1827 status = readl(port_mmio + PORT_IRQ_STAT);
1828 writel(status, port_mmio + PORT_IRQ_STAT);
1829
7865f83f 1830 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1831}
1832
a6b7fb76 1833static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1834{
1835 struct ata_port *ap = dev_instance;
5ca72c4f 1836 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1837 u32 status;
1838
5ca72c4f
AG		 1839 VPRINTK("ENTER\n");
1840
227dfb4d
AG		 1841 status = readl(port_mmio + PORT_IRQ_STAT);
1842 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1843
a6b7fb76
DW		 1844 spin_lock(ap->lock);
1845 ahci_handle_port_interrupt(ap, port_mmio, status);
1846 spin_unlock(ap->lock);
5ca72c4f
AG		 1847
1848 VPRINTK("EXIT\n");
1849
a6b7fb76 1850 return IRQ_HANDLED;
5ca72c4f 1851}
5ca72c4f 1852
f070d671 1853u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1854{
365cfa1e 1855 unsigned int i, handled = 0;
03e83cbd 1856
365cfa1e
AV		 1857 for (i = 0; i < host->n_ports; i++) {
1858 struct ata_port *ap;
1859
1860 if (!(irq_masked & (1 << i)))
1861 continue;
1862
1863 ap = host->ports[i];
1864 if (ap) {
7865f83f 1865 ahci_port_intr(ap);
365cfa1e
AV		 1866 VPRINTK("port %u\n", i);
1867 } else {
1868 VPRINTK("port %u (no irq)\n", i);
1869 if (ata_ratelimit())
a44fec1f
JP		 1870 dev_warn(host->dev,
1871 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1872 }
1873
1874 handled = 1;
1875 }
1876
a129db89
ST		 1877 return handled;
1878}
f070d671 1879EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1880
1881static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1882{
1883 struct ata_host *host = dev_instance;
1884 struct ahci_host_priv *hpriv;
1885 unsigned int rc = 0;
1886 void __iomem *mmio;
1887 u32 irq_stat, irq_masked;
1888
1889 VPRINTK("ENTER\n");
1890
1891 hpriv = host->private_data;
1892 mmio = hpriv->mmio;
1893
1894 /* sigh. 0xffffffff is a valid return from h/w */
1895 irq_stat = readl(mmio + HOST_IRQ_STAT);
1896 if (!irq_stat)
1897 return IRQ_NONE;
1898
1899 irq_masked = irq_stat & hpriv->port_map;
1900
1901 spin_lock(&host->lock);
1902
1903 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1904
1905 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1906 * it should be cleared after all the port events are cleared;
1907 * otherwise, it will raise a spurious interrupt after each
1908 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1909 * information.
1910 *
1911 * Also, use the unmasked value to clear interrupt as spurious
1912 * pending event on a dummy port might cause screaming IRQ.
1913 */
1914 writel(irq_stat, mmio + HOST_IRQ_STAT);
1915
03e83cbd
TH		 1916 spin_unlock(&host->lock);
1917
365cfa1e
AV		 1918 VPRINTK("EXIT\n");
1919
a129db89 1920 return IRQ_RETVAL(rc);
365cfa1e 1921}
365cfa1e 1922
39e0ee99 1923unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1924{
1925 struct ata_port *ap = qc->ap;
1926 void __iomem *port_mmio = ahci_port_base(ap);
1927 struct ahci_port_priv *pp = ap->private_data;
1928
1929 /* Keep track of the currently active link. It will be used
1930 * in completion path to determine whether NCQ phase is in
1931 * progress.
1932 */
1933 pp->active_link = qc->dev->link;
1934
1935 if (qc->tf.protocol == ATA_PROT_NCQ)
1936 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1937
1938 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1939 u32 fbs = readl(port_mmio + PORT_FBS);
1940 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1941 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1942 writel(fbs, port_mmio + PORT_FBS);
1943 pp->fbs_last_dev = qc->dev->link->pmp;
1944 }
1945
1946 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1947
1948 ahci_sw_activity(qc->dev->link);
1949
1950 return 0;
1951}
39e0ee99 1952EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1953
1954static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1955{
1956 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1957 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1958
1959 if (pp->fbs_enabled)
6ad60195
TH		 1960 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1961
1962 /*
1963 * After a successful execution of an ATA PIO data-in command,
1964 * the device doesn't send D2H Reg FIS to update the TF and
1965 * the host should take TF and E_Status from the preceding PIO
1966 * Setup FIS.
1967 */
1968 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1969 !(qc->flags & ATA_QCFLAG_FAILED)) {
1970 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1971 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1972 } else
1973 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1974
365cfa1e
AV		 1975 return true;
1976}
1977
1978static void ahci_freeze(struct ata_port *ap)
1979{
1980 void __iomem *port_mmio = ahci_port_base(ap);
1981
1982 /* turn IRQ off */
1983 writel(0, port_mmio + PORT_IRQ_MASK);
1984}
1985
1986static void ahci_thaw(struct ata_port *ap)
1987{
1988 struct ahci_host_priv *hpriv = ap->host->private_data;
1989 void __iomem *mmio = hpriv->mmio;
1990 void __iomem *port_mmio = ahci_port_base(ap);
1991 u32 tmp;
1992 struct ahci_port_priv *pp = ap->private_data;
1993
1994 /* clear IRQ */
1995 tmp = readl(port_mmio + PORT_IRQ_STAT);
1996 writel(tmp, port_mmio + PORT_IRQ_STAT);
1997 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1998
1999 /* turn IRQ back on */
2000 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2001}
2002
8b789d89 2003void ahci_error_handler(struct ata_port *ap)
365cfa1e 2004{
039ece38
HG		 2005 struct ahci_host_priv *hpriv = ap->host->private_data;
2006
365cfa1e
AV		 2007 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2008 /* restart engine */
2009 ahci_stop_engine(ap);
039ece38 2010 hpriv->start_engine(ap);
365cfa1e
AV		 2011 }
2012
2013 sata_pmp_error_handler(ap);
0ee71952
TH		 2014
2015 if (!ata_dev_enabled(ap->link.device))
2016 ahci_stop_engine(ap);
365cfa1e 2017}
8b789d89 2018EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2019
2020static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2021{
2022 struct ata_port *ap = qc->ap;
2023
2024 /* make DMA engine forget about the failed command */
2025 if (qc->flags & ATA_QCFLAG_FAILED)
2026 ahci_kick_engine(ap);
2027}
2028
65fe1f0f
SH		 2029static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2030{
039ece38 2031 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2032 void __iomem *port_mmio = ahci_port_base(ap);
2033 struct ata_device *dev = ap->link.device;
2034 u32 devslp, dm, dito, mdat, deto;
2035 int rc;
2036 unsigned int err_mask;
2037
2038 devslp = readl(port_mmio + PORT_DEVSLP);
2039 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2040 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2041 return;
2042 }
2043
2044 /* disable device sleep */
2045 if (!sleep) {
2046 if (devslp & PORT_DEVSLP_ADSE) {
2047 writel(devslp & ~PORT_DEVSLP_ADSE,
2048 port_mmio + PORT_DEVSLP);
2049 err_mask = ata_dev_set_feature(dev,
2050 SETFEATURES_SATA_DISABLE,
2051 SATA_DEVSLP);
2052 if (err_mask && err_mask != AC_ERR_DEV)
2053 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2054 }
2055 return;
2056 }
2057
2058 /* device sleep was already enabled */
2059 if (devslp & PORT_DEVSLP_ADSE)
2060 return;
2061
2062 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2063 rc = ahci_stop_engine(ap);
2064 if (rc)
2065 return;
2066
2067 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2068 dito = devslp_idle_timeout / (dm + 1);
2069 if (dito > 0x3ff)
2070 dito = 0x3ff;
2071
2072 /* Use the nominal value 10 ms if the read MDAT is zero,
2073 * the nominal value of DETO is 20 ms.
2074 */
803739d2 2075 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2076 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2077 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2078 ATA_LOG_DEVSLP_MDAT_MASK;
2079 if (!mdat)
2080 mdat = 10;
803739d2 2081 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2082 if (!deto)
2083 deto = 20;
2084 } else {
2085 mdat = 10;
2086 deto = 20;
2087 }
2088
2089 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2090 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2091 (deto << PORT_DEVSLP_DETO_OFFSET) |
2092 PORT_DEVSLP_ADSE);
2093 writel(devslp, port_mmio + PORT_DEVSLP);
2094
039ece38 2095 hpriv->start_engine(ap);
65fe1f0f
SH		 2096
2097 /* enable device sleep feature for the drive */
2098 err_mask = ata_dev_set_feature(dev,
2099 SETFEATURES_SATA_ENABLE,
2100 SATA_DEVSLP);
2101 if (err_mask && err_mask != AC_ERR_DEV)
2102 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2103}
2104
365cfa1e
AV		 2105static void ahci_enable_fbs(struct ata_port *ap)
2106{
039ece38 2107 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2108 struct ahci_port_priv *pp = ap->private_data;
2109 void __iomem *port_mmio = ahci_port_base(ap);
2110 u32 fbs;
2111 int rc;
2112
2113 if (!pp->fbs_supported)
2114 return;
2115
2116 fbs = readl(port_mmio + PORT_FBS);
2117 if (fbs & PORT_FBS_EN) {
2118 pp->fbs_enabled = true;
2119 pp->fbs_last_dev = -1; /* initialization */
2120 return;
2121 }
2122
2123 rc = ahci_stop_engine(ap);
2124 if (rc)
2125 return;
2126
2127 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2128 fbs = readl(port_mmio + PORT_FBS);
2129 if (fbs & PORT_FBS_EN) {
a44fec1f 2130 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2131 pp->fbs_enabled = true;
2132 pp->fbs_last_dev = -1; /* initialization */
2133 } else
a44fec1f 2134 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2135
039ece38 2136 hpriv->start_engine(ap);
365cfa1e
AV		 2137}
2138
2139static void ahci_disable_fbs(struct ata_port *ap)
2140{
039ece38 2141 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2142 struct ahci_port_priv *pp = ap->private_data;
2143 void __iomem *port_mmio = ahci_port_base(ap);
2144 u32 fbs;
2145 int rc;
2146
2147 if (!pp->fbs_supported)
2148 return;
2149
2150 fbs = readl(port_mmio + PORT_FBS);
2151 if ((fbs & PORT_FBS_EN) == 0) {
2152 pp->fbs_enabled = false;
2153 return;
2154 }
2155
2156 rc = ahci_stop_engine(ap);
2157 if (rc)
2158 return;
2159
2160 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2161 fbs = readl(port_mmio + PORT_FBS);
2162 if (fbs & PORT_FBS_EN)
a44fec1f 2163 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2164 else {
a44fec1f 2165 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2166 pp->fbs_enabled = false;
2167 }
2168
039ece38 2169 hpriv->start_engine(ap);
365cfa1e
AV		 2170}
2171
2172static void ahci_pmp_attach(struct ata_port *ap)
2173{
2174 void __iomem *port_mmio = ahci_port_base(ap);
2175 struct ahci_port_priv *pp = ap->private_data;
2176 u32 cmd;
2177
2178 cmd = readl(port_mmio + PORT_CMD);
2179 cmd |= PORT_CMD_PMP;
2180 writel(cmd, port_mmio + PORT_CMD);
2181
2182 ahci_enable_fbs(ap);
2183
2184 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2185
2186 /*
2187 * We must not change the port interrupt mask register if the
2188 * port is marked frozen, the value in pp->intr_mask will be
2189 * restored later when the port is thawed.
2190 *
2191 * Note that during initialization, the port is marked as
2192 * frozen since the irq handler is not yet registered.
2193 */
2194 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2195 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2196}
2197
2198static void ahci_pmp_detach(struct ata_port *ap)
2199{
2200 void __iomem *port_mmio = ahci_port_base(ap);
2201 struct ahci_port_priv *pp = ap->private_data;
2202 u32 cmd;
2203
2204 ahci_disable_fbs(ap);
2205
2206 cmd = readl(port_mmio + PORT_CMD);
2207 cmd &= ~PORT_CMD_PMP;
2208 writel(cmd, port_mmio + PORT_CMD);
2209
2210 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2211
2212 /* see comment above in ahci_pmp_attach() */
2213 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2214 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2215}
2216
02cdfcf0 2217int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2218{
2219 ahci_power_up(ap);
2220 ahci_start_port(ap);
2221
2222 if (sata_pmp_attached(ap))
2223 ahci_pmp_attach(ap);
2224 else
2225 ahci_pmp_detach(ap);
2226
2227 return 0;
2228}
02cdfcf0 2229EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2230
2231#ifdef CONFIG_PM
2232static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2233{
2234 const char *emsg = NULL;
2235 int rc;
2236
2237 rc = ahci_deinit_port(ap, &emsg);
2238 if (rc == 0)
2239 ahci_power_down(ap);
2240 else {
a9a79dfe 2241 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2242 ata_port_freeze(ap);
365cfa1e
AV		 2243 }
2244
2245 return rc;
2246}
2247#endif
2248
2249static int ahci_port_start(struct ata_port *ap)
2250{
2251 struct ahci_host_priv *hpriv = ap->host->private_data;
2252 struct device *dev = ap->host->dev;
2253 struct ahci_port_priv *pp;
2254 void *mem;
2255 dma_addr_t mem_dma;
2256 size_t dma_sz, rx_fis_sz;
2257
2258 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2259 if (!pp)
2260 return -ENOMEM;
2261
b29900e6
AG		 2262 if (ap->host->n_ports > 1) {
2263 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2264 if (!pp->irq_desc) {
2265 devm_kfree(dev, pp);
2266 return -ENOMEM;
2267 }
2268 snprintf(pp->irq_desc, 8,
2269 "%s%d", dev_driver_string(dev), ap->port_no);
2270 }
2271
365cfa1e
AV		 2272 /* check FBS capability */
2273 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2274 void __iomem *port_mmio = ahci_port_base(ap);
2275 u32 cmd = readl(port_mmio + PORT_CMD);
2276 if (cmd & PORT_CMD_FBSCP)
2277 pp->fbs_supported = true;
5f173107 2278 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2279 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2280 ap->port_no);
5f173107
TH		 2281 pp->fbs_supported = true;
2282 } else
a44fec1f
JP		 2283 dev_warn(dev, "port %d is not capable of FBS\n",
2284 ap->port_no);
365cfa1e
AV		 2285 }
2286
2287 if (pp->fbs_supported) {
2288 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2289 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2290 } else {
2291 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2292 rx_fis_sz = AHCI_RX_FIS_SZ;
2293 }
2294
2295 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2296 if (!mem)
2297 return -ENOMEM;
2298 memset(mem, 0, dma_sz);
2299
2300 /*
2301 * First item in chunk of DMA memory: 32-slot command table,
2302 * 32 bytes each in size
2303 */
2304 pp->cmd_slot = mem;
2305 pp->cmd_slot_dma = mem_dma;
2306
2307 mem += AHCI_CMD_SLOT_SZ;
2308 mem_dma += AHCI_CMD_SLOT_SZ;
2309
2310 /*
2311 * Second item: Received-FIS area
2312 */
2313 pp->rx_fis = mem;
2314 pp->rx_fis_dma = mem_dma;
2315
2316 mem += rx_fis_sz;
2317 mem_dma += rx_fis_sz;
2318
2319 /*
2320 * Third item: data area for storing a single command
2321 * and its scatter-gather table
2322 */
2323 pp->cmd_tbl = mem;
2324 pp->cmd_tbl_dma = mem_dma;
2325
2326 /*
2327 * Save off initial list of interrupts to be enabled.
2328 * This could be changed later
2329 */
2330 pp->intr_mask = DEF_PORT_IRQ;
2331
7865f83f
TH		 2332 /*
2333 * Switch to per-port locking in case each port has its own MSI vector.
2334 */
21bfd1aa 2335 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2336 spin_lock_init(&pp->lock);
2337 ap->lock = &pp->lock;
2338 }
5ca72c4f 2339
365cfa1e
AV		 2340 ap->private_data = pp;
2341
2342 /* engage engines, captain */
2343 return ahci_port_resume(ap);
2344}
2345
2346static void ahci_port_stop(struct ata_port *ap)
2347{
2348 const char *emsg = NULL;
2349 int rc;
2350
2351 /* de-initialize port */
2352 rc = ahci_deinit_port(ap, &emsg);
2353 if (rc)
a9a79dfe 2354 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2355}
2356
2357void ahci_print_info(struct ata_host *host, const char *scc_s)
2358{
2359 struct ahci_host_priv *hpriv = host->private_data;
2360 void __iomem *mmio = hpriv->mmio;
2361 u32 vers, cap, cap2, impl, speed;
2362 const char *speed_s;
2363
2364 vers = readl(mmio + HOST_VERSION);
2365 cap = hpriv->cap;
2366 cap2 = hpriv->cap2;
2367 impl = hpriv->port_map;
2368
2369 speed = (cap >> 20) & 0xf;
2370 if (speed == 1)
2371 speed_s = "1.5";
2372 else if (speed == 2)
2373 speed_s = "3";
2374 else if (speed == 3)
2375 speed_s = "6";
2376 else
2377 speed_s = "?";
2378
2379 dev_info(host->dev,
2380 "AHCI %02x%02x.%02x%02x "
2381 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2382 ,
2383
2384 (vers >> 24) & 0xff,
2385 (vers >> 16) & 0xff,
2386 (vers >> 8) & 0xff,
2387 vers & 0xff,
2388
2389 ((cap >> 8) & 0x1f) + 1,
2390 (cap & 0x1f) + 1,
2391 speed_s,
2392 impl,
2393 scc_s);
2394
2395 dev_info(host->dev,
2396 "flags: "
2397 "%s%s%s%s%s%s%s"
2398 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2399 "%s%s%s%s%s%s%s"
2400 "%s%s\n"
365cfa1e
AV		 2401 ,
2402
2403 cap & HOST_CAP_64 ? "64bit " : "",
2404 cap & HOST_CAP_NCQ ? "ncq " : "",
2405 cap & HOST_CAP_SNTF ? "sntf " : "",
2406 cap & HOST_CAP_MPS ? "ilck " : "",
2407 cap & HOST_CAP_SSS ? "stag " : "",
2408 cap & HOST_CAP_ALPM ? "pm " : "",
2409 cap & HOST_CAP_LED ? "led " : "",
2410 cap & HOST_CAP_CLO ? "clo " : "",
2411 cap & HOST_CAP_ONLY ? "only " : "",
2412 cap & HOST_CAP_PMP ? "pmp " : "",
2413 cap & HOST_CAP_FBS ? "fbs " : "",
2414 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2415 cap & HOST_CAP_SSC ? "slum " : "",
2416 cap & HOST_CAP_PART ? "part " : "",
2417 cap & HOST_CAP_CCC ? "ccc " : "",
2418 cap & HOST_CAP_EMS ? "ems " : "",
2419 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2420 cap2 & HOST_CAP2_DESO ? "deso " : "",
2421 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2422 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2423 cap2 & HOST_CAP2_APST ? "apst " : "",
2424 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2425 cap2 & HOST_CAP2_BOH ? "boh " : ""
2426 );
2427}
2428EXPORT_SYMBOL_GPL(ahci_print_info);
2429
2430void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2431 struct ata_port_info *pi)
2432{
2433 u8 messages;
2434 void __iomem *mmio = hpriv->mmio;
2435 u32 em_loc = readl(mmio + HOST_EM_LOC);
2436 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2437
2438 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2439 return;
2440
2441 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2442
008dbd61 2443 if (messages) {
365cfa1e
AV		 2444 /* store em_loc */
2445 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2446 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2447 hpriv->em_msg_type = messages;
365cfa1e
AV		 2448 pi->flags |= ATA_FLAG_EM;
2449 if (!(em_ctl & EM_CTL_ALHD))
2450 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2451 }
2452}
2453EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2454
d684a90d 2455static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2456 struct scsi_host_template *sht)
1c62854f 2457{
d684a90d 2458 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2459 int i, rc;
2460
2461 rc = ata_host_start(host);
2462 if (rc)
2463 return rc;
21bfd1aa
RR		 2464 /*
2465 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2466 * allocated. That is one MSI per port, starting from @irq.
2467 */
1c62854f
AG		 2468 for (i = 0; i < host->n_ports; i++) {
2469 struct ahci_port_priv *pp = host->ports[i]->private_data;
f893180b 2470 int irq = ahci_irq_vector(hpriv, i);
1c62854f
AG		 2471
2472 /* Do not receive interrupts sent by dummy ports */
2473 if (!pp) {
2474 disable_irq(irq + i);
2475 continue;
2476 }
2477
a6b7fb76
DW		 2478 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2479 0, pp->irq_desc, host->ports[i]);
2480
1c62854f 2481 if (rc)
0a142b26 2482 return rc;
d684a90d 2483 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2484 }
d684a90d 2485
0a142b26 2486 return ata_host_register(host, sht);
1c62854f 2487}
d1028e2f
AG		 2488
2489/**
2490 * ahci_host_activate - start AHCI host, request IRQs and register it
2491 * @host: target ATA host
d1028e2f
AG		 2492 * @sht: scsi_host_template to use when registering the host
2493 *
d1028e2f
AG		 2494 * LOCKING:
2495 * Inherited from calling layer (may sleep).
2496 *
2497 * RETURNS:
2498 * 0 on success, -errno otherwise.
2499 */
21bfd1aa 2500int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2501{
2502 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2503 int irq = hpriv->irq;
d1028e2f
AG		 2504 int rc;
2505
f070d671
ST		 2506 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
2507 if (hpriv->irq_handler)
2508 dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
2509 and custom irq handler implemented\n");
2510
d684a90d 2511 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2512 } else {
2513 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2514 IRQF_SHARED, sht);
f070d671
ST		 2515 }
2516
2517
d1028e2f
AG		 2518 return rc;
2519}
1c62854f
AG		 2520EXPORT_SYMBOL_GPL(ahci_host_activate);
2521
365cfa1e
AV		 2522MODULE_AUTHOR("Jeff Garzik");
2523MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2524MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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