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libahci: Implement the capability to override the generic ahci interrupt handler.
[deliverable/linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
d684a90d 46#include <linux/pci.h>
365cfa1e 47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
65fe1f0f 79static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
345347c5
YHC		 86static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
365cfa1e
AV		 88static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
f070d671
ST		 116static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance);
117
118static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 119
120static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
121static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
122static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
123static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 124static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
125 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 126static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 127
fad16e7a 128struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 129 &dev_attr_link_power_management_policy,
130 &dev_attr_em_message_type,
131 &dev_attr_em_message,
132 &dev_attr_ahci_host_caps,
133 &dev_attr_ahci_host_cap2,
134 &dev_attr_ahci_host_version,
135 &dev_attr_ahci_port_cmd,
c0623166 136 &dev_attr_em_buffer,
6e5fe5b1 137 &dev_attr_em_message_supported,
365cfa1e
AV		 138 NULL
139};
fad16e7a 140EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 141
fad16e7a 142struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 143 &dev_attr_sw_activity,
144 &dev_attr_unload_heads,
145 NULL
146};
fad16e7a 147EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 148
149struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
6b7ae954 172 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
439d7a35 177 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 178#ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181#endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184};
185EXPORT_SYMBOL_GPL(ahci_ops);
186
345347c5
YHC		 187struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190};
191EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
ed08d40c 193static bool ahci_em_messages __read_mostly = true;
365cfa1e 194EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 195module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 196/* add other LED protocol types when they become supported */
197MODULE_PARM_DESC(ahci_em_messages,
008dbd61 198 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 199
ed08d40c
CL		 200/* device sleep idle timeout in ms */
201static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 202module_param(devslp_idle_timeout, int, 0644);
203MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204
365cfa1e
AV		 205static void ahci_enable_ahci(void __iomem *mmio)
206{
207 int i;
208 u32 tmp;
209
210 /* turn on AHCI_EN */
211 tmp = readl(mmio + HOST_CTL);
212 if (tmp & HOST_AHCI_EN)
213 return;
214
215 /* Some controllers need AHCI_EN to be written multiple times.
216 * Try a few times before giving up.
217 */
218 for (i = 0; i < 5; i++) {
219 tmp |= HOST_AHCI_EN;
220 writel(tmp, mmio + HOST_CTL);
221 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
222 if (tmp & HOST_AHCI_EN)
223 return;
224 msleep(10);
225 }
226
227 WARN_ON(1);
228}
229
230static ssize_t ahci_show_host_caps(struct device *dev,
231 struct device_attribute *attr, char *buf)
232{
233 struct Scsi_Host *shost = class_to_shost(dev);
234 struct ata_port *ap = ata_shost_to_port(shost);
235 struct ahci_host_priv *hpriv = ap->host->private_data;
236
237 return sprintf(buf, "%x\n", hpriv->cap);
238}
239
240static ssize_t ahci_show_host_cap2(struct device *dev,
241 struct device_attribute *attr, char *buf)
242{
243 struct Scsi_Host *shost = class_to_shost(dev);
244 struct ata_port *ap = ata_shost_to_port(shost);
245 struct ahci_host_priv *hpriv = ap->host->private_data;
246
247 return sprintf(buf, "%x\n", hpriv->cap2);
248}
249
250static ssize_t ahci_show_host_version(struct device *dev,
251 struct device_attribute *attr, char *buf)
252{
253 struct Scsi_Host *shost = class_to_shost(dev);
254 struct ata_port *ap = ata_shost_to_port(shost);
255 struct ahci_host_priv *hpriv = ap->host->private_data;
256 void __iomem *mmio = hpriv->mmio;
257
258 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
259}
260
261static ssize_t ahci_show_port_cmd(struct device *dev,
262 struct device_attribute *attr, char *buf)
263{
264 struct Scsi_Host *shost = class_to_shost(dev);
265 struct ata_port *ap = ata_shost_to_port(shost);
266 void __iomem *port_mmio = ahci_port_base(ap);
267
268 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
269}
270
c0623166
HZ		 271static ssize_t ahci_read_em_buffer(struct device *dev,
272 struct device_attribute *attr, char *buf)
273{
274 struct Scsi_Host *shost = class_to_shost(dev);
275 struct ata_port *ap = ata_shost_to_port(shost);
276 struct ahci_host_priv *hpriv = ap->host->private_data;
277 void __iomem *mmio = hpriv->mmio;
278 void __iomem *em_mmio = mmio + hpriv->em_loc;
279 u32 em_ctl, msg;
280 unsigned long flags;
281 size_t count;
282 int i;
283
284 spin_lock_irqsave(ap->lock, flags);
285
286 em_ctl = readl(mmio + HOST_EM_CTL);
287 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
288 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
289 spin_unlock_irqrestore(ap->lock, flags);
290 return -EINVAL;
291 }
292
293 if (!(em_ctl & EM_CTL_MR)) {
294 spin_unlock_irqrestore(ap->lock, flags);
295 return -EAGAIN;
296 }
297
298 if (!(em_ctl & EM_CTL_SMB))
299 em_mmio += hpriv->em_buf_sz;
300
301 count = hpriv->em_buf_sz;
302
303 /* the count should not be larger than PAGE_SIZE */
304 if (count > PAGE_SIZE) {
305 if (printk_ratelimit())
a9a79dfe
JP		 306 ata_port_warn(ap,
307 "EM read buffer size too large: "
308 "buffer size %u, page size %lu\n",
309 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 310 count = PAGE_SIZE;
311 }
312
313 for (i = 0; i < count; i += 4) {
314 msg = readl(em_mmio + i);
315 buf[i] = msg & 0xff;
316 buf[i + 1] = (msg >> 8) & 0xff;
317 buf[i + 2] = (msg >> 16) & 0xff;
318 buf[i + 3] = (msg >> 24) & 0xff;
319 }
320
321 spin_unlock_irqrestore(ap->lock, flags);
322
323 return i;
324}
325
326static ssize_t ahci_store_em_buffer(struct device *dev,
327 struct device_attribute *attr,
328 const char *buf, size_t size)
329{
330 struct Scsi_Host *shost = class_to_shost(dev);
331 struct ata_port *ap = ata_shost_to_port(shost);
332 struct ahci_host_priv *hpriv = ap->host->private_data;
333 void __iomem *mmio = hpriv->mmio;
334 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 335 const unsigned char *msg_buf = buf;
c0623166
HZ		 336 u32 em_ctl, msg;
337 unsigned long flags;
338 int i;
339
340 /* check size validity */
341 if (!(ap->flags & ATA_FLAG_EM) ||
342 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
343 size % 4 || size > hpriv->em_buf_sz)
344 return -EINVAL;
345
346 spin_lock_irqsave(ap->lock, flags);
347
348 em_ctl = readl(mmio + HOST_EM_CTL);
349 if (em_ctl & EM_CTL_TM) {
350 spin_unlock_irqrestore(ap->lock, flags);
351 return -EBUSY;
352 }
353
354 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 355 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
356 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 357 writel(msg, em_mmio + i);
358 }
359
360 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
361
362 spin_unlock_irqrestore(ap->lock, flags);
363
364 return size;
365}
366
6e5fe5b1
HR		 367static ssize_t ahci_show_em_supported(struct device *dev,
368 struct device_attribute *attr, char *buf)
369{
370 struct Scsi_Host *shost = class_to_shost(dev);
371 struct ata_port *ap = ata_shost_to_port(shost);
372 struct ahci_host_priv *hpriv = ap->host->private_data;
373 void __iomem *mmio = hpriv->mmio;
374 u32 em_ctl;
375
376 em_ctl = readl(mmio + HOST_EM_CTL);
377
378 return sprintf(buf, "%s%s%s%s\n",
379 em_ctl & EM_CTL_LED ? "led " : "",
380 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
381 em_ctl & EM_CTL_SES ? "ses-2 " : "",
382 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
383}
384
365cfa1e
AV		 385/**
386 * ahci_save_initial_config - Save and fixup initial config values
387 * @dev: target AHCI device
388 * @hpriv: host private area to store config values
365cfa1e
AV		 389 *
390 * Some registers containing configuration info might be setup by
391 * BIOS and might be cleared on reset. This function saves the
392 * initial values of those registers into @hpriv such that they
393 * can be restored after controller reset.
394 *
395 * If inconsistent, config values are fixed up by this function.
396 *
039ece38
HG		 397 * If it is not set already this function sets hpriv->start_engine to
398 * ahci_start_engine.
399 *
365cfa1e
AV		 400 * LOCKING:
401 * None.
402 */
725c7b57 403void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 404{
405 void __iomem *mmio = hpriv->mmio;
406 u32 cap, cap2, vers, port_map;
407 int i;
408
409 /* make sure AHCI mode is enabled before accessing CAP */
410 ahci_enable_ahci(mmio);
411
412 /* Values prefixed with saved_ are written back to host after
413 * reset. Values without are used for driver operation.
414 */
415 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
416 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
417
418 /* CAP2 register is only defined for AHCI 1.2 and later */
419 vers = readl(mmio + HOST_VERSION);
420 if ((vers >> 16) > 1 ||
421 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
422 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
423 else
424 hpriv->saved_cap2 = cap2 = 0;
425
426 /* some chips have errata preventing 64bit use */
427 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 428 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 429 cap &= ~HOST_CAP_64;
430 }
431
432 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 433 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 434 cap &= ~HOST_CAP_NCQ;
435 }
436
437 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 438 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 439 cap |= HOST_CAP_NCQ;
440 }
441
442 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 443 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 444 cap &= ~HOST_CAP_PMP;
445 }
446
447 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 448 dev_info(dev,
449 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 450 cap &= ~HOST_CAP_SNTF;
451 }
452
0cf4a7d6
JP		 453 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
454 dev_info(dev,
455 "controller can't do DEVSLP, turning off\n");
456 cap2 &= ~HOST_CAP2_SDS;
457 cap2 &= ~HOST_CAP2_SADM;
458 }
459
5f173107 460 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 461 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 462 cap |= HOST_CAP_FBS;
463 }
464
888d91a0
KW		 465 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
466 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
467 cap &= ~HOST_CAP_FBS;
468 }
469
725c7b57 470 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 471 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 472 port_map, hpriv->force_port_map);
473 port_map = hpriv->force_port_map;
365cfa1e
AV		 474 }
475
725c7b57 476 if (hpriv->mask_port_map) {
a44fec1f
JP		 477 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
478 port_map,
725c7b57
AT		 479 port_map & hpriv->mask_port_map);
480 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 481 }
482
483 /* cross check port_map and cap.n_ports */
484 if (port_map) {
485 int map_ports = 0;
486
487 for (i = 0; i < AHCI_MAX_PORTS; i++)
488 if (port_map & (1 << i))
489 map_ports++;
490
491 /* If PI has more ports than n_ports, whine, clear
492 * port_map and let it be generated from n_ports.
493 */
494 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 495 dev_warn(dev,
496 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
497 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 498 port_map = 0;
499 }
500 }
501
566d1827
TH		 502 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
503 if (!port_map && vers < 0x10300) {
365cfa1e 504 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 505 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 506
507 /* write the fixed up value to the PI register */
508 hpriv->saved_port_map = port_map;
509 }
510
511 /* record values to use during operation */
512 hpriv->cap = cap;
513 hpriv->cap2 = cap2;
514 hpriv->port_map = port_map;
039ece38
HG		 515
516 if (!hpriv->start_engine)
517 hpriv->start_engine = ahci_start_engine;
f070d671
ST		 518
519 if (!hpriv->irq_handler)
520 hpriv->irq_handler = (hpriv->flags & AHCI_HFLAG_EDGE_IRQ) ?
521 ahci_single_edge_irq_intr :
522 ahci_single_level_irq_intr;
365cfa1e
AV		 523}
524EXPORT_SYMBOL_GPL(ahci_save_initial_config);
525
526/**
527 * ahci_restore_initial_config - Restore initial config
528 * @host: target ATA host
529 *
530 * Restore initial config stored by ahci_save_initial_config().
531 *
532 * LOCKING:
533 * None.
534 */
535static void ahci_restore_initial_config(struct ata_host *host)
536{
537 struct ahci_host_priv *hpriv = host->private_data;
538 void __iomem *mmio = hpriv->mmio;
539
540 writel(hpriv->saved_cap, mmio + HOST_CAP);
541 if (hpriv->saved_cap2)
542 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
543 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
544 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
545}
546
547static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
548{
549 static const int offset[] = {
550 [SCR_STATUS] = PORT_SCR_STAT,
551 [SCR_CONTROL] = PORT_SCR_CTL,
552 [SCR_ERROR] = PORT_SCR_ERR,
553 [SCR_ACTIVE] = PORT_SCR_ACT,
554 [SCR_NOTIFICATION] = PORT_SCR_NTF,
555 };
556 struct ahci_host_priv *hpriv = ap->host->private_data;
557
558 if (sc_reg < ARRAY_SIZE(offset) &&
559 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
560 return offset[sc_reg];
561 return 0;
562}
563
564static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
565{
566 void __iomem *port_mmio = ahci_port_base(link->ap);
567 int offset = ahci_scr_offset(link->ap, sc_reg);
568
569 if (offset) {
570 *val = readl(port_mmio + offset);
571 return 0;
572 }
573 return -EINVAL;
574}
575
576static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
577{
578 void __iomem *port_mmio = ahci_port_base(link->ap);
579 int offset = ahci_scr_offset(link->ap, sc_reg);
580
581 if (offset) {
582 writel(val, port_mmio + offset);
583 return 0;
584 }
585 return -EINVAL;
586}
587
588void ahci_start_engine(struct ata_port *ap)
589{
590 void __iomem *port_mmio = ahci_port_base(ap);
591 u32 tmp;
592
593 /* start DMA */
594 tmp = readl(port_mmio + PORT_CMD);
595 tmp |= PORT_CMD_START;
596 writel(tmp, port_mmio + PORT_CMD);
597 readl(port_mmio + PORT_CMD); /* flush */
598}
599EXPORT_SYMBOL_GPL(ahci_start_engine);
600
601int ahci_stop_engine(struct ata_port *ap)
602{
603 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 604 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 605 u32 tmp;
606
fb329633
DP		 607 /*
608 * On some controllers, stopping a port's DMA engine while the port
609 * is in ALPM state (partial or slumber) results in failures on
610 * subsequent DMA engine starts. For those controllers, put the
611 * port back in active state before stopping its DMA engine.
612 */
613 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
614 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
615 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
616 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
617 return -EIO;
618 }
619
365cfa1e
AV		 620 tmp = readl(port_mmio + PORT_CMD);
621
622 /* check if the HBA is idle */
623 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
624 return 0;
625
626 /* setting HBA to idle */
627 tmp &= ~PORT_CMD_START;
628 writel(tmp, port_mmio + PORT_CMD);
629
630 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 631 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 632 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
633 if (tmp & PORT_CMD_LIST_ON)
634 return -EIO;
635
636 return 0;
637}
638EXPORT_SYMBOL_GPL(ahci_stop_engine);
639
39e0ee99 640void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 641{
642 void __iomem *port_mmio = ahci_port_base(ap);
643 struct ahci_host_priv *hpriv = ap->host->private_data;
644 struct ahci_port_priv *pp = ap->private_data;
645 u32 tmp;
646
647 /* set FIS registers */
648 if (hpriv->cap & HOST_CAP_64)
649 writel((pp->cmd_slot_dma >> 16) >> 16,
650 port_mmio + PORT_LST_ADDR_HI);
651 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
652
653 if (hpriv->cap & HOST_CAP_64)
654 writel((pp->rx_fis_dma >> 16) >> 16,
655 port_mmio + PORT_FIS_ADDR_HI);
656 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
657
658 /* enable FIS reception */
659 tmp = readl(port_mmio + PORT_CMD);
660 tmp |= PORT_CMD_FIS_RX;
661 writel(tmp, port_mmio + PORT_CMD);
662
663 /* flush */
664 readl(port_mmio + PORT_CMD);
665}
39e0ee99 666EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 667
668static int ahci_stop_fis_rx(struct ata_port *ap)
669{
670 void __iomem *port_mmio = ahci_port_base(ap);
671 u32 tmp;
672
673 /* disable FIS reception */
674 tmp = readl(port_mmio + PORT_CMD);
675 tmp &= ~PORT_CMD_FIS_RX;
676 writel(tmp, port_mmio + PORT_CMD);
677
678 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 679 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 680 PORT_CMD_FIS_ON, 10, 1000);
681 if (tmp & PORT_CMD_FIS_ON)
682 return -EBUSY;
683
684 return 0;
685}
686
687static void ahci_power_up(struct ata_port *ap)
688{
689 struct ahci_host_priv *hpriv = ap->host->private_data;
690 void __iomem *port_mmio = ahci_port_base(ap);
691 u32 cmd;
692
693 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
694
695 /* spin up device */
696 if (hpriv->cap & HOST_CAP_SSS) {
697 cmd |= PORT_CMD_SPIN_UP;
698 writel(cmd, port_mmio + PORT_CMD);
699 }
700
701 /* wake up link */
702 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
703}
704
6b7ae954
TH		 705static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
706 unsigned int hints)
365cfa1e 707{
6b7ae954 708 struct ata_port *ap = link->ap;
365cfa1e 709 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 710 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 711 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 712
6b7ae954 713 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 714 /* wakeup flag only applies to the max power policy */
715 hints &= ~ATA_LPM_WAKE_ONLY;
716
365cfa1e 717 /*
6b7ae954
TH		 718 * Disable interrupts on Phy Ready. This keeps us from
719 * getting woken up due to spurious phy ready
720 * interrupts.
365cfa1e 721 */
6b7ae954
TH		 722 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
723 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
724
725 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 726 }
727
6b7ae954
TH		 728 if (hpriv->cap & HOST_CAP_ALPM) {
729 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 730
6b7ae954 731 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 732 if (!(hints & ATA_LPM_WAKE_ONLY))
733 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 734 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 735
6b7ae954
TH		 736 writel(cmd, port_mmio + PORT_CMD);
737 readl(port_mmio + PORT_CMD);
365cfa1e 738
6b7ae954 739 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 740 ata_msleep(ap, 10);
fb329633
DP		 741
742 if (hints & ATA_LPM_WAKE_ONLY)
743 return 0;
6b7ae954
TH		 744 } else {
745 cmd |= PORT_CMD_ALPE;
746 if (policy == ATA_LPM_MIN_POWER)
747 cmd |= PORT_CMD_ASP;
365cfa1e 748
6b7ae954
TH		 749 /* write out new cmd value */
750 writel(cmd, port_mmio + PORT_CMD);
751 }
752 }
365cfa1e 753
65fe1f0f
SH		 754 /* set aggressive device sleep */
755 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
756 (hpriv->cap2 & HOST_CAP2_SADM) &&
757 (link->device->flags & ATA_DFLAG_DEVSLP)) {
758 if (policy == ATA_LPM_MIN_POWER)
759 ahci_set_aggressive_devslp(ap, true);
760 else
761 ahci_set_aggressive_devslp(ap, false);
762 }
763
6b7ae954
TH		 764 if (policy == ATA_LPM_MAX_POWER) {
765 sata_link_scr_lpm(link, policy, false);
766
767 /* turn PHYRDY IRQ back on */
768 pp->intr_mask |= PORT_IRQ_PHYRDY;
769 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
770 }
365cfa1e 771
365cfa1e
AV		 772 return 0;
773}
774
775#ifdef CONFIG_PM
776static void ahci_power_down(struct ata_port *ap)
777{
778 struct ahci_host_priv *hpriv = ap->host->private_data;
779 void __iomem *port_mmio = ahci_port_base(ap);
780 u32 cmd, scontrol;
781
782 if (!(hpriv->cap & HOST_CAP_SSS))
783 return;
784
785 /* put device into listen mode, first set PxSCTL.DET to 0 */
786 scontrol = readl(port_mmio + PORT_SCR_CTL);
787 scontrol &= ~0xf;
788 writel(scontrol, port_mmio + PORT_SCR_CTL);
789
790 /* then set PxCMD.SUD to 0 */
791 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
792 cmd &= ~PORT_CMD_SPIN_UP;
793 writel(cmd, port_mmio + PORT_CMD);
794}
795#endif
796
797static void ahci_start_port(struct ata_port *ap)
798{
66583c9f 799 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 800 struct ahci_port_priv *pp = ap->private_data;
801 struct ata_link *link;
802 struct ahci_em_priv *emp;
803 ssize_t rc;
804 int i;
805
806 /* enable FIS reception */
807 ahci_start_fis_rx(ap);
808
66583c9f
BN		 809 /* enable DMA */
810 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 811 hpriv->start_engine(ap);
66583c9f 812
365cfa1e
AV		 813 /* turn on LEDs */
814 if (ap->flags & ATA_FLAG_EM) {
815 ata_for_each_link(link, ap, EDGE) {
816 emp = &pp->em_priv[link->pmp];
817
818 /* EM Transmit bit maybe busy during init */
819 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 820 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 821 emp->led_state,
822 4);
fa070ee6
LD		 823 /*
824 * If busy, give a breather but do not
825 * release EH ownership by using msleep()
826 * instead of ata_msleep(). EM Transmit
827 * bit is busy for the whole host and
828 * releasing ownership will cause other
829 * ports to fail the same way.
830 */
365cfa1e 831 if (rc == -EBUSY)
fa070ee6 832 msleep(1);
365cfa1e
AV		 833 else
834 break;
835 }
836 }
837 }
838
839 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
840 ata_for_each_link(link, ap, EDGE)
841 ahci_init_sw_activity(link);
842
843}
844
845static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
846{
847 int rc;
848
849 /* disable DMA */
850 rc = ahci_stop_engine(ap);
851 if (rc) {
852 *emsg = "failed to stop engine";
853 return rc;
854 }
855
856 /* disable FIS reception */
857 rc = ahci_stop_fis_rx(ap);
858 if (rc) {
859 *emsg = "failed stop FIS RX";
860 return rc;
861 }
862
863 return 0;
864}
865
866int ahci_reset_controller(struct ata_host *host)
867{
868 struct ahci_host_priv *hpriv = host->private_data;
869 void __iomem *mmio = hpriv->mmio;
870 u32 tmp;
871
872 /* we must be in AHCI mode, before using anything
873 * AHCI-specific, such as HOST_RESET.
874 */
875 ahci_enable_ahci(mmio);
876
877 /* global controller reset */
878 if (!ahci_skip_host_reset) {
879 tmp = readl(mmio + HOST_CTL);
880 if ((tmp & HOST_RESET) == 0) {
881 writel(tmp | HOST_RESET, mmio + HOST_CTL);
882 readl(mmio + HOST_CTL); /* flush */
883 }
884
885 /*
886 * to perform host reset, OS should set HOST_RESET
887 * and poll until this bit is read to be "0".
888 * reset must complete within 1 second, or
889 * the hardware should be considered fried.
890 */
97750ceb 891 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 892 HOST_RESET, 10, 1000);
893
894 if (tmp & HOST_RESET) {
a44fec1f
JP		 895 dev_err(host->dev, "controller reset failed (0x%x)\n",
896 tmp);
365cfa1e
AV		 897 return -EIO;
898 }
899
900 /* turn on AHCI mode */
901 ahci_enable_ahci(mmio);
902
903 /* Some registers might be cleared on reset. Restore
904 * initial values.
905 */
906 ahci_restore_initial_config(host);
907 } else
a44fec1f 908 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 909
910 return 0;
911}
912EXPORT_SYMBOL_GPL(ahci_reset_controller);
913
914static void ahci_sw_activity(struct ata_link *link)
915{
916 struct ata_port *ap = link->ap;
917 struct ahci_port_priv *pp = ap->private_data;
918 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
919
920 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
921 return;
922
923 emp->activity++;
924 if (!timer_pending(&emp->timer))
925 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
926}
927
928static void ahci_sw_activity_blink(unsigned long arg)
929{
930 struct ata_link *link = (struct ata_link *)arg;
931 struct ata_port *ap = link->ap;
932 struct ahci_port_priv *pp = ap->private_data;
933 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
934 unsigned long led_message = emp->led_state;
935 u32 activity_led_state;
936 unsigned long flags;
937
938 led_message &= EM_MSG_LED_VALUE;
939 led_message |= ap->port_no | (link->pmp << 8);
940
941 /* check to see if we've had activity. If so,
942 * toggle state of LED and reset timer. If not,
943 * turn LED to desired idle state.
944 */
945 spin_lock_irqsave(ap->lock, flags);
946 if (emp->saved_activity != emp->activity) {
947 emp->saved_activity = emp->activity;
948 /* get the current LED state */
949 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
950
951 if (activity_led_state)
952 activity_led_state = 0;
953 else
954 activity_led_state = 1;
955
956 /* clear old state */
957 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
958
959 /* toggle state */
960 led_message |= (activity_led_state << 16);
961 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
962 } else {
963 /* switch to idle */
964 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
965 if (emp->blink_policy == BLINK_OFF)
966 led_message |= (1 << 16);
967 }
968 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 969 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 970}
971
972static void ahci_init_sw_activity(struct ata_link *link)
973{
974 struct ata_port *ap = link->ap;
975 struct ahci_port_priv *pp = ap->private_data;
976 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
977
978 /* init activity stats, setup timer */
979 emp->saved_activity = emp->activity = 0;
980 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
981
982 /* check our blink policy and set flag for link if it's enabled */
983 if (emp->blink_policy)
984 link->flags |= ATA_LFLAG_SW_ACTIVITY;
985}
986
987int ahci_reset_em(struct ata_host *host)
988{
989 struct ahci_host_priv *hpriv = host->private_data;
990 void __iomem *mmio = hpriv->mmio;
991 u32 em_ctl;
992
993 em_ctl = readl(mmio + HOST_EM_CTL);
994 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
995 return -EINVAL;
996
997 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
998 return 0;
999}
1000EXPORT_SYMBOL_GPL(ahci_reset_em);
1001
1002static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1003 ssize_t size)
1004{
1005 struct ahci_host_priv *hpriv = ap->host->private_data;
1006 struct ahci_port_priv *pp = ap->private_data;
1007 void __iomem *mmio = hpriv->mmio;
1008 u32 em_ctl;
1009 u32 message[] = {0, 0};
1010 unsigned long flags;
1011 int pmp;
1012 struct ahci_em_priv *emp;
1013
1014 /* get the slot number from the message */
1015 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1016 if (pmp < EM_MAX_SLOTS)
1017 emp = &pp->em_priv[pmp];
1018 else
1019 return -EINVAL;
1020
1021 spin_lock_irqsave(ap->lock, flags);
1022
1023 /*
1024 * if we are still busy transmitting a previous message,
1025 * do not allow
1026 */
1027 em_ctl = readl(mmio + HOST_EM_CTL);
1028 if (em_ctl & EM_CTL_TM) {
1029 spin_unlock_irqrestore(ap->lock, flags);
1030 return -EBUSY;
1031 }
1032
008dbd61
HZ		 1033 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1034 /*
1035 * create message header - this is all zero except for
1036 * the message size, which is 4 bytes.
1037 */
1038 message[0] |= (4 << 8);
365cfa1e 1039
008dbd61
HZ		 1040 /* ignore 0:4 of byte zero, fill in port info yourself */
1041 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1042
008dbd61
HZ		 1043 /* write message to EM_LOC */
1044 writel(message[0], mmio + hpriv->em_loc);
1045 writel(message[1], mmio + hpriv->em_loc+4);
1046
1047 /*
1048 * tell hardware to transmit the message
1049 */
1050 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1051 }
365cfa1e
AV		 1052
1053 /* save off new led state for port/slot */
1054 emp->led_state = state;
1055
365cfa1e
AV		 1056 spin_unlock_irqrestore(ap->lock, flags);
1057 return size;
1058}
1059
1060static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1061{
1062 struct ahci_port_priv *pp = ap->private_data;
1063 struct ata_link *link;
1064 struct ahci_em_priv *emp;
1065 int rc = 0;
1066
1067 ata_for_each_link(link, ap, EDGE) {
1068 emp = &pp->em_priv[link->pmp];
1069 rc += sprintf(buf, "%lx\n", emp->led_state);
1070 }
1071 return rc;
1072}
1073
1074static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1075 size_t size)
1076{
b2a52b6a 1077 unsigned int state;
365cfa1e
AV		 1078 int pmp;
1079 struct ahci_port_priv *pp = ap->private_data;
1080 struct ahci_em_priv *emp;
1081
b2a52b6a
DY		 1082 if (kstrtouint(buf, 0, &state) < 0)
1083 return -EINVAL;
365cfa1e
AV		 1084
1085 /* get the slot number from the message */
1086 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1087 if (pmp < EM_MAX_SLOTS)
1088 emp = &pp->em_priv[pmp];
1089 else
1090 return -EINVAL;
1091
1092 /* mask off the activity bits if we are in sw_activity
1093 * mode, user should turn off sw_activity before setting
1094 * activity led through em_message
1095 */
1096 if (emp->blink_policy)
1097 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1098
439d7a35 1099 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1100}
1101
1102static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1103{
1104 struct ata_link *link = dev->link;
1105 struct ata_port *ap = link->ap;
1106 struct ahci_port_priv *pp = ap->private_data;
1107 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1108 u32 port_led_state = emp->led_state;
1109
1110 /* save the desired Activity LED behavior */
1111 if (val == OFF) {
1112 /* clear LFLAG */
1113 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1114
1115 /* set the LED to OFF */
1116 port_led_state &= EM_MSG_LED_VALUE_OFF;
1117 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1118 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1119 } else {
1120 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1121 if (val == BLINK_OFF) {
1122 /* set LED to ON for idle */
1123 port_led_state &= EM_MSG_LED_VALUE_OFF;
1124 port_led_state |= (ap->port_no | (link->pmp << 8));
1125 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1126 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1127 }
1128 }
1129 emp->blink_policy = val;
1130 return 0;
1131}
1132
1133static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1134{
1135 struct ata_link *link = dev->link;
1136 struct ata_port *ap = link->ap;
1137 struct ahci_port_priv *pp = ap->private_data;
1138 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1139
1140 /* display the saved value of activity behavior for this
1141 * disk.
1142 */
1143 return sprintf(buf, "%d\n", emp->blink_policy);
1144}
1145
1146static void ahci_port_init(struct device *dev, struct ata_port *ap,
1147 int port_no, void __iomem *mmio,
1148 void __iomem *port_mmio)
1149{
8a3e33cf 1150 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1151 const char *emsg = NULL;
1152 int rc;
1153 u32 tmp;
1154
1155 /* make sure port is not active */
1156 rc = ahci_deinit_port(ap, &emsg);
1157 if (rc)
1158 dev_warn(dev, "%s (%d)\n", emsg, rc);
1159
1160 /* clear SError */
1161 tmp = readl(port_mmio + PORT_SCR_ERR);
1162 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1163 writel(tmp, port_mmio + PORT_SCR_ERR);
1164
1165 /* clear port IRQ */
1166 tmp = readl(port_mmio + PORT_IRQ_STAT);
1167 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1168 if (tmp)
1169 writel(tmp, port_mmio + PORT_IRQ_STAT);
1170
1171 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1172
1173 /* mark esata ports */
1174 tmp = readl(port_mmio + PORT_CMD);
1175 if ((tmp & PORT_CMD_HPCP) ||
1176 ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
1177 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1178}
1179
1180void ahci_init_controller(struct ata_host *host)
1181{
1182 struct ahci_host_priv *hpriv = host->private_data;
1183 void __iomem *mmio = hpriv->mmio;
1184 int i;
1185 void __iomem *port_mmio;
1186 u32 tmp;
1187
1188 for (i = 0; i < host->n_ports; i++) {
1189 struct ata_port *ap = host->ports[i];
1190
1191 port_mmio = ahci_port_base(ap);
1192 if (ata_port_is_dummy(ap))
1193 continue;
1194
1195 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1196 }
1197
1198 tmp = readl(mmio + HOST_CTL);
1199 VPRINTK("HOST_CTL 0x%x\n", tmp);
1200 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1201 tmp = readl(mmio + HOST_CTL);
1202 VPRINTK("HOST_CTL 0x%x\n", tmp);
1203}
1204EXPORT_SYMBOL_GPL(ahci_init_controller);
1205
1206static void ahci_dev_config(struct ata_device *dev)
1207{
1208 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1209
1210 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1211 dev->max_sectors = 255;
a9a79dfe
JP		 1212 ata_dev_info(dev,
1213 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1214 }
1215}
1216
bbb4ab43 1217unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1218{
1219 void __iomem *port_mmio = ahci_port_base(ap);
1220 struct ata_taskfile tf;
1221 u32 tmp;
1222
1223 tmp = readl(port_mmio + PORT_SIG);
1224 tf.lbah = (tmp >> 24) & 0xff;
1225 tf.lbam = (tmp >> 16) & 0xff;
1226 tf.lbal = (tmp >> 8) & 0xff;
1227 tf.nsect = (tmp) & 0xff;
1228
1229 return ata_dev_classify(&tf);
1230}
bbb4ab43 1231EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1232
02cdfcf0
DM		 1233void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1234 u32 opts)
365cfa1e
AV		 1235{
1236 dma_addr_t cmd_tbl_dma;
1237
1238 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1239
1240 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1241 pp->cmd_slot[tag].status = 0;
1242 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1243 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1244}
02cdfcf0 1245EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1246
1247int ahci_kick_engine(struct ata_port *ap)
1248{
1249 void __iomem *port_mmio = ahci_port_base(ap);
1250 struct ahci_host_priv *hpriv = ap->host->private_data;
1251 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1252 u32 tmp;
1253 int busy, rc;
1254
1255 /* stop engine */
1256 rc = ahci_stop_engine(ap);
1257 if (rc)
1258 goto out_restart;
1259
1260 /* need to do CLO?
1261 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1262 */
1263 busy = status & (ATA_BUSY | ATA_DRQ);
1264 if (!busy && !sata_pmp_attached(ap)) {
1265 rc = 0;
1266 goto out_restart;
1267 }
1268
1269 if (!(hpriv->cap & HOST_CAP_CLO)) {
1270 rc = -EOPNOTSUPP;
1271 goto out_restart;
1272 }
1273
1274 /* perform CLO */
1275 tmp = readl(port_mmio + PORT_CMD);
1276 tmp |= PORT_CMD_CLO;
1277 writel(tmp, port_mmio + PORT_CMD);
1278
1279 rc = 0;
97750ceb 1280 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1281 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1282 if (tmp & PORT_CMD_CLO)
1283 rc = -EIO;
1284
1285 /* restart engine */
1286 out_restart:
039ece38 1287 hpriv->start_engine(ap);
365cfa1e
AV		 1288 return rc;
1289}
1290EXPORT_SYMBOL_GPL(ahci_kick_engine);
1291
1292static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1293 struct ata_taskfile *tf, int is_cmd, u16 flags,
1294 unsigned long timeout_msec)
1295{
1296 const u32 cmd_fis_len = 5; /* five dwords */
1297 struct ahci_port_priv *pp = ap->private_data;
1298 void __iomem *port_mmio = ahci_port_base(ap);
1299 u8 *fis = pp->cmd_tbl;
1300 u32 tmp;
1301
1302 /* prep the command */
1303 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1304 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1305
023113d2
XY		 1306 /* set port value for softreset of Port Multiplier */
1307 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1308 tmp = readl(port_mmio + PORT_FBS);
1309 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1310 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1311 writel(tmp, port_mmio + PORT_FBS);
1312 pp->fbs_last_dev = pmp;
1313 }
1314
365cfa1e
AV		 1315 /* issue & wait */
1316 writel(1, port_mmio + PORT_CMD_ISSUE);
1317
1318 if (timeout_msec) {
97750ceb
TH		 1319 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1320 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1321 if (tmp & 0x1) {
1322 ahci_kick_engine(ap);
1323 return -EBUSY;
1324 }
1325 } else
1326 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1327
1328 return 0;
1329}
1330
1331int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1332 int pmp, unsigned long deadline,
1333 int (*check_ready)(struct ata_link *link))
1334{
1335 struct ata_port *ap = link->ap;
1336 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1337 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1338 const char *reason = NULL;
1339 unsigned long now, msecs;
1340 struct ata_taskfile tf;
89dafa20 1341 bool fbs_disabled = false;
365cfa1e
AV		 1342 int rc;
1343
1344 DPRINTK("ENTER\n");
1345
1346 /* prepare for SRST (AHCI-1.1 10.4.1) */
1347 rc = ahci_kick_engine(ap);
1348 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1349 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1350
89dafa20 1351 /*
1352 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1353 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1354 * that is attached to port multiplier.
1355 */
1356 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1357 ahci_disable_fbs(ap);
1358 fbs_disabled = true;
1359 }
1360
365cfa1e
AV		 1361 ata_tf_init(link->device, &tf);
1362
1363 /* issue the first D2H Register FIS */
1364 msecs = 0;
1365 now = jiffies;
f1f5a807 1366 if (time_after(deadline, now))
365cfa1e
AV		 1367 msecs = jiffies_to_msecs(deadline - now);
1368
1369 tf.ctl |= ATA_SRST;
1370 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1371 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1372 rc = -EIO;
1373 reason = "1st FIS failed";
1374 goto fail;
1375 }
1376
1377 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1378 ata_msleep(ap, 1);
365cfa1e
AV		 1379
1380 /* issue the second D2H Register FIS */
1381 tf.ctl &= ~ATA_SRST;
1382 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1383
1384 /* wait for link to become ready */
1385 rc = ata_wait_after_reset(link, deadline, check_ready);
1386 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1387 /*
1388 * Workaround for cases where link online status can't
1389 * be trusted. Treat device readiness timeout as link
1390 * offline.
1391 */
a9a79dfe 1392 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1393 *class = ATA_DEV_NONE;
1394 } else if (rc) {
1395 /* link occupied, -ENODEV too is an error */
1396 reason = "device not ready";
1397 goto fail;
1398 } else
1399 *class = ahci_dev_classify(ap);
1400
89dafa20 1401 /* re-enable FBS if disabled before */
1402 if (fbs_disabled)
1403 ahci_enable_fbs(ap);
1404
365cfa1e
AV		 1405 DPRINTK("EXIT, class=%u\n", *class);
1406 return 0;
1407
1408 fail:
a9a79dfe 1409 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1410 return rc;
1411}
1412
1413int ahci_check_ready(struct ata_link *link)
1414{
1415 void __iomem *port_mmio = ahci_port_base(link->ap);
1416 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1417
1418 return ata_check_ready(status);
1419}
1420EXPORT_SYMBOL_GPL(ahci_check_ready);
1421
1422static int ahci_softreset(struct ata_link *link, unsigned int *class,
1423 unsigned long deadline)
1424{
1425 int pmp = sata_srst_pmp(link);
1426
1427 DPRINTK("ENTER\n");
1428
1429 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1430}
1431EXPORT_SYMBOL_GPL(ahci_do_softreset);
1432
345347c5
YHC		 1433static int ahci_bad_pmp_check_ready(struct ata_link *link)
1434{
1435 void __iomem *port_mmio = ahci_port_base(link->ap);
1436 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1437 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1438
1439 /*
1440 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1441 * which can save timeout delay.
1442 */
1443 if (irq_status & PORT_IRQ_BAD_PMP)
1444 return -EIO;
1445
1446 return ata_check_ready(status);
1447}
1448
35186d05
DY		 1449static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1450 unsigned long deadline)
345347c5
YHC		 1451{
1452 struct ata_port *ap = link->ap;
1453 void __iomem *port_mmio = ahci_port_base(ap);
1454 int pmp = sata_srst_pmp(link);
1455 int rc;
1456 u32 irq_sts;
1457
1458 DPRINTK("ENTER\n");
1459
1460 rc = ahci_do_softreset(link, class, pmp, deadline,
1461 ahci_bad_pmp_check_ready);
1462
1463 /*
1464 * Soft reset fails with IPMS set when PMP is enabled but
1465 * SATA HDD/ODD is connected to SATA port, do soft reset
1466 * again to port 0.
1467 */
1468 if (rc == -EIO) {
1469 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1470 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1471 ata_link_warn(link,
345347c5
YHC		 1472 "applying PMP SRST workaround "
1473 "and retrying\n");
1474 rc = ahci_do_softreset(link, class, 0, deadline,
1475 ahci_check_ready);
1476 }
1477 }
1478
1479 return rc;
1480}
1481
365cfa1e
AV		 1482static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1483 unsigned long deadline)
1484{
1485 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1486 struct ata_port *ap = link->ap;
1487 struct ahci_port_priv *pp = ap->private_data;
039ece38 1488 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1489 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1490 struct ata_taskfile tf;
1491 bool online;
1492 int rc;
1493
1494 DPRINTK("ENTER\n");
1495
1496 ahci_stop_engine(ap);
1497
1498 /* clear D2H reception area to properly wait for D2H FIS */
1499 ata_tf_init(link->device, &tf);
9bbb1b0e 1500 tf.command = ATA_BUSY;
365cfa1e
AV		 1501 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1502
1503 rc = sata_link_hardreset(link, timing, deadline, &online,
1504 ahci_check_ready);
1505
039ece38 1506 hpriv->start_engine(ap);
365cfa1e
AV		 1507
1508 if (online)
1509 *class = ahci_dev_classify(ap);
1510
1511 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1512 return rc;
1513}
1514
1515static void ahci_postreset(struct ata_link *link, unsigned int *class)
1516{
1517 struct ata_port *ap = link->ap;
1518 void __iomem *port_mmio = ahci_port_base(ap);
1519 u32 new_tmp, tmp;
1520
1521 ata_std_postreset(link, class);
1522
1523 /* Make sure port's ATAPI bit is set appropriately */
1524 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1525 if (*class == ATA_DEV_ATAPI)
1526 new_tmp |= PORT_CMD_ATAPI;
1527 else
1528 new_tmp &= ~PORT_CMD_ATAPI;
1529 if (new_tmp != tmp) {
1530 writel(new_tmp, port_mmio + PORT_CMD);
1531 readl(port_mmio + PORT_CMD); /* flush */
1532 }
1533}
1534
1535static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1536{
1537 struct scatterlist *sg;
1538 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1539 unsigned int si;
1540
1541 VPRINTK("ENTER\n");
1542
1543 /*
1544 * Next, the S/G list.
1545 */
1546 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1547 dma_addr_t addr = sg_dma_address(sg);
1548 u32 sg_len = sg_dma_len(sg);
1549
1550 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1551 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1552 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1553 }
1554
1555 return si;
1556}
1557
1558static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1559{
1560 struct ata_port *ap = qc->ap;
1561 struct ahci_port_priv *pp = ap->private_data;
1562
1563 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1564 return ata_std_qc_defer(qc);
1565 else
1566 return sata_pmp_qc_defer_cmd_switch(qc);
1567}
1568
1569static void ahci_qc_prep(struct ata_queued_cmd *qc)
1570{
1571 struct ata_port *ap = qc->ap;
1572 struct ahci_port_priv *pp = ap->private_data;
1573 int is_atapi = ata_is_atapi(qc->tf.protocol);
1574 void *cmd_tbl;
1575 u32 opts;
1576 const u32 cmd_fis_len = 5; /* five dwords */
1577 unsigned int n_elem;
1578
1579 /*
1580 * Fill in command table information. First, the header,
1581 * a SATA Register - Host to Device command FIS.
1582 */
1583 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1584
1585 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1586 if (is_atapi) {
1587 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1588 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1589 }
1590
1591 n_elem = 0;
1592 if (qc->flags & ATA_QCFLAG_DMAMAP)
1593 n_elem = ahci_fill_sg(qc, cmd_tbl);
1594
1595 /*
1596 * Fill in command slot information.
1597 */
1598 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1599 if (qc->tf.flags & ATA_TFLAG_WRITE)
1600 opts |= AHCI_CMD_WRITE;
1601 if (is_atapi)
1602 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1603
1604 ahci_fill_cmd_slot(pp, qc->tag, opts);
1605}
1606
1607static void ahci_fbs_dec_intr(struct ata_port *ap)
1608{
1609 struct ahci_port_priv *pp = ap->private_data;
1610 void __iomem *port_mmio = ahci_port_base(ap);
1611 u32 fbs = readl(port_mmio + PORT_FBS);
1612 int retries = 3;
1613
1614 DPRINTK("ENTER\n");
1615 BUG_ON(!pp->fbs_enabled);
1616
1617 /* time to wait for DEC is not specified by AHCI spec,
1618 * add a retry loop for safety.
1619 */
1620 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1621 fbs = readl(port_mmio + PORT_FBS);
1622 while ((fbs & PORT_FBS_DEC) && retries--) {
1623 udelay(1);
1624 fbs = readl(port_mmio + PORT_FBS);
1625 }
1626
1627 if (fbs & PORT_FBS_DEC)
a44fec1f 1628 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1629}
1630
1631static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1632{
1633 struct ahci_host_priv *hpriv = ap->host->private_data;
1634 struct ahci_port_priv *pp = ap->private_data;
1635 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1636 struct ata_link *link = NULL;
1637 struct ata_queued_cmd *active_qc;
1638 struct ata_eh_info *active_ehi;
1639 bool fbs_need_dec = false;
1640 u32 serror;
1641
1642 /* determine active link with error */
1643 if (pp->fbs_enabled) {
1644 void __iomem *port_mmio = ahci_port_base(ap);
1645 u32 fbs = readl(port_mmio + PORT_FBS);
1646 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1647
912b9ac6 1648 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1649 link = &ap->pmp_link[pmp];
1650 fbs_need_dec = true;
1651 }
1652
1653 } else
1654 ata_for_each_link(link, ap, EDGE)
1655 if (ata_link_active(link))
1656 break;
1657
1658 if (!link)
1659 link = &ap->link;
1660
1661 active_qc = ata_qc_from_tag(ap, link->active_tag);
1662 active_ehi = &link->eh_info;
1663
1664 /* record irq stat */
1665 ata_ehi_clear_desc(host_ehi);
1666 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1667
1668 /* AHCI needs SError cleared; otherwise, it might lock up */
1669 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1670 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1671 host_ehi->serror |= serror;
1672
1673 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1674 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1675 irq_stat &= ~PORT_IRQ_IF_ERR;
1676
1677 if (irq_stat & PORT_IRQ_TF_ERR) {
1678 /* If qc is active, charge it; otherwise, the active
1679 * link. There's no active qc on NCQ errors. It will
1680 * be determined by EH by reading log page 10h.
1681 */
1682 if (active_qc)
1683 active_qc->err_mask |= AC_ERR_DEV;
1684 else
1685 active_ehi->err_mask |= AC_ERR_DEV;
1686
1687 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1688 host_ehi->serror &= ~SERR_INTERNAL;
1689 }
1690
1691 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1692 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1693
1694 active_ehi->err_mask |= AC_ERR_HSM;
1695 active_ehi->action |= ATA_EH_RESET;
1696 ata_ehi_push_desc(active_ehi,
1697 "unknown FIS %08x %08x %08x %08x" ,
1698 unk[0], unk[1], unk[2], unk[3]);
1699 }
1700
1701 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1702 active_ehi->err_mask |= AC_ERR_HSM;
1703 active_ehi->action |= ATA_EH_RESET;
1704 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1705 }
1706
1707 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1708 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1709 host_ehi->action |= ATA_EH_RESET;
1710 ata_ehi_push_desc(host_ehi, "host bus error");
1711 }
1712
1713 if (irq_stat & PORT_IRQ_IF_ERR) {
1714 if (fbs_need_dec)
1715 active_ehi->err_mask |= AC_ERR_DEV;
1716 else {
1717 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1718 host_ehi->action |= ATA_EH_RESET;
1719 }
1720
1721 ata_ehi_push_desc(host_ehi, "interface fatal error");
1722 }
1723
1724 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1725 ata_ehi_hotplugged(host_ehi);
1726 ata_ehi_push_desc(host_ehi, "%s",
1727 irq_stat & PORT_IRQ_CONNECT ?
1728 "connection status changed" : "PHY RDY changed");
1729 }
1730
1731 /* okay, let's hand over to EH */
1732
1733 if (irq_stat & PORT_IRQ_FREEZE)
1734 ata_port_freeze(ap);
1735 else if (fbs_need_dec) {
1736 ata_link_abort(link);
1737 ahci_fbs_dec_intr(ap);
1738 } else
1739 ata_port_abort(ap);
1740}
1741
5ca72c4f
AG		 1742static void ahci_handle_port_interrupt(struct ata_port *ap,
1743 void __iomem *port_mmio, u32 status)
365cfa1e 1744{
365cfa1e
AV		 1745 struct ata_eh_info *ehi = &ap->link.eh_info;
1746 struct ahci_port_priv *pp = ap->private_data;
1747 struct ahci_host_priv *hpriv = ap->host->private_data;
1748 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1749 u32 qc_active = 0;
365cfa1e
AV		 1750 int rc;
1751
365cfa1e
AV		 1752 /* ignore BAD_PMP while resetting */
1753 if (unlikely(resetting))
1754 status &= ~PORT_IRQ_BAD_PMP;
1755
8393b811 1756 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1757 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1758 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1759 }
1760
1761 if (unlikely(status & PORT_IRQ_ERROR)) {
1762 ahci_error_intr(ap, status);
1763 return;
1764 }
1765
1766 if (status & PORT_IRQ_SDB_FIS) {
1767 /* If SNotification is available, leave notification
1768 * handling to sata_async_notification(). If not,
1769 * emulate it by snooping SDB FIS RX area.
1770 *
1771 * Snooping FIS RX area is probably cheaper than
1772 * poking SNotification but some constrollers which
1773 * implement SNotification, ICH9 for example, don't
1774 * store AN SDB FIS into receive area.
1775 */
1776 if (hpriv->cap & HOST_CAP_SNTF)
1777 sata_async_notification(ap);
1778 else {
1779 /* If the 'N' bit in word 0 of the FIS is set,
1780 * we just received asynchronous notification.
1781 * Tell libata about it.
1782 *
1783 * Lack of SNotification should not appear in
1784 * ahci 1.2, so the workaround is unnecessary
1785 * when FBS is enabled.
1786 */
1787 if (pp->fbs_enabled)
1788 WARN_ON_ONCE(1);
1789 else {
1790 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1791 u32 f0 = le32_to_cpu(f[0]);
1792 if (f0 & (1 << 15))
1793 sata_async_notification(ap);
1794 }
1795 }
1796 }
1797
1798 /* pp->active_link is not reliable once FBS is enabled, both
1799 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1800 * NCQ and non-NCQ commands may be in flight at the same time.
1801 */
1802 if (pp->fbs_enabled) {
1803 if (ap->qc_active) {
1804 qc_active = readl(port_mmio + PORT_SCR_ACT);
1805 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1806 }
1807 } else {
1808 /* pp->active_link is valid iff any command is in flight */
1809 if (ap->qc_active && pp->active_link->sactive)
1810 qc_active = readl(port_mmio + PORT_SCR_ACT);
1811 else
1812 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1813 }
1814
1815
1816 rc = ata_qc_complete_multiple(ap, qc_active);
1817
1818 /* while resetting, invalid completions are expected */
1819 if (unlikely(rc < 0 && !resetting)) {
1820 ehi->err_mask |= AC_ERR_HSM;
1821 ehi->action |= ATA_EH_RESET;
1822 ata_port_freeze(ap);
1823 }
1824}
1825
7865f83f 1826static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1827{
1828 void __iomem *port_mmio = ahci_port_base(ap);
1829 u32 status;
1830
1831 status = readl(port_mmio + PORT_IRQ_STAT);
1832 writel(status, port_mmio + PORT_IRQ_STAT);
1833
7865f83f 1834 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1835}
1836
a6b7fb76 1837static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1838{
1839 struct ata_port *ap = dev_instance;
5ca72c4f 1840 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1841 u32 status;
1842
5ca72c4f
AG		 1843 VPRINTK("ENTER\n");
1844
227dfb4d
AG		 1845 status = readl(port_mmio + PORT_IRQ_STAT);
1846 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1847
a6b7fb76
DW		 1848 spin_lock(ap->lock);
1849 ahci_handle_port_interrupt(ap, port_mmio, status);
1850 spin_unlock(ap->lock);
5ca72c4f
AG		 1851
1852 VPRINTK("EXIT\n");
1853
a6b7fb76 1854 return IRQ_HANDLED;
5ca72c4f 1855}
5ca72c4f 1856
f070d671 1857u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1858{
365cfa1e 1859 unsigned int i, handled = 0;
03e83cbd 1860
365cfa1e
AV		 1861 for (i = 0; i < host->n_ports; i++) {
1862 struct ata_port *ap;
1863
1864 if (!(irq_masked & (1 << i)))
1865 continue;
1866
1867 ap = host->ports[i];
1868 if (ap) {
7865f83f 1869 ahci_port_intr(ap);
365cfa1e
AV		 1870 VPRINTK("port %u\n", i);
1871 } else {
1872 VPRINTK("port %u (no irq)\n", i);
1873 if (ata_ratelimit())
a44fec1f
JP		 1874 dev_warn(host->dev,
1875 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1876 }
1877
1878 handled = 1;
1879 }
1880
a129db89
ST		 1881 return handled;
1882}
f070d671 1883EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89 1884
5903b164 1885static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
365cfa1e
AV		 1886{
1887 struct ata_host *host = dev_instance;
1888 struct ahci_host_priv *hpriv;
5903b164 1889 unsigned int rc = 0;
365cfa1e
AV		 1890 void __iomem *mmio;
1891 u32 irq_stat, irq_masked;
1892
1893 VPRINTK("ENTER\n");
1894
1895 hpriv = host->private_data;
1896 mmio = hpriv->mmio;
1897
1898 /* sigh. 0xffffffff is a valid return from h/w */
1899 irq_stat = readl(mmio + HOST_IRQ_STAT);
1900 if (!irq_stat)
1901 return IRQ_NONE;
1902
1903 irq_masked = irq_stat & hpriv->port_map;
1904
03e83cbd
TH		 1905 spin_lock(&host->lock);
1906
5903b164
ST		 1907 /*
1908 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1909 * it should be cleared before all the port events are cleared.
1910 */
1911 writel(irq_stat, mmio + HOST_IRQ_STAT);
365cfa1e 1912
5903b164 1913 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e 1914
5903b164 1915 spin_unlock(&host->lock);
365cfa1e 1916
5903b164
ST		 1917 VPRINTK("EXIT\n");
1918
1919 return IRQ_RETVAL(rc);
1920}
1921
a129db89
ST		 1922static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1923{
1924 struct ata_host *host = dev_instance;
1925 struct ahci_host_priv *hpriv;
1926 unsigned int rc = 0;
1927 void __iomem *mmio;
1928 u32 irq_stat, irq_masked;
1929
1930 VPRINTK("ENTER\n");
1931
1932 hpriv = host->private_data;
1933 mmio = hpriv->mmio;
1934
1935 /* sigh. 0xffffffff is a valid return from h/w */
1936 irq_stat = readl(mmio + HOST_IRQ_STAT);
1937 if (!irq_stat)
1938 return IRQ_NONE;
1939
1940 irq_masked = irq_stat & hpriv->port_map;
1941
1942 spin_lock(&host->lock);
1943
1944 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1945
1946 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1947 * it should be cleared after all the port events are cleared;
1948 * otherwise, it will raise a spurious interrupt after each
1949 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1950 * information.
1951 *
1952 * Also, use the unmasked value to clear interrupt as spurious
1953 * pending event on a dummy port might cause screaming IRQ.
1954 */
1955 writel(irq_stat, mmio + HOST_IRQ_STAT);
1956
03e83cbd
TH		 1957 spin_unlock(&host->lock);
1958
365cfa1e
AV		 1959 VPRINTK("EXIT\n");
1960
a129db89 1961 return IRQ_RETVAL(rc);
365cfa1e 1962}
365cfa1e 1963
39e0ee99 1964unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1965{
1966 struct ata_port *ap = qc->ap;
1967 void __iomem *port_mmio = ahci_port_base(ap);
1968 struct ahci_port_priv *pp = ap->private_data;
1969
1970 /* Keep track of the currently active link. It will be used
1971 * in completion path to determine whether NCQ phase is in
1972 * progress.
1973 */
1974 pp->active_link = qc->dev->link;
1975
1976 if (qc->tf.protocol == ATA_PROT_NCQ)
1977 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1978
1979 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1980 u32 fbs = readl(port_mmio + PORT_FBS);
1981 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1982 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1983 writel(fbs, port_mmio + PORT_FBS);
1984 pp->fbs_last_dev = qc->dev->link->pmp;
1985 }
1986
1987 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1988
1989 ahci_sw_activity(qc->dev->link);
1990
1991 return 0;
1992}
39e0ee99 1993EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 1994
1995static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1996{
1997 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1998 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1999
2000 if (pp->fbs_enabled)
6ad60195
TH		 2001 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2002
2003 /*
2004 * After a successful execution of an ATA PIO data-in command,
2005 * the device doesn't send D2H Reg FIS to update the TF and
2006 * the host should take TF and E_Status from the preceding PIO
2007 * Setup FIS.
2008 */
2009 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2010 !(qc->flags & ATA_QCFLAG_FAILED)) {
2011 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2012 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2013 } else
2014 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2015
365cfa1e
AV		 2016 return true;
2017}
2018
2019static void ahci_freeze(struct ata_port *ap)
2020{
2021 void __iomem *port_mmio = ahci_port_base(ap);
2022
2023 /* turn IRQ off */
2024 writel(0, port_mmio + PORT_IRQ_MASK);
2025}
2026
2027static void ahci_thaw(struct ata_port *ap)
2028{
2029 struct ahci_host_priv *hpriv = ap->host->private_data;
2030 void __iomem *mmio = hpriv->mmio;
2031 void __iomem *port_mmio = ahci_port_base(ap);
2032 u32 tmp;
2033 struct ahci_port_priv *pp = ap->private_data;
2034
2035 /* clear IRQ */
2036 tmp = readl(port_mmio + PORT_IRQ_STAT);
2037 writel(tmp, port_mmio + PORT_IRQ_STAT);
2038 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2039
2040 /* turn IRQ back on */
2041 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2042}
2043
8b789d89 2044void ahci_error_handler(struct ata_port *ap)
365cfa1e 2045{
039ece38
HG		 2046 struct ahci_host_priv *hpriv = ap->host->private_data;
2047
365cfa1e
AV		 2048 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2049 /* restart engine */
2050 ahci_stop_engine(ap);
039ece38 2051 hpriv->start_engine(ap);
365cfa1e
AV		 2052 }
2053
2054 sata_pmp_error_handler(ap);
0ee71952
TH		 2055
2056 if (!ata_dev_enabled(ap->link.device))
2057 ahci_stop_engine(ap);
365cfa1e 2058}
8b789d89 2059EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2060
2061static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2062{
2063 struct ata_port *ap = qc->ap;
2064
2065 /* make DMA engine forget about the failed command */
2066 if (qc->flags & ATA_QCFLAG_FAILED)
2067 ahci_kick_engine(ap);
2068}
2069
65fe1f0f
SH		 2070static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2071{
039ece38 2072 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2073 void __iomem *port_mmio = ahci_port_base(ap);
2074 struct ata_device *dev = ap->link.device;
2075 u32 devslp, dm, dito, mdat, deto;
2076 int rc;
2077 unsigned int err_mask;
2078
2079 devslp = readl(port_mmio + PORT_DEVSLP);
2080 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2081 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2082 return;
2083 }
2084
2085 /* disable device sleep */
2086 if (!sleep) {
2087 if (devslp & PORT_DEVSLP_ADSE) {
2088 writel(devslp & ~PORT_DEVSLP_ADSE,
2089 port_mmio + PORT_DEVSLP);
2090 err_mask = ata_dev_set_feature(dev,
2091 SETFEATURES_SATA_DISABLE,
2092 SATA_DEVSLP);
2093 if (err_mask && err_mask != AC_ERR_DEV)
2094 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2095 }
2096 return;
2097 }
2098
2099 /* device sleep was already enabled */
2100 if (devslp & PORT_DEVSLP_ADSE)
2101 return;
2102
2103 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2104 rc = ahci_stop_engine(ap);
2105 if (rc)
2106 return;
2107
2108 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2109 dito = devslp_idle_timeout / (dm + 1);
2110 if (dito > 0x3ff)
2111 dito = 0x3ff;
2112
2113 /* Use the nominal value 10 ms if the read MDAT is zero,
2114 * the nominal value of DETO is 20 ms.
2115 */
803739d2 2116 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2117 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2118 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2119 ATA_LOG_DEVSLP_MDAT_MASK;
2120 if (!mdat)
2121 mdat = 10;
803739d2 2122 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2123 if (!deto)
2124 deto = 20;
2125 } else {
2126 mdat = 10;
2127 deto = 20;
2128 }
2129
2130 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2131 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2132 (deto << PORT_DEVSLP_DETO_OFFSET) |
2133 PORT_DEVSLP_ADSE);
2134 writel(devslp, port_mmio + PORT_DEVSLP);
2135
039ece38 2136 hpriv->start_engine(ap);
65fe1f0f
SH		 2137
2138 /* enable device sleep feature for the drive */
2139 err_mask = ata_dev_set_feature(dev,
2140 SETFEATURES_SATA_ENABLE,
2141 SATA_DEVSLP);
2142 if (err_mask && err_mask != AC_ERR_DEV)
2143 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2144}
2145
365cfa1e
AV		 2146static void ahci_enable_fbs(struct ata_port *ap)
2147{
039ece38 2148 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2149 struct ahci_port_priv *pp = ap->private_data;
2150 void __iomem *port_mmio = ahci_port_base(ap);
2151 u32 fbs;
2152 int rc;
2153
2154 if (!pp->fbs_supported)
2155 return;
2156
2157 fbs = readl(port_mmio + PORT_FBS);
2158 if (fbs & PORT_FBS_EN) {
2159 pp->fbs_enabled = true;
2160 pp->fbs_last_dev = -1; /* initialization */
2161 return;
2162 }
2163
2164 rc = ahci_stop_engine(ap);
2165 if (rc)
2166 return;
2167
2168 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2169 fbs = readl(port_mmio + PORT_FBS);
2170 if (fbs & PORT_FBS_EN) {
a44fec1f 2171 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2172 pp->fbs_enabled = true;
2173 pp->fbs_last_dev = -1; /* initialization */
2174 } else
a44fec1f 2175 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2176
039ece38 2177 hpriv->start_engine(ap);
365cfa1e
AV		 2178}
2179
2180static void ahci_disable_fbs(struct ata_port *ap)
2181{
039ece38 2182 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2183 struct ahci_port_priv *pp = ap->private_data;
2184 void __iomem *port_mmio = ahci_port_base(ap);
2185 u32 fbs;
2186 int rc;
2187
2188 if (!pp->fbs_supported)
2189 return;
2190
2191 fbs = readl(port_mmio + PORT_FBS);
2192 if ((fbs & PORT_FBS_EN) == 0) {
2193 pp->fbs_enabled = false;
2194 return;
2195 }
2196
2197 rc = ahci_stop_engine(ap);
2198 if (rc)
2199 return;
2200
2201 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2202 fbs = readl(port_mmio + PORT_FBS);
2203 if (fbs & PORT_FBS_EN)
a44fec1f 2204 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2205 else {
a44fec1f 2206 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2207 pp->fbs_enabled = false;
2208 }
2209
039ece38 2210 hpriv->start_engine(ap);
365cfa1e
AV		 2211}
2212
2213static void ahci_pmp_attach(struct ata_port *ap)
2214{
2215 void __iomem *port_mmio = ahci_port_base(ap);
2216 struct ahci_port_priv *pp = ap->private_data;
2217 u32 cmd;
2218
2219 cmd = readl(port_mmio + PORT_CMD);
2220 cmd |= PORT_CMD_PMP;
2221 writel(cmd, port_mmio + PORT_CMD);
2222
2223 ahci_enable_fbs(ap);
2224
2225 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2226
2227 /*
2228 * We must not change the port interrupt mask register if the
2229 * port is marked frozen, the value in pp->intr_mask will be
2230 * restored later when the port is thawed.
2231 *
2232 * Note that during initialization, the port is marked as
2233 * frozen since the irq handler is not yet registered.
2234 */
2235 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2236 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2237}
2238
2239static void ahci_pmp_detach(struct ata_port *ap)
2240{
2241 void __iomem *port_mmio = ahci_port_base(ap);
2242 struct ahci_port_priv *pp = ap->private_data;
2243 u32 cmd;
2244
2245 ahci_disable_fbs(ap);
2246
2247 cmd = readl(port_mmio + PORT_CMD);
2248 cmd &= ~PORT_CMD_PMP;
2249 writel(cmd, port_mmio + PORT_CMD);
2250
2251 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2252
2253 /* see comment above in ahci_pmp_attach() */
2254 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2255 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2256}
2257
02cdfcf0 2258int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2259{
2260 ahci_power_up(ap);
2261 ahci_start_port(ap);
2262
2263 if (sata_pmp_attached(ap))
2264 ahci_pmp_attach(ap);
2265 else
2266 ahci_pmp_detach(ap);
2267
2268 return 0;
2269}
02cdfcf0 2270EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2271
2272#ifdef CONFIG_PM
2273static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2274{
2275 const char *emsg = NULL;
2276 int rc;
2277
2278 rc = ahci_deinit_port(ap, &emsg);
2279 if (rc == 0)
2280 ahci_power_down(ap);
2281 else {
a9a79dfe 2282 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2283 ata_port_freeze(ap);
365cfa1e
AV		 2284 }
2285
2286 return rc;
2287}
2288#endif
2289
2290static int ahci_port_start(struct ata_port *ap)
2291{
2292 struct ahci_host_priv *hpriv = ap->host->private_data;
2293 struct device *dev = ap->host->dev;
2294 struct ahci_port_priv *pp;
2295 void *mem;
2296 dma_addr_t mem_dma;
2297 size_t dma_sz, rx_fis_sz;
2298
2299 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2300 if (!pp)
2301 return -ENOMEM;
2302
b29900e6
AG		 2303 if (ap->host->n_ports > 1) {
2304 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2305 if (!pp->irq_desc) {
2306 devm_kfree(dev, pp);
2307 return -ENOMEM;
2308 }
2309 snprintf(pp->irq_desc, 8,
2310 "%s%d", dev_driver_string(dev), ap->port_no);
2311 }
2312
365cfa1e
AV		 2313 /* check FBS capability */
2314 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2315 void __iomem *port_mmio = ahci_port_base(ap);
2316 u32 cmd = readl(port_mmio + PORT_CMD);
2317 if (cmd & PORT_CMD_FBSCP)
2318 pp->fbs_supported = true;
5f173107 2319 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2320 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2321 ap->port_no);
5f173107
TH		 2322 pp->fbs_supported = true;
2323 } else
a44fec1f
JP		 2324 dev_warn(dev, "port %d is not capable of FBS\n",
2325 ap->port_no);
365cfa1e
AV		 2326 }
2327
2328 if (pp->fbs_supported) {
2329 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2330 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2331 } else {
2332 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2333 rx_fis_sz = AHCI_RX_FIS_SZ;
2334 }
2335
2336 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2337 if (!mem)
2338 return -ENOMEM;
2339 memset(mem, 0, dma_sz);
2340
2341 /*
2342 * First item in chunk of DMA memory: 32-slot command table,
2343 * 32 bytes each in size
2344 */
2345 pp->cmd_slot = mem;
2346 pp->cmd_slot_dma = mem_dma;
2347
2348 mem += AHCI_CMD_SLOT_SZ;
2349 mem_dma += AHCI_CMD_SLOT_SZ;
2350
2351 /*
2352 * Second item: Received-FIS area
2353 */
2354 pp->rx_fis = mem;
2355 pp->rx_fis_dma = mem_dma;
2356
2357 mem += rx_fis_sz;
2358 mem_dma += rx_fis_sz;
2359
2360 /*
2361 * Third item: data area for storing a single command
2362 * and its scatter-gather table
2363 */
2364 pp->cmd_tbl = mem;
2365 pp->cmd_tbl_dma = mem_dma;
2366
2367 /*
2368 * Save off initial list of interrupts to be enabled.
2369 * This could be changed later
2370 */
2371 pp->intr_mask = DEF_PORT_IRQ;
2372
7865f83f
TH		 2373 /*
2374 * Switch to per-port locking in case each port has its own MSI vector.
2375 */
21bfd1aa 2376 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2377 spin_lock_init(&pp->lock);
2378 ap->lock = &pp->lock;
2379 }
5ca72c4f 2380
365cfa1e
AV		 2381 ap->private_data = pp;
2382
2383 /* engage engines, captain */
2384 return ahci_port_resume(ap);
2385}
2386
2387static void ahci_port_stop(struct ata_port *ap)
2388{
2389 const char *emsg = NULL;
2390 int rc;
2391
2392 /* de-initialize port */
2393 rc = ahci_deinit_port(ap, &emsg);
2394 if (rc)
a9a79dfe 2395 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2396}
2397
2398void ahci_print_info(struct ata_host *host, const char *scc_s)
2399{
2400 struct ahci_host_priv *hpriv = host->private_data;
2401 void __iomem *mmio = hpriv->mmio;
2402 u32 vers, cap, cap2, impl, speed;
2403 const char *speed_s;
2404
2405 vers = readl(mmio + HOST_VERSION);
2406 cap = hpriv->cap;
2407 cap2 = hpriv->cap2;
2408 impl = hpriv->port_map;
2409
2410 speed = (cap >> 20) & 0xf;
2411 if (speed == 1)
2412 speed_s = "1.5";
2413 else if (speed == 2)
2414 speed_s = "3";
2415 else if (speed == 3)
2416 speed_s = "6";
2417 else
2418 speed_s = "?";
2419
2420 dev_info(host->dev,
2421 "AHCI %02x%02x.%02x%02x "
2422 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2423 ,
2424
2425 (vers >> 24) & 0xff,
2426 (vers >> 16) & 0xff,
2427 (vers >> 8) & 0xff,
2428 vers & 0xff,
2429
2430 ((cap >> 8) & 0x1f) + 1,
2431 (cap & 0x1f) + 1,
2432 speed_s,
2433 impl,
2434 scc_s);
2435
2436 dev_info(host->dev,
2437 "flags: "
2438 "%s%s%s%s%s%s%s"
2439 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2440 "%s%s%s%s%s%s%s"
2441 "%s%s\n"
365cfa1e
AV		 2442 ,
2443
2444 cap & HOST_CAP_64 ? "64bit " : "",
2445 cap & HOST_CAP_NCQ ? "ncq " : "",
2446 cap & HOST_CAP_SNTF ? "sntf " : "",
2447 cap & HOST_CAP_MPS ? "ilck " : "",
2448 cap & HOST_CAP_SSS ? "stag " : "",
2449 cap & HOST_CAP_ALPM ? "pm " : "",
2450 cap & HOST_CAP_LED ? "led " : "",
2451 cap & HOST_CAP_CLO ? "clo " : "",
2452 cap & HOST_CAP_ONLY ? "only " : "",
2453 cap & HOST_CAP_PMP ? "pmp " : "",
2454 cap & HOST_CAP_FBS ? "fbs " : "",
2455 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2456 cap & HOST_CAP_SSC ? "slum " : "",
2457 cap & HOST_CAP_PART ? "part " : "",
2458 cap & HOST_CAP_CCC ? "ccc " : "",
2459 cap & HOST_CAP_EMS ? "ems " : "",
2460 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2461 cap2 & HOST_CAP2_DESO ? "deso " : "",
2462 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2463 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2464 cap2 & HOST_CAP2_APST ? "apst " : "",
2465 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2466 cap2 & HOST_CAP2_BOH ? "boh " : ""
2467 );
2468}
2469EXPORT_SYMBOL_GPL(ahci_print_info);
2470
2471void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2472 struct ata_port_info *pi)
2473{
2474 u8 messages;
2475 void __iomem *mmio = hpriv->mmio;
2476 u32 em_loc = readl(mmio + HOST_EM_LOC);
2477 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2478
2479 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2480 return;
2481
2482 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2483
008dbd61 2484 if (messages) {
365cfa1e
AV		 2485 /* store em_loc */
2486 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2487 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2488 hpriv->em_msg_type = messages;
365cfa1e
AV		 2489 pi->flags |= ATA_FLAG_EM;
2490 if (!(em_ctl & EM_CTL_ALHD))
2491 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2492 }
2493}
2494EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2495
d684a90d 2496static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2497 struct scsi_host_template *sht)
1c62854f 2498{
d684a90d 2499 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2500 int i, rc;
2501
2502 rc = ata_host_start(host);
2503 if (rc)
2504 return rc;
21bfd1aa
RR		 2505 /*
2506 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2507 * allocated. That is one MSI per port, starting from @irq.
2508 */
1c62854f
AG		 2509 for (i = 0; i < host->n_ports; i++) {
2510 struct ahci_port_priv *pp = host->ports[i]->private_data;
f893180b 2511 int irq = ahci_irq_vector(hpriv, i);
1c62854f
AG		 2512
2513 /* Do not receive interrupts sent by dummy ports */
2514 if (!pp) {
2515 disable_irq(irq + i);
2516 continue;
2517 }
2518
a6b7fb76
DW		 2519 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2520 0, pp->irq_desc, host->ports[i]);
2521
1c62854f 2522 if (rc)
0a142b26 2523 return rc;
d684a90d 2524 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2525 }
d684a90d 2526
0a142b26 2527 return ata_host_register(host, sht);
1c62854f 2528}
d1028e2f
AG		 2529
2530/**
2531 * ahci_host_activate - start AHCI host, request IRQs and register it
2532 * @host: target ATA host
d1028e2f
AG		 2533 * @sht: scsi_host_template to use when registering the host
2534 *
d1028e2f
AG		 2535 * LOCKING:
2536 * Inherited from calling layer (may sleep).
2537 *
2538 * RETURNS:
2539 * 0 on success, -errno otherwise.
2540 */
21bfd1aa 2541int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2542{
2543 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2544 int irq = hpriv->irq;
d1028e2f
AG		 2545 int rc;
2546
f070d671
ST		 2547 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
2548 if (hpriv->irq_handler)
2549 dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
2550 and custom irq handler implemented\n");
2551
d684a90d 2552 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2553 } else {
2554 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2555 IRQF_SHARED, sht);
f070d671
ST		 2556 }
2557
2558
d1028e2f
AG		 2559 return rc;
2560}
1c62854f
AG		 2561EXPORT_SYMBOL_GPL(ahci_host_activate);
2562
365cfa1e
AV		 2563MODULE_AUTHOR("Jeff Garzik");
2564MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2565MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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