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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
624d5c51 | 38 | #include <linux/highmem.h> |
1fdffbce JG |
39 | |
40 | #include "libata.h" | |
41 | ||
624d5c51 TH |
42 | const struct ata_port_operations ata_sff_port_ops = { |
43 | .inherits = &ata_base_port_ops, | |
44 | ||
9363c382 TH |
45 | .qc_prep = ata_sff_qc_prep, |
46 | .qc_issue = ata_sff_qc_issue, | |
4c9bf4e7 | 47 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
48 | |
49 | .freeze = ata_sff_freeze, | |
50 | .thaw = ata_sff_thaw, | |
0aa1113d | 51 | .prereset = ata_sff_prereset, |
9363c382 | 52 | .softreset = ata_sff_softreset, |
57c9efdf | 53 | .hardreset = sata_sff_hardreset, |
203c75b8 | 54 | .postreset = ata_sff_postreset, |
9363c382 TH |
55 | .error_handler = ata_sff_error_handler, |
56 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
57 | ||
5682ed33 TH |
58 | .sff_dev_select = ata_sff_dev_select, |
59 | .sff_check_status = ata_sff_check_status, | |
60 | .sff_tf_load = ata_sff_tf_load, | |
61 | .sff_tf_read = ata_sff_tf_read, | |
62 | .sff_exec_command = ata_sff_exec_command, | |
63 | .sff_data_xfer = ata_sff_data_xfer, | |
64 | .sff_irq_on = ata_sff_irq_on, | |
288623a0 | 65 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 TH |
66 | |
67 | .port_start = ata_sff_port_start, | |
68 | }; | |
0fe40ff8 | 69 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 TH |
70 | |
71 | const struct ata_port_operations ata_bmdma_port_ops = { | |
72 | .inherits = &ata_sff_port_ops, | |
73 | ||
9363c382 | 74 | .mode_filter = ata_bmdma_mode_filter, |
624d5c51 TH |
75 | |
76 | .bmdma_setup = ata_bmdma_setup, | |
77 | .bmdma_start = ata_bmdma_start, | |
78 | .bmdma_stop = ata_bmdma_stop, | |
79 | .bmdma_status = ata_bmdma_status, | |
624d5c51 | 80 | }; |
0fe40ff8 | 81 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); |
624d5c51 | 82 | |
871af121 AC |
83 | const struct ata_port_operations ata_bmdma32_port_ops = { |
84 | .inherits = &ata_bmdma_port_ops, | |
85 | ||
86 | .sff_data_xfer = ata_sff_data_xfer32, | |
87 | }; | |
88 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
89 | ||
624d5c51 TH |
90 | /** |
91 | * ata_fill_sg - Fill PCI IDE PRD table | |
92 | * @qc: Metadata associated with taskfile to be transferred | |
93 | * | |
94 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
95 | * associated with the current disk command. | |
96 | * | |
97 | * LOCKING: | |
98 | * spin_lock_irqsave(host lock) | |
99 | * | |
100 | */ | |
101 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
102 | { | |
103 | struct ata_port *ap = qc->ap; | |
104 | struct scatterlist *sg; | |
105 | unsigned int si, pi; | |
106 | ||
107 | pi = 0; | |
108 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
109 | u32 addr, offset; | |
110 | u32 sg_len, len; | |
111 | ||
112 | /* determine if physical DMA addr spans 64K boundary. | |
113 | * Note h/w doesn't support 64-bit, so we unconditionally | |
114 | * truncate dma_addr_t to u32. | |
115 | */ | |
116 | addr = (u32) sg_dma_address(sg); | |
117 | sg_len = sg_dma_len(sg); | |
118 | ||
119 | while (sg_len) { | |
120 | offset = addr & 0xffff; | |
121 | len = sg_len; | |
122 | if ((offset + sg_len) > 0x10000) | |
123 | len = 0x10000 - offset; | |
124 | ||
125 | ap->prd[pi].addr = cpu_to_le32(addr); | |
126 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
127 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
128 | ||
129 | pi++; | |
130 | sg_len -= len; | |
131 | addr += len; | |
132 | } | |
133 | } | |
134 | ||
135 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
136 | } | |
137 | ||
138 | /** | |
139 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
140 | * @qc: Metadata associated with taskfile to be transferred | |
141 | * | |
142 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
143 | * associated with the current disk command. Perform the fill | |
144 | * so that we avoid writing any length 64K records for | |
145 | * controllers that don't follow the spec. | |
146 | * | |
147 | * LOCKING: | |
148 | * spin_lock_irqsave(host lock) | |
149 | * | |
150 | */ | |
151 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
152 | { | |
153 | struct ata_port *ap = qc->ap; | |
154 | struct scatterlist *sg; | |
155 | unsigned int si, pi; | |
156 | ||
157 | pi = 0; | |
158 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
159 | u32 addr, offset; | |
160 | u32 sg_len, len, blen; | |
161 | ||
162 | /* determine if physical DMA addr spans 64K boundary. | |
163 | * Note h/w doesn't support 64-bit, so we unconditionally | |
164 | * truncate dma_addr_t to u32. | |
165 | */ | |
166 | addr = (u32) sg_dma_address(sg); | |
167 | sg_len = sg_dma_len(sg); | |
168 | ||
169 | while (sg_len) { | |
170 | offset = addr & 0xffff; | |
171 | len = sg_len; | |
172 | if ((offset + sg_len) > 0x10000) | |
173 | len = 0x10000 - offset; | |
174 | ||
175 | blen = len & 0xffff; | |
176 | ap->prd[pi].addr = cpu_to_le32(addr); | |
177 | if (blen == 0) { | |
0fe40ff8 AC |
178 | /* Some PATA chipsets like the CS5530 can't |
179 | cope with 0x0000 meaning 64K as the spec | |
180 | says */ | |
624d5c51 TH |
181 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); |
182 | blen = 0x8000; | |
183 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
184 | } | |
185 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
186 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
187 | ||
188 | pi++; | |
189 | sg_len -= len; | |
190 | addr += len; | |
191 | } | |
192 | } | |
193 | ||
194 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
195 | } | |
196 | ||
197 | /** | |
9363c382 | 198 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
199 | * @qc: Metadata associated with taskfile to be prepared |
200 | * | |
201 | * Prepare ATA taskfile for submission. | |
202 | * | |
203 | * LOCKING: | |
204 | * spin_lock_irqsave(host lock) | |
205 | */ | |
9363c382 | 206 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
207 | { |
208 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
209 | return; | |
210 | ||
211 | ata_fill_sg(qc); | |
212 | } | |
0fe40ff8 | 213 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
624d5c51 TH |
214 | |
215 | /** | |
9363c382 | 216 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
217 | * @qc: Metadata associated with taskfile to be prepared |
218 | * | |
219 | * Prepare ATA taskfile for submission. | |
220 | * | |
221 | * LOCKING: | |
222 | * spin_lock_irqsave(host lock) | |
223 | */ | |
9363c382 | 224 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
225 | { |
226 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
227 | return; | |
228 | ||
229 | ata_fill_sg_dumb(qc); | |
230 | } | |
0fe40ff8 | 231 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); |
624d5c51 | 232 | |
272f7884 | 233 | /** |
9363c382 | 234 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
235 | * @ap: port where the device is |
236 | * | |
237 | * Reads ATA taskfile status register for currently-selected device | |
238 | * and return its value. This also clears pending interrupts | |
239 | * from this device | |
240 | * | |
241 | * LOCKING: | |
242 | * Inherited from caller. | |
243 | */ | |
9363c382 | 244 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
245 | { |
246 | return ioread8(ap->ioaddr.status_addr); | |
247 | } | |
0fe40ff8 | 248 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
249 | |
250 | /** | |
9363c382 | 251 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
252 | * @ap: port where the device is |
253 | * | |
254 | * Reads ATA taskfile alternate status register for | |
255 | * currently-selected device and return its value. | |
256 | * | |
257 | * Note: may NOT be used as the check_altstatus() entry in | |
258 | * ata_port_operations. | |
259 | * | |
260 | * LOCKING: | |
261 | * Inherited from caller. | |
262 | */ | |
a57c1bad | 263 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 264 | { |
5682ed33 TH |
265 | if (ap->ops->sff_check_altstatus) |
266 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
267 | |
268 | return ioread8(ap->ioaddr.altstatus_addr); | |
269 | } | |
270 | ||
a57c1bad AC |
271 | /** |
272 | * ata_sff_irq_status - Check if the device is busy | |
273 | * @ap: port where the device is | |
274 | * | |
275 | * Determine if the port is currently busy. Uses altstatus | |
276 | * if available in order to avoid clearing shared IRQ status | |
277 | * when finding an IRQ source. Non ctl capable devices don't | |
278 | * share interrupt lines fortunately for us. | |
279 | * | |
280 | * LOCKING: | |
281 | * Inherited from caller. | |
282 | */ | |
283 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
284 | { | |
285 | u8 status; | |
286 | ||
287 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
288 | status = ata_sff_altstatus(ap); | |
289 | /* Not us: We are busy */ | |
290 | if (status & ATA_BUSY) | |
0fe40ff8 | 291 | return status; |
a57c1bad AC |
292 | } |
293 | /* Clear INTRQ latch */ | |
6311c90a | 294 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
295 | return status; |
296 | } | |
297 | ||
298 | /** | |
299 | * ata_sff_sync - Flush writes | |
300 | * @ap: Port to wait for. | |
301 | * | |
302 | * CAUTION: | |
303 | * If we have an mmio device with no ctl and no altstatus | |
304 | * method this will fail. No such devices are known to exist. | |
305 | * | |
306 | * LOCKING: | |
307 | * Inherited from caller. | |
308 | */ | |
309 | ||
310 | static void ata_sff_sync(struct ata_port *ap) | |
311 | { | |
312 | if (ap->ops->sff_check_altstatus) | |
313 | ap->ops->sff_check_altstatus(ap); | |
314 | else if (ap->ioaddr.altstatus_addr) | |
315 | ioread8(ap->ioaddr.altstatus_addr); | |
316 | } | |
317 | ||
318 | /** | |
319 | * ata_sff_pause - Flush writes and wait 400nS | |
320 | * @ap: Port to pause for. | |
321 | * | |
322 | * CAUTION: | |
323 | * If we have an mmio device with no ctl and no altstatus | |
324 | * method this will fail. No such devices are known to exist. | |
325 | * | |
326 | * LOCKING: | |
327 | * Inherited from caller. | |
328 | */ | |
329 | ||
330 | void ata_sff_pause(struct ata_port *ap) | |
331 | { | |
332 | ata_sff_sync(ap); | |
333 | ndelay(400); | |
334 | } | |
0fe40ff8 | 335 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
336 | |
337 | /** | |
338 | * ata_sff_dma_pause - Pause before commencing DMA | |
339 | * @ap: Port to pause for. | |
340 | * | |
341 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
342 | * for the HDMA1:0 transition | |
343 | */ | |
0fe40ff8 | 344 | |
a57c1bad AC |
345 | void ata_sff_dma_pause(struct ata_port *ap) |
346 | { | |
347 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
348 | /* An altstatus read will cause the needed delay without | |
349 | messing up the IRQ status */ | |
350 | ata_sff_altstatus(ap); | |
351 | return; | |
352 | } | |
353 | /* There are no DMA controllers without ctl. BUG here to ensure | |
354 | we never violate the HDMA1:0 transition timing and risk | |
355 | corruption. */ | |
356 | BUG(); | |
357 | } | |
0fe40ff8 | 358 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 359 | |
624d5c51 | 360 | /** |
9363c382 | 361 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 362 | * @ap: port containing status register to be polled |
341c2c95 TH |
363 | * @tmout_pat: impatience timeout in msecs |
364 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
365 | * |
366 | * Sleep until ATA Status register bit BSY clears, | |
367 | * or a timeout occurs. | |
368 | * | |
369 | * LOCKING: | |
370 | * Kernel thread context (may sleep). | |
371 | * | |
372 | * RETURNS: | |
373 | * 0 on success, -errno otherwise. | |
374 | */ | |
9363c382 TH |
375 | int ata_sff_busy_sleep(struct ata_port *ap, |
376 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
377 | { |
378 | unsigned long timer_start, timeout; | |
379 | u8 status; | |
380 | ||
9363c382 | 381 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 382 | timer_start = jiffies; |
341c2c95 | 383 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
384 | while (status != 0xff && (status & ATA_BUSY) && |
385 | time_before(jiffies, timeout)) { | |
386 | msleep(50); | |
9363c382 | 387 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
388 | } |
389 | ||
390 | if (status != 0xff && (status & ATA_BUSY)) | |
391 | ata_port_printk(ap, KERN_WARNING, | |
392 | "port is slow to respond, please be patient " | |
393 | "(Status 0x%x)\n", status); | |
394 | ||
341c2c95 | 395 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
396 | while (status != 0xff && (status & ATA_BUSY) && |
397 | time_before(jiffies, timeout)) { | |
398 | msleep(50); | |
5682ed33 | 399 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
400 | } |
401 | ||
402 | if (status == 0xff) | |
403 | return -ENODEV; | |
404 | ||
405 | if (status & ATA_BUSY) { | |
406 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
407 | "(%lu secs, Status 0x%x)\n", | |
341c2c95 | 408 | DIV_ROUND_UP(tmout, 1000), status); |
624d5c51 TH |
409 | return -EBUSY; |
410 | } | |
411 | ||
412 | return 0; | |
413 | } | |
0fe40ff8 | 414 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 415 | |
aa2731ad TH |
416 | static int ata_sff_check_ready(struct ata_link *link) |
417 | { | |
418 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
419 | ||
78ab88f0 | 420 | return ata_check_ready(status); |
aa2731ad TH |
421 | } |
422 | ||
624d5c51 | 423 | /** |
9363c382 | 424 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 425 | * @link: SFF link to wait ready status for |
624d5c51 TH |
426 | * @deadline: deadline jiffies for the operation |
427 | * | |
428 | * Sleep until ATA Status register bit BSY clears, or timeout | |
429 | * occurs. | |
430 | * | |
431 | * LOCKING: | |
432 | * Kernel thread context (may sleep). | |
433 | * | |
434 | * RETURNS: | |
435 | * 0 on success, -errno otherwise. | |
436 | */ | |
705e76be | 437 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 438 | { |
aa2731ad | 439 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 440 | } |
0fe40ff8 | 441 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 TH |
442 | |
443 | /** | |
9363c382 | 444 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
445 | * @ap: ATA channel to manipulate |
446 | * @device: ATA device (numbered from zero) to select | |
447 | * | |
448 | * Use the method defined in the ATA specification to | |
449 | * make either device 0, or device 1, active on the | |
450 | * ATA channel. Works with both PIO and MMIO. | |
451 | * | |
452 | * May be used as the dev_select() entry in ata_port_operations. | |
453 | * | |
454 | * LOCKING: | |
455 | * caller. | |
456 | */ | |
9363c382 | 457 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
458 | { |
459 | u8 tmp; | |
460 | ||
461 | if (device == 0) | |
462 | tmp = ATA_DEVICE_OBS; | |
463 | else | |
464 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
465 | ||
466 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 467 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 468 | } |
0fe40ff8 | 469 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
470 | |
471 | /** | |
472 | * ata_dev_select - Select device 0/1 on ATA bus | |
473 | * @ap: ATA channel to manipulate | |
474 | * @device: ATA device (numbered from zero) to select | |
475 | * @wait: non-zero to wait for Status register BSY bit to clear | |
476 | * @can_sleep: non-zero if context allows sleeping | |
477 | * | |
478 | * Use the method defined in the ATA specification to | |
479 | * make either device 0, or device 1, active on the | |
480 | * ATA channel. | |
481 | * | |
9363c382 TH |
482 | * This is a high-level version of ata_sff_dev_select(), which |
483 | * additionally provides the services of inserting the proper | |
484 | * pauses and status polling, where needed. | |
624d5c51 TH |
485 | * |
486 | * LOCKING: | |
487 | * caller. | |
488 | */ | |
489 | void ata_dev_select(struct ata_port *ap, unsigned int device, | |
490 | unsigned int wait, unsigned int can_sleep) | |
491 | { | |
492 | if (ata_msg_probe(ap)) | |
493 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
494 | "device %u, wait %u\n", device, wait); | |
495 | ||
496 | if (wait) | |
497 | ata_wait_idle(ap); | |
498 | ||
5682ed33 | 499 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
500 | |
501 | if (wait) { | |
502 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
503 | msleep(150); | |
504 | ata_wait_idle(ap); | |
505 | } | |
506 | } | |
507 | ||
508 | /** | |
9363c382 | 509 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
510 | * @ap: Port on which interrupts are enabled. |
511 | * | |
512 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
513 | * wait for idle, clear any pending interrupts. | |
514 | * | |
515 | * LOCKING: | |
516 | * Inherited from caller. | |
517 | */ | |
9363c382 | 518 | u8 ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
519 | { |
520 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
521 | u8 tmp; | |
522 | ||
523 | ap->ctl &= ~ATA_NIEN; | |
524 | ap->last_ctl = ap->ctl; | |
525 | ||
526 | if (ioaddr->ctl_addr) | |
527 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
528 | tmp = ata_wait_idle(ap); | |
529 | ||
5682ed33 | 530 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
531 | |
532 | return tmp; | |
533 | } | |
0fe40ff8 | 534 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 TH |
535 | |
536 | /** | |
9363c382 | 537 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
538 | * @ap: Port associated with this ATA transaction. |
539 | * | |
540 | * Clear interrupt and error flags in DMA status register. | |
541 | * | |
542 | * May be used as the irq_clear() entry in ata_port_operations. | |
543 | * | |
544 | * LOCKING: | |
545 | * spin_lock_irqsave(host lock) | |
546 | */ | |
9363c382 | 547 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
548 | { |
549 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
550 | ||
551 | if (!mmio) | |
552 | return; | |
553 | ||
554 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
555 | } | |
0fe40ff8 | 556 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); |
624d5c51 TH |
557 | |
558 | /** | |
9363c382 | 559 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
560 | * @ap: Port to which output is sent |
561 | * @tf: ATA taskfile register set | |
562 | * | |
563 | * Outputs ATA taskfile to standard ATA host controller. | |
564 | * | |
565 | * LOCKING: | |
566 | * Inherited from caller. | |
567 | */ | |
9363c382 | 568 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
569 | { |
570 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
571 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
572 | ||
573 | if (tf->ctl != ap->last_ctl) { | |
574 | if (ioaddr->ctl_addr) | |
575 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
576 | ap->last_ctl = tf->ctl; | |
577 | ata_wait_idle(ap); | |
578 | } | |
579 | ||
580 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 581 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
582 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
583 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
584 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
585 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
586 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
587 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
588 | tf->hob_feature, | |
589 | tf->hob_nsect, | |
590 | tf->hob_lbal, | |
591 | tf->hob_lbam, | |
592 | tf->hob_lbah); | |
593 | } | |
594 | ||
595 | if (is_addr) { | |
596 | iowrite8(tf->feature, ioaddr->feature_addr); | |
597 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
598 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
599 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
600 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
601 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
602 | tf->feature, | |
603 | tf->nsect, | |
604 | tf->lbal, | |
605 | tf->lbam, | |
606 | tf->lbah); | |
607 | } | |
608 | ||
609 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
610 | iowrite8(tf->device, ioaddr->device_addr); | |
611 | VPRINTK("device 0x%X\n", tf->device); | |
612 | } | |
613 | ||
614 | ata_wait_idle(ap); | |
615 | } | |
0fe40ff8 | 616 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
617 | |
618 | /** | |
9363c382 | 619 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
620 | * @ap: Port from which input is read |
621 | * @tf: ATA taskfile register set for storing input | |
622 | * | |
623 | * Reads ATA taskfile registers for currently-selected device | |
624 | * into @tf. Assumes the device has a fully SFF compliant task file | |
625 | * layout and behaviour. If you device does not (eg has a different | |
626 | * status method) then you will need to provide a replacement tf_read | |
627 | * | |
628 | * LOCKING: | |
629 | * Inherited from caller. | |
630 | */ | |
9363c382 | 631 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
632 | { |
633 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
634 | ||
9363c382 | 635 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
636 | tf->feature = ioread8(ioaddr->error_addr); |
637 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
638 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
639 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
640 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
641 | tf->device = ioread8(ioaddr->device_addr); | |
642 | ||
643 | if (tf->flags & ATA_TFLAG_LBA48) { | |
644 | if (likely(ioaddr->ctl_addr)) { | |
645 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
646 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
647 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
648 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
649 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
650 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
651 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
652 | ap->last_ctl = tf->ctl; | |
653 | } else | |
efcb3cf7 | 654 | WARN_ON_ONCE(1); |
624d5c51 TH |
655 | } |
656 | } | |
0fe40ff8 | 657 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
658 | |
659 | /** | |
9363c382 | 660 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
661 | * @ap: port to which command is being issued |
662 | * @tf: ATA taskfile register set | |
663 | * | |
664 | * Issues ATA command, with proper synchronization with interrupt | |
665 | * handler / other threads. | |
666 | * | |
667 | * LOCKING: | |
668 | * spin_lock_irqsave(host lock) | |
669 | */ | |
9363c382 | 670 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
671 | { |
672 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
673 | ||
674 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 675 | ata_sff_pause(ap); |
624d5c51 | 676 | } |
0fe40ff8 | 677 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
678 | |
679 | /** | |
680 | * ata_tf_to_host - issue ATA taskfile to host controller | |
681 | * @ap: port to which command is being issued | |
682 | * @tf: ATA taskfile register set | |
683 | * | |
684 | * Issues ATA taskfile register set to ATA host controller, | |
685 | * with proper synchronization with interrupt handler and | |
686 | * other threads. | |
687 | * | |
688 | * LOCKING: | |
689 | * spin_lock_irqsave(host lock) | |
690 | */ | |
691 | static inline void ata_tf_to_host(struct ata_port *ap, | |
692 | const struct ata_taskfile *tf) | |
693 | { | |
5682ed33 TH |
694 | ap->ops->sff_tf_load(ap, tf); |
695 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
696 | } |
697 | ||
698 | /** | |
9363c382 | 699 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
700 | * @dev: device to target |
701 | * @buf: data buffer | |
702 | * @buflen: buffer length | |
703 | * @rw: read/write | |
704 | * | |
705 | * Transfer data from/to the device data register by PIO. | |
706 | * | |
707 | * LOCKING: | |
708 | * Inherited from caller. | |
709 | * | |
710 | * RETURNS: | |
711 | * Bytes consumed. | |
712 | */ | |
9363c382 TH |
713 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
714 | unsigned int buflen, int rw) | |
624d5c51 TH |
715 | { |
716 | struct ata_port *ap = dev->link->ap; | |
717 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
718 | unsigned int words = buflen >> 1; | |
719 | ||
720 | /* Transfer multiple of 2 bytes */ | |
721 | if (rw == READ) | |
722 | ioread16_rep(data_addr, buf, words); | |
723 | else | |
724 | iowrite16_rep(data_addr, buf, words); | |
725 | ||
726 | /* Transfer trailing 1 byte, if any. */ | |
727 | if (unlikely(buflen & 0x01)) { | |
728 | __le16 align_buf[1] = { 0 }; | |
729 | unsigned char *trailing_buf = buf + buflen - 1; | |
730 | ||
731 | if (rw == READ) { | |
732 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
733 | memcpy(trailing_buf, align_buf, 1); | |
734 | } else { | |
735 | memcpy(align_buf, trailing_buf, 1); | |
736 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
737 | } | |
738 | words++; | |
739 | } | |
740 | ||
741 | return words << 1; | |
742 | } | |
0fe40ff8 | 743 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 744 | |
871af121 AC |
745 | /** |
746 | * ata_sff_data_xfer32 - Transfer data by PIO | |
747 | * @dev: device to target | |
748 | * @buf: data buffer | |
749 | * @buflen: buffer length | |
750 | * @rw: read/write | |
751 | * | |
752 | * Transfer data from/to the device data register by PIO using 32bit | |
753 | * I/O operations. | |
754 | * | |
755 | * LOCKING: | |
756 | * Inherited from caller. | |
757 | * | |
758 | * RETURNS: | |
759 | * Bytes consumed. | |
760 | */ | |
761 | ||
762 | unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, | |
763 | unsigned int buflen, int rw) | |
764 | { | |
765 | struct ata_port *ap = dev->link->ap; | |
766 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
767 | unsigned int words = buflen >> 2; | |
768 | int slop = buflen & 3; | |
769 | ||
770 | /* Transfer multiple of 4 bytes */ | |
771 | if (rw == READ) | |
772 | ioread32_rep(data_addr, buf, words); | |
773 | else | |
774 | iowrite32_rep(data_addr, buf, words); | |
775 | ||
d1b3525b | 776 | /* Transfer trailing bytes, if any */ |
871af121 | 777 | if (unlikely(slop)) { |
d1b3525b SS |
778 | unsigned char pad[4]; |
779 | ||
780 | /* Point buf to the tail of buffer */ | |
781 | buf += buflen - slop; | |
782 | ||
783 | /* | |
784 | * Use io*_rep() accessors here as well to avoid pointlessly | |
785 | * swapping bytes to and fro on the big endian machines... | |
786 | */ | |
871af121 | 787 | if (rw == READ) { |
d1b3525b SS |
788 | if (slop < 3) |
789 | ioread16_rep(data_addr, pad, 1); | |
790 | else | |
791 | ioread32_rep(data_addr, pad, 1); | |
792 | memcpy(buf, pad, slop); | |
871af121 | 793 | } else { |
d1b3525b SS |
794 | memcpy(pad, buf, slop); |
795 | if (slop < 3) | |
796 | iowrite16_rep(data_addr, pad, 1); | |
797 | else | |
798 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 799 | } |
871af121 | 800 | } |
d1b3525b | 801 | return (buflen + 1) & ~1; |
871af121 AC |
802 | } |
803 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
804 | ||
624d5c51 | 805 | /** |
9363c382 | 806 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
807 | * @dev: device to target |
808 | * @buf: data buffer | |
809 | * @buflen: buffer length | |
810 | * @rw: read/write | |
811 | * | |
812 | * Transfer data from/to the device data register by PIO. Do the | |
813 | * transfer with interrupts disabled. | |
814 | * | |
815 | * LOCKING: | |
816 | * Inherited from caller. | |
817 | * | |
818 | * RETURNS: | |
819 | * Bytes consumed. | |
820 | */ | |
9363c382 TH |
821 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
822 | unsigned int buflen, int rw) | |
624d5c51 TH |
823 | { |
824 | unsigned long flags; | |
825 | unsigned int consumed; | |
826 | ||
827 | local_irq_save(flags); | |
9363c382 | 828 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
829 | local_irq_restore(flags); |
830 | ||
831 | return consumed; | |
832 | } | |
0fe40ff8 | 833 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); |
624d5c51 TH |
834 | |
835 | /** | |
836 | * ata_pio_sector - Transfer a sector of data. | |
837 | * @qc: Command on going | |
838 | * | |
839 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
840 | * | |
841 | * LOCKING: | |
842 | * Inherited from caller. | |
843 | */ | |
844 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
845 | { | |
846 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
847 | struct ata_port *ap = qc->ap; | |
848 | struct page *page; | |
849 | unsigned int offset; | |
850 | unsigned char *buf; | |
851 | ||
852 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
853 | ap->hsm_task_state = HSM_ST_LAST; | |
854 | ||
855 | page = sg_page(qc->cursg); | |
856 | offset = qc->cursg->offset + qc->cursg_ofs; | |
857 | ||
858 | /* get the current page and offset */ | |
859 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
860 | offset %= PAGE_SIZE; | |
861 | ||
862 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
863 | ||
864 | if (PageHighMem(page)) { | |
865 | unsigned long flags; | |
866 | ||
867 | /* FIXME: use a bounce buffer */ | |
868 | local_irq_save(flags); | |
869 | buf = kmap_atomic(page, KM_IRQ0); | |
870 | ||
871 | /* do the actual data transfer */ | |
5682ed33 TH |
872 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
873 | do_write); | |
624d5c51 TH |
874 | |
875 | kunmap_atomic(buf, KM_IRQ0); | |
876 | local_irq_restore(flags); | |
877 | } else { | |
878 | buf = page_address(page); | |
5682ed33 TH |
879 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
880 | do_write); | |
624d5c51 TH |
881 | } |
882 | ||
883 | qc->curbytes += qc->sect_size; | |
884 | qc->cursg_ofs += qc->sect_size; | |
885 | ||
886 | if (qc->cursg_ofs == qc->cursg->length) { | |
887 | qc->cursg = sg_next(qc->cursg); | |
888 | qc->cursg_ofs = 0; | |
889 | } | |
890 | } | |
891 | ||
892 | /** | |
893 | * ata_pio_sectors - Transfer one or many sectors. | |
894 | * @qc: Command on going | |
895 | * | |
896 | * Transfer one or many sectors of data from/to the | |
897 | * ATA device for the DRQ request. | |
898 | * | |
899 | * LOCKING: | |
900 | * Inherited from caller. | |
901 | */ | |
902 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
903 | { | |
904 | if (is_multi_taskfile(&qc->tf)) { | |
905 | /* READ/WRITE MULTIPLE */ | |
906 | unsigned int nsect; | |
907 | ||
efcb3cf7 | 908 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
909 | |
910 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
911 | qc->dev->multi_count); | |
912 | while (nsect--) | |
913 | ata_pio_sector(qc); | |
914 | } else | |
915 | ata_pio_sector(qc); | |
916 | ||
a57c1bad | 917 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
918 | } |
919 | ||
920 | /** | |
921 | * atapi_send_cdb - Write CDB bytes to hardware | |
922 | * @ap: Port to which ATAPI device is attached. | |
923 | * @qc: Taskfile currently active | |
924 | * | |
925 | * When device has indicated its readiness to accept | |
926 | * a CDB, this function is called. Send the CDB. | |
927 | * | |
928 | * LOCKING: | |
929 | * caller. | |
930 | */ | |
931 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
932 | { | |
933 | /* send SCSI cdb */ | |
934 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 935 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 936 | |
5682ed33 | 937 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
938 | ata_sff_sync(ap); |
939 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
940 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
941 | switch (qc->tf.protocol) { |
942 | case ATAPI_PROT_PIO: | |
943 | ap->hsm_task_state = HSM_ST; | |
944 | break; | |
945 | case ATAPI_PROT_NODATA: | |
946 | ap->hsm_task_state = HSM_ST_LAST; | |
947 | break; | |
948 | case ATAPI_PROT_DMA: | |
949 | ap->hsm_task_state = HSM_ST_LAST; | |
950 | /* initiate bmdma */ | |
951 | ap->ops->bmdma_start(qc); | |
952 | break; | |
953 | } | |
954 | } | |
955 | ||
956 | /** | |
957 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
958 | * @qc: Command on going | |
959 | * @bytes: number of bytes | |
960 | * | |
961 | * Transfer Transfer data from/to the ATAPI device. | |
962 | * | |
963 | * LOCKING: | |
964 | * Inherited from caller. | |
965 | * | |
966 | */ | |
967 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
968 | { | |
969 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
970 | struct ata_port *ap = qc->ap; | |
971 | struct ata_device *dev = qc->dev; | |
972 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
973 | struct scatterlist *sg; | |
974 | struct page *page; | |
975 | unsigned char *buf; | |
976 | unsigned int offset, count, consumed; | |
977 | ||
978 | next_sg: | |
979 | sg = qc->cursg; | |
980 | if (unlikely(!sg)) { | |
981 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
982 | "buf=%u cur=%u bytes=%u", | |
983 | qc->nbytes, qc->curbytes, bytes); | |
984 | return -1; | |
985 | } | |
986 | ||
987 | page = sg_page(sg); | |
988 | offset = sg->offset + qc->cursg_ofs; | |
989 | ||
990 | /* get the current page and offset */ | |
991 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
992 | offset %= PAGE_SIZE; | |
993 | ||
994 | /* don't overrun current sg */ | |
995 | count = min(sg->length - qc->cursg_ofs, bytes); | |
996 | ||
997 | /* don't cross page boundaries */ | |
998 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
999 | ||
1000 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
1001 | ||
1002 | if (PageHighMem(page)) { | |
1003 | unsigned long flags; | |
1004 | ||
1005 | /* FIXME: use bounce buffer */ | |
1006 | local_irq_save(flags); | |
1007 | buf = kmap_atomic(page, KM_IRQ0); | |
1008 | ||
1009 | /* do the actual data transfer */ | |
0fe40ff8 AC |
1010 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1011 | count, rw); | |
624d5c51 TH |
1012 | |
1013 | kunmap_atomic(buf, KM_IRQ0); | |
1014 | local_irq_restore(flags); | |
1015 | } else { | |
1016 | buf = page_address(page); | |
0fe40ff8 AC |
1017 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1018 | count, rw); | |
624d5c51 TH |
1019 | } |
1020 | ||
1021 | bytes -= min(bytes, consumed); | |
1022 | qc->curbytes += count; | |
1023 | qc->cursg_ofs += count; | |
1024 | ||
1025 | if (qc->cursg_ofs == sg->length) { | |
1026 | qc->cursg = sg_next(qc->cursg); | |
1027 | qc->cursg_ofs = 0; | |
1028 | } | |
1029 | ||
a0f79f7a CB |
1030 | /* |
1031 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
1032 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
1033 | * check correctly as it doesn't know if it is the last request being | |
1034 | * made. Somebody should implement a proper sanity check. | |
1035 | */ | |
624d5c51 TH |
1036 | if (bytes) |
1037 | goto next_sg; | |
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | /** | |
1042 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
1043 | * @qc: Command on going | |
1044 | * | |
1045 | * Transfer Transfer data from/to the ATAPI device. | |
1046 | * | |
1047 | * LOCKING: | |
1048 | * Inherited from caller. | |
1049 | */ | |
1050 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
1051 | { | |
1052 | struct ata_port *ap = qc->ap; | |
1053 | struct ata_device *dev = qc->dev; | |
1054 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
1055 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
1056 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
1057 | ||
1058 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
1059 | * here to save some kernel stack usage. | |
1060 | * For normal completion, qc->result_tf is not relevant. For | |
1061 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
1062 | * So, the correctness of qc->result_tf is not affected. | |
1063 | */ | |
5682ed33 | 1064 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
1065 | ireason = qc->result_tf.nsect; |
1066 | bc_lo = qc->result_tf.lbam; | |
1067 | bc_hi = qc->result_tf.lbah; | |
1068 | bytes = (bc_hi << 8) | bc_lo; | |
1069 | ||
1070 | /* shall be cleared to zero, indicating xfer of data */ | |
1071 | if (unlikely(ireason & (1 << 0))) | |
1072 | goto atapi_check; | |
1073 | ||
1074 | /* make sure transfer direction matches expected */ | |
1075 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
1076 | if (unlikely(do_write != i_write)) | |
1077 | goto atapi_check; | |
1078 | ||
1079 | if (unlikely(!bytes)) | |
1080 | goto atapi_check; | |
1081 | ||
1082 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
1083 | ||
1084 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
1085 | goto err_out; | |
a57c1bad | 1086 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
1087 | |
1088 | return; | |
1089 | ||
1090 | atapi_check: | |
1091 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
1092 | ireason, bytes); | |
1093 | err_out: | |
1094 | qc->err_mask |= AC_ERR_HSM; | |
1095 | ap->hsm_task_state = HSM_ST_ERR; | |
1096 | } | |
1097 | ||
1098 | /** | |
1099 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
1100 | * @ap: the target ata_port | |
1101 | * @qc: qc on going | |
1102 | * | |
1103 | * RETURNS: | |
1104 | * 1 if ok in workqueue, 0 otherwise. | |
1105 | */ | |
0fe40ff8 AC |
1106 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
1107 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1108 | { |
1109 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1110 | return 1; | |
1111 | ||
1112 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
1113 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 1114 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
1115 | return 1; |
1116 | ||
1117 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 1118 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
1119 | return 1; |
1120 | } | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | /** | |
1126 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
1127 | * @qc: Command to complete | |
1128 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1129 | * | |
1130 | * Finish @qc which is running on standard HSM. | |
1131 | * | |
1132 | * LOCKING: | |
1133 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
1134 | * Otherwise, none on entry and grabs host lock. | |
1135 | */ | |
1136 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
1137 | { | |
1138 | struct ata_port *ap = qc->ap; | |
1139 | unsigned long flags; | |
1140 | ||
1141 | if (ap->ops->error_handler) { | |
1142 | if (in_wq) { | |
1143 | spin_lock_irqsave(ap->lock, flags); | |
1144 | ||
1145 | /* EH might have kicked in while host lock is | |
1146 | * released. | |
1147 | */ | |
1148 | qc = ata_qc_from_tag(ap, qc->tag); | |
1149 | if (qc) { | |
1150 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
5682ed33 | 1151 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1152 | ata_qc_complete(qc); |
1153 | } else | |
1154 | ata_port_freeze(ap); | |
1155 | } | |
1156 | ||
1157 | spin_unlock_irqrestore(ap->lock, flags); | |
1158 | } else { | |
1159 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1160 | ata_qc_complete(qc); | |
1161 | else | |
1162 | ata_port_freeze(ap); | |
1163 | } | |
1164 | } else { | |
1165 | if (in_wq) { | |
1166 | spin_lock_irqsave(ap->lock, flags); | |
5682ed33 | 1167 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1168 | ata_qc_complete(qc); |
1169 | spin_unlock_irqrestore(ap->lock, flags); | |
1170 | } else | |
1171 | ata_qc_complete(qc); | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | /** | |
9363c382 | 1176 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1177 | * @ap: the target ata_port |
1178 | * @qc: qc on going | |
1179 | * @status: current device status | |
1180 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1181 | * | |
1182 | * RETURNS: | |
1183 | * 1 when poll next status needed, 0 otherwise. | |
1184 | */ | |
9363c382 TH |
1185 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1186 | u8 status, int in_wq) | |
624d5c51 | 1187 | { |
a836d3e8 | 1188 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1189 | unsigned long flags = 0; |
1190 | int poll_next; | |
1191 | ||
efcb3cf7 | 1192 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 1193 | |
9363c382 | 1194 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1195 | * like DMA polling into the workqueue. Notice that |
1196 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1197 | */ | |
efcb3cf7 | 1198 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
1199 | |
1200 | fsm_start: | |
1201 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1202 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1203 | ||
1204 | switch (ap->hsm_task_state) { | |
1205 | case HSM_ST_FIRST: | |
1206 | /* Send first data block or PACKET CDB */ | |
1207 | ||
1208 | /* If polling, we will stay in the work queue after | |
1209 | * sending the data. Otherwise, interrupt handler | |
1210 | * takes over after sending the data. | |
1211 | */ | |
1212 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1213 | ||
1214 | /* check device status */ | |
1215 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1216 | /* handle BSY=0, DRQ=0 as error */ | |
1217 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1218 | /* device stops HSM for abort/error */ | |
1219 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1220 | else { |
624d5c51 | 1221 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1222 | ata_ehi_push_desc(ehi, |
1223 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1224 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1225 | } |
624d5c51 TH |
1226 | |
1227 | ap->hsm_task_state = HSM_ST_ERR; | |
1228 | goto fsm_start; | |
1229 | } | |
1230 | ||
1231 | /* Device should not ask for data transfer (DRQ=1) | |
1232 | * when it finds something wrong. | |
1233 | * We ignore DRQ here and stop the HSM by | |
1234 | * changing hsm_task_state to HSM_ST_ERR and | |
1235 | * let the EH abort the command or reset the device. | |
1236 | */ | |
1237 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1238 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1239 | * when doing the next command (mostly request sense). | |
1240 | * We ignore ERR here to workaround and proceed sending | |
1241 | * the CDB. | |
1242 | */ | |
1243 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1244 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1245 | "DRQ=1 with device error, " | |
1246 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1247 | qc->err_mask |= AC_ERR_HSM; |
1248 | ap->hsm_task_state = HSM_ST_ERR; | |
1249 | goto fsm_start; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1254 | * During the state transition, interrupt handler shouldn't | |
1255 | * be invoked before the data transfer is complete and | |
1256 | * hsm_task_state is changed. Hence, the following locking. | |
1257 | */ | |
1258 | if (in_wq) | |
1259 | spin_lock_irqsave(ap->lock, flags); | |
1260 | ||
1261 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1262 | /* PIO data out protocol. | |
1263 | * send first data block. | |
1264 | */ | |
1265 | ||
1266 | /* ata_pio_sectors() might change the state | |
1267 | * to HSM_ST_LAST. so, the state is changed here | |
1268 | * before ata_pio_sectors(). | |
1269 | */ | |
1270 | ap->hsm_task_state = HSM_ST; | |
1271 | ata_pio_sectors(qc); | |
1272 | } else | |
1273 | /* send CDB */ | |
1274 | atapi_send_cdb(ap, qc); | |
1275 | ||
1276 | if (in_wq) | |
1277 | spin_unlock_irqrestore(ap->lock, flags); | |
1278 | ||
1279 | /* if polling, ata_pio_task() handles the rest. | |
1280 | * otherwise, interrupt handler takes over from here. | |
1281 | */ | |
1282 | break; | |
1283 | ||
1284 | case HSM_ST: | |
1285 | /* complete command or read/write the data register */ | |
1286 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1287 | /* ATAPI PIO protocol */ | |
1288 | if ((status & ATA_DRQ) == 0) { | |
1289 | /* No more data to transfer or device error. | |
1290 | * Device error will be tagged in HSM_ST_LAST. | |
1291 | */ | |
1292 | ap->hsm_task_state = HSM_ST_LAST; | |
1293 | goto fsm_start; | |
1294 | } | |
1295 | ||
1296 | /* Device should not ask for data transfer (DRQ=1) | |
1297 | * when it finds something wrong. | |
1298 | * We ignore DRQ here and stop the HSM by | |
1299 | * changing hsm_task_state to HSM_ST_ERR and | |
1300 | * let the EH abort the command or reset the device. | |
1301 | */ | |
1302 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1303 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1304 | "DRQ=1 with device error, " | |
1305 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1306 | qc->err_mask |= AC_ERR_HSM; |
1307 | ap->hsm_task_state = HSM_ST_ERR; | |
1308 | goto fsm_start; | |
1309 | } | |
1310 | ||
1311 | atapi_pio_bytes(qc); | |
1312 | ||
1313 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1314 | /* bad ireason reported by device */ | |
1315 | goto fsm_start; | |
1316 | ||
1317 | } else { | |
1318 | /* ATA PIO protocol */ | |
1319 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1320 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1321 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1322 | /* device stops HSM for abort/error */ |
1323 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1324 | |
1325 | /* If diagnostic failed and this is | |
1326 | * IDENTIFY, it's likely a phantom | |
1327 | * device. Mark hint. | |
1328 | */ | |
1329 | if (qc->dev->horkage & | |
1330 | ATA_HORKAGE_DIAGNOSTIC) | |
1331 | qc->err_mask |= | |
1332 | AC_ERR_NODEV_HINT; | |
1333 | } else { | |
624d5c51 TH |
1334 | /* HSM violation. Let EH handle this. |
1335 | * Phantom devices also trigger this | |
1336 | * condition. Mark hint. | |
1337 | */ | |
a836d3e8 | 1338 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1339 | "DRQ=0 without device error, " |
a836d3e8 | 1340 | "dev_stat 0x%X", status); |
624d5c51 TH |
1341 | qc->err_mask |= AC_ERR_HSM | |
1342 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1343 | } |
624d5c51 TH |
1344 | |
1345 | ap->hsm_task_state = HSM_ST_ERR; | |
1346 | goto fsm_start; | |
1347 | } | |
1348 | ||
1349 | /* For PIO reads, some devices may ask for | |
1350 | * data transfer (DRQ=1) alone with ERR=1. | |
1351 | * We respect DRQ here and transfer one | |
1352 | * block of junk data before changing the | |
1353 | * hsm_task_state to HSM_ST_ERR. | |
1354 | * | |
1355 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1356 | * sense since the data block has been | |
1357 | * transferred to the device. | |
1358 | */ | |
1359 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1360 | /* data might be corrputed */ | |
1361 | qc->err_mask |= AC_ERR_DEV; | |
1362 | ||
1363 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1364 | ata_pio_sectors(qc); | |
1365 | status = ata_wait_idle(ap); | |
1366 | } | |
1367 | ||
a836d3e8 TH |
1368 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1369 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1370 | "BUSY|DRQ persists on ERR|DF, " | |
1371 | "dev_stat 0x%X", status); | |
624d5c51 | 1372 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1373 | } |
624d5c51 | 1374 | |
b919930c TH |
1375 | /* There are oddball controllers with |
1376 | * status register stuck at 0x7f and | |
1377 | * lbal/m/h at zero which makes it | |
1378 | * pass all other presence detection | |
1379 | * mechanisms we have. Set NODEV_HINT | |
1380 | * for it. Kernel bz#7241. | |
1381 | */ | |
1382 | if (status == 0x7f) | |
1383 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1384 | ||
624d5c51 TH |
1385 | /* ata_pio_sectors() might change the |
1386 | * state to HSM_ST_LAST. so, the state | |
1387 | * is changed after ata_pio_sectors(). | |
1388 | */ | |
1389 | ap->hsm_task_state = HSM_ST_ERR; | |
1390 | goto fsm_start; | |
1391 | } | |
1392 | ||
1393 | ata_pio_sectors(qc); | |
1394 | ||
1395 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1396 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1397 | /* all data read */ | |
1398 | status = ata_wait_idle(ap); | |
1399 | goto fsm_start; | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | poll_next = 1; | |
1404 | break; | |
1405 | ||
1406 | case HSM_ST_LAST: | |
1407 | if (unlikely(!ata_ok(status))) { | |
1408 | qc->err_mask |= __ac_err_mask(status); | |
1409 | ap->hsm_task_state = HSM_ST_ERR; | |
1410 | goto fsm_start; | |
1411 | } | |
1412 | ||
1413 | /* no more data to transfer */ | |
1414 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1415 | ap->print_id, qc->dev->devno, status); | |
1416 | ||
efcb3cf7 | 1417 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1418 | |
1419 | ap->hsm_task_state = HSM_ST_IDLE; | |
1420 | ||
1421 | /* complete taskfile transaction */ | |
1422 | ata_hsm_qc_complete(qc, in_wq); | |
1423 | ||
1424 | poll_next = 0; | |
1425 | break; | |
1426 | ||
1427 | case HSM_ST_ERR: | |
624d5c51 TH |
1428 | ap->hsm_task_state = HSM_ST_IDLE; |
1429 | ||
1430 | /* complete taskfile transaction */ | |
1431 | ata_hsm_qc_complete(qc, in_wq); | |
1432 | ||
1433 | poll_next = 0; | |
1434 | break; | |
1435 | default: | |
1436 | poll_next = 0; | |
1437 | BUG(); | |
1438 | } | |
1439 | ||
1440 | return poll_next; | |
1441 | } | |
0fe40ff8 | 1442 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 TH |
1443 | |
1444 | void ata_pio_task(struct work_struct *work) | |
1445 | { | |
1446 | struct ata_port *ap = | |
1447 | container_of(work, struct ata_port, port_task.work); | |
1448 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1449 | u8 status; | |
1450 | int poll_next; | |
1451 | ||
1452 | fsm_start: | |
efcb3cf7 | 1453 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1454 | |
1455 | /* | |
1456 | * This is purely heuristic. This is a fast path. | |
1457 | * Sometimes when we enter, BSY will be cleared in | |
1458 | * a chk-status or two. If not, the drive is probably seeking | |
1459 | * or something. Snooze for a couple msecs, then | |
1460 | * chk-status again. If still busy, queue delayed work. | |
1461 | */ | |
9363c382 | 1462 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1463 | if (status & ATA_BUSY) { |
1464 | msleep(2); | |
9363c382 | 1465 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1466 | if (status & ATA_BUSY) { |
1467 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1468 | return; | |
1469 | } | |
1470 | } | |
1471 | ||
1472 | /* move the HSM */ | |
9363c382 | 1473 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1474 | |
1475 | /* another command or interrupt handler | |
1476 | * may be running at this point. | |
1477 | */ | |
1478 | if (poll_next) | |
1479 | goto fsm_start; | |
1480 | } | |
1481 | ||
1482 | /** | |
9363c382 | 1483 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1484 | * @qc: command to issue to device |
1485 | * | |
1486 | * Using various libata functions and hooks, this function | |
1487 | * starts an ATA command. ATA commands are grouped into | |
1488 | * classes called "protocols", and issuing each type of protocol | |
1489 | * is slightly different. | |
1490 | * | |
1491 | * May be used as the qc_issue() entry in ata_port_operations. | |
1492 | * | |
1493 | * LOCKING: | |
1494 | * spin_lock_irqsave(host lock) | |
1495 | * | |
1496 | * RETURNS: | |
1497 | * Zero on success, AC_ERR_* mask on failure | |
1498 | */ | |
9363c382 | 1499 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1500 | { |
1501 | struct ata_port *ap = qc->ap; | |
1502 | ||
1503 | /* Use polling pio if the LLD doesn't handle | |
1504 | * interrupt driven pio and atapi CDB interrupt. | |
1505 | */ | |
1506 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1507 | switch (qc->tf.protocol) { | |
1508 | case ATA_PROT_PIO: | |
1509 | case ATA_PROT_NODATA: | |
1510 | case ATAPI_PROT_PIO: | |
1511 | case ATAPI_PROT_NODATA: | |
1512 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1513 | break; | |
1514 | case ATAPI_PROT_DMA: | |
1515 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1516 | /* see ata_dma_blacklisted() */ | |
1517 | BUG(); | |
1518 | break; | |
1519 | default: | |
1520 | break; | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | /* select the device */ | |
1525 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1526 | ||
1527 | /* start the command */ | |
1528 | switch (qc->tf.protocol) { | |
1529 | case ATA_PROT_NODATA: | |
1530 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1531 | ata_qc_set_polling(qc); | |
1532 | ||
1533 | ata_tf_to_host(ap, &qc->tf); | |
1534 | ap->hsm_task_state = HSM_ST_LAST; | |
1535 | ||
1536 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1537 | ata_pio_queue_task(ap, qc, 0); | |
1538 | ||
1539 | break; | |
1540 | ||
1541 | case ATA_PROT_DMA: | |
efcb3cf7 | 1542 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1543 | |
5682ed33 | 1544 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1545 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1546 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1547 | ap->hsm_task_state = HSM_ST_LAST; | |
1548 | break; | |
1549 | ||
1550 | case ATA_PROT_PIO: | |
1551 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1552 | ata_qc_set_polling(qc); | |
1553 | ||
1554 | ata_tf_to_host(ap, &qc->tf); | |
1555 | ||
1556 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1557 | /* PIO data out protocol */ | |
1558 | ap->hsm_task_state = HSM_ST_FIRST; | |
1559 | ata_pio_queue_task(ap, qc, 0); | |
1560 | ||
1561 | /* always send first data block using | |
1562 | * the ata_pio_task() codepath. | |
1563 | */ | |
1564 | } else { | |
1565 | /* PIO data in protocol */ | |
1566 | ap->hsm_task_state = HSM_ST; | |
1567 | ||
1568 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1569 | ata_pio_queue_task(ap, qc, 0); | |
1570 | ||
1571 | /* if polling, ata_pio_task() handles the rest. | |
1572 | * otherwise, interrupt handler takes over from here. | |
1573 | */ | |
1574 | } | |
1575 | ||
1576 | break; | |
1577 | ||
1578 | case ATAPI_PROT_PIO: | |
1579 | case ATAPI_PROT_NODATA: | |
1580 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1581 | ata_qc_set_polling(qc); | |
1582 | ||
1583 | ata_tf_to_host(ap, &qc->tf); | |
1584 | ||
1585 | ap->hsm_task_state = HSM_ST_FIRST; | |
1586 | ||
1587 | /* send cdb by polling if no cdb interrupt */ | |
1588 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1589 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1590 | ata_pio_queue_task(ap, qc, 0); | |
1591 | break; | |
1592 | ||
1593 | case ATAPI_PROT_DMA: | |
efcb3cf7 | 1594 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1595 | |
5682ed33 | 1596 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1597 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1598 | ap->hsm_task_state = HSM_ST_FIRST; | |
1599 | ||
1600 | /* send cdb by polling if no cdb interrupt */ | |
1601 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1602 | ata_pio_queue_task(ap, qc, 0); | |
1603 | break; | |
1604 | ||
1605 | default: | |
efcb3cf7 | 1606 | WARN_ON_ONCE(1); |
624d5c51 TH |
1607 | return AC_ERR_SYSTEM; |
1608 | } | |
1609 | ||
1610 | return 0; | |
1611 | } | |
0fe40ff8 | 1612 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1613 | |
22183bf5 TH |
1614 | /** |
1615 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1616 | * @qc: qc to fill result TF for | |
1617 | * | |
1618 | * @qc is finished and result TF needs to be filled. Fill it | |
1619 | * using ->sff_tf_read. | |
1620 | * | |
1621 | * LOCKING: | |
1622 | * spin_lock_irqsave(host lock) | |
1623 | * | |
1624 | * RETURNS: | |
1625 | * true indicating that result TF is successfully filled. | |
1626 | */ | |
1627 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1628 | { | |
1629 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1630 | return true; | |
1631 | } | |
0fe40ff8 | 1632 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1633 | |
624d5c51 | 1634 | /** |
9363c382 | 1635 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1636 | * @ap: Port on which interrupt arrived (possibly...) |
1637 | * @qc: Taskfile currently active in engine | |
1638 | * | |
1639 | * Handle host interrupt for given queued command. Currently, | |
1640 | * only DMA interrupts are handled. All other commands are | |
1641 | * handled via polling with interrupts disabled (nIEN bit). | |
1642 | * | |
1643 | * LOCKING: | |
1644 | * spin_lock_irqsave(host lock) | |
1645 | * | |
1646 | * RETURNS: | |
1647 | * One if interrupt was handled, zero if not (shared irq). | |
1648 | */ | |
9363c382 TH |
1649 | inline unsigned int ata_sff_host_intr(struct ata_port *ap, |
1650 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1651 | { |
1652 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1653 | u8 status, host_stat = 0; | |
1654 | ||
1655 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1656 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1657 | ||
1658 | /* Check whether we are expecting interrupt in this state */ | |
1659 | switch (ap->hsm_task_state) { | |
1660 | case HSM_ST_FIRST: | |
1661 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1662 | * at this state when ready to receive CDB. | |
1663 | */ | |
1664 | ||
1665 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1666 | * The flag was turned on only for atapi devices. No | |
1667 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1668 | */ | |
1669 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1670 | goto idle_irq; | |
1671 | break; | |
1672 | case HSM_ST_LAST: | |
1673 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1674 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1675 | /* check status of DMA engine */ | |
1676 | host_stat = ap->ops->bmdma_status(ap); | |
1677 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1678 | ap->print_id, host_stat); | |
1679 | ||
1680 | /* if it's not our irq... */ | |
1681 | if (!(host_stat & ATA_DMA_INTR)) | |
1682 | goto idle_irq; | |
1683 | ||
1684 | /* before we do anything else, clear DMA-Start bit */ | |
1685 | ap->ops->bmdma_stop(qc); | |
1686 | ||
1687 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1688 | /* error when transfering data to/from memory */ | |
1689 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1690 | ap->hsm_task_state = HSM_ST_ERR; | |
1691 | } | |
1692 | } | |
1693 | break; | |
1694 | case HSM_ST: | |
1695 | break; | |
1696 | default: | |
1697 | goto idle_irq; | |
1698 | } | |
1699 | ||
624d5c51 | 1700 | |
a57c1bad AC |
1701 | /* check main status, clearing INTRQ if needed */ |
1702 | status = ata_sff_irq_status(ap); | |
1703 | if (status & ATA_BUSY) | |
624d5c51 TH |
1704 | goto idle_irq; |
1705 | ||
1706 | /* ack bmdma irq events */ | |
5682ed33 | 1707 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1708 | |
9363c382 | 1709 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1710 | |
1711 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1712 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1713 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1714 | ||
1715 | return 1; /* irq handled */ | |
1716 | ||
1717 | idle_irq: | |
1718 | ap->stats.idle_irq++; | |
1719 | ||
1720 | #ifdef ATA_IRQ_TRAP | |
1721 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1722 | ap->ops->sff_check_status(ap); |
1723 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1724 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1725 | return 1; | |
1726 | } | |
1727 | #endif | |
1728 | return 0; /* irq not handled */ | |
1729 | } | |
0fe40ff8 | 1730 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
624d5c51 TH |
1731 | |
1732 | /** | |
9363c382 | 1733 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1734 | * @irq: irq line (unused) |
1735 | * @dev_instance: pointer to our ata_host information structure | |
1736 | * | |
1737 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1738 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1739 | * |
1740 | * LOCKING: | |
1741 | * Obtains host lock during operation. | |
1742 | * | |
1743 | * RETURNS: | |
1744 | * IRQ_NONE or IRQ_HANDLED. | |
1745 | */ | |
9363c382 | 1746 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1747 | { |
1748 | struct ata_host *host = dev_instance; | |
1749 | unsigned int i; | |
1750 | unsigned int handled = 0; | |
1751 | unsigned long flags; | |
1752 | ||
1753 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1754 | spin_lock_irqsave(&host->lock, flags); | |
1755 | ||
1756 | for (i = 0; i < host->n_ports; i++) { | |
1757 | struct ata_port *ap; | |
1758 | ||
1759 | ap = host->ports[i]; | |
1760 | if (ap && | |
1761 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
1762 | struct ata_queued_cmd *qc; | |
1763 | ||
1764 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1765 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && | |
1766 | (qc->flags & ATA_QCFLAG_ACTIVE)) | |
9363c382 | 1767 | handled |= ata_sff_host_intr(ap, qc); |
624d5c51 TH |
1768 | } |
1769 | } | |
1770 | ||
1771 | spin_unlock_irqrestore(&host->lock, flags); | |
1772 | ||
1773 | return IRQ_RETVAL(handled); | |
1774 | } | |
0fe40ff8 | 1775 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 TH |
1776 | |
1777 | /** | |
9363c382 | 1778 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1779 | * @ap: port to freeze |
1780 | * | |
1781 | * Freeze BMDMA controller port. | |
1782 | * | |
1783 | * LOCKING: | |
1784 | * Inherited from caller. | |
1785 | */ | |
9363c382 | 1786 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 TH |
1787 | { |
1788 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
1789 | ||
1790 | ap->ctl |= ATA_NIEN; | |
1791 | ap->last_ctl = ap->ctl; | |
1792 | ||
1793 | if (ioaddr->ctl_addr) | |
1794 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1795 | ||
1796 | /* Under certain circumstances, some controllers raise IRQ on | |
1797 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1798 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1799 | */ | |
5682ed33 | 1800 | ap->ops->sff_check_status(ap); |
624d5c51 | 1801 | |
5682ed33 | 1802 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1803 | } |
0fe40ff8 | 1804 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1805 | |
1806 | /** | |
9363c382 | 1807 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1808 | * @ap: port to thaw |
1809 | * | |
9363c382 | 1810 | * Thaw SFF controller port. |
624d5c51 TH |
1811 | * |
1812 | * LOCKING: | |
1813 | * Inherited from caller. | |
1814 | */ | |
9363c382 | 1815 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1816 | { |
624d5c51 | 1817 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1818 | ap->ops->sff_check_status(ap); |
1819 | ap->ops->sff_irq_clear(ap); | |
1820 | ap->ops->sff_irq_on(ap); | |
272f7884 | 1821 | } |
0fe40ff8 | 1822 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1823 | |
0aa1113d TH |
1824 | /** |
1825 | * ata_sff_prereset - prepare SFF link for reset | |
1826 | * @link: SFF link to be reset | |
1827 | * @deadline: deadline jiffies for the operation | |
1828 | * | |
1829 | * SFF link @link is about to be reset. Initialize it. It first | |
1830 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1831 | * being softreset. | |
1832 | * | |
1833 | * LOCKING: | |
1834 | * Kernel thread context (may sleep) | |
1835 | * | |
1836 | * RETURNS: | |
1837 | * 0 on success, -errno otherwise. | |
1838 | */ | |
1839 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1840 | { | |
0aa1113d TH |
1841 | struct ata_eh_context *ehc = &link->eh_context; |
1842 | int rc; | |
1843 | ||
1844 | rc = ata_std_prereset(link, deadline); | |
1845 | if (rc) | |
1846 | return rc; | |
1847 | ||
1848 | /* if we're about to do hardreset, nothing more to do */ | |
1849 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1850 | return 0; | |
1851 | ||
1852 | /* wait for !BSY if we don't know that no device is attached */ | |
1853 | if (!ata_link_offline(link)) { | |
705e76be | 1854 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1855 | if (rc && rc != -ENODEV) { |
1856 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1857 | "(errno=%d), forcing hardreset\n", rc); | |
1858 | ehc->i.action |= ATA_EH_HARDRESET; | |
1859 | } | |
1860 | } | |
1861 | ||
1862 | return 0; | |
1863 | } | |
0fe40ff8 | 1864 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1865 | |
90088bb4 | 1866 | /** |
624d5c51 TH |
1867 | * ata_devchk - PATA device presence detection |
1868 | * @ap: ATA channel to examine | |
1869 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1870 | * |
624d5c51 TH |
1871 | * This technique was originally described in |
1872 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1873 | * later found its way into the ATA/ATAPI spec. | |
1874 | * | |
1875 | * Write a pattern to the ATA shadow registers, | |
1876 | * and if a device is present, it will respond by | |
1877 | * correctly storing and echoing back the | |
1878 | * ATA shadow register contents. | |
90088bb4 TH |
1879 | * |
1880 | * LOCKING: | |
624d5c51 | 1881 | * caller. |
90088bb4 | 1882 | */ |
624d5c51 | 1883 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1884 | { |
1885 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1886 | u8 nsect, lbal; |
90088bb4 | 1887 | |
5682ed33 | 1888 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1889 | |
624d5c51 TH |
1890 | iowrite8(0x55, ioaddr->nsect_addr); |
1891 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1892 | |
624d5c51 TH |
1893 | iowrite8(0xaa, ioaddr->nsect_addr); |
1894 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1895 | |
624d5c51 TH |
1896 | iowrite8(0x55, ioaddr->nsect_addr); |
1897 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1898 | ||
1899 | nsect = ioread8(ioaddr->nsect_addr); | |
1900 | lbal = ioread8(ioaddr->lbal_addr); | |
1901 | ||
1902 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1903 | return 1; /* we found a device */ | |
1904 | ||
1905 | return 0; /* nothing found */ | |
90088bb4 TH |
1906 | } |
1907 | ||
272f7884 | 1908 | /** |
9363c382 | 1909 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1910 | * @dev: ATA device to classify (starting at zero) |
1911 | * @present: device seems present | |
1912 | * @r_err: Value of error register on completion | |
272f7884 | 1913 | * |
624d5c51 TH |
1914 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1915 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1916 | * shadow registers, indicating the results of device detection | |
1917 | * and diagnostics. | |
272f7884 | 1918 | * |
624d5c51 TH |
1919 | * Select the ATA device, and read the values from the ATA shadow |
1920 | * registers. Then parse according to the Error register value, | |
1921 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1922 | * |
1923 | * LOCKING: | |
624d5c51 TH |
1924 | * caller. |
1925 | * | |
1926 | * RETURNS: | |
1927 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1928 | */ |
9363c382 | 1929 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1930 | u8 *r_err) |
272f7884 | 1931 | { |
624d5c51 TH |
1932 | struct ata_port *ap = dev->link->ap; |
1933 | struct ata_taskfile tf; | |
1934 | unsigned int class; | |
1935 | u8 err; | |
1936 | ||
5682ed33 | 1937 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1938 | |
1939 | memset(&tf, 0, sizeof(tf)); | |
1940 | ||
5682ed33 | 1941 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1942 | err = tf.feature; |
1943 | if (r_err) | |
1944 | *r_err = err; | |
1945 | ||
1946 | /* see if device passed diags: continue and warn later */ | |
1947 | if (err == 0) | |
1948 | /* diagnostic fail : do nothing _YET_ */ | |
1949 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1950 | else if (err == 1) | |
1951 | /* do nothing */ ; | |
1952 | else if ((dev->devno == 0) && (err == 0x81)) | |
1953 | /* do nothing */ ; | |
1954 | else | |
1955 | return ATA_DEV_NONE; | |
272f7884 | 1956 | |
624d5c51 TH |
1957 | /* determine if device is ATA or ATAPI */ |
1958 | class = ata_dev_classify(&tf); | |
272f7884 | 1959 | |
624d5c51 TH |
1960 | if (class == ATA_DEV_UNKNOWN) { |
1961 | /* If the device failed diagnostic, it's likely to | |
1962 | * have reported incorrect device signature too. | |
1963 | * Assume ATA device if the device seems present but | |
1964 | * device signature is invalid with diagnostic | |
1965 | * failure. | |
1966 | */ | |
1967 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1968 | class = ATA_DEV_ATA; | |
1969 | else | |
1970 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1971 | } else if ((class == ATA_DEV_ATA) && |
1972 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1973 | class = ATA_DEV_NONE; |
1974 | ||
1975 | return class; | |
272f7884 | 1976 | } |
0fe40ff8 | 1977 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 1978 | |
705e76be TH |
1979 | /** |
1980 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1981 | * @link: SFF link which is just reset | |
1982 | * @devmask: mask of present devices | |
1983 | * @deadline: deadline jiffies for the operation | |
1984 | * | |
1985 | * Wait devices attached to SFF @link to become ready after | |
1986 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1987 | * status register too early. | |
1988 | * | |
1989 | * LOCKING: | |
1990 | * Kernel thread context (may sleep). | |
1991 | * | |
1992 | * RETURNS: | |
1993 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1994 | * don't seem to exist. -errno on other errors. | |
1995 | */ | |
1996 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1997 | unsigned long deadline) | |
1fdffbce | 1998 | { |
705e76be | 1999 | struct ata_port *ap = link->ap; |
1fdffbce | 2000 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
2001 | unsigned int dev0 = devmask & (1 << 0); |
2002 | unsigned int dev1 = devmask & (1 << 1); | |
2003 | int rc, ret = 0; | |
1fdffbce | 2004 | |
341c2c95 | 2005 | msleep(ATA_WAIT_AFTER_RESET); |
705e76be TH |
2006 | |
2007 | /* always check readiness of the master device */ | |
2008 | rc = ata_sff_wait_ready(link, deadline); | |
2009 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
2010 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 2011 | */ |
705e76be TH |
2012 | if (rc) |
2013 | return rc; | |
1fdffbce | 2014 | |
624d5c51 TH |
2015 | /* if device 1 was found in ata_devchk, wait for register |
2016 | * access briefly, then wait for BSY to clear. | |
2017 | */ | |
2018 | if (dev1) { | |
2019 | int i; | |
1fdffbce | 2020 | |
5682ed33 | 2021 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 2022 | |
624d5c51 TH |
2023 | /* Wait for register access. Some ATAPI devices fail |
2024 | * to set nsect/lbal after reset, so don't waste too | |
2025 | * much time on it. We're gonna wait for !BSY anyway. | |
2026 | */ | |
2027 | for (i = 0; i < 2; i++) { | |
2028 | u8 nsect, lbal; | |
2029 | ||
2030 | nsect = ioread8(ioaddr->nsect_addr); | |
2031 | lbal = ioread8(ioaddr->lbal_addr); | |
2032 | if ((nsect == 1) && (lbal == 1)) | |
2033 | break; | |
2034 | msleep(50); /* give drive a breather */ | |
2035 | } | |
2036 | ||
705e76be | 2037 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
2038 | if (rc) { |
2039 | if (rc != -ENODEV) | |
2040 | return rc; | |
2041 | ret = rc; | |
2042 | } | |
1fdffbce JG |
2043 | } |
2044 | ||
624d5c51 | 2045 | /* is all this really necessary? */ |
5682ed33 | 2046 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 2047 | if (dev1) |
5682ed33 | 2048 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2049 | if (dev0) |
5682ed33 | 2050 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2051 | |
2052 | return ret; | |
1fdffbce | 2053 | } |
0fe40ff8 | 2054 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 2055 | |
624d5c51 TH |
2056 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
2057 | unsigned long deadline) | |
2cc432ee | 2058 | { |
624d5c51 | 2059 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 2060 | |
624d5c51 TH |
2061 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
2062 | ||
2063 | /* software reset. causes dev0 to be selected */ | |
2064 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2065 | udelay(20); /* FIXME: flush */ | |
2066 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
2067 | udelay(20); /* FIXME: flush */ | |
2068 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2069 | ||
705e76be TH |
2070 | /* wait the port to become ready */ |
2071 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
2072 | } |
2073 | ||
6d97dbd7 | 2074 | /** |
9363c382 | 2075 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
2076 | * @link: ATA link to reset |
2077 | * @classes: resulting classes of attached devices | |
2078 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2079 | * |
624d5c51 | 2080 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
2081 | * |
2082 | * LOCKING: | |
624d5c51 TH |
2083 | * Kernel thread context (may sleep) |
2084 | * | |
2085 | * RETURNS: | |
2086 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2087 | */ |
9363c382 | 2088 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 2089 | unsigned long deadline) |
6d97dbd7 | 2090 | { |
624d5c51 TH |
2091 | struct ata_port *ap = link->ap; |
2092 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2093 | unsigned int devmask = 0; | |
2094 | int rc; | |
2095 | u8 err; | |
6d97dbd7 | 2096 | |
624d5c51 | 2097 | DPRINTK("ENTER\n"); |
6d97dbd7 | 2098 | |
624d5c51 TH |
2099 | /* determine if device 0/1 are present */ |
2100 | if (ata_devchk(ap, 0)) | |
2101 | devmask |= (1 << 0); | |
2102 | if (slave_possible && ata_devchk(ap, 1)) | |
2103 | devmask |= (1 << 1); | |
2104 | ||
2105 | /* select device 0 again */ | |
5682ed33 | 2106 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2107 | |
2108 | /* issue bus reset */ | |
2109 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2110 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2111 | /* if link is occupied, -ENODEV too is an error */ | |
2112 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
2113 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
2114 | return rc; | |
2115 | } | |
0f0a3ad3 | 2116 | |
624d5c51 | 2117 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2118 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2119 | devmask & (1 << 0), &err); |
2120 | if (slave_possible && err != 0x81) | |
9363c382 | 2121 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2122 | devmask & (1 << 1), &err); |
2123 | ||
624d5c51 TH |
2124 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2125 | return 0; | |
6d97dbd7 | 2126 | } |
0fe40ff8 | 2127 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2128 | |
2129 | /** | |
9363c382 | 2130 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2131 | * @link: link to reset |
2132 | * @class: resulting class of attached device | |
2133 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2134 | * |
624d5c51 TH |
2135 | * SATA phy-reset host port using DET bits of SControl register, |
2136 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2137 | * |
2138 | * LOCKING: | |
624d5c51 TH |
2139 | * Kernel thread context (may sleep) |
2140 | * | |
2141 | * RETURNS: | |
2142 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2143 | */ |
9363c382 | 2144 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2145 | unsigned long deadline) |
6d97dbd7 | 2146 | { |
9dadd45b TH |
2147 | struct ata_eh_context *ehc = &link->eh_context; |
2148 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2149 | bool online; | |
624d5c51 TH |
2150 | int rc; |
2151 | ||
9dadd45b TH |
2152 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2153 | ata_sff_check_ready); | |
9dadd45b TH |
2154 | if (online) |
2155 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2156 | |
2157 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2158 | return rc; |
6d97dbd7 | 2159 | } |
0fe40ff8 | 2160 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2161 | |
203c75b8 TH |
2162 | /** |
2163 | * ata_sff_postreset - SFF postreset callback | |
2164 | * @link: the target SFF ata_link | |
2165 | * @classes: classes of attached devices | |
2166 | * | |
2167 | * This function is invoked after a successful reset. It first | |
2168 | * calls ata_std_postreset() and performs SFF specific postreset | |
2169 | * processing. | |
2170 | * | |
2171 | * LOCKING: | |
2172 | * Kernel thread context (may sleep) | |
2173 | */ | |
2174 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2175 | { | |
2176 | struct ata_port *ap = link->ap; | |
2177 | ||
2178 | ata_std_postreset(link, classes); | |
2179 | ||
2180 | /* is double-select really necessary? */ | |
2181 | if (classes[0] != ATA_DEV_NONE) | |
2182 | ap->ops->sff_dev_select(ap, 1); | |
2183 | if (classes[1] != ATA_DEV_NONE) | |
2184 | ap->ops->sff_dev_select(ap, 0); | |
2185 | ||
2186 | /* bail out if no device is present */ | |
2187 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2188 | DPRINTK("EXIT, no device\n"); | |
2189 | return; | |
2190 | } | |
2191 | ||
2192 | /* set up device control */ | |
2193 | if (ap->ioaddr.ctl_addr) | |
2194 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | |
2195 | } | |
0fe40ff8 | 2196 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2197 | |
6d97dbd7 | 2198 | /** |
9363c382 | 2199 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2200 | * @ap: port to handle error for |
6d97dbd7 | 2201 | * |
9363c382 | 2202 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2203 | * PATA and SATA controllers. Many controllers should be able to |
2204 | * use this EH as-is or with some added handling before and | |
2205 | * after. | |
2206 | * | |
6d97dbd7 TH |
2207 | * LOCKING: |
2208 | * Kernel thread context (may sleep) | |
2209 | */ | |
9363c382 | 2210 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2211 | { |
a1efdaba TH |
2212 | ata_reset_fn_t softreset = ap->ops->softreset; |
2213 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2214 | struct ata_queued_cmd *qc; |
2215 | unsigned long flags; | |
2216 | int thaw = 0; | |
2217 | ||
9af5c9c9 | 2218 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2219 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2220 | qc = NULL; | |
2221 | ||
2222 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2223 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2224 | |
6d97dbd7 TH |
2225 | ap->hsm_task_state = HSM_ST_IDLE; |
2226 | ||
ed82f964 TH |
2227 | if (ap->ioaddr.bmdma_addr && |
2228 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2229 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2230 | u8 host_stat; |
2231 | ||
fbbb262d | 2232 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2233 | |
6d97dbd7 TH |
2234 | /* BMDMA controllers indicate host bus error by |
2235 | * setting DMA_ERR bit and timing out. As it wasn't | |
2236 | * really a timeout event, adjust error mask and | |
2237 | * cancel frozen state. | |
2238 | */ | |
18d90deb | 2239 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
2240 | qc->err_mask = AC_ERR_HOST_BUS; |
2241 | thaw = 1; | |
2242 | } | |
2243 | ||
2244 | ap->ops->bmdma_stop(qc); | |
2245 | } | |
2246 | ||
a57c1bad | 2247 | ata_sff_sync(ap); /* FIXME: We don't need this */ |
5682ed33 TH |
2248 | ap->ops->sff_check_status(ap); |
2249 | ap->ops->sff_irq_clear(ap); | |
6d97dbd7 | 2250 | |
ba6a1308 | 2251 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
2252 | |
2253 | if (thaw) | |
2254 | ata_eh_thaw_port(ap); | |
2255 | ||
2256 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 2257 | |
57c9efdf TH |
2258 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2259 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2260 | */ |
9363c382 | 2261 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2262 | softreset = NULL; |
57c9efdf | 2263 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2264 | hardreset = NULL; |
6d97dbd7 | 2265 | |
a1efdaba TH |
2266 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2267 | ap->ops->postreset); | |
6d97dbd7 | 2268 | } |
0fe40ff8 | 2269 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 TH |
2270 | |
2271 | /** | |
9363c382 | 2272 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2273 | * @qc: internal command to clean up |
2274 | * | |
2275 | * LOCKING: | |
2276 | * Kernel thread context (may sleep) | |
2277 | */ | |
9363c382 | 2278 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2279 | { |
570106df TH |
2280 | struct ata_port *ap = qc->ap; |
2281 | unsigned long flags; | |
2282 | ||
2283 | spin_lock_irqsave(ap->lock, flags); | |
2284 | ||
2285 | ap->hsm_task_state = HSM_ST_IDLE; | |
2286 | ||
2287 | if (ap->ioaddr.bmdma_addr) | |
61dd08c6 | 2288 | ata_bmdma_stop(qc); |
570106df TH |
2289 | |
2290 | spin_unlock_irqrestore(ap->lock, flags); | |
6d97dbd7 | 2291 | } |
0fe40ff8 | 2292 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); |
6d97dbd7 | 2293 | |
d92e74d3 AC |
2294 | /** |
2295 | * ata_sff_port_start - Set port up for dma. | |
2296 | * @ap: Port to initialize | |
2297 | * | |
2298 | * Called just after data structures for each port are | |
2299 | * initialized. Allocates space for PRD table if the device | |
2300 | * is DMA capable SFF. | |
2301 | * | |
2302 | * May be used as the port_start() entry in ata_port_operations. | |
2303 | * | |
2304 | * LOCKING: | |
2305 | * Inherited from caller. | |
2306 | */ | |
d92e74d3 AC |
2307 | int ata_sff_port_start(struct ata_port *ap) |
2308 | { | |
2309 | if (ap->ioaddr.bmdma_addr) | |
2310 | return ata_port_start(ap); | |
2311 | return 0; | |
2312 | } | |
0fe40ff8 | 2313 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
d92e74d3 | 2314 | |
624d5c51 | 2315 | /** |
9363c382 | 2316 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2317 | * @ioaddr: IO address structure to be initialized |
2318 | * | |
2319 | * Utility function which initializes data_addr, error_addr, | |
2320 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2321 | * device_addr, status_addr, and command_addr to standard offsets | |
2322 | * relative to cmd_addr. | |
2323 | * | |
2324 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2325 | */ | |
9363c382 | 2326 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2327 | { |
2328 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2329 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2330 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2331 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2332 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2333 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2334 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2335 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2336 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2337 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2338 | } | |
0fe40ff8 | 2339 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2340 | |
9363c382 TH |
2341 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, |
2342 | unsigned long xfer_mask) | |
071ce34d TH |
2343 | { |
2344 | /* Filter out DMA modes if the device has been configured by | |
2345 | the BIOS as PIO only */ | |
2346 | ||
2347 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2348 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2349 | return xfer_mask; | |
2350 | } | |
0fe40ff8 | 2351 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); |
071ce34d | 2352 | |
272f7884 TH |
2353 | /** |
2354 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2355 | * @qc: Info associated with this ATA transaction. | |
2356 | * | |
2357 | * LOCKING: | |
2358 | * spin_lock_irqsave(host lock) | |
2359 | */ | |
2360 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2361 | { | |
2362 | struct ata_port *ap = qc->ap; | |
2363 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2364 | u8 dmactl; | |
2365 | ||
2366 | /* load PRD table addr. */ | |
2367 | mb(); /* make sure PRD table writes are visible to controller */ | |
2368 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2369 | ||
2370 | /* specify data direction, triple-check start bit is clear */ | |
2371 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2372 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2373 | if (!rw) | |
2374 | dmactl |= ATA_DMA_WR; | |
2375 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2376 | ||
2377 | /* issue r/w command */ | |
5682ed33 | 2378 | ap->ops->sff_exec_command(ap, &qc->tf); |
272f7884 | 2379 | } |
0fe40ff8 | 2380 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
272f7884 TH |
2381 | |
2382 | /** | |
2383 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2384 | * @qc: Info associated with this ATA transaction. | |
2385 | * | |
2386 | * LOCKING: | |
2387 | * spin_lock_irqsave(host lock) | |
2388 | */ | |
2389 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2390 | { | |
2391 | struct ata_port *ap = qc->ap; | |
2392 | u8 dmactl; | |
2393 | ||
2394 | /* start host DMA transaction */ | |
2395 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2396 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2397 | ||
2398 | /* Strictly, one may wish to issue an ioread8() here, to | |
2399 | * flush the mmio write. However, control also passes | |
2400 | * to the hardware at this point, and it will interrupt | |
2401 | * us when we are to resume control. So, in effect, | |
2402 | * we don't care when the mmio write flushes. | |
2403 | * Further, a read of the DMA status register _immediately_ | |
2404 | * following the write may not be what certain flaky hardware | |
2405 | * is expected, so I think it is best to not add a readb() | |
2406 | * without first all the MMIO ATA cards/mobos. | |
2407 | * Or maybe I'm just being paranoid. | |
2408 | * | |
2409 | * FIXME: The posting of this write means I/O starts are | |
2410 | * unneccessarily delayed for MMIO | |
2411 | */ | |
2412 | } | |
0fe40ff8 | 2413 | EXPORT_SYMBOL_GPL(ata_bmdma_start); |
272f7884 TH |
2414 | |
2415 | /** | |
2416 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2417 | * @qc: Command we are ending DMA for | |
2418 | * | |
2419 | * Clears the ATA_DMA_START flag in the dma control register | |
2420 | * | |
2421 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2422 | * | |
2423 | * LOCKING: | |
2424 | * spin_lock_irqsave(host lock) | |
2425 | */ | |
2426 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2427 | { | |
2428 | struct ata_port *ap = qc->ap; | |
2429 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2430 | ||
2431 | /* clear start/stop bit */ | |
2432 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2433 | mmio + ATA_DMA_CMD); | |
2434 | ||
2435 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
a57c1bad | 2436 | ata_sff_dma_pause(ap); |
272f7884 | 2437 | } |
0fe40ff8 | 2438 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); |
272f7884 TH |
2439 | |
2440 | /** | |
2441 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2442 | * @ap: Port associated with this ATA transaction. | |
2443 | * | |
2444 | * Read and return BMDMA status register. | |
2445 | * | |
2446 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2447 | * | |
2448 | * LOCKING: | |
2449 | * spin_lock_irqsave(host lock) | |
2450 | */ | |
2451 | u8 ata_bmdma_status(struct ata_port *ap) | |
2452 | { | |
2453 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2454 | } | |
0fe40ff8 | 2455 | EXPORT_SYMBOL_GPL(ata_bmdma_status); |
272f7884 TH |
2456 | |
2457 | /** | |
624d5c51 TH |
2458 | * ata_bus_reset - reset host port and associated ATA channel |
2459 | * @ap: port to reset | |
2460 | * | |
2461 | * This is typically the first time we actually start issuing | |
2462 | * commands to the ATA channel. We wait for BSY to clear, then | |
2463 | * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its | |
2464 | * result. Determine what devices, if any, are on the channel | |
2465 | * by looking at the device 0/1 error register. Look at the signature | |
2466 | * stored in each device's taskfile registers, to determine if | |
2467 | * the device is ATA or ATAPI. | |
2468 | * | |
2469 | * LOCKING: | |
2470 | * PCI/etc. bus probe sem. | |
2471 | * Obtains host lock. | |
2472 | * | |
2473 | * SIDE EFFECTS: | |
2474 | * Sets ATA_FLAG_DISABLED if bus reset fails. | |
2475 | * | |
2476 | * DEPRECATED: | |
2477 | * This function is only for drivers which still use old EH and | |
2478 | * will be removed soon. | |
272f7884 | 2479 | */ |
624d5c51 | 2480 | void ata_bus_reset(struct ata_port *ap) |
272f7884 | 2481 | { |
624d5c51 TH |
2482 | struct ata_device *device = ap->link.device; |
2483 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
2484 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2485 | u8 err; | |
2486 | unsigned int dev0, dev1 = 0, devmask = 0; | |
2487 | int rc; | |
2488 | ||
2489 | DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no); | |
2490 | ||
2491 | /* determine if device 0/1 are present */ | |
2492 | if (ap->flags & ATA_FLAG_SATA_RESET) | |
2493 | dev0 = 1; | |
2494 | else { | |
2495 | dev0 = ata_devchk(ap, 0); | |
2496 | if (slave_possible) | |
2497 | dev1 = ata_devchk(ap, 1); | |
2498 | } | |
2499 | ||
2500 | if (dev0) | |
2501 | devmask |= (1 << 0); | |
2502 | if (dev1) | |
2503 | devmask |= (1 << 1); | |
2504 | ||
2505 | /* select device 0 again */ | |
5682ed33 | 2506 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2507 | |
2508 | /* issue bus reset */ | |
2509 | if (ap->flags & ATA_FLAG_SRST) { | |
341c2c95 TH |
2510 | rc = ata_bus_softreset(ap, devmask, |
2511 | ata_deadline(jiffies, 40000)); | |
624d5c51 TH |
2512 | if (rc && rc != -ENODEV) |
2513 | goto err_out; | |
2514 | } | |
2515 | ||
2516 | /* | |
2517 | * determine by signature whether we have ATA or ATAPI devices | |
2518 | */ | |
9363c382 | 2519 | device[0].class = ata_sff_dev_classify(&device[0], dev0, &err); |
624d5c51 | 2520 | if ((slave_possible) && (err != 0x81)) |
9363c382 | 2521 | device[1].class = ata_sff_dev_classify(&device[1], dev1, &err); |
624d5c51 TH |
2522 | |
2523 | /* is double-select really necessary? */ | |
2524 | if (device[1].class != ATA_DEV_NONE) | |
5682ed33 | 2525 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2526 | if (device[0].class != ATA_DEV_NONE) |
5682ed33 | 2527 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2528 | |
2529 | /* if no devices were detected, disable this port */ | |
2530 | if ((device[0].class == ATA_DEV_NONE) && | |
2531 | (device[1].class == ATA_DEV_NONE)) | |
2532 | goto err_out; | |
2533 | ||
2534 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | |
2535 | /* set up device control for ATA_FLAG_SATA_RESET */ | |
2536 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2537 | } | |
2538 | ||
2539 | DPRINTK("EXIT\n"); | |
2540 | return; | |
2541 | ||
2542 | err_out: | |
2543 | ata_port_printk(ap, KERN_ERR, "disabling port\n"); | |
2544 | ata_port_disable(ap); | |
2545 | ||
2546 | DPRINTK("EXIT\n"); | |
272f7884 | 2547 | } |
0fe40ff8 | 2548 | EXPORT_SYMBOL_GPL(ata_bus_reset); |
272f7884 | 2549 | |
1fdffbce | 2550 | #ifdef CONFIG_PCI |
4112e16a | 2551 | |
272f7884 | 2552 | /** |
9363c382 | 2553 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex |
272f7884 TH |
2554 | * @pdev: PCI device |
2555 | * | |
2556 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2557 | * enter non simplex mode. This implements the necessary logic to | |
2558 | * perform the task on such devices. Calling it on other devices will | |
2559 | * have -undefined- behaviour. | |
2560 | */ | |
9363c382 | 2561 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) |
4112e16a | 2562 | { |
272f7884 TH |
2563 | unsigned long bmdma = pci_resource_start(pdev, 4); |
2564 | u8 simplex; | |
a84471fe | 2565 | |
272f7884 TH |
2566 | if (bmdma == 0) |
2567 | return -ENOENT; | |
2568 | ||
2569 | simplex = inb(bmdma + 0x02); | |
2570 | outb(simplex & 0x60, bmdma + 0x02); | |
2571 | simplex = inb(bmdma + 0x02); | |
2572 | if (simplex & 0x80) | |
2573 | return -EOPNOTSUPP; | |
2574 | return 0; | |
2575 | } | |
0fe40ff8 | 2576 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); |
272f7884 | 2577 | |
0f834de3 | 2578 | /** |
9363c382 | 2579 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host |
0f834de3 TH |
2580 | * @host: target ATA host |
2581 | * | |
2582 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
2583 | * | |
2584 | * LOCKING: | |
2585 | * Inherited from calling layer (may sleep). | |
2586 | * | |
2587 | * RETURNS: | |
2588 | * 0 on success, -errno otherwise. | |
2589 | */ | |
9363c382 | 2590 | int ata_pci_bmdma_init(struct ata_host *host) |
1fdffbce | 2591 | { |
0f834de3 TH |
2592 | struct device *gdev = host->dev; |
2593 | struct pci_dev *pdev = to_pci_dev(gdev); | |
2594 | int i, rc; | |
0d5ff566 | 2595 | |
6fdc99a2 AC |
2596 | /* No BAR4 allocation: No DMA */ |
2597 | if (pci_resource_start(pdev, 4) == 0) | |
2598 | return 0; | |
2599 | ||
0f834de3 TH |
2600 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
2601 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
2602 | if (rc) | |
2603 | return rc; | |
2604 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
2605 | if (rc) | |
2606 | return rc; | |
2607 | ||
2608 | /* request and iomap DMA region */ | |
35a10a80 | 2609 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
2610 | if (rc) { |
2611 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
2612 | return -ENOMEM; | |
0d5ff566 | 2613 | } |
0f834de3 | 2614 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 2615 | |
1626aeb8 | 2616 | for (i = 0; i < 2; i++) { |
0f834de3 | 2617 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
2618 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
2619 | ||
2620 | if (ata_port_is_dummy(ap)) | |
2621 | continue; | |
2622 | ||
21b0ad4f | 2623 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
2624 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
2625 | (ioread8(bmdma + 2) & 0x80)) | |
2626 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
2627 | |
2628 | ata_port_desc(ap, "bmdma 0x%llx", | |
0fe40ff8 | 2629 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); |
0d5ff566 TH |
2630 | } |
2631 | ||
0f834de3 TH |
2632 | return 0; |
2633 | } | |
0fe40ff8 | 2634 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); |
2ec7df04 | 2635 | |
272f7884 TH |
2636 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2637 | { | |
2638 | int i; | |
2639 | ||
2640 | /* Check the PCI resources for this channel are enabled */ | |
2641 | port = port * 2; | |
0fe40ff8 | 2642 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2643 | if (pci_resource_start(pdev, port + i) == 0 || |
2644 | pci_resource_len(pdev, port + i) == 0) | |
2645 | return 0; | |
2646 | } | |
2647 | return 1; | |
2648 | } | |
2649 | ||
d491b27b | 2650 | /** |
9363c382 | 2651 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2652 | * @host: target ATA host |
d491b27b | 2653 | * |
1626aeb8 TH |
2654 | * Acquire native PCI ATA resources for @host and initialize the |
2655 | * first two ports of @host accordingly. Ports marked dummy are | |
2656 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2657 | * |
d583bc18 TH |
2658 | * Note that native PCI resources are valid even for legacy hosts |
2659 | * as we fix up pdev resources array early in boot, so this | |
2660 | * function can be used for both native and legacy SFF hosts. | |
2661 | * | |
d491b27b TH |
2662 | * LOCKING: |
2663 | * Inherited from calling layer (may sleep). | |
2664 | * | |
2665 | * RETURNS: | |
1626aeb8 TH |
2666 | * 0 if at least one port is initialized, -ENODEV if no port is |
2667 | * available. | |
d491b27b | 2668 | */ |
9363c382 | 2669 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2670 | { |
2671 | struct device *gdev = host->dev; | |
2672 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2673 | unsigned int mask = 0; |
d491b27b TH |
2674 | int i, rc; |
2675 | ||
d491b27b TH |
2676 | /* request, iomap BARs and init port addresses accordingly */ |
2677 | for (i = 0; i < 2; i++) { | |
2678 | struct ata_port *ap = host->ports[i]; | |
2679 | int base = i * 2; | |
2680 | void __iomem * const *iomap; | |
2681 | ||
1626aeb8 TH |
2682 | if (ata_port_is_dummy(ap)) |
2683 | continue; | |
2684 | ||
2685 | /* Discard disabled ports. Some controllers show | |
2686 | * their unused channels this way. Disabled ports are | |
2687 | * made dummy. | |
2688 | */ | |
2689 | if (!ata_resources_present(pdev, i)) { | |
2690 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2691 | continue; |
1626aeb8 | 2692 | } |
d491b27b | 2693 | |
35a10a80 TH |
2694 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2695 | dev_driver_string(gdev)); | |
d491b27b | 2696 | if (rc) { |
1626aeb8 TH |
2697 | dev_printk(KERN_WARNING, gdev, |
2698 | "failed to request/iomap BARs for port %d " | |
2699 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2700 | if (rc == -EBUSY) |
2701 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2702 | ap->ops = &ata_dummy_port_ops; |
2703 | continue; | |
d491b27b TH |
2704 | } |
2705 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2706 | ||
2707 | ap->ioaddr.cmd_addr = iomap[base]; | |
2708 | ap->ioaddr.altstatus_addr = | |
2709 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2710 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2711 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2712 | |
cbcdd875 TH |
2713 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2714 | (unsigned long long)pci_resource_start(pdev, base), | |
2715 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2716 | ||
1626aeb8 TH |
2717 | mask |= 1 << i; |
2718 | } | |
2719 | ||
2720 | if (!mask) { | |
2721 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2722 | return -ENODEV; | |
d491b27b TH |
2723 | } |
2724 | ||
2725 | return 0; | |
2726 | } | |
0fe40ff8 | 2727 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2728 | |
21b0ad4f | 2729 | /** |
9363c382 | 2730 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2731 | * @pdev: target PCI device |
1626aeb8 | 2732 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2733 | * @r_host: out argument for the initialized ATA host |
2734 | * | |
2735 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2736 | * resources and initialize it accordingly in one go. | |
2737 | * | |
2738 | * LOCKING: | |
2739 | * Inherited from calling layer (may sleep). | |
2740 | * | |
2741 | * RETURNS: | |
2742 | * 0 on success, -errno otherwise. | |
2743 | */ | |
9363c382 | 2744 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2745 | const struct ata_port_info * const *ppi, |
d583bc18 | 2746 | struct ata_host **r_host) |
21b0ad4f TH |
2747 | { |
2748 | struct ata_host *host; | |
21b0ad4f TH |
2749 | int rc; |
2750 | ||
2751 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2752 | return -ENOMEM; | |
2753 | ||
2754 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2755 | if (!host) { | |
2756 | dev_printk(KERN_ERR, &pdev->dev, | |
2757 | "failed to allocate ATA host\n"); | |
2758 | rc = -ENOMEM; | |
2759 | goto err_out; | |
2760 | } | |
2761 | ||
9363c382 | 2762 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2763 | if (rc) |
2764 | goto err_out; | |
2765 | ||
2766 | /* init DMA related stuff */ | |
9363c382 | 2767 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2768 | if (rc) |
2769 | goto err_bmdma; | |
2770 | ||
2771 | devres_remove_group(&pdev->dev, NULL); | |
2772 | *r_host = host; | |
2773 | return 0; | |
2774 | ||
0fe40ff8 | 2775 | err_bmdma: |
21b0ad4f TH |
2776 | /* This is necessary because PCI and iomap resources are |
2777 | * merged and releasing the top group won't release the | |
2778 | * acquired resources if some of those have been acquired | |
2779 | * before entering this function. | |
2780 | */ | |
2781 | pcim_iounmap_regions(pdev, 0xf); | |
0fe40ff8 | 2782 | err_out: |
21b0ad4f TH |
2783 | devres_release_group(&pdev->dev, NULL); |
2784 | return rc; | |
2785 | } | |
0fe40ff8 | 2786 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2787 | |
4e6b79fa | 2788 | /** |
9363c382 | 2789 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2790 | * @host: target SFF ATA host |
2791 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2792 | * @sht: scsi_host_template to use when registering the host | |
2793 | * | |
2794 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2795 | * hosts. This separate helper is necessary because SFF hosts | |
2796 | * use two separate interrupts in legacy mode. | |
2797 | * | |
2798 | * LOCKING: | |
2799 | * Inherited from calling layer (may sleep). | |
2800 | * | |
2801 | * RETURNS: | |
2802 | * 0 on success, -errno otherwise. | |
2803 | */ | |
9363c382 | 2804 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2805 | irq_handler_t irq_handler, |
2806 | struct scsi_host_template *sht) | |
2807 | { | |
2808 | struct device *dev = host->dev; | |
2809 | struct pci_dev *pdev = to_pci_dev(dev); | |
2810 | const char *drv_name = dev_driver_string(host->dev); | |
2811 | int legacy_mode = 0, rc; | |
2812 | ||
2813 | rc = ata_host_start(host); | |
2814 | if (rc) | |
2815 | return rc; | |
2816 | ||
2817 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2818 | u8 tmp8, mask; | |
2819 | ||
2820 | /* TODO: What if one channel is in native mode ... */ | |
2821 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2822 | mask = (1 << 2) | (1 << 0); | |
2823 | if ((tmp8 & mask) != mask) | |
2824 | legacy_mode = 1; | |
2825 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2826 | /* Some platforms with PCI limits cannot address compat | |
2827 | port space. In that case we punt if their firmware has | |
2828 | left a device in compatibility mode */ | |
2829 | if (legacy_mode) { | |
2830 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2831 | return -EOPNOTSUPP; | |
2832 | } | |
2833 | #endif | |
2834 | } | |
2835 | ||
2836 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2837 | return -ENOMEM; | |
2838 | ||
2839 | if (!legacy_mode && pdev->irq) { | |
2840 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2841 | IRQF_SHARED, drv_name, host); | |
2842 | if (rc) | |
2843 | goto out; | |
2844 | ||
2845 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2846 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2847 | } else if (legacy_mode) { | |
2848 | if (!ata_port_is_dummy(host->ports[0])) { | |
2849 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2850 | irq_handler, IRQF_SHARED, | |
2851 | drv_name, host); | |
2852 | if (rc) | |
2853 | goto out; | |
2854 | ||
2855 | ata_port_desc(host->ports[0], "irq %d", | |
2856 | ATA_PRIMARY_IRQ(pdev)); | |
2857 | } | |
2858 | ||
2859 | if (!ata_port_is_dummy(host->ports[1])) { | |
2860 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2861 | irq_handler, IRQF_SHARED, | |
2862 | drv_name, host); | |
2863 | if (rc) | |
2864 | goto out; | |
2865 | ||
2866 | ata_port_desc(host->ports[1], "irq %d", | |
2867 | ATA_SECONDARY_IRQ(pdev)); | |
2868 | } | |
2869 | } | |
2870 | ||
2871 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2872 | out: |
4e6b79fa TH |
2873 | if (rc == 0) |
2874 | devres_remove_group(dev, NULL); | |
2875 | else | |
2876 | devres_release_group(dev, NULL); | |
2877 | ||
2878 | return rc; | |
2879 | } | |
0fe40ff8 | 2880 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2881 | |
1fdffbce | 2882 | /** |
9363c382 | 2883 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2884 | * @pdev: Controller to be initialized |
1626aeb8 | 2885 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2886 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2887 | * @host_priv: host private_data |
1fdffbce JG |
2888 | * |
2889 | * This is a helper function which can be called from a driver's | |
2890 | * xxx_init_one() probe function if the hardware uses traditional | |
2891 | * IDE taskfile registers. | |
2892 | * | |
2893 | * This function calls pci_enable_device(), reserves its register | |
2894 | * regions, sets the dma mask, enables bus master mode, and calls | |
2895 | * ata_device_add() | |
2896 | * | |
2ec7df04 AC |
2897 | * ASSUMPTION: |
2898 | * Nobody makes a single channel controller that appears solely as | |
2899 | * the secondary legacy port on PCI. | |
2900 | * | |
1fdffbce JG |
2901 | * LOCKING: |
2902 | * Inherited from PCI layer (may sleep). | |
2903 | * | |
2904 | * RETURNS: | |
2905 | * Zero on success, negative on errno-based value on error. | |
2906 | */ | |
9363c382 | 2907 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
0fe40ff8 | 2908 | const struct ata_port_info * const *ppi, |
9363c382 | 2909 | struct scsi_host_template *sht, void *host_priv) |
1fdffbce | 2910 | { |
f0d36efd | 2911 | struct device *dev = &pdev->dev; |
1626aeb8 | 2912 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2913 | struct ata_host *host = NULL; |
1626aeb8 | 2914 | int i, rc; |
1fdffbce JG |
2915 | |
2916 | DPRINTK("ENTER\n"); | |
2917 | ||
1626aeb8 TH |
2918 | /* look up the first valid port_info */ |
2919 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2920 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2921 | pi = ppi[i]; | |
2922 | break; | |
2923 | } | |
2924 | } | |
f0d36efd | 2925 | |
1626aeb8 TH |
2926 | if (!pi) { |
2927 | dev_printk(KERN_ERR, &pdev->dev, | |
2928 | "no valid port_info specified\n"); | |
2929 | return -EINVAL; | |
2930 | } | |
c791c306 | 2931 | |
1626aeb8 TH |
2932 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2933 | return -ENOMEM; | |
1fdffbce | 2934 | |
f0d36efd | 2935 | rc = pcim_enable_device(pdev); |
1fdffbce | 2936 | if (rc) |
4e6b79fa | 2937 | goto out; |
1fdffbce | 2938 | |
4e6b79fa | 2939 | /* prepare and activate SFF host */ |
9363c382 | 2940 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2941 | if (rc) |
4e6b79fa | 2942 | goto out; |
887125e3 | 2943 | host->private_data = host_priv; |
d491b27b | 2944 | |
d491b27b | 2945 | pci_set_master(pdev); |
9363c382 | 2946 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2947 | out: |
4e6b79fa TH |
2948 | if (rc == 0) |
2949 | devres_remove_group(&pdev->dev, NULL); | |
2950 | else | |
2951 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2952 | |
1fdffbce JG |
2953 | return rc; |
2954 | } | |
0fe40ff8 | 2955 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2956 | |
2957 | #endif /* CONFIG_PCI */ | |
2958 |