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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
90088bb4 TH |
41 | /** |
42 | * ata_irq_on - Enable interrupts on a port. | |
43 | * @ap: Port on which interrupts are enabled. | |
44 | * | |
45 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
46 | * wait for idle, clear any pending interrupts. | |
47 | * | |
48 | * LOCKING: | |
49 | * Inherited from caller. | |
50 | */ | |
51 | u8 ata_irq_on(struct ata_port *ap) | |
52 | { | |
53 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
54 | u8 tmp; | |
55 | ||
56 | ap->ctl &= ~ATA_NIEN; | |
57 | ap->last_ctl = ap->ctl; | |
58 | ||
f659f0e4 TH |
59 | if (ioaddr->ctl_addr) |
60 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
90088bb4 TH |
61 | tmp = ata_wait_idle(ap); |
62 | ||
63 | ap->ops->irq_clear(ap); | |
64 | ||
65 | return tmp; | |
66 | } | |
67 | ||
1fdffbce | 68 | /** |
0d5ff566 | 69 | * ata_tf_load - send taskfile registers to host controller |
1fdffbce JG |
70 | * @ap: Port to which output is sent |
71 | * @tf: ATA taskfile register set | |
72 | * | |
73 | * Outputs ATA taskfile to standard ATA host controller. | |
74 | * | |
75 | * LOCKING: | |
76 | * Inherited from caller. | |
77 | */ | |
78 | ||
0d5ff566 | 79 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
80 | { |
81 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
82 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
83 | ||
84 | if (tf->ctl != ap->last_ctl) { | |
f659f0e4 TH |
85 | if (ioaddr->ctl_addr) |
86 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
1fdffbce JG |
87 | ap->last_ctl = tf->ctl; |
88 | ata_wait_idle(ap); | |
89 | } | |
90 | ||
91 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
f659f0e4 | 92 | WARN_ON(!ioaddr->ctl_addr); |
0d5ff566 TH |
93 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
94 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
95 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
96 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
97 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
98 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
99 | tf->hob_feature, | |
100 | tf->hob_nsect, | |
101 | tf->hob_lbal, | |
102 | tf->hob_lbam, | |
103 | tf->hob_lbah); | |
104 | } | |
105 | ||
106 | if (is_addr) { | |
0d5ff566 TH |
107 | iowrite8(tf->feature, ioaddr->feature_addr); |
108 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
109 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
110 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
111 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
112 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
113 | tf->feature, | |
114 | tf->nsect, | |
115 | tf->lbal, | |
116 | tf->lbam, | |
117 | tf->lbah); | |
118 | } | |
119 | ||
120 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
0d5ff566 | 121 | iowrite8(tf->device, ioaddr->device_addr); |
1fdffbce JG |
122 | VPRINTK("device 0x%X\n", tf->device); |
123 | } | |
124 | ||
125 | ata_wait_idle(ap); | |
126 | } | |
127 | ||
1fdffbce | 128 | /** |
0d5ff566 | 129 | * ata_exec_command - issue ATA command to host controller |
1fdffbce JG |
130 | * @ap: port to which command is being issued |
131 | * @tf: ATA taskfile register set | |
132 | * | |
0d5ff566 TH |
133 | * Issues ATA command, with proper synchronization with interrupt |
134 | * handler / other threads. | |
7c74ffd0 | 135 | * |
1fdffbce | 136 | * LOCKING: |
cca3974e | 137 | * spin_lock_irqsave(host lock) |
1fdffbce | 138 | */ |
0d5ff566 | 139 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce | 140 | { |
44877b4e | 141 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
1fdffbce | 142 | |
0d5ff566 | 143 | iowrite8(tf->command, ap->ioaddr.command_addr); |
1fdffbce JG |
144 | ata_pause(ap); |
145 | } | |
146 | ||
1fdffbce | 147 | /** |
0d5ff566 | 148 | * ata_tf_read - input device's ATA taskfile shadow registers |
1fdffbce JG |
149 | * @ap: Port from which input is read |
150 | * @tf: ATA taskfile register set for storing input | |
151 | * | |
152 | * Reads ATA taskfile registers for currently-selected device | |
76548eda AC |
153 | * into @tf. Assumes the device has a fully SFF compliant task file |
154 | * layout and behaviour. If you device does not (eg has a different | |
155 | * status method) then you will need to provide a replacement tf_read | |
1fdffbce JG |
156 | * |
157 | * LOCKING: | |
158 | * Inherited from caller. | |
159 | */ | |
0d5ff566 | 160 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1fdffbce JG |
161 | { |
162 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
163 | ||
76548eda | 164 | tf->command = ata_check_status(ap); |
0d5ff566 TH |
165 | tf->feature = ioread8(ioaddr->error_addr); |
166 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
167 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
168 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
169 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
170 | tf->device = ioread8(ioaddr->device_addr); | |
1fdffbce JG |
171 | |
172 | if (tf->flags & ATA_TFLAG_LBA48) { | |
f659f0e4 TH |
173 | if (likely(ioaddr->ctl_addr)) { |
174 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
175 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
176 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
177 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
178 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
179 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
180 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
181 | ap->last_ctl = tf->ctl; | |
182 | } else | |
183 | WARN_ON(1); | |
1fdffbce JG |
184 | } |
185 | } | |
186 | ||
1fdffbce JG |
187 | /** |
188 | * ata_check_status - Read device status reg & clear interrupt | |
189 | * @ap: port where the device is | |
190 | * | |
191 | * Reads ATA taskfile status register for currently-selected device | |
192 | * and return its value. This also clears pending interrupts | |
193 | * from this device | |
194 | * | |
1fdffbce JG |
195 | * LOCKING: |
196 | * Inherited from caller. | |
197 | */ | |
198 | u8 ata_check_status(struct ata_port *ap) | |
199 | { | |
0d5ff566 | 200 | return ioread8(ap->ioaddr.status_addr); |
1fdffbce JG |
201 | } |
202 | ||
1fdffbce JG |
203 | /** |
204 | * ata_altstatus - Read device alternate status reg | |
205 | * @ap: port where the device is | |
206 | * | |
207 | * Reads ATA taskfile alternate status register for | |
208 | * currently-selected device and return its value. | |
209 | * | |
210 | * Note: may NOT be used as the check_altstatus() entry in | |
211 | * ata_port_operations. | |
212 | * | |
213 | * LOCKING: | |
214 | * Inherited from caller. | |
215 | */ | |
216 | u8 ata_altstatus(struct ata_port *ap) | |
217 | { | |
218 | if (ap->ops->check_altstatus) | |
219 | return ap->ops->check_altstatus(ap); | |
220 | ||
0d5ff566 | 221 | return ioread8(ap->ioaddr.altstatus_addr); |
1fdffbce JG |
222 | } |
223 | ||
2cc432ee | 224 | /** |
0d5ff566 | 225 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
2cc432ee JG |
226 | * @qc: Info associated with this ATA transaction. |
227 | * | |
228 | * LOCKING: | |
cca3974e | 229 | * spin_lock_irqsave(host lock) |
2cc432ee | 230 | */ |
0d5ff566 | 231 | void ata_bmdma_setup(struct ata_queued_cmd *qc) |
2cc432ee JG |
232 | { |
233 | struct ata_port *ap = qc->ap; | |
234 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
235 | u8 dmactl; | |
2cc432ee JG |
236 | |
237 | /* load PRD table addr. */ | |
238 | mb(); /* make sure PRD table writes are visible to controller */ | |
0d5ff566 | 239 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
2cc432ee JG |
240 | |
241 | /* specify data direction, triple-check start bit is clear */ | |
0d5ff566 | 242 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
243 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
244 | if (!rw) | |
245 | dmactl |= ATA_DMA_WR; | |
0d5ff566 | 246 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
247 | |
248 | /* issue r/w command */ | |
249 | ap->ops->exec_command(ap, &qc->tf); | |
250 | } | |
251 | ||
252 | /** | |
0d5ff566 | 253 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
2cc432ee JG |
254 | * @qc: Info associated with this ATA transaction. |
255 | * | |
256 | * LOCKING: | |
cca3974e | 257 | * spin_lock_irqsave(host lock) |
2cc432ee | 258 | */ |
2dcb407e | 259 | void ata_bmdma_start(struct ata_queued_cmd *qc) |
2cc432ee JG |
260 | { |
261 | struct ata_port *ap = qc->ap; | |
2cc432ee JG |
262 | u8 dmactl; |
263 | ||
264 | /* start host DMA transaction */ | |
0d5ff566 TH |
265 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
266 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2cc432ee | 267 | |
e1cc9de8 | 268 | /* Strictly, one may wish to issue an ioread8() here, to |
2cc432ee JG |
269 | * flush the mmio write. However, control also passes |
270 | * to the hardware at this point, and it will interrupt | |
271 | * us when we are to resume control. So, in effect, | |
272 | * we don't care when the mmio write flushes. | |
273 | * Further, a read of the DMA status register _immediately_ | |
274 | * following the write may not be what certain flaky hardware | |
275 | * is expected, so I think it is best to not add a readb() | |
276 | * without first all the MMIO ATA cards/mobos. | |
277 | * Or maybe I'm just being paranoid. | |
e1cc9de8 AC |
278 | * |
279 | * FIXME: The posting of this write means I/O starts are | |
280 | * unneccessarily delayed for MMIO | |
2cc432ee JG |
281 | */ |
282 | } | |
283 | ||
2cc432ee JG |
284 | /** |
285 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
286 | * @ap: Port associated with this ATA transaction. | |
287 | * | |
288 | * Clear interrupt and error flags in DMA status register. | |
289 | * | |
290 | * May be used as the irq_clear() entry in ata_port_operations. | |
291 | * | |
292 | * LOCKING: | |
cca3974e | 293 | * spin_lock_irqsave(host lock) |
2cc432ee | 294 | */ |
2cc432ee JG |
295 | void ata_bmdma_irq_clear(struct ata_port *ap) |
296 | { | |
0d5ff566 TH |
297 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
298 | ||
299 | if (!mmio) | |
2cc432ee JG |
300 | return; |
301 | ||
0d5ff566 | 302 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
2cc432ee JG |
303 | } |
304 | ||
358f9a77 TH |
305 | /** |
306 | * ata_noop_irq_clear - Noop placeholder for irq_clear | |
307 | * @ap: Port associated with this ATA transaction. | |
308 | */ | |
309 | void ata_noop_irq_clear(struct ata_port *ap) | |
310 | { | |
311 | } | |
312 | ||
2cc432ee JG |
313 | /** |
314 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
315 | * @ap: Port associated with this ATA transaction. | |
316 | * | |
317 | * Read and return BMDMA status register. | |
318 | * | |
319 | * May be used as the bmdma_status() entry in ata_port_operations. | |
320 | * | |
321 | * LOCKING: | |
cca3974e | 322 | * spin_lock_irqsave(host lock) |
2cc432ee | 323 | */ |
2cc432ee JG |
324 | u8 ata_bmdma_status(struct ata_port *ap) |
325 | { | |
0d5ff566 | 326 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
2cc432ee JG |
327 | } |
328 | ||
2cc432ee JG |
329 | /** |
330 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
331 | * @qc: Command we are ending DMA for | |
332 | * | |
333 | * Clears the ATA_DMA_START flag in the dma control register | |
334 | * | |
335 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
336 | * | |
337 | * LOCKING: | |
cca3974e | 338 | * spin_lock_irqsave(host lock) |
2cc432ee | 339 | */ |
2cc432ee JG |
340 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
341 | { | |
342 | struct ata_port *ap = qc->ap; | |
0d5ff566 TH |
343 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
344 | ||
345 | /* clear start/stop bit */ | |
346 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
347 | mmio + ATA_DMA_CMD); | |
2cc432ee JG |
348 | |
349 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
350 | ata_altstatus(ap); /* dummy read */ | |
351 | } | |
352 | ||
6d97dbd7 TH |
353 | /** |
354 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
355 | * @ap: port to freeze | |
356 | * | |
357 | * Freeze BMDMA controller port. | |
358 | * | |
359 | * LOCKING: | |
360 | * Inherited from caller. | |
361 | */ | |
362 | void ata_bmdma_freeze(struct ata_port *ap) | |
363 | { | |
364 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
365 | ||
366 | ap->ctl |= ATA_NIEN; | |
367 | ap->last_ctl = ap->ctl; | |
368 | ||
f659f0e4 TH |
369 | if (ioaddr->ctl_addr) |
370 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
0f0a3ad3 TH |
371 | |
372 | /* Under certain circumstances, some controllers raise IRQ on | |
373 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
374 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
375 | */ | |
376 | ata_chk_status(ap); | |
377 | ||
378 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
379 | } |
380 | ||
381 | /** | |
382 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
383 | * @ap: port to thaw | |
384 | * | |
385 | * Thaw BMDMA controller port. | |
386 | * | |
387 | * LOCKING: | |
388 | * Inherited from caller. | |
389 | */ | |
390 | void ata_bmdma_thaw(struct ata_port *ap) | |
391 | { | |
392 | /* clear & re-enable interrupts */ | |
393 | ata_chk_status(ap); | |
394 | ap->ops->irq_clear(ap); | |
83625006 | 395 | ap->ops->irq_on(ap); |
6d97dbd7 TH |
396 | } |
397 | ||
398 | /** | |
a1efdaba | 399 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 400 | * @ap: port to handle error for |
6d97dbd7 | 401 | * |
a1efdaba | 402 | * Stock error handler for BMDMA controller. It can handle both |
6d97dbd7 TH |
403 | * PATA and SATA controllers. Many controllers should be able to |
404 | * use this EH as-is or with some added handling before and | |
405 | * after. | |
406 | * | |
6d97dbd7 TH |
407 | * LOCKING: |
408 | * Kernel thread context (may sleep) | |
409 | */ | |
a1efdaba | 410 | void ata_bmdma_error_handler(struct ata_port *ap) |
6d97dbd7 | 411 | { |
a1efdaba TH |
412 | ata_reset_fn_t softreset = ap->ops->softreset; |
413 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
414 | struct ata_queued_cmd *qc; |
415 | unsigned long flags; | |
416 | int thaw = 0; | |
417 | ||
9af5c9c9 | 418 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
419 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
420 | qc = NULL; | |
421 | ||
422 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 423 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 424 | |
6d97dbd7 TH |
425 | ap->hsm_task_state = HSM_ST_IDLE; |
426 | ||
427 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 428 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
429 | u8 host_stat; |
430 | ||
fbbb262d | 431 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 432 | |
6d97dbd7 TH |
433 | /* BMDMA controllers indicate host bus error by |
434 | * setting DMA_ERR bit and timing out. As it wasn't | |
435 | * really a timeout event, adjust error mask and | |
436 | * cancel frozen state. | |
437 | */ | |
18d90deb | 438 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
439 | qc->err_mask = AC_ERR_HOST_BUS; |
440 | thaw = 1; | |
441 | } | |
442 | ||
443 | ap->ops->bmdma_stop(qc); | |
444 | } | |
445 | ||
446 | ata_altstatus(ap); | |
447 | ata_chk_status(ap); | |
448 | ap->ops->irq_clear(ap); | |
449 | ||
ba6a1308 | 450 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
451 | |
452 | if (thaw) | |
453 | ata_eh_thaw_port(ap); | |
454 | ||
455 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 456 | |
a1efdaba TH |
457 | /* ata_std_softreset and sata_std_hardreset are inherited to |
458 | * all SFF drivers from ata_sff_port_ops. Ignore softreset if | |
459 | * ctl isn't accessible. Ignore hardreset if SCR access isn't | |
460 | * available. | |
461 | */ | |
462 | if (softreset == ata_std_softreset && !ap->ioaddr.ctl_addr) | |
463 | softreset = NULL; | |
464 | if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link)) | |
465 | hardreset = NULL; | |
6d97dbd7 | 466 | |
a1efdaba TH |
467 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
468 | ap->ops->postreset); | |
6d97dbd7 TH |
469 | } |
470 | ||
471 | /** | |
472 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
473 | * BMDMA controller | |
474 | * @qc: internal command to clean up | |
475 | * | |
476 | * LOCKING: | |
477 | * Kernel thread context (may sleep) | |
478 | */ | |
479 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
480 | { | |
61dd08c6 A |
481 | if (qc->ap->ioaddr.bmdma_addr) |
482 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
483 | } |
484 | ||
d92e74d3 AC |
485 | /** |
486 | * ata_sff_port_start - Set port up for dma. | |
487 | * @ap: Port to initialize | |
488 | * | |
489 | * Called just after data structures for each port are | |
490 | * initialized. Allocates space for PRD table if the device | |
491 | * is DMA capable SFF. | |
492 | * | |
493 | * May be used as the port_start() entry in ata_port_operations. | |
494 | * | |
495 | * LOCKING: | |
496 | * Inherited from caller. | |
497 | */ | |
498 | ||
499 | int ata_sff_port_start(struct ata_port *ap) | |
500 | { | |
501 | if (ap->ioaddr.bmdma_addr) | |
502 | return ata_port_start(ap); | |
503 | return 0; | |
504 | } | |
505 | ||
1fdffbce | 506 | #ifdef CONFIG_PCI |
4112e16a A |
507 | |
508 | static int ata_resources_present(struct pci_dev *pdev, int port) | |
509 | { | |
510 | int i; | |
a84471fe | 511 | |
4112e16a A |
512 | /* Check the PCI resources for this channel are enabled */ |
513 | port = port * 2; | |
514 | for (i = 0; i < 2; i ++) { | |
515 | if (pci_resource_start(pdev, port + i) == 0 || | |
55a6adee TH |
516 | pci_resource_len(pdev, port + i) == 0) |
517 | return 0; | |
4112e16a A |
518 | } |
519 | return 1; | |
520 | } | |
a84471fe | 521 | |
0f834de3 TH |
522 | /** |
523 | * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host | |
524 | * @host: target ATA host | |
525 | * | |
526 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
527 | * | |
528 | * LOCKING: | |
529 | * Inherited from calling layer (may sleep). | |
530 | * | |
531 | * RETURNS: | |
532 | * 0 on success, -errno otherwise. | |
533 | */ | |
1626aeb8 | 534 | int ata_pci_init_bmdma(struct ata_host *host) |
1fdffbce | 535 | { |
0f834de3 TH |
536 | struct device *gdev = host->dev; |
537 | struct pci_dev *pdev = to_pci_dev(gdev); | |
538 | int i, rc; | |
0d5ff566 | 539 | |
6fdc99a2 AC |
540 | /* No BAR4 allocation: No DMA */ |
541 | if (pci_resource_start(pdev, 4) == 0) | |
542 | return 0; | |
543 | ||
0f834de3 TH |
544 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
545 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
546 | if (rc) | |
547 | return rc; | |
548 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
549 | if (rc) | |
550 | return rc; | |
551 | ||
552 | /* request and iomap DMA region */ | |
35a10a80 | 553 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
554 | if (rc) { |
555 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
556 | return -ENOMEM; | |
0d5ff566 | 557 | } |
0f834de3 | 558 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 559 | |
1626aeb8 | 560 | for (i = 0; i < 2; i++) { |
0f834de3 | 561 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
562 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
563 | ||
564 | if (ata_port_is_dummy(ap)) | |
565 | continue; | |
566 | ||
21b0ad4f | 567 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
568 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
569 | (ioread8(bmdma + 2) & 0x80)) | |
570 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
571 | |
572 | ata_port_desc(ap, "bmdma 0x%llx", | |
573 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
574 | } |
575 | ||
0f834de3 TH |
576 | return 0; |
577 | } | |
2ec7df04 | 578 | |
d491b27b | 579 | /** |
d583bc18 | 580 | * ata_pci_init_sff_host - acquire native PCI ATA resources and init host |
d491b27b | 581 | * @host: target ATA host |
d491b27b | 582 | * |
1626aeb8 TH |
583 | * Acquire native PCI ATA resources for @host and initialize the |
584 | * first two ports of @host accordingly. Ports marked dummy are | |
585 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 586 | * |
d583bc18 TH |
587 | * Note that native PCI resources are valid even for legacy hosts |
588 | * as we fix up pdev resources array early in boot, so this | |
589 | * function can be used for both native and legacy SFF hosts. | |
590 | * | |
d491b27b TH |
591 | * LOCKING: |
592 | * Inherited from calling layer (may sleep). | |
593 | * | |
594 | * RETURNS: | |
1626aeb8 TH |
595 | * 0 if at least one port is initialized, -ENODEV if no port is |
596 | * available. | |
d491b27b | 597 | */ |
d583bc18 | 598 | int ata_pci_init_sff_host(struct ata_host *host) |
d491b27b TH |
599 | { |
600 | struct device *gdev = host->dev; | |
601 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 602 | unsigned int mask = 0; |
d491b27b TH |
603 | int i, rc; |
604 | ||
d491b27b TH |
605 | /* request, iomap BARs and init port addresses accordingly */ |
606 | for (i = 0; i < 2; i++) { | |
607 | struct ata_port *ap = host->ports[i]; | |
608 | int base = i * 2; | |
609 | void __iomem * const *iomap; | |
610 | ||
1626aeb8 TH |
611 | if (ata_port_is_dummy(ap)) |
612 | continue; | |
613 | ||
614 | /* Discard disabled ports. Some controllers show | |
615 | * their unused channels this way. Disabled ports are | |
616 | * made dummy. | |
617 | */ | |
618 | if (!ata_resources_present(pdev, i)) { | |
619 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 620 | continue; |
1626aeb8 | 621 | } |
d491b27b | 622 | |
35a10a80 TH |
623 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
624 | dev_driver_string(gdev)); | |
d491b27b | 625 | if (rc) { |
1626aeb8 TH |
626 | dev_printk(KERN_WARNING, gdev, |
627 | "failed to request/iomap BARs for port %d " | |
628 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
629 | if (rc == -EBUSY) |
630 | pcim_pin_device(pdev); | |
1626aeb8 TH |
631 | ap->ops = &ata_dummy_port_ops; |
632 | continue; | |
d491b27b TH |
633 | } |
634 | host->iomap = iomap = pcim_iomap_table(pdev); | |
635 | ||
636 | ap->ioaddr.cmd_addr = iomap[base]; | |
637 | ap->ioaddr.altstatus_addr = | |
638 | ap->ioaddr.ctl_addr = (void __iomem *) | |
639 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
640 | ata_std_ports(&ap->ioaddr); | |
1626aeb8 | 641 | |
cbcdd875 TH |
642 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
643 | (unsigned long long)pci_resource_start(pdev, base), | |
644 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
645 | ||
1626aeb8 TH |
646 | mask |= 1 << i; |
647 | } | |
648 | ||
649 | if (!mask) { | |
650 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
651 | return -ENODEV; | |
d491b27b TH |
652 | } |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
21b0ad4f | 657 | /** |
d583bc18 | 658 | * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host |
21b0ad4f | 659 | * @pdev: target PCI device |
1626aeb8 | 660 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
661 | * @r_host: out argument for the initialized ATA host |
662 | * | |
663 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
664 | * resources and initialize it accordingly in one go. | |
665 | * | |
666 | * LOCKING: | |
667 | * Inherited from calling layer (may sleep). | |
668 | * | |
669 | * RETURNS: | |
670 | * 0 on success, -errno otherwise. | |
671 | */ | |
d583bc18 TH |
672 | int ata_pci_prepare_sff_host(struct pci_dev *pdev, |
673 | const struct ata_port_info * const * ppi, | |
674 | struct ata_host **r_host) | |
21b0ad4f TH |
675 | { |
676 | struct ata_host *host; | |
21b0ad4f TH |
677 | int rc; |
678 | ||
679 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
680 | return -ENOMEM; | |
681 | ||
682 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
683 | if (!host) { | |
684 | dev_printk(KERN_ERR, &pdev->dev, | |
685 | "failed to allocate ATA host\n"); | |
686 | rc = -ENOMEM; | |
687 | goto err_out; | |
688 | } | |
689 | ||
d583bc18 | 690 | rc = ata_pci_init_sff_host(host); |
21b0ad4f TH |
691 | if (rc) |
692 | goto err_out; | |
693 | ||
694 | /* init DMA related stuff */ | |
695 | rc = ata_pci_init_bmdma(host); | |
696 | if (rc) | |
697 | goto err_bmdma; | |
698 | ||
699 | devres_remove_group(&pdev->dev, NULL); | |
700 | *r_host = host; | |
701 | return 0; | |
702 | ||
703 | err_bmdma: | |
704 | /* This is necessary because PCI and iomap resources are | |
705 | * merged and releasing the top group won't release the | |
706 | * acquired resources if some of those have been acquired | |
707 | * before entering this function. | |
708 | */ | |
709 | pcim_iounmap_regions(pdev, 0xf); | |
710 | err_out: | |
711 | devres_release_group(&pdev->dev, NULL); | |
712 | return rc; | |
713 | } | |
714 | ||
4e6b79fa TH |
715 | /** |
716 | * ata_pci_activate_sff_host - start SFF host, request IRQ and register it | |
717 | * @host: target SFF ATA host | |
718 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
719 | * @sht: scsi_host_template to use when registering the host | |
720 | * | |
721 | * This is the counterpart of ata_host_activate() for SFF ATA | |
722 | * hosts. This separate helper is necessary because SFF hosts | |
723 | * use two separate interrupts in legacy mode. | |
724 | * | |
725 | * LOCKING: | |
726 | * Inherited from calling layer (may sleep). | |
727 | * | |
728 | * RETURNS: | |
729 | * 0 on success, -errno otherwise. | |
730 | */ | |
731 | int ata_pci_activate_sff_host(struct ata_host *host, | |
732 | irq_handler_t irq_handler, | |
733 | struct scsi_host_template *sht) | |
734 | { | |
735 | struct device *dev = host->dev; | |
736 | struct pci_dev *pdev = to_pci_dev(dev); | |
737 | const char *drv_name = dev_driver_string(host->dev); | |
738 | int legacy_mode = 0, rc; | |
739 | ||
740 | rc = ata_host_start(host); | |
741 | if (rc) | |
742 | return rc; | |
743 | ||
744 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
745 | u8 tmp8, mask; | |
746 | ||
747 | /* TODO: What if one channel is in native mode ... */ | |
748 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
749 | mask = (1 << 2) | (1 << 0); | |
750 | if ((tmp8 & mask) != mask) | |
751 | legacy_mode = 1; | |
752 | #if defined(CONFIG_NO_ATA_LEGACY) | |
753 | /* Some platforms with PCI limits cannot address compat | |
754 | port space. In that case we punt if their firmware has | |
755 | left a device in compatibility mode */ | |
756 | if (legacy_mode) { | |
757 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
758 | return -EOPNOTSUPP; | |
759 | } | |
760 | #endif | |
761 | } | |
762 | ||
763 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
764 | return -ENOMEM; | |
765 | ||
766 | if (!legacy_mode && pdev->irq) { | |
767 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
768 | IRQF_SHARED, drv_name, host); | |
769 | if (rc) | |
770 | goto out; | |
771 | ||
772 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
773 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
774 | } else if (legacy_mode) { | |
775 | if (!ata_port_is_dummy(host->ports[0])) { | |
776 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
777 | irq_handler, IRQF_SHARED, | |
778 | drv_name, host); | |
779 | if (rc) | |
780 | goto out; | |
781 | ||
782 | ata_port_desc(host->ports[0], "irq %d", | |
783 | ATA_PRIMARY_IRQ(pdev)); | |
784 | } | |
785 | ||
786 | if (!ata_port_is_dummy(host->ports[1])) { | |
787 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
788 | irq_handler, IRQF_SHARED, | |
789 | drv_name, host); | |
790 | if (rc) | |
791 | goto out; | |
792 | ||
793 | ata_port_desc(host->ports[1], "irq %d", | |
794 | ATA_SECONDARY_IRQ(pdev)); | |
795 | } | |
796 | } | |
797 | ||
798 | rc = ata_host_register(host, sht); | |
799 | out: | |
800 | if (rc == 0) | |
801 | devres_remove_group(dev, NULL); | |
802 | else | |
803 | devres_release_group(dev, NULL); | |
804 | ||
805 | return rc; | |
806 | } | |
807 | ||
1fdffbce JG |
808 | /** |
809 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
810 | * @pdev: Controller to be initialized | |
1626aeb8 | 811 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 812 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 813 | * @host_priv: host private_data |
1fdffbce JG |
814 | * |
815 | * This is a helper function which can be called from a driver's | |
816 | * xxx_init_one() probe function if the hardware uses traditional | |
817 | * IDE taskfile registers. | |
818 | * | |
819 | * This function calls pci_enable_device(), reserves its register | |
820 | * regions, sets the dma mask, enables bus master mode, and calls | |
821 | * ata_device_add() | |
822 | * | |
2ec7df04 AC |
823 | * ASSUMPTION: |
824 | * Nobody makes a single channel controller that appears solely as | |
825 | * the secondary legacy port on PCI. | |
826 | * | |
1fdffbce JG |
827 | * LOCKING: |
828 | * Inherited from PCI layer (may sleep). | |
829 | * | |
830 | * RETURNS: | |
831 | * Zero on success, negative on errno-based value on error. | |
832 | */ | |
1626aeb8 | 833 | int ata_pci_init_one(struct pci_dev *pdev, |
1bd5b715 | 834 | const struct ata_port_info * const * ppi, |
887125e3 | 835 | struct scsi_host_template *sht, void *host_priv) |
1fdffbce | 836 | { |
f0d36efd | 837 | struct device *dev = &pdev->dev; |
1626aeb8 | 838 | const struct ata_port_info *pi = NULL; |
0f834de3 | 839 | struct ata_host *host = NULL; |
1626aeb8 | 840 | int i, rc; |
1fdffbce JG |
841 | |
842 | DPRINTK("ENTER\n"); | |
843 | ||
1626aeb8 TH |
844 | /* look up the first valid port_info */ |
845 | for (i = 0; i < 2 && ppi[i]; i++) { | |
846 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
847 | pi = ppi[i]; | |
848 | break; | |
849 | } | |
850 | } | |
f0d36efd | 851 | |
1626aeb8 TH |
852 | if (!pi) { |
853 | dev_printk(KERN_ERR, &pdev->dev, | |
854 | "no valid port_info specified\n"); | |
855 | return -EINVAL; | |
856 | } | |
c791c306 | 857 | |
1626aeb8 TH |
858 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
859 | return -ENOMEM; | |
1fdffbce | 860 | |
f0d36efd | 861 | rc = pcim_enable_device(pdev); |
1fdffbce | 862 | if (rc) |
4e6b79fa | 863 | goto out; |
1fdffbce | 864 | |
4e6b79fa | 865 | /* prepare and activate SFF host */ |
d583bc18 TH |
866 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
867 | if (rc) | |
4e6b79fa | 868 | goto out; |
887125e3 | 869 | host->private_data = host_priv; |
d491b27b | 870 | |
d491b27b | 871 | pci_set_master(pdev); |
1bd5b715 | 872 | rc = ata_pci_activate_sff_host(host, ata_interrupt, sht); |
4e6b79fa TH |
873 | out: |
874 | if (rc == 0) | |
875 | devres_remove_group(&pdev->dev, NULL); | |
876 | else | |
877 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 878 | |
1fdffbce JG |
879 | return rc; |
880 | } | |
881 | ||
d33d44fa AC |
882 | /** |
883 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
884 | * @pdev: PCI device | |
885 | * | |
886 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3a4fa0a2 | 887 | * enter non simplex mode. This implements the necessary logic to |
d33d44fa AC |
888 | * perform the task on such devices. Calling it on other devices will |
889 | * have -undefined- behaviour. | |
890 | */ | |
891 | ||
892 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
893 | { | |
894 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
895 | u8 simplex; | |
896 | ||
897 | if (bmdma == 0) | |
898 | return -ENOENT; | |
899 | ||
900 | simplex = inb(bmdma + 0x02); | |
901 | outb(simplex & 0x60, bmdma + 0x02); | |
902 | simplex = inb(bmdma + 0x02); | |
903 | if (simplex & 0x80) | |
904 | return -EOPNOTSUPP; | |
905 | return 0; | |
906 | } | |
907 | ||
a76b62ca | 908 | unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask) |
d33d44fa AC |
909 | { |
910 | /* Filter out DMA modes if the device has been configured by | |
911 | the BIOS as PIO only */ | |
2e9edbf8 | 912 | |
c80544dc | 913 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) |
d33d44fa AC |
914 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); |
915 | return xfer_mask; | |
916 | } | |
917 | ||
1fdffbce JG |
918 | #endif /* CONFIG_PCI */ |
919 |