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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
272f7884 TH |
41 | /** |
42 | * ata_check_status - Read device status reg & clear interrupt | |
43 | * @ap: port where the device is | |
44 | * | |
45 | * Reads ATA taskfile status register for currently-selected device | |
46 | * and return its value. This also clears pending interrupts | |
47 | * from this device | |
48 | * | |
49 | * LOCKING: | |
50 | * Inherited from caller. | |
51 | */ | |
52 | u8 ata_check_status(struct ata_port *ap) | |
53 | { | |
54 | return ioread8(ap->ioaddr.status_addr); | |
55 | } | |
56 | ||
57 | /** | |
58 | * ata_altstatus - Read device alternate status reg | |
59 | * @ap: port where the device is | |
60 | * | |
61 | * Reads ATA taskfile alternate status register for | |
62 | * currently-selected device and return its value. | |
63 | * | |
64 | * Note: may NOT be used as the check_altstatus() entry in | |
65 | * ata_port_operations. | |
66 | * | |
67 | * LOCKING: | |
68 | * Inherited from caller. | |
69 | */ | |
70 | u8 ata_altstatus(struct ata_port *ap) | |
71 | { | |
72 | if (ap->ops->check_altstatus) | |
73 | return ap->ops->check_altstatus(ap); | |
74 | ||
75 | return ioread8(ap->ioaddr.altstatus_addr); | |
76 | } | |
77 | ||
90088bb4 TH |
78 | /** |
79 | * ata_irq_on - Enable interrupts on a port. | |
80 | * @ap: Port on which interrupts are enabled. | |
81 | * | |
82 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
83 | * wait for idle, clear any pending interrupts. | |
84 | * | |
85 | * LOCKING: | |
86 | * Inherited from caller. | |
87 | */ | |
88 | u8 ata_irq_on(struct ata_port *ap) | |
89 | { | |
90 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
91 | u8 tmp; | |
92 | ||
93 | ap->ctl &= ~ATA_NIEN; | |
94 | ap->last_ctl = ap->ctl; | |
95 | ||
f659f0e4 TH |
96 | if (ioaddr->ctl_addr) |
97 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
90088bb4 TH |
98 | tmp = ata_wait_idle(ap); |
99 | ||
100 | ap->ops->irq_clear(ap); | |
101 | ||
102 | return tmp; | |
103 | } | |
104 | ||
272f7884 TH |
105 | /** |
106 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
107 | * @ap: Port associated with this ATA transaction. | |
108 | * | |
109 | * Clear interrupt and error flags in DMA status register. | |
110 | * | |
111 | * May be used as the irq_clear() entry in ata_port_operations. | |
112 | * | |
113 | * LOCKING: | |
114 | * spin_lock_irqsave(host lock) | |
115 | */ | |
116 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
117 | { | |
118 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
119 | ||
120 | if (!mmio) | |
121 | return; | |
122 | ||
123 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
124 | } | |
125 | ||
1fdffbce | 126 | /** |
0d5ff566 | 127 | * ata_tf_load - send taskfile registers to host controller |
1fdffbce JG |
128 | * @ap: Port to which output is sent |
129 | * @tf: ATA taskfile register set | |
130 | * | |
131 | * Outputs ATA taskfile to standard ATA host controller. | |
132 | * | |
133 | * LOCKING: | |
134 | * Inherited from caller. | |
135 | */ | |
0d5ff566 | 136 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
137 | { |
138 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
139 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
140 | ||
141 | if (tf->ctl != ap->last_ctl) { | |
f659f0e4 TH |
142 | if (ioaddr->ctl_addr) |
143 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
1fdffbce JG |
144 | ap->last_ctl = tf->ctl; |
145 | ata_wait_idle(ap); | |
146 | } | |
147 | ||
148 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
f659f0e4 | 149 | WARN_ON(!ioaddr->ctl_addr); |
0d5ff566 TH |
150 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
151 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
152 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
153 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
154 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
155 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
156 | tf->hob_feature, | |
157 | tf->hob_nsect, | |
158 | tf->hob_lbal, | |
159 | tf->hob_lbam, | |
160 | tf->hob_lbah); | |
161 | } | |
162 | ||
163 | if (is_addr) { | |
0d5ff566 TH |
164 | iowrite8(tf->feature, ioaddr->feature_addr); |
165 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
166 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
167 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
168 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
169 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
170 | tf->feature, | |
171 | tf->nsect, | |
172 | tf->lbal, | |
173 | tf->lbam, | |
174 | tf->lbah); | |
175 | } | |
176 | ||
177 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
0d5ff566 | 178 | iowrite8(tf->device, ioaddr->device_addr); |
1fdffbce JG |
179 | VPRINTK("device 0x%X\n", tf->device); |
180 | } | |
181 | ||
182 | ata_wait_idle(ap); | |
183 | } | |
184 | ||
1fdffbce | 185 | /** |
0d5ff566 | 186 | * ata_tf_read - input device's ATA taskfile shadow registers |
1fdffbce JG |
187 | * @ap: Port from which input is read |
188 | * @tf: ATA taskfile register set for storing input | |
189 | * | |
190 | * Reads ATA taskfile registers for currently-selected device | |
76548eda AC |
191 | * into @tf. Assumes the device has a fully SFF compliant task file |
192 | * layout and behaviour. If you device does not (eg has a different | |
193 | * status method) then you will need to provide a replacement tf_read | |
1fdffbce JG |
194 | * |
195 | * LOCKING: | |
196 | * Inherited from caller. | |
197 | */ | |
0d5ff566 | 198 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1fdffbce JG |
199 | { |
200 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
201 | ||
76548eda | 202 | tf->command = ata_check_status(ap); |
0d5ff566 TH |
203 | tf->feature = ioread8(ioaddr->error_addr); |
204 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
205 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
206 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
207 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
208 | tf->device = ioread8(ioaddr->device_addr); | |
1fdffbce JG |
209 | |
210 | if (tf->flags & ATA_TFLAG_LBA48) { | |
f659f0e4 TH |
211 | if (likely(ioaddr->ctl_addr)) { |
212 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
213 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
214 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
215 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
216 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
217 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
218 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
219 | ap->last_ctl = tf->ctl; | |
220 | } else | |
221 | WARN_ON(1); | |
1fdffbce JG |
222 | } |
223 | } | |
224 | ||
1fdffbce | 225 | /** |
272f7884 TH |
226 | * ata_exec_command - issue ATA command to host controller |
227 | * @ap: port to which command is being issued | |
228 | * @tf: ATA taskfile register set | |
2cc432ee | 229 | * |
272f7884 TH |
230 | * Issues ATA command, with proper synchronization with interrupt |
231 | * handler / other threads. | |
2cc432ee JG |
232 | * |
233 | * LOCKING: | |
cca3974e | 234 | * spin_lock_irqsave(host lock) |
2cc432ee | 235 | */ |
272f7884 | 236 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
2cc432ee | 237 | { |
272f7884 | 238 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
2cc432ee | 239 | |
272f7884 TH |
240 | iowrite8(tf->command, ap->ioaddr.command_addr); |
241 | ata_pause(ap); | |
2cc432ee JG |
242 | } |
243 | ||
6d97dbd7 TH |
244 | /** |
245 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
246 | * @ap: port to freeze | |
247 | * | |
248 | * Freeze BMDMA controller port. | |
249 | * | |
250 | * LOCKING: | |
251 | * Inherited from caller. | |
252 | */ | |
253 | void ata_bmdma_freeze(struct ata_port *ap) | |
254 | { | |
255 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
256 | ||
257 | ap->ctl |= ATA_NIEN; | |
258 | ap->last_ctl = ap->ctl; | |
259 | ||
f659f0e4 TH |
260 | if (ioaddr->ctl_addr) |
261 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
0f0a3ad3 TH |
262 | |
263 | /* Under certain circumstances, some controllers raise IRQ on | |
264 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
265 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
266 | */ | |
267 | ata_chk_status(ap); | |
268 | ||
269 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
270 | } |
271 | ||
272 | /** | |
273 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
274 | * @ap: port to thaw | |
275 | * | |
276 | * Thaw BMDMA controller port. | |
277 | * | |
278 | * LOCKING: | |
279 | * Inherited from caller. | |
280 | */ | |
281 | void ata_bmdma_thaw(struct ata_port *ap) | |
282 | { | |
283 | /* clear & re-enable interrupts */ | |
284 | ata_chk_status(ap); | |
285 | ap->ops->irq_clear(ap); | |
83625006 | 286 | ap->ops->irq_on(ap); |
6d97dbd7 TH |
287 | } |
288 | ||
289 | /** | |
a1efdaba | 290 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 291 | * @ap: port to handle error for |
6d97dbd7 | 292 | * |
a1efdaba | 293 | * Stock error handler for BMDMA controller. It can handle both |
6d97dbd7 TH |
294 | * PATA and SATA controllers. Many controllers should be able to |
295 | * use this EH as-is or with some added handling before and | |
296 | * after. | |
297 | * | |
6d97dbd7 TH |
298 | * LOCKING: |
299 | * Kernel thread context (may sleep) | |
300 | */ | |
a1efdaba | 301 | void ata_bmdma_error_handler(struct ata_port *ap) |
6d97dbd7 | 302 | { |
a1efdaba TH |
303 | ata_reset_fn_t softreset = ap->ops->softreset; |
304 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
305 | struct ata_queued_cmd *qc; |
306 | unsigned long flags; | |
307 | int thaw = 0; | |
308 | ||
9af5c9c9 | 309 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
310 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
311 | qc = NULL; | |
312 | ||
313 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 314 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 315 | |
6d97dbd7 TH |
316 | ap->hsm_task_state = HSM_ST_IDLE; |
317 | ||
318 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 319 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
320 | u8 host_stat; |
321 | ||
fbbb262d | 322 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 323 | |
6d97dbd7 TH |
324 | /* BMDMA controllers indicate host bus error by |
325 | * setting DMA_ERR bit and timing out. As it wasn't | |
326 | * really a timeout event, adjust error mask and | |
327 | * cancel frozen state. | |
328 | */ | |
18d90deb | 329 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
330 | qc->err_mask = AC_ERR_HOST_BUS; |
331 | thaw = 1; | |
332 | } | |
333 | ||
334 | ap->ops->bmdma_stop(qc); | |
335 | } | |
336 | ||
337 | ata_altstatus(ap); | |
338 | ata_chk_status(ap); | |
339 | ap->ops->irq_clear(ap); | |
340 | ||
ba6a1308 | 341 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
342 | |
343 | if (thaw) | |
344 | ata_eh_thaw_port(ap); | |
345 | ||
346 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 347 | |
a1efdaba TH |
348 | /* ata_std_softreset and sata_std_hardreset are inherited to |
349 | * all SFF drivers from ata_sff_port_ops. Ignore softreset if | |
350 | * ctl isn't accessible. Ignore hardreset if SCR access isn't | |
351 | * available. | |
352 | */ | |
353 | if (softreset == ata_std_softreset && !ap->ioaddr.ctl_addr) | |
354 | softreset = NULL; | |
355 | if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link)) | |
356 | hardreset = NULL; | |
6d97dbd7 | 357 | |
a1efdaba TH |
358 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
359 | ap->ops->postreset); | |
6d97dbd7 TH |
360 | } |
361 | ||
362 | /** | |
363 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
364 | * BMDMA controller | |
365 | * @qc: internal command to clean up | |
366 | * | |
367 | * LOCKING: | |
368 | * Kernel thread context (may sleep) | |
369 | */ | |
370 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
371 | { | |
61dd08c6 A |
372 | if (qc->ap->ioaddr.bmdma_addr) |
373 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
374 | } |
375 | ||
d92e74d3 AC |
376 | /** |
377 | * ata_sff_port_start - Set port up for dma. | |
378 | * @ap: Port to initialize | |
379 | * | |
380 | * Called just after data structures for each port are | |
381 | * initialized. Allocates space for PRD table if the device | |
382 | * is DMA capable SFF. | |
383 | * | |
384 | * May be used as the port_start() entry in ata_port_operations. | |
385 | * | |
386 | * LOCKING: | |
387 | * Inherited from caller. | |
388 | */ | |
d92e74d3 AC |
389 | int ata_sff_port_start(struct ata_port *ap) |
390 | { | |
391 | if (ap->ioaddr.bmdma_addr) | |
392 | return ata_port_start(ap); | |
393 | return 0; | |
394 | } | |
395 | ||
272f7884 TH |
396 | /** |
397 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
398 | * @qc: Info associated with this ATA transaction. | |
399 | * | |
400 | * LOCKING: | |
401 | * spin_lock_irqsave(host lock) | |
402 | */ | |
403 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
404 | { | |
405 | struct ata_port *ap = qc->ap; | |
406 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
407 | u8 dmactl; | |
408 | ||
409 | /* load PRD table addr. */ | |
410 | mb(); /* make sure PRD table writes are visible to controller */ | |
411 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
412 | ||
413 | /* specify data direction, triple-check start bit is clear */ | |
414 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
415 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
416 | if (!rw) | |
417 | dmactl |= ATA_DMA_WR; | |
418 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
419 | ||
420 | /* issue r/w command */ | |
421 | ap->ops->exec_command(ap, &qc->tf); | |
422 | } | |
423 | ||
424 | /** | |
425 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
426 | * @qc: Info associated with this ATA transaction. | |
427 | * | |
428 | * LOCKING: | |
429 | * spin_lock_irqsave(host lock) | |
430 | */ | |
431 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
432 | { | |
433 | struct ata_port *ap = qc->ap; | |
434 | u8 dmactl; | |
435 | ||
436 | /* start host DMA transaction */ | |
437 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
438 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
439 | ||
440 | /* Strictly, one may wish to issue an ioread8() here, to | |
441 | * flush the mmio write. However, control also passes | |
442 | * to the hardware at this point, and it will interrupt | |
443 | * us when we are to resume control. So, in effect, | |
444 | * we don't care when the mmio write flushes. | |
445 | * Further, a read of the DMA status register _immediately_ | |
446 | * following the write may not be what certain flaky hardware | |
447 | * is expected, so I think it is best to not add a readb() | |
448 | * without first all the MMIO ATA cards/mobos. | |
449 | * Or maybe I'm just being paranoid. | |
450 | * | |
451 | * FIXME: The posting of this write means I/O starts are | |
452 | * unneccessarily delayed for MMIO | |
453 | */ | |
454 | } | |
455 | ||
456 | /** | |
457 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
458 | * @qc: Command we are ending DMA for | |
459 | * | |
460 | * Clears the ATA_DMA_START flag in the dma control register | |
461 | * | |
462 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
463 | * | |
464 | * LOCKING: | |
465 | * spin_lock_irqsave(host lock) | |
466 | */ | |
467 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
468 | { | |
469 | struct ata_port *ap = qc->ap; | |
470 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
471 | ||
472 | /* clear start/stop bit */ | |
473 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
474 | mmio + ATA_DMA_CMD); | |
475 | ||
476 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
477 | ata_altstatus(ap); /* dummy read */ | |
478 | } | |
479 | ||
480 | /** | |
481 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
482 | * @ap: Port associated with this ATA transaction. | |
483 | * | |
484 | * Read and return BMDMA status register. | |
485 | * | |
486 | * May be used as the bmdma_status() entry in ata_port_operations. | |
487 | * | |
488 | * LOCKING: | |
489 | * spin_lock_irqsave(host lock) | |
490 | */ | |
491 | u8 ata_bmdma_status(struct ata_port *ap) | |
492 | { | |
493 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
494 | } | |
495 | ||
496 | /** | |
497 | * ata_noop_irq_clear - Noop placeholder for irq_clear | |
498 | * @ap: Port associated with this ATA transaction. | |
499 | */ | |
500 | void ata_noop_irq_clear(struct ata_port *ap) | |
501 | { | |
502 | } | |
503 | ||
1fdffbce | 504 | #ifdef CONFIG_PCI |
4112e16a | 505 | |
272f7884 TH |
506 | /** |
507 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
508 | * @pdev: PCI device | |
509 | * | |
510 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
511 | * enter non simplex mode. This implements the necessary logic to | |
512 | * perform the task on such devices. Calling it on other devices will | |
513 | * have -undefined- behaviour. | |
514 | */ | |
515 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
4112e16a | 516 | { |
272f7884 TH |
517 | unsigned long bmdma = pci_resource_start(pdev, 4); |
518 | u8 simplex; | |
a84471fe | 519 | |
272f7884 TH |
520 | if (bmdma == 0) |
521 | return -ENOENT; | |
522 | ||
523 | simplex = inb(bmdma + 0x02); | |
524 | outb(simplex & 0x60, bmdma + 0x02); | |
525 | simplex = inb(bmdma + 0x02); | |
526 | if (simplex & 0x80) | |
527 | return -EOPNOTSUPP; | |
528 | return 0; | |
529 | } | |
530 | ||
531 | unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask) | |
532 | { | |
533 | /* Filter out DMA modes if the device has been configured by | |
534 | the BIOS as PIO only */ | |
535 | ||
536 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
537 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
538 | return xfer_mask; | |
4112e16a | 539 | } |
a84471fe | 540 | |
0f834de3 TH |
541 | /** |
542 | * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host | |
543 | * @host: target ATA host | |
544 | * | |
545 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
546 | * | |
547 | * LOCKING: | |
548 | * Inherited from calling layer (may sleep). | |
549 | * | |
550 | * RETURNS: | |
551 | * 0 on success, -errno otherwise. | |
552 | */ | |
1626aeb8 | 553 | int ata_pci_init_bmdma(struct ata_host *host) |
1fdffbce | 554 | { |
0f834de3 TH |
555 | struct device *gdev = host->dev; |
556 | struct pci_dev *pdev = to_pci_dev(gdev); | |
557 | int i, rc; | |
0d5ff566 | 558 | |
6fdc99a2 AC |
559 | /* No BAR4 allocation: No DMA */ |
560 | if (pci_resource_start(pdev, 4) == 0) | |
561 | return 0; | |
562 | ||
0f834de3 TH |
563 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
564 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
565 | if (rc) | |
566 | return rc; | |
567 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
568 | if (rc) | |
569 | return rc; | |
570 | ||
571 | /* request and iomap DMA region */ | |
35a10a80 | 572 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
573 | if (rc) { |
574 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
575 | return -ENOMEM; | |
0d5ff566 | 576 | } |
0f834de3 | 577 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 578 | |
1626aeb8 | 579 | for (i = 0; i < 2; i++) { |
0f834de3 | 580 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
581 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
582 | ||
583 | if (ata_port_is_dummy(ap)) | |
584 | continue; | |
585 | ||
21b0ad4f | 586 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
587 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
588 | (ioread8(bmdma + 2) & 0x80)) | |
589 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
590 | |
591 | ata_port_desc(ap, "bmdma 0x%llx", | |
592 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
593 | } |
594 | ||
0f834de3 TH |
595 | return 0; |
596 | } | |
2ec7df04 | 597 | |
272f7884 TH |
598 | static int ata_resources_present(struct pci_dev *pdev, int port) |
599 | { | |
600 | int i; | |
601 | ||
602 | /* Check the PCI resources for this channel are enabled */ | |
603 | port = port * 2; | |
604 | for (i = 0; i < 2; i ++) { | |
605 | if (pci_resource_start(pdev, port + i) == 0 || | |
606 | pci_resource_len(pdev, port + i) == 0) | |
607 | return 0; | |
608 | } | |
609 | return 1; | |
610 | } | |
611 | ||
d491b27b | 612 | /** |
d583bc18 | 613 | * ata_pci_init_sff_host - acquire native PCI ATA resources and init host |
d491b27b | 614 | * @host: target ATA host |
d491b27b | 615 | * |
1626aeb8 TH |
616 | * Acquire native PCI ATA resources for @host and initialize the |
617 | * first two ports of @host accordingly. Ports marked dummy are | |
618 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 619 | * |
d583bc18 TH |
620 | * Note that native PCI resources are valid even for legacy hosts |
621 | * as we fix up pdev resources array early in boot, so this | |
622 | * function can be used for both native and legacy SFF hosts. | |
623 | * | |
d491b27b TH |
624 | * LOCKING: |
625 | * Inherited from calling layer (may sleep). | |
626 | * | |
627 | * RETURNS: | |
1626aeb8 TH |
628 | * 0 if at least one port is initialized, -ENODEV if no port is |
629 | * available. | |
d491b27b | 630 | */ |
d583bc18 | 631 | int ata_pci_init_sff_host(struct ata_host *host) |
d491b27b TH |
632 | { |
633 | struct device *gdev = host->dev; | |
634 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 635 | unsigned int mask = 0; |
d491b27b TH |
636 | int i, rc; |
637 | ||
d491b27b TH |
638 | /* request, iomap BARs and init port addresses accordingly */ |
639 | for (i = 0; i < 2; i++) { | |
640 | struct ata_port *ap = host->ports[i]; | |
641 | int base = i * 2; | |
642 | void __iomem * const *iomap; | |
643 | ||
1626aeb8 TH |
644 | if (ata_port_is_dummy(ap)) |
645 | continue; | |
646 | ||
647 | /* Discard disabled ports. Some controllers show | |
648 | * their unused channels this way. Disabled ports are | |
649 | * made dummy. | |
650 | */ | |
651 | if (!ata_resources_present(pdev, i)) { | |
652 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 653 | continue; |
1626aeb8 | 654 | } |
d491b27b | 655 | |
35a10a80 TH |
656 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
657 | dev_driver_string(gdev)); | |
d491b27b | 658 | if (rc) { |
1626aeb8 TH |
659 | dev_printk(KERN_WARNING, gdev, |
660 | "failed to request/iomap BARs for port %d " | |
661 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
662 | if (rc == -EBUSY) |
663 | pcim_pin_device(pdev); | |
1626aeb8 TH |
664 | ap->ops = &ata_dummy_port_ops; |
665 | continue; | |
d491b27b TH |
666 | } |
667 | host->iomap = iomap = pcim_iomap_table(pdev); | |
668 | ||
669 | ap->ioaddr.cmd_addr = iomap[base]; | |
670 | ap->ioaddr.altstatus_addr = | |
671 | ap->ioaddr.ctl_addr = (void __iomem *) | |
672 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
673 | ata_std_ports(&ap->ioaddr); | |
1626aeb8 | 674 | |
cbcdd875 TH |
675 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
676 | (unsigned long long)pci_resource_start(pdev, base), | |
677 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
678 | ||
1626aeb8 TH |
679 | mask |= 1 << i; |
680 | } | |
681 | ||
682 | if (!mask) { | |
683 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
684 | return -ENODEV; | |
d491b27b TH |
685 | } |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
21b0ad4f | 690 | /** |
d583bc18 | 691 | * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host |
21b0ad4f | 692 | * @pdev: target PCI device |
1626aeb8 | 693 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
694 | * @r_host: out argument for the initialized ATA host |
695 | * | |
696 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
697 | * resources and initialize it accordingly in one go. | |
698 | * | |
699 | * LOCKING: | |
700 | * Inherited from calling layer (may sleep). | |
701 | * | |
702 | * RETURNS: | |
703 | * 0 on success, -errno otherwise. | |
704 | */ | |
d583bc18 TH |
705 | int ata_pci_prepare_sff_host(struct pci_dev *pdev, |
706 | const struct ata_port_info * const * ppi, | |
707 | struct ata_host **r_host) | |
21b0ad4f TH |
708 | { |
709 | struct ata_host *host; | |
21b0ad4f TH |
710 | int rc; |
711 | ||
712 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
713 | return -ENOMEM; | |
714 | ||
715 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
716 | if (!host) { | |
717 | dev_printk(KERN_ERR, &pdev->dev, | |
718 | "failed to allocate ATA host\n"); | |
719 | rc = -ENOMEM; | |
720 | goto err_out; | |
721 | } | |
722 | ||
d583bc18 | 723 | rc = ata_pci_init_sff_host(host); |
21b0ad4f TH |
724 | if (rc) |
725 | goto err_out; | |
726 | ||
727 | /* init DMA related stuff */ | |
728 | rc = ata_pci_init_bmdma(host); | |
729 | if (rc) | |
730 | goto err_bmdma; | |
731 | ||
732 | devres_remove_group(&pdev->dev, NULL); | |
733 | *r_host = host; | |
734 | return 0; | |
735 | ||
736 | err_bmdma: | |
737 | /* This is necessary because PCI and iomap resources are | |
738 | * merged and releasing the top group won't release the | |
739 | * acquired resources if some of those have been acquired | |
740 | * before entering this function. | |
741 | */ | |
742 | pcim_iounmap_regions(pdev, 0xf); | |
743 | err_out: | |
744 | devres_release_group(&pdev->dev, NULL); | |
745 | return rc; | |
746 | } | |
747 | ||
4e6b79fa TH |
748 | /** |
749 | * ata_pci_activate_sff_host - start SFF host, request IRQ and register it | |
750 | * @host: target SFF ATA host | |
751 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
752 | * @sht: scsi_host_template to use when registering the host | |
753 | * | |
754 | * This is the counterpart of ata_host_activate() for SFF ATA | |
755 | * hosts. This separate helper is necessary because SFF hosts | |
756 | * use two separate interrupts in legacy mode. | |
757 | * | |
758 | * LOCKING: | |
759 | * Inherited from calling layer (may sleep). | |
760 | * | |
761 | * RETURNS: | |
762 | * 0 on success, -errno otherwise. | |
763 | */ | |
764 | int ata_pci_activate_sff_host(struct ata_host *host, | |
765 | irq_handler_t irq_handler, | |
766 | struct scsi_host_template *sht) | |
767 | { | |
768 | struct device *dev = host->dev; | |
769 | struct pci_dev *pdev = to_pci_dev(dev); | |
770 | const char *drv_name = dev_driver_string(host->dev); | |
771 | int legacy_mode = 0, rc; | |
772 | ||
773 | rc = ata_host_start(host); | |
774 | if (rc) | |
775 | return rc; | |
776 | ||
777 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
778 | u8 tmp8, mask; | |
779 | ||
780 | /* TODO: What if one channel is in native mode ... */ | |
781 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
782 | mask = (1 << 2) | (1 << 0); | |
783 | if ((tmp8 & mask) != mask) | |
784 | legacy_mode = 1; | |
785 | #if defined(CONFIG_NO_ATA_LEGACY) | |
786 | /* Some platforms with PCI limits cannot address compat | |
787 | port space. In that case we punt if their firmware has | |
788 | left a device in compatibility mode */ | |
789 | if (legacy_mode) { | |
790 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
791 | return -EOPNOTSUPP; | |
792 | } | |
793 | #endif | |
794 | } | |
795 | ||
796 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
797 | return -ENOMEM; | |
798 | ||
799 | if (!legacy_mode && pdev->irq) { | |
800 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
801 | IRQF_SHARED, drv_name, host); | |
802 | if (rc) | |
803 | goto out; | |
804 | ||
805 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
806 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
807 | } else if (legacy_mode) { | |
808 | if (!ata_port_is_dummy(host->ports[0])) { | |
809 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
810 | irq_handler, IRQF_SHARED, | |
811 | drv_name, host); | |
812 | if (rc) | |
813 | goto out; | |
814 | ||
815 | ata_port_desc(host->ports[0], "irq %d", | |
816 | ATA_PRIMARY_IRQ(pdev)); | |
817 | } | |
818 | ||
819 | if (!ata_port_is_dummy(host->ports[1])) { | |
820 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
821 | irq_handler, IRQF_SHARED, | |
822 | drv_name, host); | |
823 | if (rc) | |
824 | goto out; | |
825 | ||
826 | ata_port_desc(host->ports[1], "irq %d", | |
827 | ATA_SECONDARY_IRQ(pdev)); | |
828 | } | |
829 | } | |
830 | ||
831 | rc = ata_host_register(host, sht); | |
832 | out: | |
833 | if (rc == 0) | |
834 | devres_remove_group(dev, NULL); | |
835 | else | |
836 | devres_release_group(dev, NULL); | |
837 | ||
838 | return rc; | |
839 | } | |
840 | ||
1fdffbce JG |
841 | /** |
842 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
843 | * @pdev: Controller to be initialized | |
1626aeb8 | 844 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 845 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 846 | * @host_priv: host private_data |
1fdffbce JG |
847 | * |
848 | * This is a helper function which can be called from a driver's | |
849 | * xxx_init_one() probe function if the hardware uses traditional | |
850 | * IDE taskfile registers. | |
851 | * | |
852 | * This function calls pci_enable_device(), reserves its register | |
853 | * regions, sets the dma mask, enables bus master mode, and calls | |
854 | * ata_device_add() | |
855 | * | |
2ec7df04 AC |
856 | * ASSUMPTION: |
857 | * Nobody makes a single channel controller that appears solely as | |
858 | * the secondary legacy port on PCI. | |
859 | * | |
1fdffbce JG |
860 | * LOCKING: |
861 | * Inherited from PCI layer (may sleep). | |
862 | * | |
863 | * RETURNS: | |
864 | * Zero on success, negative on errno-based value on error. | |
865 | */ | |
1626aeb8 | 866 | int ata_pci_init_one(struct pci_dev *pdev, |
1bd5b715 | 867 | const struct ata_port_info * const * ppi, |
887125e3 | 868 | struct scsi_host_template *sht, void *host_priv) |
1fdffbce | 869 | { |
f0d36efd | 870 | struct device *dev = &pdev->dev; |
1626aeb8 | 871 | const struct ata_port_info *pi = NULL; |
0f834de3 | 872 | struct ata_host *host = NULL; |
1626aeb8 | 873 | int i, rc; |
1fdffbce JG |
874 | |
875 | DPRINTK("ENTER\n"); | |
876 | ||
1626aeb8 TH |
877 | /* look up the first valid port_info */ |
878 | for (i = 0; i < 2 && ppi[i]; i++) { | |
879 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
880 | pi = ppi[i]; | |
881 | break; | |
882 | } | |
883 | } | |
f0d36efd | 884 | |
1626aeb8 TH |
885 | if (!pi) { |
886 | dev_printk(KERN_ERR, &pdev->dev, | |
887 | "no valid port_info specified\n"); | |
888 | return -EINVAL; | |
889 | } | |
c791c306 | 890 | |
1626aeb8 TH |
891 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
892 | return -ENOMEM; | |
1fdffbce | 893 | |
f0d36efd | 894 | rc = pcim_enable_device(pdev); |
1fdffbce | 895 | if (rc) |
4e6b79fa | 896 | goto out; |
1fdffbce | 897 | |
4e6b79fa | 898 | /* prepare and activate SFF host */ |
d583bc18 TH |
899 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
900 | if (rc) | |
4e6b79fa | 901 | goto out; |
887125e3 | 902 | host->private_data = host_priv; |
d491b27b | 903 | |
d491b27b | 904 | pci_set_master(pdev); |
1bd5b715 | 905 | rc = ata_pci_activate_sff_host(host, ata_interrupt, sht); |
4e6b79fa TH |
906 | out: |
907 | if (rc == 0) | |
908 | devres_remove_group(&pdev->dev, NULL); | |
909 | else | |
910 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 911 | |
1fdffbce JG |
912 | return rc; |
913 | } | |
914 | ||
915 | #endif /* CONFIG_PCI */ | |
916 |