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1fdffbce JG |
1 | /* |
2 | * libata-bmdma.c - helper library for PCI IDE BMDMA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
90088bb4 TH |
41 | /** |
42 | * ata_irq_on - Enable interrupts on a port. | |
43 | * @ap: Port on which interrupts are enabled. | |
44 | * | |
45 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
46 | * wait for idle, clear any pending interrupts. | |
47 | * | |
48 | * LOCKING: | |
49 | * Inherited from caller. | |
50 | */ | |
51 | u8 ata_irq_on(struct ata_port *ap) | |
52 | { | |
53 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
54 | u8 tmp; | |
55 | ||
56 | ap->ctl &= ~ATA_NIEN; | |
57 | ap->last_ctl = ap->ctl; | |
58 | ||
0d5ff566 | 59 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
90088bb4 TH |
60 | tmp = ata_wait_idle(ap); |
61 | ||
62 | ap->ops->irq_clear(ap); | |
63 | ||
64 | return tmp; | |
65 | } | |
66 | ||
1fdffbce | 67 | /** |
0d5ff566 | 68 | * ata_tf_load - send taskfile registers to host controller |
1fdffbce JG |
69 | * @ap: Port to which output is sent |
70 | * @tf: ATA taskfile register set | |
71 | * | |
72 | * Outputs ATA taskfile to standard ATA host controller. | |
73 | * | |
74 | * LOCKING: | |
75 | * Inherited from caller. | |
76 | */ | |
77 | ||
0d5ff566 | 78 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
79 | { |
80 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
81 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
82 | ||
83 | if (tf->ctl != ap->last_ctl) { | |
0d5ff566 | 84 | iowrite8(tf->ctl, ioaddr->ctl_addr); |
1fdffbce JG |
85 | ap->last_ctl = tf->ctl; |
86 | ata_wait_idle(ap); | |
87 | } | |
88 | ||
89 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
0d5ff566 TH |
90 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
91 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
92 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
93 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
94 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
95 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
96 | tf->hob_feature, | |
97 | tf->hob_nsect, | |
98 | tf->hob_lbal, | |
99 | tf->hob_lbam, | |
100 | tf->hob_lbah); | |
101 | } | |
102 | ||
103 | if (is_addr) { | |
0d5ff566 TH |
104 | iowrite8(tf->feature, ioaddr->feature_addr); |
105 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
106 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
107 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
108 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
109 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
110 | tf->feature, | |
111 | tf->nsect, | |
112 | tf->lbal, | |
113 | tf->lbam, | |
114 | tf->lbah); | |
115 | } | |
116 | ||
117 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
0d5ff566 | 118 | iowrite8(tf->device, ioaddr->device_addr); |
1fdffbce JG |
119 | VPRINTK("device 0x%X\n", tf->device); |
120 | } | |
121 | ||
122 | ata_wait_idle(ap); | |
123 | } | |
124 | ||
1fdffbce | 125 | /** |
0d5ff566 | 126 | * ata_exec_command - issue ATA command to host controller |
1fdffbce JG |
127 | * @ap: port to which command is being issued |
128 | * @tf: ATA taskfile register set | |
129 | * | |
0d5ff566 TH |
130 | * Issues ATA command, with proper synchronization with interrupt |
131 | * handler / other threads. | |
7c74ffd0 | 132 | * |
1fdffbce | 133 | * LOCKING: |
cca3974e | 134 | * spin_lock_irqsave(host lock) |
1fdffbce | 135 | */ |
0d5ff566 | 136 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
137 | { |
138 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | |
139 | ||
0d5ff566 | 140 | iowrite8(tf->command, ap->ioaddr.command_addr); |
1fdffbce JG |
141 | ata_pause(ap); |
142 | } | |
143 | ||
1fdffbce | 144 | /** |
0d5ff566 | 145 | * ata_tf_read - input device's ATA taskfile shadow registers |
1fdffbce JG |
146 | * @ap: Port from which input is read |
147 | * @tf: ATA taskfile register set for storing input | |
148 | * | |
149 | * Reads ATA taskfile registers for currently-selected device | |
150 | * into @tf. | |
151 | * | |
152 | * LOCKING: | |
153 | * Inherited from caller. | |
154 | */ | |
0d5ff566 | 155 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1fdffbce JG |
156 | { |
157 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
158 | ||
159 | tf->command = ata_check_status(ap); | |
0d5ff566 TH |
160 | tf->feature = ioread8(ioaddr->error_addr); |
161 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
162 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
163 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
164 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
165 | tf->device = ioread8(ioaddr->device_addr); | |
1fdffbce JG |
166 | |
167 | if (tf->flags & ATA_TFLAG_LBA48) { | |
0d5ff566 TH |
168 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
169 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
170 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
171 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
172 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
173 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
1fdffbce JG |
174 | } |
175 | } | |
176 | ||
1fdffbce JG |
177 | /** |
178 | * ata_check_status - Read device status reg & clear interrupt | |
179 | * @ap: port where the device is | |
180 | * | |
181 | * Reads ATA taskfile status register for currently-selected device | |
182 | * and return its value. This also clears pending interrupts | |
183 | * from this device | |
184 | * | |
1fdffbce JG |
185 | * LOCKING: |
186 | * Inherited from caller. | |
187 | */ | |
188 | u8 ata_check_status(struct ata_port *ap) | |
189 | { | |
0d5ff566 | 190 | return ioread8(ap->ioaddr.status_addr); |
1fdffbce JG |
191 | } |
192 | ||
1fdffbce JG |
193 | /** |
194 | * ata_altstatus - Read device alternate status reg | |
195 | * @ap: port where the device is | |
196 | * | |
197 | * Reads ATA taskfile alternate status register for | |
198 | * currently-selected device and return its value. | |
199 | * | |
200 | * Note: may NOT be used as the check_altstatus() entry in | |
201 | * ata_port_operations. | |
202 | * | |
203 | * LOCKING: | |
204 | * Inherited from caller. | |
205 | */ | |
206 | u8 ata_altstatus(struct ata_port *ap) | |
207 | { | |
208 | if (ap->ops->check_altstatus) | |
209 | return ap->ops->check_altstatus(ap); | |
210 | ||
0d5ff566 | 211 | return ioread8(ap->ioaddr.altstatus_addr); |
1fdffbce JG |
212 | } |
213 | ||
2cc432ee | 214 | /** |
0d5ff566 | 215 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
2cc432ee JG |
216 | * @qc: Info associated with this ATA transaction. |
217 | * | |
218 | * LOCKING: | |
cca3974e | 219 | * spin_lock_irqsave(host lock) |
2cc432ee | 220 | */ |
0d5ff566 | 221 | void ata_bmdma_setup(struct ata_queued_cmd *qc) |
2cc432ee JG |
222 | { |
223 | struct ata_port *ap = qc->ap; | |
224 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
225 | u8 dmactl; | |
2cc432ee JG |
226 | |
227 | /* load PRD table addr. */ | |
228 | mb(); /* make sure PRD table writes are visible to controller */ | |
0d5ff566 | 229 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
2cc432ee JG |
230 | |
231 | /* specify data direction, triple-check start bit is clear */ | |
0d5ff566 | 232 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
233 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
234 | if (!rw) | |
235 | dmactl |= ATA_DMA_WR; | |
0d5ff566 | 236 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
237 | |
238 | /* issue r/w command */ | |
239 | ap->ops->exec_command(ap, &qc->tf); | |
240 | } | |
241 | ||
242 | /** | |
0d5ff566 | 243 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
2cc432ee JG |
244 | * @qc: Info associated with this ATA transaction. |
245 | * | |
246 | * LOCKING: | |
cca3974e | 247 | * spin_lock_irqsave(host lock) |
2cc432ee | 248 | */ |
0d5ff566 | 249 | void ata_bmdma_start (struct ata_queued_cmd *qc) |
2cc432ee JG |
250 | { |
251 | struct ata_port *ap = qc->ap; | |
2cc432ee JG |
252 | u8 dmactl; |
253 | ||
254 | /* start host DMA transaction */ | |
0d5ff566 TH |
255 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
256 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2cc432ee JG |
257 | |
258 | /* Strictly, one may wish to issue a readb() here, to | |
259 | * flush the mmio write. However, control also passes | |
260 | * to the hardware at this point, and it will interrupt | |
261 | * us when we are to resume control. So, in effect, | |
262 | * we don't care when the mmio write flushes. | |
263 | * Further, a read of the DMA status register _immediately_ | |
264 | * following the write may not be what certain flaky hardware | |
265 | * is expected, so I think it is best to not add a readb() | |
266 | * without first all the MMIO ATA cards/mobos. | |
267 | * Or maybe I'm just being paranoid. | |
268 | */ | |
269 | } | |
270 | ||
2cc432ee JG |
271 | /** |
272 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
273 | * @ap: Port associated with this ATA transaction. | |
274 | * | |
275 | * Clear interrupt and error flags in DMA status register. | |
276 | * | |
277 | * May be used as the irq_clear() entry in ata_port_operations. | |
278 | * | |
279 | * LOCKING: | |
cca3974e | 280 | * spin_lock_irqsave(host lock) |
2cc432ee | 281 | */ |
2cc432ee JG |
282 | void ata_bmdma_irq_clear(struct ata_port *ap) |
283 | { | |
0d5ff566 TH |
284 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
285 | ||
286 | if (!mmio) | |
2cc432ee JG |
287 | return; |
288 | ||
0d5ff566 | 289 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
2cc432ee JG |
290 | } |
291 | ||
2cc432ee JG |
292 | /** |
293 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
294 | * @ap: Port associated with this ATA transaction. | |
295 | * | |
296 | * Read and return BMDMA status register. | |
297 | * | |
298 | * May be used as the bmdma_status() entry in ata_port_operations. | |
299 | * | |
300 | * LOCKING: | |
cca3974e | 301 | * spin_lock_irqsave(host lock) |
2cc432ee | 302 | */ |
2cc432ee JG |
303 | u8 ata_bmdma_status(struct ata_port *ap) |
304 | { | |
0d5ff566 | 305 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
2cc432ee JG |
306 | } |
307 | ||
2cc432ee JG |
308 | /** |
309 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
310 | * @qc: Command we are ending DMA for | |
311 | * | |
312 | * Clears the ATA_DMA_START flag in the dma control register | |
313 | * | |
314 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
315 | * | |
316 | * LOCKING: | |
cca3974e | 317 | * spin_lock_irqsave(host lock) |
2cc432ee | 318 | */ |
2cc432ee JG |
319 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
320 | { | |
321 | struct ata_port *ap = qc->ap; | |
0d5ff566 TH |
322 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
323 | ||
324 | /* clear start/stop bit */ | |
325 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
326 | mmio + ATA_DMA_CMD); | |
2cc432ee JG |
327 | |
328 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
329 | ata_altstatus(ap); /* dummy read */ | |
330 | } | |
331 | ||
6d97dbd7 TH |
332 | /** |
333 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
334 | * @ap: port to freeze | |
335 | * | |
336 | * Freeze BMDMA controller port. | |
337 | * | |
338 | * LOCKING: | |
339 | * Inherited from caller. | |
340 | */ | |
341 | void ata_bmdma_freeze(struct ata_port *ap) | |
342 | { | |
343 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
344 | ||
345 | ap->ctl |= ATA_NIEN; | |
346 | ap->last_ctl = ap->ctl; | |
347 | ||
0d5ff566 | 348 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
0f0a3ad3 TH |
349 | |
350 | /* Under certain circumstances, some controllers raise IRQ on | |
351 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
352 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
353 | */ | |
354 | ata_chk_status(ap); | |
355 | ||
356 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
357 | } |
358 | ||
359 | /** | |
360 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
361 | * @ap: port to thaw | |
362 | * | |
363 | * Thaw BMDMA controller port. | |
364 | * | |
365 | * LOCKING: | |
366 | * Inherited from caller. | |
367 | */ | |
368 | void ata_bmdma_thaw(struct ata_port *ap) | |
369 | { | |
370 | /* clear & re-enable interrupts */ | |
371 | ata_chk_status(ap); | |
372 | ap->ops->irq_clear(ap); | |
373 | if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */ | |
374 | ata_irq_on(ap); | |
375 | } | |
376 | ||
377 | /** | |
378 | * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller | |
379 | * @ap: port to handle error for | |
f5914a46 | 380 | * @prereset: prereset method (can be NULL) |
6d97dbd7 TH |
381 | * @softreset: softreset method (can be NULL) |
382 | * @hardreset: hardreset method (can be NULL) | |
383 | * @postreset: postreset method (can be NULL) | |
384 | * | |
385 | * Handle error for ATA BMDMA controller. It can handle both | |
386 | * PATA and SATA controllers. Many controllers should be able to | |
387 | * use this EH as-is or with some added handling before and | |
388 | * after. | |
389 | * | |
390 | * This function is intended to be used for constructing | |
391 | * ->error_handler callback by low level drivers. | |
392 | * | |
393 | * LOCKING: | |
394 | * Kernel thread context (may sleep) | |
395 | */ | |
f5914a46 TH |
396 | void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, |
397 | ata_reset_fn_t softreset, ata_reset_fn_t hardreset, | |
398 | ata_postreset_fn_t postreset) | |
6d97dbd7 | 399 | { |
6d97dbd7 TH |
400 | struct ata_queued_cmd *qc; |
401 | unsigned long flags; | |
402 | int thaw = 0; | |
403 | ||
404 | qc = __ata_qc_from_tag(ap, ap->active_tag); | |
405 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
406 | qc = NULL; | |
407 | ||
408 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 409 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 410 | |
6d97dbd7 TH |
411 | ap->hsm_task_state = HSM_ST_IDLE; |
412 | ||
413 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
414 | qc->tf.protocol == ATA_PROT_ATAPI_DMA)) { | |
415 | u8 host_stat; | |
416 | ||
fbbb262d | 417 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 418 | |
6d97dbd7 TH |
419 | /* BMDMA controllers indicate host bus error by |
420 | * setting DMA_ERR bit and timing out. As it wasn't | |
421 | * really a timeout event, adjust error mask and | |
422 | * cancel frozen state. | |
423 | */ | |
18d90deb | 424 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
425 | qc->err_mask = AC_ERR_HOST_BUS; |
426 | thaw = 1; | |
427 | } | |
428 | ||
429 | ap->ops->bmdma_stop(qc); | |
430 | } | |
431 | ||
432 | ata_altstatus(ap); | |
433 | ata_chk_status(ap); | |
434 | ap->ops->irq_clear(ap); | |
435 | ||
ba6a1308 | 436 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
437 | |
438 | if (thaw) | |
439 | ata_eh_thaw_port(ap); | |
440 | ||
441 | /* PIO and DMA engines have been stopped, perform recovery */ | |
f5914a46 | 442 | ata_do_eh(ap, prereset, softreset, hardreset, postreset); |
6d97dbd7 TH |
443 | } |
444 | ||
445 | /** | |
446 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
447 | * @ap: port to handle error for | |
448 | * | |
449 | * Stock error handler for BMDMA controller. | |
450 | * | |
451 | * LOCKING: | |
452 | * Kernel thread context (may sleep) | |
453 | */ | |
454 | void ata_bmdma_error_handler(struct ata_port *ap) | |
455 | { | |
456 | ata_reset_fn_t hardreset; | |
457 | ||
458 | hardreset = NULL; | |
459 | if (sata_scr_valid(ap)) | |
460 | hardreset = sata_std_hardreset; | |
461 | ||
f5914a46 TH |
462 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
463 | ata_std_postreset); | |
6d97dbd7 TH |
464 | } |
465 | ||
466 | /** | |
467 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
468 | * BMDMA controller | |
469 | * @qc: internal command to clean up | |
470 | * | |
471 | * LOCKING: | |
472 | * Kernel thread context (may sleep) | |
473 | */ | |
474 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
475 | { | |
61dd08c6 A |
476 | if (qc->ap->ioaddr.bmdma_addr) |
477 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
478 | } |
479 | ||
1fdffbce | 480 | #ifdef CONFIG_PCI |
4112e16a A |
481 | |
482 | static int ata_resources_present(struct pci_dev *pdev, int port) | |
483 | { | |
484 | int i; | |
485 | ||
486 | /* Check the PCI resources for this channel are enabled */ | |
487 | port = port * 2; | |
488 | for (i = 0; i < 2; i ++) { | |
489 | if (pci_resource_start(pdev, port + i) == 0 || | |
490 | pci_resource_len(pdev, port + i) == 0) | |
491 | return 0; | |
492 | } | |
493 | return 1; | |
494 | } | |
495 | ||
1fdffbce JG |
496 | /** |
497 | * ata_pci_init_native_mode - Initialize native-mode driver | |
498 | * @pdev: pci device to be initialized | |
499 | * @port: array[2] of pointers to port info structures. | |
500 | * @ports: bitmap of ports present | |
501 | * | |
502 | * Utility function which allocates and initializes an | |
503 | * ata_probe_ent structure for a standard dual-port | |
504 | * PIO-based IDE controller. The returned ata_probe_ent | |
505 | * structure can be passed to ata_device_add(). The returned | |
506 | * ata_probe_ent structure should then be freed with kfree(). | |
507 | * | |
508 | * The caller need only pass the address of the primary port, the | |
509 | * secondary will be deduced automatically. If the device has non | |
510 | * standard secondary port mappings this function can be called twice, | |
511 | * once for each interface. | |
512 | */ | |
513 | ||
514 | struct ata_probe_ent * | |
515 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) | |
516 | { | |
0d5ff566 TH |
517 | struct ata_probe_ent *probe_ent; |
518 | int i, p = 0; | |
519 | void __iomem * const *iomap; | |
520 | ||
521 | /* iomap BARs */ | |
522 | for (i = 0; i < 4; i++) { | |
523 | if (pcim_iomap(pdev, i, 0) == NULL) { | |
524 | dev_printk(KERN_ERR, &pdev->dev, | |
525 | "failed to iomap PCI BAR %d\n", i); | |
526 | return NULL; | |
527 | } | |
528 | } | |
1fdffbce | 529 | |
0d5ff566 TH |
530 | pcim_iomap(pdev, 4, 0); /* may fail */ |
531 | iomap = pcim_iomap_table(pdev); | |
532 | ||
533 | /* alloc and init probe_ent */ | |
534 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | |
1fdffbce JG |
535 | if (!probe_ent) |
536 | return NULL; | |
537 | ||
538 | probe_ent->irq = pdev->irq; | |
1d6f359a | 539 | probe_ent->irq_flags = IRQF_SHARED; |
4112e16a A |
540 | |
541 | /* Discard disabled ports. Some controllers show their | |
542 | unused channels this way */ | |
543 | if (ata_resources_present(pdev, 0) == 0) | |
544 | ports &= ~ATA_PORT_PRIMARY; | |
545 | if (ata_resources_present(pdev, 1) == 0) | |
546 | ports &= ~ATA_PORT_SECONDARY; | |
1fdffbce JG |
547 | |
548 | if (ports & ATA_PORT_PRIMARY) { | |
0d5ff566 | 549 | probe_ent->port[p].cmd_addr = iomap[0]; |
1fdffbce | 550 | probe_ent->port[p].altstatus_addr = |
0d5ff566 TH |
551 | probe_ent->port[p].ctl_addr = (void __iomem *) |
552 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS); | |
553 | if (iomap[4]) { | |
b2a8bbe6 | 554 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 555 | (ioread8(iomap[4] + 2) & 0x80)) |
cca3974e | 556 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
0d5ff566 | 557 | probe_ent->port[p].bmdma_addr = iomap[4]; |
4e5ec5db | 558 | } |
1fdffbce JG |
559 | ata_std_ports(&probe_ent->port[p]); |
560 | p++; | |
561 | } | |
562 | ||
563 | if (ports & ATA_PORT_SECONDARY) { | |
0d5ff566 | 564 | probe_ent->port[p].cmd_addr = iomap[2]; |
1fdffbce | 565 | probe_ent->port[p].altstatus_addr = |
0d5ff566 TH |
566 | probe_ent->port[p].ctl_addr = (void __iomem *) |
567 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS); | |
568 | if (iomap[4]) { | |
b2a8bbe6 | 569 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 570 | (ioread8(iomap[4] + 10) & 0x80)) |
cca3974e | 571 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
0d5ff566 | 572 | probe_ent->port[p].bmdma_addr = iomap[4] + 8; |
4e5ec5db | 573 | } |
1fdffbce | 574 | ata_std_ports(&probe_ent->port[p]); |
fea63e38 | 575 | probe_ent->pinfo2 = port[1]; |
1fdffbce JG |
576 | p++; |
577 | } | |
578 | ||
579 | probe_ent->n_ports = p; | |
580 | return probe_ent; | |
581 | } | |
582 | ||
1fdffbce | 583 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, |
2ec7df04 | 584 | struct ata_port_info **port, int port_mask) |
1fdffbce JG |
585 | { |
586 | struct ata_probe_ent *probe_ent; | |
0d5ff566 TH |
587 | void __iomem *iomap[5] = { }, *bmdma; |
588 | ||
589 | if (port_mask & ATA_PORT_PRIMARY) { | |
590 | iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8); | |
591 | iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1); | |
592 | if (!iomap[0] || !iomap[1]) | |
593 | return NULL; | |
594 | } | |
595 | ||
596 | if (port_mask & ATA_PORT_SECONDARY) { | |
597 | iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8); | |
598 | iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1); | |
599 | if (!iomap[2] || !iomap[3]) | |
600 | return NULL; | |
601 | } | |
602 | ||
603 | bmdma = pcim_iomap(pdev, 4, 16); /* may fail */ | |
2ec7df04 | 604 | |
0d5ff566 | 605 | /* alloc and init probe_ent */ |
2ec7df04 | 606 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); |
1fdffbce JG |
607 | if (!probe_ent) |
608 | return NULL; | |
609 | ||
c4b01f1d | 610 | probe_ent->n_ports = 2; |
8070217d | 611 | probe_ent->irq_flags = IRQF_SHARED; |
2ec7df04 AC |
612 | |
613 | if (port_mask & ATA_PORT_PRIMARY) { | |
8cdf92a9 | 614 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); |
0d5ff566 | 615 | probe_ent->port[0].cmd_addr = iomap[0]; |
c4b01f1d | 616 | probe_ent->port[0].altstatus_addr = |
0d5ff566 | 617 | probe_ent->port[0].ctl_addr = iomap[1]; |
2ec7df04 AC |
618 | if (bmdma) { |
619 | probe_ent->port[0].bmdma_addr = bmdma; | |
b2a8bbe6 | 620 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 621 | (ioread8(bmdma + 2) & 0x80)) |
cca3974e | 622 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 623 | } |
c4b01f1d TH |
624 | ata_std_ports(&probe_ent->port[0]); |
625 | } else | |
626 | probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY; | |
627 | ||
2ec7df04 | 628 | if (port_mask & ATA_PORT_SECONDARY) { |
c4b01f1d | 629 | if (probe_ent->irq) |
8cdf92a9 | 630 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); |
c4b01f1d | 631 | else |
8cdf92a9 | 632 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); |
0d5ff566 | 633 | probe_ent->port[1].cmd_addr = iomap[2]; |
c4b01f1d | 634 | probe_ent->port[1].altstatus_addr = |
0d5ff566 | 635 | probe_ent->port[1].ctl_addr = iomap[3]; |
2ec7df04 | 636 | if (bmdma) { |
c4b01f1d | 637 | probe_ent->port[1].bmdma_addr = bmdma + 8; |
b2a8bbe6 | 638 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 639 | (ioread8(bmdma + 10) & 0x80)) |
cca3974e | 640 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 641 | } |
c4b01f1d | 642 | ata_std_ports(&probe_ent->port[1]); |
d639ca94 JG |
643 | |
644 | /* FIXME: could be pointing to stack area; must copy */ | |
fea63e38 | 645 | probe_ent->pinfo2 = port[1]; |
c4b01f1d TH |
646 | } else |
647 | probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY; | |
1fdffbce JG |
648 | |
649 | return probe_ent; | |
650 | } | |
651 | ||
652 | ||
653 | /** | |
654 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
655 | * @pdev: Controller to be initialized | |
656 | * @port_info: Information from low-level host driver | |
657 | * @n_ports: Number of ports attached to host controller | |
658 | * | |
659 | * This is a helper function which can be called from a driver's | |
660 | * xxx_init_one() probe function if the hardware uses traditional | |
661 | * IDE taskfile registers. | |
662 | * | |
663 | * This function calls pci_enable_device(), reserves its register | |
664 | * regions, sets the dma mask, enables bus master mode, and calls | |
665 | * ata_device_add() | |
666 | * | |
2ec7df04 AC |
667 | * ASSUMPTION: |
668 | * Nobody makes a single channel controller that appears solely as | |
669 | * the secondary legacy port on PCI. | |
670 | * | |
1fdffbce JG |
671 | * LOCKING: |
672 | * Inherited from PCI layer (may sleep). | |
673 | * | |
674 | * RETURNS: | |
675 | * Zero on success, negative on errno-based value on error. | |
676 | */ | |
677 | ||
678 | int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info, | |
679 | unsigned int n_ports) | |
680 | { | |
f0d36efd | 681 | struct device *dev = &pdev->dev; |
2ec7df04 | 682 | struct ata_probe_ent *probe_ent = NULL; |
1fdffbce | 683 | struct ata_port_info *port[2]; |
c791c306 | 684 | u8 mask; |
1fdffbce | 685 | unsigned int legacy_mode = 0; |
1fdffbce JG |
686 | int rc; |
687 | ||
688 | DPRINTK("ENTER\n"); | |
689 | ||
f0d36efd TH |
690 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
691 | return -ENOMEM; | |
692 | ||
c791c306 JG |
693 | BUG_ON(n_ports < 1 || n_ports > 2); |
694 | ||
1fdffbce JG |
695 | port[0] = port_info[0]; |
696 | if (n_ports > 1) | |
697 | port[1] = port_info[1]; | |
698 | else | |
699 | port[1] = port[0]; | |
700 | ||
1fdffbce JG |
701 | /* FIXME: Really for ATA it isn't safe because the device may be |
702 | multi-purpose and we want to leave it alone if it was already | |
703 | enabled. Secondly for shared use as Arjan says we want refcounting | |
704 | ||
705 | Checking dev->is_enabled is insufficient as this is not set at | |
706 | boot for the primary video which is BIOS enabled | |
707 | */ | |
708 | ||
f0d36efd | 709 | rc = pcim_enable_device(pdev); |
1fdffbce | 710 | if (rc) |
f0d36efd | 711 | goto err_out; |
1fdffbce | 712 | |
c791c306 JG |
713 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { |
714 | u8 tmp8; | |
715 | ||
716 | /* TODO: What if one channel is in native mode ... */ | |
717 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
718 | mask = (1 << 2) | (1 << 0); | |
719 | if ((tmp8 & mask) != mask) | |
720 | legacy_mode = (1 << 3); | |
8eb166bf AC |
721 | #if defined(CONFIG_NO_ATA_LEGACY) |
722 | /* Some platforms with PCI limits cannot address compat | |
723 | port space. In that case we punt if their firmware has | |
724 | left a device in compatibility mode */ | |
725 | if (legacy_mode) { | |
726 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
f0d36efd TH |
727 | rc = -EOPNOTSUPP; |
728 | goto err_out; | |
8eb166bf AC |
729 | } |
730 | #endif | |
c791c306 JG |
731 | } |
732 | ||
dc3c3377 A |
733 | if (!legacy_mode) { |
734 | rc = pci_request_regions(pdev, DRV_NAME); | |
735 | if (rc) { | |
f0d36efd | 736 | pcim_pin_device(pdev); |
dc3c3377 A |
737 | goto err_out; |
738 | } | |
739 | } else { | |
740 | /* Deal with combined mode hack. This side of the logic all | |
741 | goes away once the combined mode hack is killed in 2.6.21 */ | |
f0d36efd | 742 | if (!devm_request_region(dev, ATA_PRIMARY_CMD, 8, "libata")) { |
1fdffbce | 743 | struct resource *conflict, res; |
2ec7df04 AC |
744 | res.start = ATA_PRIMARY_CMD; |
745 | res.end = ATA_PRIMARY_CMD + 8 - 1; | |
1fdffbce | 746 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
747 | while (conflict->child) |
748 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 749 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 750 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce | 751 | else { |
f0d36efd | 752 | pcim_pin_device(pdev); |
a64f97f2 JG |
753 | printk(KERN_WARNING "ata: 0x%0X IDE port busy\n" \ |
754 | "ata: conflict with %s\n", | |
755 | ATA_PRIMARY_CMD, | |
756 | conflict->name); | |
1fdffbce JG |
757 | } |
758 | } else | |
2ec7df04 | 759 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce | 760 | |
f0d36efd | 761 | if (!devm_request_region(dev, ATA_SECONDARY_CMD, 8, "libata")) { |
1fdffbce | 762 | struct resource *conflict, res; |
2ec7df04 AC |
763 | res.start = ATA_SECONDARY_CMD; |
764 | res.end = ATA_SECONDARY_CMD + 8 - 1; | |
1fdffbce | 765 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
766 | while (conflict->child) |
767 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 768 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 769 | legacy_mode |= ATA_PORT_SECONDARY; |
1fdffbce | 770 | else { |
f0d36efd | 771 | pcim_pin_device(pdev); |
a64f97f2 JG |
772 | printk(KERN_WARNING "ata: 0x%X IDE port busy\n" \ |
773 | "ata: conflict with %s\n", | |
774 | ATA_SECONDARY_CMD, | |
775 | conflict->name); | |
1fdffbce JG |
776 | } |
777 | } else | |
2ec7df04 | 778 | legacy_mode |= ATA_PORT_SECONDARY; |
dc3c3377 A |
779 | |
780 | if (legacy_mode & ATA_PORT_PRIMARY) | |
781 | pci_request_region(pdev, 1, DRV_NAME); | |
782 | if (legacy_mode & ATA_PORT_SECONDARY) | |
783 | pci_request_region(pdev, 3, DRV_NAME); | |
784 | /* If there is a DMA resource, allocate it */ | |
785 | pci_request_region(pdev, 4, DRV_NAME); | |
1fdffbce JG |
786 | } |
787 | ||
788 | /* we have legacy mode, but all ports are unavailable */ | |
789 | if (legacy_mode == (1 << 3)) { | |
790 | rc = -EBUSY; | |
f0d36efd | 791 | goto err_out; |
1fdffbce JG |
792 | } |
793 | ||
c791c306 | 794 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
1fdffbce JG |
795 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
796 | if (rc) | |
f0d36efd | 797 | goto err_out; |
1fdffbce JG |
798 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
799 | if (rc) | |
f0d36efd | 800 | goto err_out; |
1fdffbce JG |
801 | |
802 | if (legacy_mode) { | |
2ec7df04 | 803 | probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode); |
1fdffbce JG |
804 | } else { |
805 | if (n_ports == 2) | |
806 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); | |
807 | else | |
808 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY); | |
809 | } | |
2ec7df04 | 810 | if (!probe_ent) { |
1fdffbce | 811 | rc = -ENOMEM; |
f0d36efd | 812 | goto err_out; |
1fdffbce JG |
813 | } |
814 | ||
815 | pci_set_master(pdev); | |
816 | ||
c791c306 JG |
817 | if (!ata_device_add(probe_ent)) { |
818 | rc = -ENODEV; | |
f0d36efd | 819 | goto err_out; |
c791c306 | 820 | } |
1fdffbce | 821 | |
f0d36efd TH |
822 | devm_kfree(dev, probe_ent); |
823 | devres_remove_group(dev, NULL); | |
1fdffbce JG |
824 | return 0; |
825 | ||
1fdffbce | 826 | err_out: |
f0d36efd | 827 | devres_release_group(dev, NULL); |
1fdffbce JG |
828 | return rc; |
829 | } | |
830 | ||
d33d44fa AC |
831 | /** |
832 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
833 | * @pdev: PCI device | |
834 | * | |
835 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2e9edbf8 | 836 | * enter non simplex mode. This implements the neccessary logic to |
d33d44fa AC |
837 | * perform the task on such devices. Calling it on other devices will |
838 | * have -undefined- behaviour. | |
839 | */ | |
840 | ||
841 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
842 | { | |
843 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
844 | u8 simplex; | |
845 | ||
846 | if (bmdma == 0) | |
847 | return -ENOENT; | |
848 | ||
849 | simplex = inb(bmdma + 0x02); | |
850 | outb(simplex & 0x60, bmdma + 0x02); | |
851 | simplex = inb(bmdma + 0x02); | |
852 | if (simplex & 0x80) | |
853 | return -EOPNOTSUPP; | |
854 | return 0; | |
855 | } | |
856 | ||
857 | unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask) | |
858 | { | |
859 | /* Filter out DMA modes if the device has been configured by | |
860 | the BIOS as PIO only */ | |
2e9edbf8 | 861 | |
d33d44fa AC |
862 | if (ap->ioaddr.bmdma_addr == 0) |
863 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
864 | return xfer_mask; | |
865 | } | |
866 | ||
1fdffbce JG |
867 | #endif /* CONFIG_PCI */ |
868 |