Commit | Line | Data |
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1fdffbce JG |
1 | /* |
2 | * libata-bmdma.c - helper library for PCI IDE BMDMA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
90088bb4 TH |
41 | /** |
42 | * ata_irq_on - Enable interrupts on a port. | |
43 | * @ap: Port on which interrupts are enabled. | |
44 | * | |
45 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
46 | * wait for idle, clear any pending interrupts. | |
47 | * | |
48 | * LOCKING: | |
49 | * Inherited from caller. | |
50 | */ | |
51 | u8 ata_irq_on(struct ata_port *ap) | |
52 | { | |
53 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
54 | u8 tmp; | |
55 | ||
56 | ap->ctl &= ~ATA_NIEN; | |
57 | ap->last_ctl = ap->ctl; | |
58 | ||
0d5ff566 | 59 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
90088bb4 TH |
60 | tmp = ata_wait_idle(ap); |
61 | ||
62 | ap->ops->irq_clear(ap); | |
63 | ||
64 | return tmp; | |
65 | } | |
66 | ||
83625006 AI |
67 | u8 ata_dummy_irq_on (struct ata_port *ap) { return 0; } |
68 | ||
69 | /** | |
70 | * ata_irq_ack - Acknowledge a device interrupt. | |
71 | * @ap: Port on which interrupts are enabled. | |
72 | * | |
73 | * Wait up to 10 ms for legacy IDE device to become idle (BUSY | |
74 | * or BUSY+DRQ clear). Obtain dma status and port status from | |
75 | * device. Clear the interrupt. Return port status. | |
76 | * | |
77 | * LOCKING: | |
78 | */ | |
79 | ||
80 | u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq) | |
81 | { | |
82 | unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; | |
83 | u8 host_stat, post_stat, status; | |
84 | ||
85 | status = ata_busy_wait(ap, bits, 1000); | |
86 | if (status & bits) | |
87 | if (ata_msg_err(ap)) | |
88 | printk(KERN_ERR "abnormal status 0x%X\n", status); | |
89 | ||
90 | /* get controller status; clear intr, err bits */ | |
91 | host_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
92 | iowrite8(host_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
93 | ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
94 | ||
95 | post_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
96 | ||
97 | if (ata_msg_intr(ap)) | |
98 | printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n", | |
99 | __FUNCTION__, | |
100 | host_stat, post_stat, status); | |
101 | ||
102 | return status; | |
103 | } | |
104 | ||
105 | u8 ata_dummy_irq_ack(struct ata_port *ap, unsigned int chk_drq) { return 0; } | |
106 | ||
1fdffbce | 107 | /** |
0d5ff566 | 108 | * ata_tf_load - send taskfile registers to host controller |
1fdffbce JG |
109 | * @ap: Port to which output is sent |
110 | * @tf: ATA taskfile register set | |
111 | * | |
112 | * Outputs ATA taskfile to standard ATA host controller. | |
113 | * | |
114 | * LOCKING: | |
115 | * Inherited from caller. | |
116 | */ | |
117 | ||
0d5ff566 | 118 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
119 | { |
120 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
121 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
122 | ||
123 | if (tf->ctl != ap->last_ctl) { | |
0d5ff566 | 124 | iowrite8(tf->ctl, ioaddr->ctl_addr); |
1fdffbce JG |
125 | ap->last_ctl = tf->ctl; |
126 | ata_wait_idle(ap); | |
127 | } | |
128 | ||
129 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
0d5ff566 TH |
130 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
131 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
132 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
133 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
134 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
135 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
136 | tf->hob_feature, | |
137 | tf->hob_nsect, | |
138 | tf->hob_lbal, | |
139 | tf->hob_lbam, | |
140 | tf->hob_lbah); | |
141 | } | |
142 | ||
143 | if (is_addr) { | |
0d5ff566 TH |
144 | iowrite8(tf->feature, ioaddr->feature_addr); |
145 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
146 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
147 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
148 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
149 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
150 | tf->feature, | |
151 | tf->nsect, | |
152 | tf->lbal, | |
153 | tf->lbam, | |
154 | tf->lbah); | |
155 | } | |
156 | ||
157 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
0d5ff566 | 158 | iowrite8(tf->device, ioaddr->device_addr); |
1fdffbce JG |
159 | VPRINTK("device 0x%X\n", tf->device); |
160 | } | |
161 | ||
162 | ata_wait_idle(ap); | |
163 | } | |
164 | ||
1fdffbce | 165 | /** |
0d5ff566 | 166 | * ata_exec_command - issue ATA command to host controller |
1fdffbce JG |
167 | * @ap: port to which command is being issued |
168 | * @tf: ATA taskfile register set | |
169 | * | |
0d5ff566 TH |
170 | * Issues ATA command, with proper synchronization with interrupt |
171 | * handler / other threads. | |
7c74ffd0 | 172 | * |
1fdffbce | 173 | * LOCKING: |
cca3974e | 174 | * spin_lock_irqsave(host lock) |
1fdffbce | 175 | */ |
0d5ff566 | 176 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce | 177 | { |
44877b4e | 178 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
1fdffbce | 179 | |
0d5ff566 | 180 | iowrite8(tf->command, ap->ioaddr.command_addr); |
1fdffbce JG |
181 | ata_pause(ap); |
182 | } | |
183 | ||
1fdffbce | 184 | /** |
0d5ff566 | 185 | * ata_tf_read - input device's ATA taskfile shadow registers |
1fdffbce JG |
186 | * @ap: Port from which input is read |
187 | * @tf: ATA taskfile register set for storing input | |
188 | * | |
189 | * Reads ATA taskfile registers for currently-selected device | |
190 | * into @tf. | |
191 | * | |
192 | * LOCKING: | |
193 | * Inherited from caller. | |
194 | */ | |
0d5ff566 | 195 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1fdffbce JG |
196 | { |
197 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
198 | ||
199 | tf->command = ata_check_status(ap); | |
0d5ff566 TH |
200 | tf->feature = ioread8(ioaddr->error_addr); |
201 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
202 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
203 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
204 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
205 | tf->device = ioread8(ioaddr->device_addr); | |
1fdffbce JG |
206 | |
207 | if (tf->flags & ATA_TFLAG_LBA48) { | |
0d5ff566 TH |
208 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); |
209 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
210 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
211 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
212 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
213 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
1fdffbce JG |
214 | } |
215 | } | |
216 | ||
1fdffbce JG |
217 | /** |
218 | * ata_check_status - Read device status reg & clear interrupt | |
219 | * @ap: port where the device is | |
220 | * | |
221 | * Reads ATA taskfile status register for currently-selected device | |
222 | * and return its value. This also clears pending interrupts | |
223 | * from this device | |
224 | * | |
1fdffbce JG |
225 | * LOCKING: |
226 | * Inherited from caller. | |
227 | */ | |
228 | u8 ata_check_status(struct ata_port *ap) | |
229 | { | |
0d5ff566 | 230 | return ioread8(ap->ioaddr.status_addr); |
1fdffbce JG |
231 | } |
232 | ||
1fdffbce JG |
233 | /** |
234 | * ata_altstatus - Read device alternate status reg | |
235 | * @ap: port where the device is | |
236 | * | |
237 | * Reads ATA taskfile alternate status register for | |
238 | * currently-selected device and return its value. | |
239 | * | |
240 | * Note: may NOT be used as the check_altstatus() entry in | |
241 | * ata_port_operations. | |
242 | * | |
243 | * LOCKING: | |
244 | * Inherited from caller. | |
245 | */ | |
246 | u8 ata_altstatus(struct ata_port *ap) | |
247 | { | |
248 | if (ap->ops->check_altstatus) | |
249 | return ap->ops->check_altstatus(ap); | |
250 | ||
0d5ff566 | 251 | return ioread8(ap->ioaddr.altstatus_addr); |
1fdffbce JG |
252 | } |
253 | ||
2cc432ee | 254 | /** |
0d5ff566 | 255 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
2cc432ee JG |
256 | * @qc: Info associated with this ATA transaction. |
257 | * | |
258 | * LOCKING: | |
cca3974e | 259 | * spin_lock_irqsave(host lock) |
2cc432ee | 260 | */ |
0d5ff566 | 261 | void ata_bmdma_setup(struct ata_queued_cmd *qc) |
2cc432ee JG |
262 | { |
263 | struct ata_port *ap = qc->ap; | |
264 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
265 | u8 dmactl; | |
2cc432ee JG |
266 | |
267 | /* load PRD table addr. */ | |
268 | mb(); /* make sure PRD table writes are visible to controller */ | |
0d5ff566 | 269 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
2cc432ee JG |
270 | |
271 | /* specify data direction, triple-check start bit is clear */ | |
0d5ff566 | 272 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
273 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
274 | if (!rw) | |
275 | dmactl |= ATA_DMA_WR; | |
0d5ff566 | 276 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
277 | |
278 | /* issue r/w command */ | |
279 | ap->ops->exec_command(ap, &qc->tf); | |
280 | } | |
281 | ||
282 | /** | |
0d5ff566 | 283 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
2cc432ee JG |
284 | * @qc: Info associated with this ATA transaction. |
285 | * | |
286 | * LOCKING: | |
cca3974e | 287 | * spin_lock_irqsave(host lock) |
2cc432ee | 288 | */ |
0d5ff566 | 289 | void ata_bmdma_start (struct ata_queued_cmd *qc) |
2cc432ee JG |
290 | { |
291 | struct ata_port *ap = qc->ap; | |
2cc432ee JG |
292 | u8 dmactl; |
293 | ||
294 | /* start host DMA transaction */ | |
0d5ff566 TH |
295 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
296 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2cc432ee JG |
297 | |
298 | /* Strictly, one may wish to issue a readb() here, to | |
299 | * flush the mmio write. However, control also passes | |
300 | * to the hardware at this point, and it will interrupt | |
301 | * us when we are to resume control. So, in effect, | |
302 | * we don't care when the mmio write flushes. | |
303 | * Further, a read of the DMA status register _immediately_ | |
304 | * following the write may not be what certain flaky hardware | |
305 | * is expected, so I think it is best to not add a readb() | |
306 | * without first all the MMIO ATA cards/mobos. | |
307 | * Or maybe I'm just being paranoid. | |
308 | */ | |
309 | } | |
310 | ||
2cc432ee JG |
311 | /** |
312 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
313 | * @ap: Port associated with this ATA transaction. | |
314 | * | |
315 | * Clear interrupt and error flags in DMA status register. | |
316 | * | |
317 | * May be used as the irq_clear() entry in ata_port_operations. | |
318 | * | |
319 | * LOCKING: | |
cca3974e | 320 | * spin_lock_irqsave(host lock) |
2cc432ee | 321 | */ |
2cc432ee JG |
322 | void ata_bmdma_irq_clear(struct ata_port *ap) |
323 | { | |
0d5ff566 TH |
324 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
325 | ||
326 | if (!mmio) | |
2cc432ee JG |
327 | return; |
328 | ||
0d5ff566 | 329 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
2cc432ee JG |
330 | } |
331 | ||
2cc432ee JG |
332 | /** |
333 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
334 | * @ap: Port associated with this ATA transaction. | |
335 | * | |
336 | * Read and return BMDMA status register. | |
337 | * | |
338 | * May be used as the bmdma_status() entry in ata_port_operations. | |
339 | * | |
340 | * LOCKING: | |
cca3974e | 341 | * spin_lock_irqsave(host lock) |
2cc432ee | 342 | */ |
2cc432ee JG |
343 | u8 ata_bmdma_status(struct ata_port *ap) |
344 | { | |
0d5ff566 | 345 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
2cc432ee JG |
346 | } |
347 | ||
2cc432ee JG |
348 | /** |
349 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
350 | * @qc: Command we are ending DMA for | |
351 | * | |
352 | * Clears the ATA_DMA_START flag in the dma control register | |
353 | * | |
354 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
355 | * | |
356 | * LOCKING: | |
cca3974e | 357 | * spin_lock_irqsave(host lock) |
2cc432ee | 358 | */ |
2cc432ee JG |
359 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
360 | { | |
361 | struct ata_port *ap = qc->ap; | |
0d5ff566 TH |
362 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
363 | ||
364 | /* clear start/stop bit */ | |
365 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
366 | mmio + ATA_DMA_CMD); | |
2cc432ee JG |
367 | |
368 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
369 | ata_altstatus(ap); /* dummy read */ | |
370 | } | |
371 | ||
6d97dbd7 TH |
372 | /** |
373 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
374 | * @ap: port to freeze | |
375 | * | |
376 | * Freeze BMDMA controller port. | |
377 | * | |
378 | * LOCKING: | |
379 | * Inherited from caller. | |
380 | */ | |
381 | void ata_bmdma_freeze(struct ata_port *ap) | |
382 | { | |
383 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
384 | ||
385 | ap->ctl |= ATA_NIEN; | |
386 | ap->last_ctl = ap->ctl; | |
387 | ||
0d5ff566 | 388 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
0f0a3ad3 TH |
389 | |
390 | /* Under certain circumstances, some controllers raise IRQ on | |
391 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
392 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
393 | */ | |
394 | ata_chk_status(ap); | |
395 | ||
396 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
397 | } |
398 | ||
399 | /** | |
400 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
401 | * @ap: port to thaw | |
402 | * | |
403 | * Thaw BMDMA controller port. | |
404 | * | |
405 | * LOCKING: | |
406 | * Inherited from caller. | |
407 | */ | |
408 | void ata_bmdma_thaw(struct ata_port *ap) | |
409 | { | |
410 | /* clear & re-enable interrupts */ | |
411 | ata_chk_status(ap); | |
412 | ap->ops->irq_clear(ap); | |
83625006 | 413 | ap->ops->irq_on(ap); |
6d97dbd7 TH |
414 | } |
415 | ||
416 | /** | |
417 | * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller | |
418 | * @ap: port to handle error for | |
f5914a46 | 419 | * @prereset: prereset method (can be NULL) |
6d97dbd7 TH |
420 | * @softreset: softreset method (can be NULL) |
421 | * @hardreset: hardreset method (can be NULL) | |
422 | * @postreset: postreset method (can be NULL) | |
423 | * | |
424 | * Handle error for ATA BMDMA controller. It can handle both | |
425 | * PATA and SATA controllers. Many controllers should be able to | |
426 | * use this EH as-is or with some added handling before and | |
427 | * after. | |
428 | * | |
429 | * This function is intended to be used for constructing | |
430 | * ->error_handler callback by low level drivers. | |
431 | * | |
432 | * LOCKING: | |
433 | * Kernel thread context (may sleep) | |
434 | */ | |
f5914a46 TH |
435 | void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, |
436 | ata_reset_fn_t softreset, ata_reset_fn_t hardreset, | |
437 | ata_postreset_fn_t postreset) | |
6d97dbd7 | 438 | { |
6d97dbd7 TH |
439 | struct ata_queued_cmd *qc; |
440 | unsigned long flags; | |
441 | int thaw = 0; | |
442 | ||
443 | qc = __ata_qc_from_tag(ap, ap->active_tag); | |
444 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
445 | qc = NULL; | |
446 | ||
447 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 448 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 449 | |
6d97dbd7 TH |
450 | ap->hsm_task_state = HSM_ST_IDLE; |
451 | ||
452 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
453 | qc->tf.protocol == ATA_PROT_ATAPI_DMA)) { | |
454 | u8 host_stat; | |
455 | ||
fbbb262d | 456 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 457 | |
6d97dbd7 TH |
458 | /* BMDMA controllers indicate host bus error by |
459 | * setting DMA_ERR bit and timing out. As it wasn't | |
460 | * really a timeout event, adjust error mask and | |
461 | * cancel frozen state. | |
462 | */ | |
18d90deb | 463 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
464 | qc->err_mask = AC_ERR_HOST_BUS; |
465 | thaw = 1; | |
466 | } | |
467 | ||
468 | ap->ops->bmdma_stop(qc); | |
469 | } | |
470 | ||
471 | ata_altstatus(ap); | |
472 | ata_chk_status(ap); | |
473 | ap->ops->irq_clear(ap); | |
474 | ||
ba6a1308 | 475 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
476 | |
477 | if (thaw) | |
478 | ata_eh_thaw_port(ap); | |
479 | ||
480 | /* PIO and DMA engines have been stopped, perform recovery */ | |
f5914a46 | 481 | ata_do_eh(ap, prereset, softreset, hardreset, postreset); |
6d97dbd7 TH |
482 | } |
483 | ||
484 | /** | |
485 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
486 | * @ap: port to handle error for | |
487 | * | |
488 | * Stock error handler for BMDMA controller. | |
489 | * | |
490 | * LOCKING: | |
491 | * Kernel thread context (may sleep) | |
492 | */ | |
493 | void ata_bmdma_error_handler(struct ata_port *ap) | |
494 | { | |
495 | ata_reset_fn_t hardreset; | |
496 | ||
497 | hardreset = NULL; | |
498 | if (sata_scr_valid(ap)) | |
499 | hardreset = sata_std_hardreset; | |
500 | ||
f5914a46 TH |
501 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
502 | ata_std_postreset); | |
6d97dbd7 TH |
503 | } |
504 | ||
505 | /** | |
506 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
507 | * BMDMA controller | |
508 | * @qc: internal command to clean up | |
509 | * | |
510 | * LOCKING: | |
511 | * Kernel thread context (may sleep) | |
512 | */ | |
513 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
514 | { | |
61dd08c6 A |
515 | if (qc->ap->ioaddr.bmdma_addr) |
516 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
517 | } |
518 | ||
1fdffbce | 519 | #ifdef CONFIG_PCI |
4112e16a A |
520 | |
521 | static int ata_resources_present(struct pci_dev *pdev, int port) | |
522 | { | |
523 | int i; | |
a84471fe | 524 | |
4112e16a A |
525 | /* Check the PCI resources for this channel are enabled */ |
526 | port = port * 2; | |
527 | for (i = 0; i < 2; i ++) { | |
528 | if (pci_resource_start(pdev, port + i) == 0 || | |
529 | pci_resource_len(pdev, port + i) == 0) | |
530 | return 0; | |
531 | } | |
532 | return 1; | |
533 | } | |
a84471fe | 534 | |
1fdffbce JG |
535 | /** |
536 | * ata_pci_init_native_mode - Initialize native-mode driver | |
537 | * @pdev: pci device to be initialized | |
538 | * @port: array[2] of pointers to port info structures. | |
539 | * @ports: bitmap of ports present | |
540 | * | |
541 | * Utility function which allocates and initializes an | |
542 | * ata_probe_ent structure for a standard dual-port | |
543 | * PIO-based IDE controller. The returned ata_probe_ent | |
544 | * structure can be passed to ata_device_add(). The returned | |
545 | * ata_probe_ent structure should then be freed with kfree(). | |
546 | * | |
547 | * The caller need only pass the address of the primary port, the | |
548 | * secondary will be deduced automatically. If the device has non | |
549 | * standard secondary port mappings this function can be called twice, | |
550 | * once for each interface. | |
551 | */ | |
552 | ||
553 | struct ata_probe_ent * | |
554 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) | |
555 | { | |
0d5ff566 TH |
556 | struct ata_probe_ent *probe_ent; |
557 | int i, p = 0; | |
558 | void __iomem * const *iomap; | |
559 | ||
560 | /* iomap BARs */ | |
561 | for (i = 0; i < 4; i++) { | |
562 | if (pcim_iomap(pdev, i, 0) == NULL) { | |
563 | dev_printk(KERN_ERR, &pdev->dev, | |
564 | "failed to iomap PCI BAR %d\n", i); | |
565 | return NULL; | |
566 | } | |
567 | } | |
1fdffbce | 568 | |
0d5ff566 TH |
569 | pcim_iomap(pdev, 4, 0); /* may fail */ |
570 | iomap = pcim_iomap_table(pdev); | |
571 | ||
572 | /* alloc and init probe_ent */ | |
573 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | |
1fdffbce JG |
574 | if (!probe_ent) |
575 | return NULL; | |
576 | ||
577 | probe_ent->irq = pdev->irq; | |
1d6f359a | 578 | probe_ent->irq_flags = IRQF_SHARED; |
a84471fe | 579 | |
4112e16a A |
580 | /* Discard disabled ports. Some controllers show their |
581 | unused channels this way */ | |
582 | if (ata_resources_present(pdev, 0) == 0) | |
583 | ports &= ~ATA_PORT_PRIMARY; | |
584 | if (ata_resources_present(pdev, 1) == 0) | |
585 | ports &= ~ATA_PORT_SECONDARY; | |
1fdffbce JG |
586 | |
587 | if (ports & ATA_PORT_PRIMARY) { | |
0d5ff566 | 588 | probe_ent->port[p].cmd_addr = iomap[0]; |
1fdffbce | 589 | probe_ent->port[p].altstatus_addr = |
0d5ff566 TH |
590 | probe_ent->port[p].ctl_addr = (void __iomem *) |
591 | ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS); | |
592 | if (iomap[4]) { | |
b2a8bbe6 | 593 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 594 | (ioread8(iomap[4] + 2) & 0x80)) |
cca3974e | 595 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
0d5ff566 | 596 | probe_ent->port[p].bmdma_addr = iomap[4]; |
4e5ec5db | 597 | } |
1fdffbce JG |
598 | ata_std_ports(&probe_ent->port[p]); |
599 | p++; | |
600 | } | |
601 | ||
602 | if (ports & ATA_PORT_SECONDARY) { | |
0d5ff566 | 603 | probe_ent->port[p].cmd_addr = iomap[2]; |
1fdffbce | 604 | probe_ent->port[p].altstatus_addr = |
0d5ff566 TH |
605 | probe_ent->port[p].ctl_addr = (void __iomem *) |
606 | ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS); | |
607 | if (iomap[4]) { | |
b2a8bbe6 | 608 | if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 609 | (ioread8(iomap[4] + 10) & 0x80)) |
cca3974e | 610 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
0d5ff566 | 611 | probe_ent->port[p].bmdma_addr = iomap[4] + 8; |
4e5ec5db | 612 | } |
1fdffbce | 613 | ata_std_ports(&probe_ent->port[p]); |
fea63e38 | 614 | probe_ent->pinfo2 = port[1]; |
1fdffbce JG |
615 | p++; |
616 | } | |
617 | ||
618 | probe_ent->n_ports = p; | |
619 | return probe_ent; | |
620 | } | |
621 | ||
1fdffbce | 622 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, |
2ec7df04 | 623 | struct ata_port_info **port, int port_mask) |
1fdffbce JG |
624 | { |
625 | struct ata_probe_ent *probe_ent; | |
0d5ff566 TH |
626 | void __iomem *iomap[5] = { }, *bmdma; |
627 | ||
628 | if (port_mask & ATA_PORT_PRIMARY) { | |
629 | iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8); | |
630 | iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1); | |
631 | if (!iomap[0] || !iomap[1]) | |
632 | return NULL; | |
633 | } | |
634 | ||
635 | if (port_mask & ATA_PORT_SECONDARY) { | |
636 | iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8); | |
637 | iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1); | |
638 | if (!iomap[2] || !iomap[3]) | |
639 | return NULL; | |
640 | } | |
641 | ||
642 | bmdma = pcim_iomap(pdev, 4, 16); /* may fail */ | |
2ec7df04 | 643 | |
0d5ff566 | 644 | /* alloc and init probe_ent */ |
2ec7df04 | 645 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); |
1fdffbce JG |
646 | if (!probe_ent) |
647 | return NULL; | |
648 | ||
c4b01f1d | 649 | probe_ent->n_ports = 2; |
8070217d | 650 | probe_ent->irq_flags = IRQF_SHARED; |
2ec7df04 AC |
651 | |
652 | if (port_mask & ATA_PORT_PRIMARY) { | |
8cdf92a9 | 653 | probe_ent->irq = ATA_PRIMARY_IRQ(pdev); |
0d5ff566 | 654 | probe_ent->port[0].cmd_addr = iomap[0]; |
c4b01f1d | 655 | probe_ent->port[0].altstatus_addr = |
0d5ff566 | 656 | probe_ent->port[0].ctl_addr = iomap[1]; |
2ec7df04 AC |
657 | if (bmdma) { |
658 | probe_ent->port[0].bmdma_addr = bmdma; | |
b2a8bbe6 | 659 | if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 660 | (ioread8(bmdma + 2) & 0x80)) |
cca3974e | 661 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 662 | } |
c4b01f1d TH |
663 | ata_std_ports(&probe_ent->port[0]); |
664 | } else | |
665 | probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY; | |
666 | ||
2ec7df04 | 667 | if (port_mask & ATA_PORT_SECONDARY) { |
c4b01f1d | 668 | if (probe_ent->irq) |
8cdf92a9 | 669 | probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); |
c4b01f1d | 670 | else |
8cdf92a9 | 671 | probe_ent->irq = ATA_SECONDARY_IRQ(pdev); |
0d5ff566 | 672 | probe_ent->port[1].cmd_addr = iomap[2]; |
c4b01f1d | 673 | probe_ent->port[1].altstatus_addr = |
0d5ff566 | 674 | probe_ent->port[1].ctl_addr = iomap[3]; |
2ec7df04 | 675 | if (bmdma) { |
c4b01f1d | 676 | probe_ent->port[1].bmdma_addr = bmdma + 8; |
b2a8bbe6 | 677 | if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && |
0d5ff566 | 678 | (ioread8(bmdma + 10) & 0x80)) |
cca3974e | 679 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 680 | } |
c4b01f1d | 681 | ata_std_ports(&probe_ent->port[1]); |
d639ca94 JG |
682 | |
683 | /* FIXME: could be pointing to stack area; must copy */ | |
fea63e38 | 684 | probe_ent->pinfo2 = port[1]; |
c4b01f1d TH |
685 | } else |
686 | probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY; | |
1fdffbce JG |
687 | |
688 | return probe_ent; | |
689 | } | |
690 | ||
691 | ||
692 | /** | |
693 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
694 | * @pdev: Controller to be initialized | |
695 | * @port_info: Information from low-level host driver | |
696 | * @n_ports: Number of ports attached to host controller | |
697 | * | |
698 | * This is a helper function which can be called from a driver's | |
699 | * xxx_init_one() probe function if the hardware uses traditional | |
700 | * IDE taskfile registers. | |
701 | * | |
702 | * This function calls pci_enable_device(), reserves its register | |
703 | * regions, sets the dma mask, enables bus master mode, and calls | |
704 | * ata_device_add() | |
705 | * | |
2ec7df04 AC |
706 | * ASSUMPTION: |
707 | * Nobody makes a single channel controller that appears solely as | |
708 | * the secondary legacy port on PCI. | |
709 | * | |
1fdffbce JG |
710 | * LOCKING: |
711 | * Inherited from PCI layer (may sleep). | |
712 | * | |
713 | * RETURNS: | |
714 | * Zero on success, negative on errno-based value on error. | |
715 | */ | |
716 | ||
717 | int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info, | |
718 | unsigned int n_ports) | |
719 | { | |
f0d36efd | 720 | struct device *dev = &pdev->dev; |
2ec7df04 | 721 | struct ata_probe_ent *probe_ent = NULL; |
1fdffbce | 722 | struct ata_port_info *port[2]; |
c791c306 | 723 | u8 mask; |
1fdffbce | 724 | unsigned int legacy_mode = 0; |
1fdffbce JG |
725 | int rc; |
726 | ||
727 | DPRINTK("ENTER\n"); | |
728 | ||
f0d36efd TH |
729 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
730 | return -ENOMEM; | |
731 | ||
c791c306 JG |
732 | BUG_ON(n_ports < 1 || n_ports > 2); |
733 | ||
1fdffbce JG |
734 | port[0] = port_info[0]; |
735 | if (n_ports > 1) | |
736 | port[1] = port_info[1]; | |
737 | else | |
738 | port[1] = port[0]; | |
739 | ||
1fdffbce JG |
740 | /* FIXME: Really for ATA it isn't safe because the device may be |
741 | multi-purpose and we want to leave it alone if it was already | |
742 | enabled. Secondly for shared use as Arjan says we want refcounting | |
743 | ||
744 | Checking dev->is_enabled is insufficient as this is not set at | |
745 | boot for the primary video which is BIOS enabled | |
746 | */ | |
747 | ||
f0d36efd | 748 | rc = pcim_enable_device(pdev); |
1fdffbce | 749 | if (rc) |
f0d36efd | 750 | goto err_out; |
1fdffbce | 751 | |
c791c306 JG |
752 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { |
753 | u8 tmp8; | |
754 | ||
755 | /* TODO: What if one channel is in native mode ... */ | |
756 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
757 | mask = (1 << 2) | (1 << 0); | |
758 | if ((tmp8 & mask) != mask) | |
759 | legacy_mode = (1 << 3); | |
8eb166bf AC |
760 | #if defined(CONFIG_NO_ATA_LEGACY) |
761 | /* Some platforms with PCI limits cannot address compat | |
762 | port space. In that case we punt if their firmware has | |
763 | left a device in compatibility mode */ | |
764 | if (legacy_mode) { | |
765 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
f0d36efd TH |
766 | rc = -EOPNOTSUPP; |
767 | goto err_out; | |
8eb166bf AC |
768 | } |
769 | #endif | |
c791c306 JG |
770 | } |
771 | ||
dc3c3377 A |
772 | if (!legacy_mode) { |
773 | rc = pci_request_regions(pdev, DRV_NAME); | |
774 | if (rc) { | |
f0d36efd | 775 | pcim_pin_device(pdev); |
dc3c3377 A |
776 | goto err_out; |
777 | } | |
778 | } else { | |
779 | /* Deal with combined mode hack. This side of the logic all | |
780 | goes away once the combined mode hack is killed in 2.6.21 */ | |
f0d36efd | 781 | if (!devm_request_region(dev, ATA_PRIMARY_CMD, 8, "libata")) { |
1fdffbce | 782 | struct resource *conflict, res; |
2ec7df04 AC |
783 | res.start = ATA_PRIMARY_CMD; |
784 | res.end = ATA_PRIMARY_CMD + 8 - 1; | |
1fdffbce | 785 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
786 | while (conflict->child) |
787 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 788 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 789 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce | 790 | else { |
f0d36efd | 791 | pcim_pin_device(pdev); |
a64f97f2 JG |
792 | printk(KERN_WARNING "ata: 0x%0X IDE port busy\n" \ |
793 | "ata: conflict with %s\n", | |
794 | ATA_PRIMARY_CMD, | |
795 | conflict->name); | |
1fdffbce JG |
796 | } |
797 | } else | |
2ec7df04 | 798 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce | 799 | |
f0d36efd | 800 | if (!devm_request_region(dev, ATA_SECONDARY_CMD, 8, "libata")) { |
1fdffbce | 801 | struct resource *conflict, res; |
2ec7df04 AC |
802 | res.start = ATA_SECONDARY_CMD; |
803 | res.end = ATA_SECONDARY_CMD + 8 - 1; | |
1fdffbce | 804 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
805 | while (conflict->child) |
806 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 807 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 808 | legacy_mode |= ATA_PORT_SECONDARY; |
1fdffbce | 809 | else { |
f0d36efd | 810 | pcim_pin_device(pdev); |
a64f97f2 JG |
811 | printk(KERN_WARNING "ata: 0x%X IDE port busy\n" \ |
812 | "ata: conflict with %s\n", | |
813 | ATA_SECONDARY_CMD, | |
814 | conflict->name); | |
1fdffbce JG |
815 | } |
816 | } else | |
2ec7df04 | 817 | legacy_mode |= ATA_PORT_SECONDARY; |
dc3c3377 A |
818 | |
819 | if (legacy_mode & ATA_PORT_PRIMARY) | |
820 | pci_request_region(pdev, 1, DRV_NAME); | |
821 | if (legacy_mode & ATA_PORT_SECONDARY) | |
822 | pci_request_region(pdev, 3, DRV_NAME); | |
823 | /* If there is a DMA resource, allocate it */ | |
824 | pci_request_region(pdev, 4, DRV_NAME); | |
1fdffbce JG |
825 | } |
826 | ||
827 | /* we have legacy mode, but all ports are unavailable */ | |
828 | if (legacy_mode == (1 << 3)) { | |
829 | rc = -EBUSY; | |
f0d36efd | 830 | goto err_out; |
1fdffbce JG |
831 | } |
832 | ||
c791c306 | 833 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
1fdffbce JG |
834 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
835 | if (rc) | |
f0d36efd | 836 | goto err_out; |
1fdffbce JG |
837 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
838 | if (rc) | |
f0d36efd | 839 | goto err_out; |
1fdffbce JG |
840 | |
841 | if (legacy_mode) { | |
2ec7df04 | 842 | probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode); |
1fdffbce JG |
843 | } else { |
844 | if (n_ports == 2) | |
845 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); | |
846 | else | |
847 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY); | |
848 | } | |
2ec7df04 | 849 | if (!probe_ent) { |
1fdffbce | 850 | rc = -ENOMEM; |
f0d36efd | 851 | goto err_out; |
1fdffbce JG |
852 | } |
853 | ||
854 | pci_set_master(pdev); | |
855 | ||
c791c306 JG |
856 | if (!ata_device_add(probe_ent)) { |
857 | rc = -ENODEV; | |
f0d36efd | 858 | goto err_out; |
c791c306 | 859 | } |
1fdffbce | 860 | |
f0d36efd TH |
861 | devm_kfree(dev, probe_ent); |
862 | devres_remove_group(dev, NULL); | |
1fdffbce JG |
863 | return 0; |
864 | ||
1fdffbce | 865 | err_out: |
f0d36efd | 866 | devres_release_group(dev, NULL); |
1fdffbce JG |
867 | return rc; |
868 | } | |
869 | ||
d33d44fa AC |
870 | /** |
871 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
872 | * @pdev: PCI device | |
873 | * | |
874 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2e9edbf8 | 875 | * enter non simplex mode. This implements the neccessary logic to |
d33d44fa AC |
876 | * perform the task on such devices. Calling it on other devices will |
877 | * have -undefined- behaviour. | |
878 | */ | |
879 | ||
880 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
881 | { | |
882 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
883 | u8 simplex; | |
884 | ||
885 | if (bmdma == 0) | |
886 | return -ENOENT; | |
887 | ||
888 | simplex = inb(bmdma + 0x02); | |
889 | outb(simplex & 0x60, bmdma + 0x02); | |
890 | simplex = inb(bmdma + 0x02); | |
891 | if (simplex & 0x80) | |
892 | return -EOPNOTSUPP; | |
893 | return 0; | |
894 | } | |
895 | ||
896 | unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask) | |
897 | { | |
898 | /* Filter out DMA modes if the device has been configured by | |
899 | the BIOS as PIO only */ | |
2e9edbf8 | 900 | |
d33d44fa AC |
901 | if (ap->ioaddr.bmdma_addr == 0) |
902 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
903 | return xfer_mask; | |
904 | } | |
905 | ||
1fdffbce JG |
906 | #endif /* CONFIG_PCI */ |
907 |