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libata: reimplement ata_acpi_cbl_80wire() using ata_acpi_gtm_xfermask()
[deliverable/linux.git] / drivers / ata / pata_amd.c
CommitLineData
669a5db4
JG		 1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_amd"
943547ab 28#define DRV_VERSION "0.3.10"
669a5db4
JG		 29
30/**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45{
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
943547ab
BZ		 118 if (at.udma)
119 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
669a5db4
JG		 120}
121
122/**
cc0680a5
TH		 123 * amd_pre_reset - perform reset handling
124 * @link: ATA link
d4b2bab4 125 * @deadline: deadline jiffies for the operation
669a5db4 126 *
eb4a2c7f
AC		 127 * Reset sequence checking enable bits to see which ports are
128 * active.
669a5db4
JG		 129 */
130
cc0680a5 131static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 132{
669a5db4
JG		 133 static const struct pci_bits amd_enable_bits[] = {
134 { 0x40, 1, 0x02, 0x02 },
135 { 0x40, 1, 0x01, 0x01 }
136 };
137
cc0680a5 138 struct ata_port *ap = link->ap;
669a5db4 139 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251 140
c961922b
AC		 141 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
142 return -ENOENT;
669a5db4 143
cc0680a5 144 return ata_std_prereset(link, deadline);
669a5db4
JG		 145}
146
147static void amd_error_handler(struct ata_port *ap)
148{
149 return ata_bmdma_drive_eh(ap, amd_pre_reset,
150 ata_std_softreset, NULL,
151 ata_std_postreset);
152}
153
eb4a2c7f 154static int amd_cable_detect(struct ata_port *ap)
669a5db4 155{
eb4a2c7f 156 static const u32 bitmask[2] = {0x03, 0x0C};
669a5db4 157 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
eb4a2c7f 158 u8 ata66;
669a5db4 159
eb4a2c7f
AC		 160 pci_read_config_byte(pdev, 0x42, &ata66);
161 if (ata66 & bitmask[ap->port_no])
162 return ATA_CBL_PATA80;
163 return ATA_CBL_PATA40;
669a5db4
JG		 164}
165
166/**
167 * amd33_set_piomode - set initial PIO mode data
168 * @ap: ATA interface
169 * @adev: ATA device
170 *
171 * Program the AMD registers for PIO mode.
172 */
173
174static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
175{
176 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
177}
178
179static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
180{
181 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
182}
183
184static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
185{
186 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
187}
188
189static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
190{
191 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
192}
193
194/**
195 * amd33_set_dmamode - set initial DMA mode data
196 * @ap: ATA interface
197 * @adev: ATA device
198 *
199 * Program the MWDMA/UDMA modes for the AMD and Nvidia
200 * chipset.
201 */
202
203static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204{
205 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
206}
207
208static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
209{
210 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
211}
212
213static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
214{
215 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
216}
217
218static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
219{
220 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
221}
222
223
224/**
225 * nv_probe_init - cable detection
cc0680a5 226 * @lin: ATA link
669a5db4
JG		 227 *
228 * Perform cable detection. The BIOS stores this in PCI config
229 * space for us.
230 */
231
cc0680a5 232static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
d4b2bab4 233{
76ff3c6e
AC		 234 static const struct pci_bits nv_enable_bits[] = {
235 { 0x50, 1, 0x02, 0x02 },
236 { 0x50, 1, 0x01, 0x01 }
237 };
669a5db4 238
cc0680a5 239 struct ata_port *ap = link->ap;
669a5db4 240 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 241
c961922b
AC		 242 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
243 return -ENOENT;
76ff3c6e 244
cc0680a5 245 return ata_std_prereset(link, deadline);
669a5db4
JG		 246}
247
248static void nv_error_handler(struct ata_port *ap)
249{
250 ata_bmdma_drive_eh(ap, nv_pre_reset,
251 ata_std_softreset, NULL,
252 ata_std_postreset);
253}
eb4a2c7f
AC		 254
255static int nv_cable_detect(struct ata_port *ap)
256{
257 static const u8 bitmask[2] = {0x03, 0x0C};
258 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
259 u8 ata66;
260 u16 udma;
261 int cbl;
262
263 pci_read_config_byte(pdev, 0x52, &ata66);
264 if (ata66 & bitmask[ap->port_no])
265 cbl = ATA_CBL_PATA80;
266 else
267 cbl = ATA_CBL_PATA40;
268
269 /* We now have to double check because the Nvidia boxes BIOS
270 doesn't always set the cable bits but does set mode bits */
271 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
272 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
273 cbl = ATA_CBL_PATA80;
e708eb9b 274 /* And a triple check across suspend/resume with ACPI around */
021ee9a6
TH		 275 if (ata_acpi_init_gtm(ap) &&
276 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
e708eb9b 277 cbl = ATA_CBL_PATA80;
eb4a2c7f
AC		 278 return cbl;
279}
280
669a5db4
JG		 281/**
282 * nv100_set_piomode - set initial PIO mode data
283 * @ap: ATA interface
284 * @adev: ATA device
285 *
286 * Program the AMD registers for PIO mode.
287 */
288
289static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
290{
291 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
292}
293
294static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
295{
296 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
297}
298
299/**
300 * nv100_set_dmamode - set initial DMA mode data
301 * @ap: ATA interface
302 * @adev: ATA device
303 *
304 * Program the MWDMA/UDMA modes for the AMD and Nvidia
305 * chipset.
306 */
307
308static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
309{
310 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
311}
312
313static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
314{
315 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
316}
317
318static struct scsi_host_template amd_sht = {
319 .module = THIS_MODULE,
320 .name = DRV_NAME,
321 .ioctl = ata_scsi_ioctl,
322 .queuecommand = ata_scsi_queuecmd,
323 .can_queue = ATA_DEF_QUEUE,
324 .this_id = ATA_SHT_THIS_ID,
325 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 326 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
327 .emulated = ATA_SHT_EMULATED,
328 .use_clustering = ATA_SHT_USE_CLUSTERING,
329 .proc_name = DRV_NAME,
330 .dma_boundary = ATA_DMA_BOUNDARY,
331 .slave_configure = ata_scsi_slave_config,
afdfe899 332 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 333 .bios_param = ata_std_bios_param,
334};
335
336static struct ata_port_operations amd33_port_ops = {
669a5db4
JG		 337 .set_piomode = amd33_set_piomode,
338 .set_dmamode = amd33_set_dmamode,
339 .mode_filter = ata_pci_default_filter,
340 .tf_load = ata_tf_load,
341 .tf_read = ata_tf_read,
342 .check_status = ata_check_status,
343 .exec_command = ata_exec_command,
344 .dev_select = ata_std_dev_select,
345
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
eb4a2c7f 348 .error_handler = amd_error_handler,
669a5db4 349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 350 .cable_detect = ata_cable_40wire,
669a5db4
JG		 351
352 .bmdma_setup = ata_bmdma_setup,
353 .bmdma_start = ata_bmdma_start,
354 .bmdma_stop = ata_bmdma_stop,
355 .bmdma_status = ata_bmdma_status,
356
357 .qc_prep = ata_qc_prep,
358 .qc_issue = ata_qc_issue_prot,
bda30288 359
0d5ff566 360 .data_xfer = ata_data_xfer,
669a5db4
JG		 361
362 .irq_handler = ata_interrupt,
363 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 364 .irq_on = ata_irq_on,
669a5db4 365
81ad1837 366 .port_start = ata_sff_port_start,
669a5db4
JG		 367};
368
369static struct ata_port_operations amd66_port_ops = {
669a5db4
JG		 370 .set_piomode = amd66_set_piomode,
371 .set_dmamode = amd66_set_dmamode,
372 .mode_filter = ata_pci_default_filter,
373 .tf_load = ata_tf_load,
374 .tf_read = ata_tf_read,
375 .check_status = ata_check_status,
376 .exec_command = ata_exec_command,
377 .dev_select = ata_std_dev_select,
378
379 .freeze = ata_bmdma_freeze,
380 .thaw = ata_bmdma_thaw,
eb4a2c7f 381 .error_handler = amd_error_handler,
669a5db4 382 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 383 .cable_detect = ata_cable_unknown,
669a5db4
JG		 384
385 .bmdma_setup = ata_bmdma_setup,
386 .bmdma_start = ata_bmdma_start,
387 .bmdma_stop = ata_bmdma_stop,
388 .bmdma_status = ata_bmdma_status,
389
390 .qc_prep = ata_qc_prep,
391 .qc_issue = ata_qc_issue_prot,
bda30288 392
0d5ff566 393 .data_xfer = ata_data_xfer,
669a5db4
JG		 394
395 .irq_handler = ata_interrupt,
396 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 397 .irq_on = ata_irq_on,
669a5db4 398
81ad1837 399 .port_start = ata_sff_port_start,
669a5db4
JG		 400};
401
402static struct ata_port_operations amd100_port_ops = {
669a5db4
JG		 403 .set_piomode = amd100_set_piomode,
404 .set_dmamode = amd100_set_dmamode,
405 .mode_filter = ata_pci_default_filter,
406 .tf_load = ata_tf_load,
407 .tf_read = ata_tf_read,
408 .check_status = ata_check_status,
409 .exec_command = ata_exec_command,
410 .dev_select = ata_std_dev_select,
411
412 .freeze = ata_bmdma_freeze,
413 .thaw = ata_bmdma_thaw,
414 .error_handler = amd_error_handler,
415 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 416 .cable_detect = ata_cable_unknown,
669a5db4
JG		 417
418 .bmdma_setup = ata_bmdma_setup,
419 .bmdma_start = ata_bmdma_start,
420 .bmdma_stop = ata_bmdma_stop,
421 .bmdma_status = ata_bmdma_status,
422
423 .qc_prep = ata_qc_prep,
424 .qc_issue = ata_qc_issue_prot,
bda30288 425
0d5ff566 426 .data_xfer = ata_data_xfer,
669a5db4
JG		 427
428 .irq_handler = ata_interrupt,
429 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 430 .irq_on = ata_irq_on,
669a5db4 431
81ad1837 432 .port_start = ata_sff_port_start,
669a5db4
JG		 433};
434
435static struct ata_port_operations amd133_port_ops = {
669a5db4
JG		 436 .set_piomode = amd133_set_piomode,
437 .set_dmamode = amd133_set_dmamode,
438 .mode_filter = ata_pci_default_filter,
439 .tf_load = ata_tf_load,
440 .tf_read = ata_tf_read,
441 .check_status = ata_check_status,
442 .exec_command = ata_exec_command,
443 .dev_select = ata_std_dev_select,
444
445 .freeze = ata_bmdma_freeze,
446 .thaw = ata_bmdma_thaw,
447 .error_handler = amd_error_handler,
448 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 449 .cable_detect = amd_cable_detect,
669a5db4
JG		 450
451 .bmdma_setup = ata_bmdma_setup,
452 .bmdma_start = ata_bmdma_start,
453 .bmdma_stop = ata_bmdma_stop,
454 .bmdma_status = ata_bmdma_status,
455
456 .qc_prep = ata_qc_prep,
457 .qc_issue = ata_qc_issue_prot,
bda30288 458
0d5ff566 459 .data_xfer = ata_data_xfer,
669a5db4
JG		 460
461 .irq_handler = ata_interrupt,
462 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 463 .irq_on = ata_irq_on,
669a5db4 464
81ad1837 465 .port_start = ata_sff_port_start,
669a5db4
JG		 466};
467
468static struct ata_port_operations nv100_port_ops = {
669a5db4
JG		 469 .set_piomode = nv100_set_piomode,
470 .set_dmamode = nv100_set_dmamode,
471 .mode_filter = ata_pci_default_filter,
472 .tf_load = ata_tf_load,
473 .tf_read = ata_tf_read,
474 .check_status = ata_check_status,
475 .exec_command = ata_exec_command,
476 .dev_select = ata_std_dev_select,
477
478 .freeze = ata_bmdma_freeze,
479 .thaw = ata_bmdma_thaw,
480 .error_handler = nv_error_handler,
481 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 482 .cable_detect = nv_cable_detect,
669a5db4
JG		 483
484 .bmdma_setup = ata_bmdma_setup,
485 .bmdma_start = ata_bmdma_start,
486 .bmdma_stop = ata_bmdma_stop,
487 .bmdma_status = ata_bmdma_status,
488
489 .qc_prep = ata_qc_prep,
490 .qc_issue = ata_qc_issue_prot,
bda30288 491
0d5ff566 492 .data_xfer = ata_data_xfer,
669a5db4
JG		 493
494 .irq_handler = ata_interrupt,
495 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 496 .irq_on = ata_irq_on,
669a5db4 497
81ad1837 498 .port_start = ata_sff_port_start,
669a5db4
JG		 499};
500
501static struct ata_port_operations nv133_port_ops = {
669a5db4
JG		 502 .set_piomode = nv133_set_piomode,
503 .set_dmamode = nv133_set_dmamode,
504 .mode_filter = ata_pci_default_filter,
505 .tf_load = ata_tf_load,
506 .tf_read = ata_tf_read,
507 .check_status = ata_check_status,
508 .exec_command = ata_exec_command,
509 .dev_select = ata_std_dev_select,
510
511 .freeze = ata_bmdma_freeze,
512 .thaw = ata_bmdma_thaw,
513 .error_handler = nv_error_handler,
514 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 515 .cable_detect = nv_cable_detect,
669a5db4
JG		 516
517 .bmdma_setup = ata_bmdma_setup,
518 .bmdma_start = ata_bmdma_start,
519 .bmdma_stop = ata_bmdma_stop,
520 .bmdma_status = ata_bmdma_status,
521
522 .qc_prep = ata_qc_prep,
523 .qc_issue = ata_qc_issue_prot,
bda30288 524
0d5ff566 525 .data_xfer = ata_data_xfer,
669a5db4
JG		 526
527 .irq_handler = ata_interrupt,
528 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 529 .irq_on = ata_irq_on,
669a5db4 530
81ad1837 531 .port_start = ata_sff_port_start,
669a5db4
JG		 532};
533
534static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
535{
1626aeb8 536 static const struct ata_port_info info[10] = {
669a5db4
JG		 537 { /* 0: AMD 7401 */
538 .sht = &amd_sht,
1d2808fd 539 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 540 .pio_mask = 0x1f,
541 .mwdma_mask = 0x07, /* No SWDMA */
542 .udma_mask = 0x07, /* UDMA 33 */
543 .port_ops = &amd33_port_ops
544 },
545 { /* 1: Early AMD7409 - no swdma */
546 .sht = &amd_sht,
1d2808fd 547 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 548 .pio_mask = 0x1f,
549 .mwdma_mask = 0x07,
bf6263a8 550 .udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4
JG		 551 .port_ops = &amd66_port_ops
552 },
553 { /* 2: AMD 7409, no swdma errata */
554 .sht = &amd_sht,
1d2808fd 555 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 556 .pio_mask = 0x1f,
557 .mwdma_mask = 0x07,
bf6263a8 558 .udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4
JG		 559 .port_ops = &amd66_port_ops
560 },
561 { /* 3: AMD 7411 */
562 .sht = &amd_sht,
1d2808fd 563 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 564 .pio_mask = 0x1f,
565 .mwdma_mask = 0x07,
bf6263a8 566 .udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4
JG		 567 .port_ops = &amd100_port_ops
568 },
569 { /* 4: AMD 7441 */
570 .sht = &amd_sht,
1d2808fd 571 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 572 .pio_mask = 0x1f,
573 .mwdma_mask = 0x07,
bf6263a8 574 .udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4
JG		 575 .port_ops = &amd100_port_ops
576 },
577 { /* 5: AMD 8111*/
578 .sht = &amd_sht,
1d2808fd 579 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 580 .pio_mask = 0x1f,
581 .mwdma_mask = 0x07,
bf6263a8 582 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4
JG		 583 .port_ops = &amd133_port_ops
584 },
585 { /* 6: AMD 8111 UDMA 100 (Serenade) */
586 .sht = &amd_sht,
1d2808fd 587 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 588 .pio_mask = 0x1f,
589 .mwdma_mask = 0x07,
bf6263a8 590 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
669a5db4
JG		 591 .port_ops = &amd133_port_ops
592 },
593 { /* 7: Nvidia Nforce */
594 .sht = &amd_sht,
1d2808fd 595 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 596 .pio_mask = 0x1f,
597 .mwdma_mask = 0x07,
bf6263a8 598 .udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4
JG		 599 .port_ops = &nv100_port_ops
600 },
601 { /* 8: Nvidia Nforce2 and later */
602 .sht = &amd_sht,
1d2808fd 603 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 604 .pio_mask = 0x1f,
605 .mwdma_mask = 0x07,
bf6263a8 606 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4
JG		 607 .port_ops = &nv133_port_ops
608 },
609 { /* 9: AMD CS5536 (Geode companion) */
610 .sht = &amd_sht,
1d2808fd 611 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 612 .pio_mask = 0x1f,
613 .mwdma_mask = 0x07,
bf6263a8 614 .udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4
JG		 615 .port_ops = &amd100_port_ops
616 }
617 };
1626aeb8 618 const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4
JG		 619 static int printed_version;
620 int type = id->driver_data;
669a5db4
JG		 621 u8 fifo;
622
623 if (!printed_version++)
624 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
625
669a5db4
JG		 626 pci_read_config_byte(pdev, 0x41, &fifo);
627
628 /* Check for AMD7409 without swdma errata and if found adjust type */
44c10138 629 if (type == 1 && pdev->revision > 0x7)
669a5db4
JG		 630 type = 2;
631
632 /* Check for AMD7411 */
633 if (type == 3)
634 /* FIFO is broken */
635 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
636 else
637 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
638
639 /* Serenade ? */
640 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
641 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
642 type = 6; /* UDMA 100 only */
643
644 if (type < 3)
645 ata_pci_clear_simplex(pdev);
646
647 /* And fire it up */
1626aeb8
TH		 648 ppi[0] = &info[type];
649 return ata_pci_init_one(pdev, ppi);
669a5db4
JG		 650}
651
438ac6d5 652#ifdef CONFIG_PM
c304193a
A		 653static int amd_reinit_one(struct pci_dev *pdev)
654{
655 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
656 u8 fifo;
657 pci_read_config_byte(pdev, 0x41, &fifo);
658 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
659 /* FIFO is broken */
660 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
661 else
662 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
663 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
664 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
665 ata_pci_clear_simplex(pdev);
666 }
667 return ata_pci_device_resume(pdev);
668}
438ac6d5 669#endif
c304193a 670
669a5db4 671static const struct pci_device_id amd[] = {
2d2744fc
JG		 672 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
673 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
674 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
675 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
676 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
677 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
678 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
679 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
680 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
681 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
682 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
683 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
684 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
685 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
686 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a
PC		 687 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
688 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
9f789755
PC		 689 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
2d2744fc
JG		 691 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
692
693 { },
669a5db4
JG		 694};
695
696static struct pci_driver amd_pci_driver = {
2d2744fc 697 .name = DRV_NAME,
669a5db4
JG		 698 .id_table = amd,
699 .probe = amd_init_one,
c304193a 700 .remove = ata_pci_remove_one,
438ac6d5 701#ifdef CONFIG_PM
c304193a
A		 702 .suspend = ata_pci_device_suspend,
703 .resume = amd_reinit_one,
438ac6d5 704#endif
669a5db4
JG		 705};
706
707static int __init amd_init(void)
708{
709 return pci_register_driver(&amd_pci_driver);
710}
711
712static void __exit amd_exit(void)
713{
714 pci_unregister_driver(&amd_pci_driver);
715}
716
669a5db4
JG		 717MODULE_AUTHOR("Alan Cox");
718MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
719MODULE_LICENSE("GPL");
720MODULE_DEVICE_TABLE(pci, amd);
721MODULE_VERSION(DRV_VERSION);
722
723module_init(amd_init);
724module_exit(amd_exit);
Linux kernel - Deliverables
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