[deliverable/linux.git] / drivers / ata / pata_amd.c

/*
 * pata_amd.c 	- AMD PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *  Based on pata-sil680. Errata information is taken from data sheets
 *  and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
 *  claimed by sata-nv.c.
 *
 *  TODO:
 *	Variable system clock when/if it makes sense
 *	Power management on ports
 *
 *
 *  Documentation publically available.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_amd"
#define DRV_VERSION "0.3.10"

/**
 *	timing_setup		-	shared timing computation and load
 *	@ap: ATA port being set up
 *	@adev: drive being configured
 *	@offset: port offset
 *	@speed: target speed
 *	@clock: clock multiplier (number of times 33MHz for this part)
 *
 *	Perform the actual timing set up for Nvidia or AMD PATA devices.
 *	The actual devices vary so they all call into this helper function
 *	providing the clock multipler and offset (because AMD and Nvidia put
 *	the ports at different locations).
 */

static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
{
	static const unsigned char amd_cyc2udma[] = {
		6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	int dn = ap->port_no * 2 + adev->devno;
	struct ata_timing at, apeer;
	int T, UT;
	const int amd_clock = 33333;	/* KHz. */
	u8 t;

	T = 1000000000 / amd_clock;
	UT = T;
	if (clock >= 2)
		UT = T / 2;

	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
		dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
		return;
	}

	if (peer) {
		/* This may be over conservative */
		if (peer->dma_mode) {
			ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
			ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
		}
		ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
		ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;

	/*
	 *	Now do the setup work
	 */

	/* Configure the address set up timing */
	pci_read_config_byte(pdev, offset + 0x0C, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(pdev, offset + 0x0C , t);

	/* Configure the 8bit I/O timing */
	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
		((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));

	/* Drive timing */
	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
		((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));

	switch (clock) {
		case 1:
		t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
		break;

		case 2:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
		break;

		case 3:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
		break;

		case 4:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
		break;

		default:
			return;
	}

	/* UDMA timing */
	if (at.udma)
		pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
}

/**
 *	amd_pre_reset		-	perform reset handling
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Reset sequence checking enable bits to see which ports are
 *	active.
 */

static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits amd_enable_bits[] = {
		{ 0x40, 1, 0x02, 0x02 },
		{ 0x40, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

static int amd_cable_detect(struct ata_port *ap)
{
	static const u32 bitmask[2] = {0x03, 0x0C};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	pci_read_config_byte(pdev, 0x42, &ata66);
	if (ata66 & bitmask[ap->port_no])
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	amd33_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
}

static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
}

static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
}

static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
}

/**
 *	amd33_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
}

static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
}

static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
}

static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
}

/* Both host-side and drive-side detection results are worthless on NV
 * PATAs.  Ignore them and just follow what BIOS configured.  Both the
 * current configuration in PCI config reg and ACPI GTM result are
 * cached during driver attach and are consulted to select transfer
 * mode.
 */
static unsigned long nv_mode_filter(struct ata_device *dev,
				    unsigned long xfer_mask)
{
	static const unsigned int udma_mask_map[] =
		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
		  ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	struct ata_port *ap = dev->link->ap;
	char acpi_str[32] = "";
	u32 saved_udma, udma;
	const struct ata_acpi_gtm *gtm;
	unsigned long bios_limit = 0, acpi_limit = 0, limit;

	/* find out what BIOS configured */
	udma = saved_udma = (unsigned long)ap->host->private_data;

	if (ap->port_no == 0)
		udma >>= 16;
	if (dev->devno == 0)
		udma >>= 8;

	if ((udma & 0xc0) == 0xc0)
		bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);

	/* consult ACPI GTM too */
	gtm = ata_acpi_init_gtm(ap);
	if (gtm) {
		acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);

		snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
			 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	}

	/* be optimistic, EH can take care of things if something goes wrong */
	limit = bios_limit | acpi_limit;

	/* If PIO or DMA isn't configured at all, don't limit.  Let EH
	 * handle it.
	 */
	if (!(limit & ATA_MASK_PIO))
		limit |= ATA_MASK_PIO;
	if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
		limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;

	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
			xfer_mask, limit, xfer_mask & limit, bios_limit,
			saved_udma, acpi_limit, acpi_str);

	return xfer_mask & limit;
}

/**
 *	nv_probe_init	-	cable detection
 *	@lin: ATA link
 *
 *	Perform cable detection. The BIOS stores this in PCI config
 *	space for us.
 */

static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits nv_enable_bits[] = {
		{ 0x50, 1, 0x02, 0x02 },
		{ 0x50, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	nv100_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
}

static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
}

/**
 *	nv100_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
}

static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
}

static void nv_host_stop(struct ata_host *host)
{
	u32 udma = (unsigned long)host->private_data;

	/* restore PCI config register 0x60 */
	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
}

static struct scsi_host_template amd_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations amd_base_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.prereset	= amd_pre_reset,
};

static struct ata_port_operations amd33_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= amd33_set_piomode,
	.set_dmamode	= amd33_set_dmamode,
};

static struct ata_port_operations amd66_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd66_set_piomode,
	.set_dmamode	= amd66_set_dmamode,
};

static struct ata_port_operations amd100_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd100_set_piomode,
	.set_dmamode	= amd100_set_dmamode,
};

static struct ata_port_operations amd133_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= amd_cable_detect,
	.set_piomode	= amd133_set_piomode,
	.set_dmamode	= amd133_set_dmamode,
};

static const struct ata_port_operations nv_base_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= ata_cable_ignore,
	.mode_filter	= nv_mode_filter,
	.prereset	= nv_pre_reset,
	.host_stop	= nv_host_stop,
};

static struct ata_port_operations nv100_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv100_set_piomode,
	.set_dmamode	= nv100_set_dmamode,
};

static struct ata_port_operations nv133_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv133_set_piomode,
	.set_dmamode	= nv133_set_dmamode,
};

static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[10] = {
		{	/* 0: AMD 7401 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,	/* No SWDMA */
			.udma_mask = 0x07,	/* UDMA 33 */
			.port_ops = &amd33_port_ops
		},
		{	/* 1: Early AMD7409 - no swdma */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 2: AMD 7409, no swdma errata */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 3: AMD 7411 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 4: AMD 7441 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 5: AMD 8111*/
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 6: AMD 8111 UDMA 100 (Serenade) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 7: Nvidia Nforce */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &nv100_port_ops
		},
		{	/* 8: Nvidia Nforce2 and later */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &nv133_port_ops
		},
		{	/* 9: AMD CS5536 (Geode companion) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	static int printed_version;
	int type = id->driver_data;
	void *hpriv = NULL;
	u8 fifo;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	pci_read_config_byte(pdev, 0x41, &fifo);

	/* Check for AMD7409 without swdma errata and if found adjust type */
	if (type == 1 && pdev->revision > 0x7)
		type = 2;

	/* Serenade ? */
	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
			 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
		type = 6;	/* UDMA 100 only */

	/*
	 * Okay, type is determined now.  Apply type-specific workarounds.
	 */
	ppi[0] = &info[type];

	if (type < 3)
		ata_pci_bmdma_clear_simplex(pdev);

	/* Check for AMD7411 */
	if (type == 3)
		/* FIFO is broken */
		pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	else
		pci_write_config_byte(pdev, 0x41, fifo | 0xF0);

	/* Cable detection on Nvidia chips doesn't work too well,
	 * cache BIOS programmed UDMA mode.
	 */
	if (type == 7 || type == 8) {
		u32 udma;

		pci_read_config_dword(pdev, 0x60, &udma);
		hpriv = (void *)(unsigned long)udma;
	}

	/* And fire it up */
	return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
}

#ifdef CONFIG_PM
static int amd_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
		u8 fifo;
		pci_read_config_byte(pdev, 0x41, &fifo);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
			/* FIFO is broken */
			pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
		else
			pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
		    pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
			ata_pci_bmdma_clear_simplex(pdev);
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id amd[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		4 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	7 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	8 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		9 },

	{ },
};

static struct pci_driver amd_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= amd,
	.probe 		= amd_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= amd_reinit_one,
#endif
};

static int __init amd_init(void)
{
	return pci_register_driver(&amd_pci_driver);
}

static void __exit amd_exit(void)
{
	pci_unregister_driver(&amd_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, amd);
MODULE_VERSION(DRV_VERSION);

module_init(amd_init);
module_exit(amd_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_amd.c - AMD PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based on pata-sil680. Errata information is taken from data sheets
	7	* and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
	8	* claimed by sata-nv.c.
	9	*
	10	* TODO:
	11	* Variable system clock when/if it makes sense
	12	* Power management on ports
	13	*
	14	*
	15	* Documentation publically available.
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "pata_amd"
943547ab	28	#define DRV_VERSION "0.3.10"
669a5db4 JG	29
	30	/**
	31	* timing_setup - shared timing computation and load
	32	* @ap: ATA port being set up
	33	* @adev: drive being configured
	34	* @offset: port offset
	35	* @speed: target speed
	36	* @clock: clock multiplier (number of times 33MHz for this part)
	37	*
	38	* Perform the actual timing set up for Nvidia or AMD PATA devices.
	39	* The actual devices vary so they all call into this helper function
	40	* providing the clock multipler and offset (because AMD and Nvidia put
	41	* the ports at different locations).
	42	*/
	43
	44	static void timing_setup(struct ata_port ap, struct ata_device adev, int offset, int speed, int clock)
	45	{
	46	static const unsigned char amd_cyc2udma[] = {
	47	6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	48	};
	49
	50	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	51	struct ata_device *peer = ata_dev_pair(adev);
	52	int dn = ap->port_no * 2 + adev->devno;
	53	struct ata_timing at, apeer;
	54	int T, UT;
	55	const int amd_clock = 33333; /* KHz. */
	56	u8 t;
	57
	58	T = 1000000000 / amd_clock;
d9c74fbe HH	59	UT = T;
	60	if (clock >= 2)
	61	UT = T / 2;
669a5db4 JG	62
	63	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
	64	dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
	65	return;
	66	}
	67
	68	if (peer) {
	69	/* This may be over conservative */
	70	if (peer->dma_mode) {
	71	ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
	72	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	73	}
	74	ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
	75	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	76	}
	77
	78	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	79	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
	80
	81	/*
	82	* Now do the setup work
	83	*/
	84
	85	/* Configure the address set up timing */
	86	pci_read_config_byte(pdev, offset + 0x0C, &t);
	87	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
	88	pci_write_config_byte(pdev, offset + 0x0C , t);
	89
	90	/* Configure the 8bit I/O timing */
	91	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
	92	((FIT(at.act8b, 1, 16) - 1) << 4) \| (FIT(at.rec8b, 1, 16) - 1));
	93
	94	/* Drive timing */
	95	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
	96	((FIT(at.active, 1, 16) - 1) << 4) \| (FIT(at.recover, 1, 16) - 1));
	97
	98	switch (clock) {
	99	case 1:
	100	t = at.udma ? (0xc0 \| (FIT(at.udma, 2, 5) - 2)) : 0x03;
	101	break;
	102
	103	case 2:
	104	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
	105	break;
	106
	107	case 3:
	108	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
	109	break;
	110
	111	case 4:
	112	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
	113	break;
	114
	115	default:
	116	return;
	117	}
	118
	119	/* UDMA timing */
943547ab BZ	120	if (at.udma)
943547ab BZ	121	pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
669a5db4 JG	122	}
	123
	124	/**
cc0680a5 TH	125	* amd_pre_reset - perform reset handling
cc0680a5 TH	126	* @link: ATA link
d4b2bab4	127	* @deadline: deadline jiffies for the operation
669a5db4	128	*
eb4a2c7f AC	129	* Reset sequence checking enable bits to see which ports are
eb4a2c7f AC	130	* active.
669a5db4 JG	131	*/
669a5db4 JG	132
cc0680a5	133	static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	134	{
669a5db4 JG	135	static const struct pci_bits amd_enable_bits[] = {
	136	{ 0x40, 1, 0x02, 0x02 },
	137	{ 0x40, 1, 0x01, 0x01 }
	138	};
	139
cc0680a5	140	struct ata_port *ap = link->ap;
669a5db4	141	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	142
c961922b AC	143	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
c961922b AC	144	return -ENOENT;
669a5db4	145
9363c382	146	return ata_sff_prereset(link, deadline);
669a5db4 JG	147	}
669a5db4 JG	148
eb4a2c7f	149	static int amd_cable_detect(struct ata_port *ap)
669a5db4	150	{
eb4a2c7f	151	static const u32 bitmask[2] = {0x03, 0x0C};
669a5db4	152	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
eb4a2c7f	153	u8 ata66;
669a5db4	154
eb4a2c7f AC	155	pci_read_config_byte(pdev, 0x42, &ata66);
	156	if (ata66 & bitmask[ap->port_no])
	157	return ATA_CBL_PATA80;
	158	return ATA_CBL_PATA40;
669a5db4 JG	159	}
	160
	161	/**
	162	* amd33_set_piomode - set initial PIO mode data
	163	* @ap: ATA interface
	164	* @adev: ATA device
	165	*
	166	* Program the AMD registers for PIO mode.
	167	*/
	168
	169	static void amd33_set_piomode(struct ata_port ap, struct ata_device adev)
	170	{
	171	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
	172	}
	173
	174	static void amd66_set_piomode(struct ata_port ap, struct ata_device adev)
	175	{
	176	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
	177	}
	178
	179	static void amd100_set_piomode(struct ata_port ap, struct ata_device adev)
	180	{
	181	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
	182	}
	183
	184	static void amd133_set_piomode(struct ata_port ap, struct ata_device adev)
	185	{
	186	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
	187	}
	188
	189	/**
	190	* amd33_set_dmamode - set initial DMA mode data
	191	* @ap: ATA interface
	192	* @adev: ATA device
	193	*
	194	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	195	* chipset.
	196	*/
	197
	198	static void amd33_set_dmamode(struct ata_port ap, struct ata_device adev)
	199	{
	200	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
	201	}
	202
	203	static void amd66_set_dmamode(struct ata_port ap, struct ata_device adev)
	204	{
	205	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
	206	}
	207
	208	static void amd100_set_dmamode(struct ata_port ap, struct ata_device adev)
	209	{
	210	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
	211	}
	212
	213	static void amd133_set_dmamode(struct ata_port ap, struct ata_device adev)
	214	{
	215	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
	216	}
	217
ce54d161 TH	218	/* Both host-side and drive-side detection results are worthless on NV
	219	* PATAs. Ignore them and just follow what BIOS configured. Both the
	220	* current configuration in PCI config reg and ACPI GTM result are
	221	* cached during driver attach and are consulted to select transfer
	222	* mode.
	223	*/
	224	static unsigned long nv_mode_filter(struct ata_device *dev,
	225	unsigned long xfer_mask)
	226	{
	227	static const unsigned int udma_mask_map[] =
	228	{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
	229	ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	230	struct ata_port *ap = dev->link->ap;
	231	char acpi_str[32] = "";
	232	u32 saved_udma, udma;
	233	const struct ata_acpi_gtm *gtm;
	234	unsigned long bios_limit = 0, acpi_limit = 0, limit;
	235
	236	/* find out what BIOS configured */
	237	udma = saved_udma = (unsigned long)ap->host->private_data;
	238
	239	if (ap->port_no == 0)
	240	udma >>= 16;
	241	if (dev->devno == 0)
	242	udma >>= 8;
	243
	244	if ((udma & 0xc0) == 0xc0)
	245	bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
	246
	247	/* consult ACPI GTM too */
	248	gtm = ata_acpi_init_gtm(ap);
	249	if (gtm) {
	250	acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
	251
	252	snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
	253	gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	254	}
	255
	256	/* be optimistic, EH can take care of things if something goes wrong */
	257	limit = bios_limit \| acpi_limit;
	258
	259	/* If PIO or DMA isn't configured at all, don't limit. Let EH
	260	* handle it.
	261	*/
	262	if (!(limit & ATA_MASK_PIO))
	263	limit \|= ATA_MASK_PIO;
	264	if (!(limit & (ATA_MASK_MWDMA \| ATA_MASK_UDMA)))
	265	limit \|= ATA_MASK_MWDMA \| ATA_MASK_UDMA;
	266
	267	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
	268	"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
	269	xfer_mask, limit, xfer_mask & limit, bios_limit,
	270	saved_udma, acpi_limit, acpi_str);
	271
	272	return xfer_mask & limit;
	273	}
669a5db4 JG	274
	275	/**
	276	* nv_probe_init - cable detection
cc0680a5	277	* @lin: ATA link
669a5db4 JG	278	*
	279	* Perform cable detection. The BIOS stores this in PCI config
	280	* space for us.
	281	*/
	282
cc0680a5	283	static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
d4b2bab4	284	{
76ff3c6e AC	285	static const struct pci_bits nv_enable_bits[] = {
	286	{ 0x50, 1, 0x02, 0x02 },
	287	{ 0x50, 1, 0x01, 0x01 }
	288	};
669a5db4	289
cc0680a5	290	struct ata_port *ap = link->ap;
669a5db4	291	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	292
c961922b AC	293	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
c961922b AC	294	return -ENOENT;
76ff3c6e	295
9363c382	296	return ata_sff_prereset(link, deadline);
669a5db4 JG	297	}
669a5db4 JG	298
669a5db4 JG	299	/**
	300	* nv100_set_piomode - set initial PIO mode data
	301	* @ap: ATA interface
	302	* @adev: ATA device
	303	*
	304	* Program the AMD registers for PIO mode.
	305	*/
	306
	307	static void nv100_set_piomode(struct ata_port ap, struct ata_device adev)
	308	{
	309	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
	310	}
	311
	312	static void nv133_set_piomode(struct ata_port ap, struct ata_device adev)
	313	{
	314	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
	315	}
	316
	317	/**
	318	* nv100_set_dmamode - set initial DMA mode data
	319	* @ap: ATA interface
	320	* @adev: ATA device
	321	*
	322	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	323	* chipset.
	324	*/
	325
	326	static void nv100_set_dmamode(struct ata_port ap, struct ata_device adev)
	327	{
	328	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
	329	}
	330
	331	static void nv133_set_dmamode(struct ata_port ap, struct ata_device adev)
	332	{
	333	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
	334	}
	335
ce54d161 TH	336	static void nv_host_stop(struct ata_host *host)
	337	{
	338	u32 udma = (unsigned long)host->private_data;
	339
	340	/* restore PCI config register 0x60 */
	341	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
	342	}
	343
669a5db4	344	static struct scsi_host_template amd_sht = {
68d1d07b	345	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	346	};
669a5db4 JG	347
029cfd6b TH	348	static const struct ata_port_operations amd_base_port_ops = {
029cfd6b TH	349	.inherits = &ata_bmdma_port_ops,
887125e3	350	.prereset = amd_pre_reset,
029cfd6b TH	351	};
029cfd6b TH	352
669a5db4	353	static struct ata_port_operations amd33_port_ops = {
029cfd6b TH	354	.inherits = &amd_base_port_ops,
029cfd6b TH	355	.cable_detect = ata_cable_40wire,
669a5db4 JG	356	.set_piomode = amd33_set_piomode,
669a5db4 JG	357	.set_dmamode = amd33_set_dmamode,
669a5db4 JG	358	};
	359
	360	static struct ata_port_operations amd66_port_ops = {
029cfd6b TH	361	.inherits = &amd_base_port_ops,
029cfd6b TH	362	.cable_detect = ata_cable_unknown,
669a5db4 JG	363	.set_piomode = amd66_set_piomode,
669a5db4 JG	364	.set_dmamode = amd66_set_dmamode,
669a5db4 JG	365	};
	366
	367	static struct ata_port_operations amd100_port_ops = {
029cfd6b TH	368	.inherits = &amd_base_port_ops,
029cfd6b TH	369	.cable_detect = ata_cable_unknown,
669a5db4 JG	370	.set_piomode = amd100_set_piomode,
669a5db4 JG	371	.set_dmamode = amd100_set_dmamode,
669a5db4 JG	372	};
	373
	374	static struct ata_port_operations amd133_port_ops = {
029cfd6b TH	375	.inherits = &amd_base_port_ops,
029cfd6b TH	376	.cable_detect = amd_cable_detect,
669a5db4 JG	377	.set_piomode = amd133_set_piomode,
669a5db4 JG	378	.set_dmamode = amd133_set_dmamode,
029cfd6b	379	};
669a5db4	380
029cfd6b TH	381	static const struct ata_port_operations nv_base_port_ops = {
	382	.inherits = &ata_bmdma_port_ops,
	383	.cable_detect = ata_cable_ignore,
	384	.mode_filter = nv_mode_filter,
887125e3	385	.prereset = nv_pre_reset,
029cfd6b	386	.host_stop = nv_host_stop,
669a5db4 JG	387	};
	388
	389	static struct ata_port_operations nv100_port_ops = {
029cfd6b	390	.inherits = &nv_base_port_ops,
669a5db4 JG	391	.set_piomode = nv100_set_piomode,
669a5db4 JG	392	.set_dmamode = nv100_set_dmamode,
669a5db4 JG	393	};
	394
	395	static struct ata_port_operations nv133_port_ops = {
029cfd6b	396	.inherits = &nv_base_port_ops,
669a5db4 JG	397	.set_piomode = nv133_set_piomode,
669a5db4 JG	398	.set_dmamode = nv133_set_dmamode,
669a5db4 JG	399	};
	400
	401	static int amd_init_one(struct pci_dev pdev, const struct pci_device_id id)
	402	{
1626aeb8	403	static const struct ata_port_info info[10] = {
669a5db4	404	{ /* 0: AMD 7401 */
1d2808fd	405	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	406	.pio_mask = 0x1f,
	407	.mwdma_mask = 0x07, /* No SWDMA */
	408	.udma_mask = 0x07, /* UDMA 33 */
	409	.port_ops = &amd33_port_ops
	410	},
	411	{ /* 1: Early AMD7409 - no swdma */
1d2808fd	412	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	413	.pio_mask = 0x1f,
669a5db4 JG	414	.mwdma_mask = 0x07,
bf6263a8	415	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	416	.port_ops = &amd66_port_ops
	417	},
	418	{ /* 2: AMD 7409, no swdma errata */
1d2808fd	419	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	420	.pio_mask = 0x1f,
669a5db4 JG	421	.mwdma_mask = 0x07,
bf6263a8	422	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	423	.port_ops = &amd66_port_ops
	424	},
	425	{ /* 3: AMD 7411 */
1d2808fd	426	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	427	.pio_mask = 0x1f,
669a5db4 JG	428	.mwdma_mask = 0x07,
bf6263a8	429	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	430	.port_ops = &amd100_port_ops
	431	},
	432	{ /* 4: AMD 7441 */
1d2808fd	433	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	434	.pio_mask = 0x1f,
669a5db4 JG	435	.mwdma_mask = 0x07,
bf6263a8	436	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	437	.port_ops = &amd100_port_ops
	438	},
	439	{ /* 5: AMD 8111*/
1d2808fd	440	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	441	.pio_mask = 0x1f,
669a5db4 JG	442	.mwdma_mask = 0x07,
bf6263a8	443	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	444	.port_ops = &amd133_port_ops
	445	},
	446	{ /* 6: AMD 8111 UDMA 100 (Serenade) */
1d2808fd	447	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	448	.pio_mask = 0x1f,
669a5db4 JG	449	.mwdma_mask = 0x07,
bf6263a8	450	.udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
669a5db4 JG	451	.port_ops = &amd133_port_ops
	452	},
	453	{ /* 7: Nvidia Nforce */
1d2808fd	454	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	455	.pio_mask = 0x1f,
669a5db4 JG	456	.mwdma_mask = 0x07,
bf6263a8	457	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	458	.port_ops = &nv100_port_ops
	459	},
	460	{ /* 8: Nvidia Nforce2 and later */
1d2808fd	461	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	462	.pio_mask = 0x1f,
669a5db4 JG	463	.mwdma_mask = 0x07,
bf6263a8	464	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	465	.port_ops = &nv133_port_ops
	466	},
	467	{ /* 9: AMD CS5536 (Geode companion) */
1d2808fd	468	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	469	.pio_mask = 0x1f,
669a5db4 JG	470	.mwdma_mask = 0x07,
bf6263a8	471	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	472	.port_ops = &amd100_port_ops
	473	}
	474	};
887125e3	475	const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 JG	476	static int printed_version;
669a5db4 JG	477	int type = id->driver_data;
887125e3	478	void *hpriv = NULL;
669a5db4	479	u8 fifo;
f08048e9	480	int rc;
669a5db4 JG	481
	482	if (!printed_version++)
	483	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	484
f08048e9 TH	485	rc = pcim_enable_device(pdev);
	486	if (rc)
	487	return rc;
	488
669a5db4 JG	489	pci_read_config_byte(pdev, 0x41, &fifo);
	490
	491	/* Check for AMD7409 without swdma errata and if found adjust type */
44c10138	492	if (type == 1 && pdev->revision > 0x7)
669a5db4 JG	493	type = 2;
669a5db4 JG	494
ce54d161 TH	495	/* Serenade ? */
	496	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	497	pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	498	type = 6; /* UDMA 100 only */
	499
	500	/*
	501	* Okay, type is determined now. Apply type-specific workarounds.
	502	*/
887125e3	503	ppi[0] = &info[type];
ce54d161 TH	504
ce54d161 TH	505	if (type < 3)
9363c382	506	ata_pci_bmdma_clear_simplex(pdev);
ce54d161	507
669a5db4 JG	508	/* Check for AMD7411 */
	509	if (type == 3)
	510	/* FIFO is broken */
	511	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	512	else
	513	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	514
ce54d161 TH	515	/* Cable detection on Nvidia chips doesn't work too well,
	516	* cache BIOS programmed UDMA mode.
	517	*/
	518	if (type == 7 \|\| type == 8) {
	519	u32 udma;
669a5db4	520
ce54d161	521	pci_read_config_dword(pdev, 0x60, &udma);
887125e3	522	hpriv = (void *)(unsigned long)udma;
ce54d161	523	}
669a5db4 JG	524
669a5db4 JG	525	/* And fire it up */
9363c382	526	return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
669a5db4 JG	527	}
669a5db4 JG	528
438ac6d5	529	#ifdef CONFIG_PM
c304193a A	530	static int amd_reinit_one(struct pci_dev *pdev)
c304193a A	531	{
f08048e9 TH	532	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	533	int rc;
	534
	535	rc = ata_pci_device_do_resume(pdev);
	536	if (rc)
	537	return rc;
	538
c304193a A	539	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
	540	u8 fifo;
	541	pci_read_config_byte(pdev, 0x41, &fifo);
	542	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
	543	/* FIFO is broken */
	544	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	545	else
	546	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	547	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 \|\|
	548	pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
9363c382	549	ata_pci_bmdma_clear_simplex(pdev);
c304193a	550	}
f08048e9 TH	551
	552	ata_host_resume(host);
	553	return 0;
c304193a	554	}
438ac6d5	555	#endif
c304193a	556
669a5db4	557	static const struct pci_device_id amd[] = {
2d2744fc JG	558	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	559	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	560	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
	561	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
	562	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
	563	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
	564	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
	565	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
	566	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
	567	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
	568	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
	569	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
	570	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
	571	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
	572	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a PC	573	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
05e2867a PC	574	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
9f789755 PC	575	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
9f789755 PC	576	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
2d2744fc JG	577	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
	578
	579	{ },
669a5db4 JG	580	};
	581
	582	static struct pci_driver amd_pci_driver = {
2d2744fc	583	.name = DRV_NAME,
669a5db4 JG	584	.id_table = amd,
669a5db4 JG	585	.probe = amd_init_one,
c304193a	586	.remove = ata_pci_remove_one,
438ac6d5	587	#ifdef CONFIG_PM
c304193a A	588	.suspend = ata_pci_device_suspend,
c304193a A	589	.resume = amd_reinit_one,
438ac6d5	590	#endif
669a5db4 JG	591	};
	592
	593	static int __init amd_init(void)
	594	{
	595	return pci_register_driver(&amd_pci_driver);
	596	}
	597
	598	static void __exit amd_exit(void)
	599	{
	600	pci_unregister_driver(&amd_pci_driver);
	601	}
	602
669a5db4	603	MODULE_AUTHOR("Alan Cox");
c9544bcb	604	MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
669a5db4 JG	605	MODULE_LICENSE("GPL");
	606	MODULE_DEVICE_TABLE(pci, amd);
	607	MODULE_VERSION(DRV_VERSION);
	608
	609	module_init(amd_init);
	610	module_exit(amd_exit);