[deliverable/linux.git] / drivers / ata / pata_amd.c

/*
 * pata_amd.c 	- AMD PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *  Based on pata-sil680. Errata information is taken from data sheets
 *  and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
 *  claimed by sata-nv.c.
 *
 *  TODO:
 *	Variable system clock when/if it makes sense
 *	Power management on ports
 *
 *
 *  Documentation publically available.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_amd"
#define DRV_VERSION "0.3.10"

/**
 *	timing_setup		-	shared timing computation and load
 *	@ap: ATA port being set up
 *	@adev: drive being configured
 *	@offset: port offset
 *	@speed: target speed
 *	@clock: clock multiplier (number of times 33MHz for this part)
 *
 *	Perform the actual timing set up for Nvidia or AMD PATA devices.
 *	The actual devices vary so they all call into this helper function
 *	providing the clock multipler and offset (because AMD and Nvidia put
 *	the ports at different locations).
 */

static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
{
	static const unsigned char amd_cyc2udma[] = {
		6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	int dn = ap->port_no * 2 + adev->devno;
	struct ata_timing at, apeer;
	int T, UT;
	const int amd_clock = 33333;	/* KHz. */
	u8 t;

	T = 1000000000 / amd_clock;
	UT = T / min_t(int, max_t(int, clock, 1), 2);

	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
		dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
		return;
	}

	if (peer) {
		/* This may be over conservative */
		if (peer->dma_mode) {
			ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
			ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
		}
		ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
		ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;

	/*
	 *	Now do the setup work
	 */

	/* Configure the address set up timing */
	pci_read_config_byte(pdev, offset + 0x0C, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(pdev, offset + 0x0C , t);

	/* Configure the 8bit I/O timing */
	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
		((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));

	/* Drive timing */
	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
		((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));

	switch (clock) {
		case 1:
		t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
		break;

		case 2:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
		break;

		case 3:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
		break;

		case 4:
		t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
		break;

		default:
			return;
	}

	/* UDMA timing */
	if (at.udma)
		pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
}

/**
 *	amd_pre_reset		-	perform reset handling
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Reset sequence checking enable bits to see which ports are
 *	active.
 */

static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits amd_enable_bits[] = {
		{ 0x40, 1, 0x02, 0x02 },
		{ 0x40, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(link, deadline);
}

static void amd_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, amd_pre_reset, ata_std_softreset, NULL,
			   ata_std_postreset);
}

static int amd_cable_detect(struct ata_port *ap)
{
	static const u32 bitmask[2] = {0x03, 0x0C};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	pci_read_config_byte(pdev, 0x42, &ata66);
	if (ata66 & bitmask[ap->port_no])
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	amd33_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
}

static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
}

static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
}

static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
}

/**
 *	amd33_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
}

static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
}

static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
}

static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
}

/* Both host-side and drive-side detection results are worthless on NV
 * PATAs.  Ignore them and just follow what BIOS configured.  Both the
 * current configuration in PCI config reg and ACPI GTM result are
 * cached during driver attach and are consulted to select transfer
 * mode.
 */
static unsigned long nv_mode_filter(struct ata_device *dev,
				    unsigned long xfer_mask)
{
	static const unsigned int udma_mask_map[] =
		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
		  ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	struct ata_port *ap = dev->link->ap;
	char acpi_str[32] = "";
	u32 saved_udma, udma;
	const struct ata_acpi_gtm *gtm;
	unsigned long bios_limit = 0, acpi_limit = 0, limit;

	/* find out what BIOS configured */
	udma = saved_udma = (unsigned long)ap->host->private_data;

	if (ap->port_no == 0)
		udma >>= 16;
	if (dev->devno == 0)
		udma >>= 8;

	if ((udma & 0xc0) == 0xc0)
		bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);

	/* consult ACPI GTM too */
	gtm = ata_acpi_init_gtm(ap);
	if (gtm) {
		acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);

		snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
			 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	}

	/* be optimistic, EH can take care of things if something goes wrong */
	limit = bios_limit | acpi_limit;

	/* If PIO or DMA isn't configured at all, don't limit.  Let EH
	 * handle it.
	 */
	if (!(limit & ATA_MASK_PIO))
		limit |= ATA_MASK_PIO;
	if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
		limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;

	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
			xfer_mask, limit, xfer_mask & limit, bios_limit,
			saved_udma, acpi_limit, acpi_str);

	return xfer_mask & limit;
}

/**
 *	nv_probe_init	-	cable detection
 *	@lin: ATA link
 *
 *	Perform cable detection. The BIOS stores this in PCI config
 *	space for us.
 */

static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits nv_enable_bits[] = {
		{ 0x50, 1, 0x02, 0x02 },
		{ 0x50, 1, 0x01, 0x01 }
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(link, deadline);
}

static void nv_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, nv_pre_reset,
			       ata_std_softreset, NULL,
			       ata_std_postreset);
}

/**
 *	nv100_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the AMD registers for PIO mode.
 */

static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
}

static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
}

/**
 *	nv100_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the AMD and Nvidia
 *	chipset.
 */

static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
}

static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
}

static void nv_host_stop(struct ata_host *host)
{
	u32 udma = (unsigned long)host->private_data;

	/* restore PCI config register 0x60 */
	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
}

static struct scsi_host_template amd_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations amd_base_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.error_handler	= amd_error_handler,
};

static struct ata_port_operations amd33_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= amd33_set_piomode,
	.set_dmamode	= amd33_set_dmamode,
};

static struct ata_port_operations amd66_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd66_set_piomode,
	.set_dmamode	= amd66_set_dmamode,
};

static struct ata_port_operations amd100_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_piomode	= amd100_set_piomode,
	.set_dmamode	= amd100_set_dmamode,
};

static struct ata_port_operations amd133_port_ops = {
	.inherits	= &amd_base_port_ops,
	.cable_detect	= amd_cable_detect,
	.set_piomode	= amd133_set_piomode,
	.set_dmamode	= amd133_set_dmamode,
};

static const struct ata_port_operations nv_base_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= ata_cable_ignore,
	.mode_filter	= nv_mode_filter,
	.error_handler	= nv_error_handler,
	.host_stop	= nv_host_stop,
};

static struct ata_port_operations nv100_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv100_set_piomode,
	.set_dmamode	= nv100_set_dmamode,
};

static struct ata_port_operations nv133_port_ops = {
	.inherits	= &nv_base_port_ops,
	.set_piomode	= nv133_set_piomode,
	.set_dmamode	= nv133_set_dmamode,
};

static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[10] = {
		{	/* 0: AMD 7401 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,	/* No SWDMA */
			.udma_mask = 0x07,	/* UDMA 33 */
			.port_ops = &amd33_port_ops
		},
		{	/* 1: Early AMD7409 - no swdma */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 2: AMD 7409, no swdma errata */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,	/* UDMA 66 */
			.port_ops = &amd66_port_ops
		},
		{	/* 3: AMD 7411 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 4: AMD 7441 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		},
		{	/* 5: AMD 8111*/
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 6: AMD 8111 UDMA 100 (Serenade) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100, no swdma */
			.port_ops = &amd133_port_ops
		},
		{	/* 7: Nvidia Nforce */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &nv100_port_ops
		},
		{	/* 8: Nvidia Nforce2 and later */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA6,	/* UDMA 133, no swdma */
			.port_ops = &nv133_port_ops
		},
		{	/* 9: AMD CS5536 (Geode companion) */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,	/* UDMA 100 */
			.port_ops = &amd100_port_ops
		}
	};
	struct ata_port_info pi;
	const struct ata_port_info *ppi[] = { &pi, NULL };
	static int printed_version;
	int type = id->driver_data;
	u8 fifo;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	pci_read_config_byte(pdev, 0x41, &fifo);

	/* Check for AMD7409 without swdma errata and if found adjust type */
	if (type == 1 && pdev->revision > 0x7)
		type = 2;

	/* Serenade ? */
	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
			 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
		type = 6;	/* UDMA 100 only */

	/*
	 * Okay, type is determined now.  Apply type-specific workarounds.
	 */
	pi = info[type];

	if (type < 3)
		ata_pci_clear_simplex(pdev);

	/* Check for AMD7411 */
	if (type == 3)
		/* FIFO is broken */
		pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	else
		pci_write_config_byte(pdev, 0x41, fifo | 0xF0);

	/* Cable detection on Nvidia chips doesn't work too well,
	 * cache BIOS programmed UDMA mode.
	 */
	if (type == 7 || type == 8) {
		u32 udma;

		pci_read_config_dword(pdev, 0x60, &udma);
		pi.private_data = (void *)(unsigned long)udma;
	}

	/* And fire it up */
	return ata_pci_init_one(pdev, ppi, &amd_sht);
}

#ifdef CONFIG_PM
static int amd_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
		u8 fifo;
		pci_read_config_byte(pdev, 0x41, &fifo);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
			/* FIFO is broken */
			pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
		else
			pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
		    pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
		    	ata_pci_clear_simplex(pdev);
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id amd[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		4 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	7 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	8 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	8 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		9 },

	{ },
};

static struct pci_driver amd_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= amd,
	.probe 		= amd_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= amd_reinit_one,
#endif
};

static int __init amd_init(void)
{
	return pci_register_driver(&amd_pci_driver);
}

static void __exit amd_exit(void)
{
	pci_unregister_driver(&amd_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, amd);
MODULE_VERSION(DRV_VERSION);

module_init(amd_init);
module_exit(amd_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_amd.c - AMD PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based on pata-sil680. Errata information is taken from data sheets
	7	* and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
	8	* claimed by sata-nv.c.
	9	*
	10	* TODO:
	11	* Variable system clock when/if it makes sense
	12	* Power management on ports
	13	*
	14	*
	15	* Documentation publically available.
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "pata_amd"
943547ab	28	#define DRV_VERSION "0.3.10"
669a5db4 JG	29
	30	/**
	31	* timing_setup - shared timing computation and load
	32	* @ap: ATA port being set up
	33	* @adev: drive being configured
	34	* @offset: port offset
	35	* @speed: target speed
	36	* @clock: clock multiplier (number of times 33MHz for this part)
	37	*
	38	* Perform the actual timing set up for Nvidia or AMD PATA devices.
	39	* The actual devices vary so they all call into this helper function
	40	* providing the clock multipler and offset (because AMD and Nvidia put
	41	* the ports at different locations).
	42	*/
	43
	44	static void timing_setup(struct ata_port ap, struct ata_device adev, int offset, int speed, int clock)
	45	{
	46	static const unsigned char amd_cyc2udma[] = {
	47	6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
	48	};
	49
	50	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	51	struct ata_device *peer = ata_dev_pair(adev);
	52	int dn = ap->port_no * 2 + adev->devno;
	53	struct ata_timing at, apeer;
	54	int T, UT;
	55	const int amd_clock = 33333; /* KHz. */
	56	u8 t;
	57
	58	T = 1000000000 / amd_clock;
	59	UT = T / min_t(int, max_t(int, clock, 1), 2);
	60
	61	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
	62	dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
	63	return;
	64	}
	65
	66	if (peer) {
	67	/* This may be over conservative */
	68	if (peer->dma_mode) {
	69	ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
	70	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	71	}
	72	ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
	73	ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
	74	}
	75
	76	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
	77	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
	78
	79	/*
	80	* Now do the setup work
	81	*/
	82
	83	/* Configure the address set up timing */
	84	pci_read_config_byte(pdev, offset + 0x0C, &t);
	85	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
	86	pci_write_config_byte(pdev, offset + 0x0C , t);
	87
	88	/* Configure the 8bit I/O timing */
	89	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
	90	((FIT(at.act8b, 1, 16) - 1) << 4) \| (FIT(at.rec8b, 1, 16) - 1));
	91
	92	/* Drive timing */
93	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94	((FIT(at.active, 1, 16) - 1) << 4) \| (FIT(at.recover, 1, 16) - 1));
95
96	switch (clock) {
97	case 1:
98	t = at.udma ? (0xc0 \| (FIT(at.udma, 2, 5) - 2)) : 0x03;
99	break;
100
101	case 2:
102	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103	break;
104
105	case 3:
106	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107	break;
108
109	case 4:
110	t = at.udma ? (0xc0 \| amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111	break;
112
113	default:
114	return;
115	}
116
117	/* UDMA timing */
943547ab BZ	118	if (at.udma)
943547ab BZ	119	pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
669a5db4 JG	120	}
	121
	122	/**
cc0680a5 TH	123	* amd_pre_reset - perform reset handling
cc0680a5 TH	124	* @link: ATA link
d4b2bab4	125	* @deadline: deadline jiffies for the operation
669a5db4	126	*
eb4a2c7f AC	127	* Reset sequence checking enable bits to see which ports are
eb4a2c7f AC	128	* active.
669a5db4 JG	129	*/
669a5db4 JG	130
cc0680a5	131	static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	132	{
669a5db4 JG	133	static const struct pci_bits amd_enable_bits[] = {
	134	{ 0x40, 1, 0x02, 0x02 },
	135	{ 0x40, 1, 0x01, 0x01 }
	136	};
	137
cc0680a5	138	struct ata_port *ap = link->ap;
669a5db4	139	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	140
c961922b AC	141	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
c961922b AC	142	return -ENOENT;
669a5db4	143
cc0680a5	144	return ata_std_prereset(link, deadline);
669a5db4 JG	145	}
	146
	147	static void amd_error_handler(struct ata_port *ap)
	148	{
d98f88c2 HH	149	ata_bmdma_drive_eh(ap, amd_pre_reset, ata_std_softreset, NULL,
d98f88c2 HH	150	ata_std_postreset);
669a5db4 JG	151	}
669a5db4 JG	152
eb4a2c7f	153	static int amd_cable_detect(struct ata_port *ap)
669a5db4	154	{
eb4a2c7f	155	static const u32 bitmask[2] = {0x03, 0x0C};
669a5db4	156	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
eb4a2c7f	157	u8 ata66;
669a5db4	158
eb4a2c7f AC	159	pci_read_config_byte(pdev, 0x42, &ata66);
	160	if (ata66 & bitmask[ap->port_no])
	161	return ATA_CBL_PATA80;
	162	return ATA_CBL_PATA40;
669a5db4 JG	163	}
	164
	165	/**
	166	* amd33_set_piomode - set initial PIO mode data
	167	* @ap: ATA interface
	168	* @adev: ATA device
	169	*
	170	* Program the AMD registers for PIO mode.
	171	*/
	172
	173	static void amd33_set_piomode(struct ata_port ap, struct ata_device adev)
	174	{
	175	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
	176	}
	177
	178	static void amd66_set_piomode(struct ata_port ap, struct ata_device adev)
	179	{
	180	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
	181	}
	182
	183	static void amd100_set_piomode(struct ata_port ap, struct ata_device adev)
	184	{
	185	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
	186	}
	187
	188	static void amd133_set_piomode(struct ata_port ap, struct ata_device adev)
	189	{
	190	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
	191	}
	192
	193	/**
	194	* amd33_set_dmamode - set initial DMA mode data
	195	* @ap: ATA interface
	196	* @adev: ATA device
	197	*
	198	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	199	* chipset.
	200	*/
	201
	202	static void amd33_set_dmamode(struct ata_port ap, struct ata_device adev)
	203	{
	204	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
	205	}
	206
	207	static void amd66_set_dmamode(struct ata_port ap, struct ata_device adev)
	208	{
	209	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
	210	}
	211
	212	static void amd100_set_dmamode(struct ata_port ap, struct ata_device adev)
	213	{
	214	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
	215	}
	216
	217	static void amd133_set_dmamode(struct ata_port ap, struct ata_device adev)
	218	{
	219	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
	220	}
	221
ce54d161 TH	222	/* Both host-side and drive-side detection results are worthless on NV
	223	* PATAs. Ignore them and just follow what BIOS configured. Both the
	224	* current configuration in PCI config reg and ACPI GTM result are
	225	* cached during driver attach and are consulted to select transfer
	226	* mode.
	227	*/
	228	static unsigned long nv_mode_filter(struct ata_device *dev,
	229	unsigned long xfer_mask)
	230	{
	231	static const unsigned int udma_mask_map[] =
	232	{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
	233	ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
	234	struct ata_port *ap = dev->link->ap;
	235	char acpi_str[32] = "";
	236	u32 saved_udma, udma;
	237	const struct ata_acpi_gtm *gtm;
	238	unsigned long bios_limit = 0, acpi_limit = 0, limit;
	239
	240	/* find out what BIOS configured */
	241	udma = saved_udma = (unsigned long)ap->host->private_data;
	242
	243	if (ap->port_no == 0)
	244	udma >>= 16;
	245	if (dev->devno == 0)
	246	udma >>= 8;
	247
	248	if ((udma & 0xc0) == 0xc0)
	249	bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
	250
	251	/* consult ACPI GTM too */
	252	gtm = ata_acpi_init_gtm(ap);
	253	if (gtm) {
	254	acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
	255
	256	snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
	257	gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
	258	}
	259
	260	/* be optimistic, EH can take care of things if something goes wrong */
	261	limit = bios_limit \| acpi_limit;
	262
	263	/* If PIO or DMA isn't configured at all, don't limit. Let EH
	264	* handle it.
	265	*/
	266	if (!(limit & ATA_MASK_PIO))
	267	limit \|= ATA_MASK_PIO;
	268	if (!(limit & (ATA_MASK_MWDMA \| ATA_MASK_UDMA)))
	269	limit \|= ATA_MASK_MWDMA \| ATA_MASK_UDMA;
	270
	271	ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
	272	"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
	273	xfer_mask, limit, xfer_mask & limit, bios_limit,
	274	saved_udma, acpi_limit, acpi_str);
	275
	276	return xfer_mask & limit;
	277	}
669a5db4 JG	278
	279	/**
	280	* nv_probe_init - cable detection
cc0680a5	281	* @lin: ATA link
669a5db4 JG	282	*
	283	* Perform cable detection. The BIOS stores this in PCI config
	284	* space for us.
	285	*/
	286
cc0680a5	287	static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
d4b2bab4	288	{
76ff3c6e AC	289	static const struct pci_bits nv_enable_bits[] = {
	290	{ 0x50, 1, 0x02, 0x02 },
	291	{ 0x50, 1, 0x01, 0x01 }
	292	};
669a5db4	293
cc0680a5	294	struct ata_port *ap = link->ap;
669a5db4	295	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	296
c961922b AC	297	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
c961922b AC	298	return -ENOENT;
76ff3c6e	299
cc0680a5	300	return ata_std_prereset(link, deadline);
669a5db4 JG	301	}
	302
	303	static void nv_error_handler(struct ata_port *ap)
	304	{
	305	ata_bmdma_drive_eh(ap, nv_pre_reset,
	306	ata_std_softreset, NULL,
	307	ata_std_postreset);
	308	}
eb4a2c7f	309
669a5db4 JG	310	/**
	311	* nv100_set_piomode - set initial PIO mode data
	312	* @ap: ATA interface
	313	* @adev: ATA device
	314	*
	315	* Program the AMD registers for PIO mode.
	316	*/
	317
	318	static void nv100_set_piomode(struct ata_port ap, struct ata_device adev)
	319	{
	320	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
	321	}
	322
	323	static void nv133_set_piomode(struct ata_port ap, struct ata_device adev)
	324	{
	325	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
	326	}
	327
	328	/**
	329	* nv100_set_dmamode - set initial DMA mode data
	330	* @ap: ATA interface
	331	* @adev: ATA device
	332	*
	333	* Program the MWDMA/UDMA modes for the AMD and Nvidia
	334	* chipset.
	335	*/
	336
	337	static void nv100_set_dmamode(struct ata_port ap, struct ata_device adev)
	338	{
	339	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
	340	}
	341
	342	static void nv133_set_dmamode(struct ata_port ap, struct ata_device adev)
	343	{
	344	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
	345	}
	346
ce54d161 TH	347	static void nv_host_stop(struct ata_host *host)
	348	{
	349	u32 udma = (unsigned long)host->private_data;
	350
	351	/* restore PCI config register 0x60 */
	352	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
	353	}
	354
669a5db4	355	static struct scsi_host_template amd_sht = {
68d1d07b	356	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	357	};
669a5db4 JG	358
029cfd6b TH	359	static const struct ata_port_operations amd_base_port_ops = {
	360	.inherits = &ata_bmdma_port_ops,
	361	.error_handler = amd_error_handler,
	362	};
	363
669a5db4	364	static struct ata_port_operations amd33_port_ops = {
029cfd6b TH	365	.inherits = &amd_base_port_ops,
029cfd6b TH	366	.cable_detect = ata_cable_40wire,
669a5db4 JG	367	.set_piomode = amd33_set_piomode,
669a5db4 JG	368	.set_dmamode = amd33_set_dmamode,
669a5db4 JG	369	};
	370
	371	static struct ata_port_operations amd66_port_ops = {
029cfd6b TH	372	.inherits = &amd_base_port_ops,
029cfd6b TH	373	.cable_detect = ata_cable_unknown,
669a5db4 JG	374	.set_piomode = amd66_set_piomode,
669a5db4 JG	375	.set_dmamode = amd66_set_dmamode,
669a5db4 JG	376	};
	377
	378	static struct ata_port_operations amd100_port_ops = {
029cfd6b TH	379	.inherits = &amd_base_port_ops,
029cfd6b TH	380	.cable_detect = ata_cable_unknown,
669a5db4 JG	381	.set_piomode = amd100_set_piomode,
669a5db4 JG	382	.set_dmamode = amd100_set_dmamode,
669a5db4 JG	383	};
	384
	385	static struct ata_port_operations amd133_port_ops = {
029cfd6b TH	386	.inherits = &amd_base_port_ops,
029cfd6b TH	387	.cable_detect = amd_cable_detect,
669a5db4 JG	388	.set_piomode = amd133_set_piomode,
669a5db4 JG	389	.set_dmamode = amd133_set_dmamode,
029cfd6b	390	};
669a5db4	391
029cfd6b TH	392	static const struct ata_port_operations nv_base_port_ops = {
	393	.inherits = &ata_bmdma_port_ops,
	394	.cable_detect = ata_cable_ignore,
	395	.mode_filter = nv_mode_filter,
	396	.error_handler = nv_error_handler,
	397	.host_stop = nv_host_stop,
669a5db4 JG	398	};
	399
	400	static struct ata_port_operations nv100_port_ops = {
029cfd6b	401	.inherits = &nv_base_port_ops,
669a5db4 JG	402	.set_piomode = nv100_set_piomode,
669a5db4 JG	403	.set_dmamode = nv100_set_dmamode,
669a5db4 JG	404	};
	405
	406	static struct ata_port_operations nv133_port_ops = {
029cfd6b	407	.inherits = &nv_base_port_ops,
669a5db4 JG	408	.set_piomode = nv133_set_piomode,
669a5db4 JG	409	.set_dmamode = nv133_set_dmamode,
669a5db4 JG	410	};
	411
	412	static int amd_init_one(struct pci_dev pdev, const struct pci_device_id id)
	413	{
1626aeb8	414	static const struct ata_port_info info[10] = {
669a5db4	415	{ /* 0: AMD 7401 */
1d2808fd	416	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	417	.pio_mask = 0x1f,
	418	.mwdma_mask = 0x07, /* No SWDMA */
	419	.udma_mask = 0x07, /* UDMA 33 */
	420	.port_ops = &amd33_port_ops
	421	},
	422	{ /* 1: Early AMD7409 - no swdma */
1d2808fd	423	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	424	.pio_mask = 0x1f,
669a5db4 JG	425	.mwdma_mask = 0x07,
bf6263a8	426	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	427	.port_ops = &amd66_port_ops
	428	},
	429	{ /* 2: AMD 7409, no swdma errata */
1d2808fd	430	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	431	.pio_mask = 0x1f,
669a5db4 JG	432	.mwdma_mask = 0x07,
bf6263a8	433	.udma_mask = ATA_UDMA4, /* UDMA 66 */
669a5db4 JG	434	.port_ops = &amd66_port_ops
	435	},
	436	{ /* 3: AMD 7411 */
1d2808fd	437	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	438	.pio_mask = 0x1f,
669a5db4 JG	439	.mwdma_mask = 0x07,
bf6263a8	440	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	441	.port_ops = &amd100_port_ops
	442	},
	443	{ /* 4: AMD 7441 */
1d2808fd	444	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	445	.pio_mask = 0x1f,
669a5db4 JG	446	.mwdma_mask = 0x07,
bf6263a8	447	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	448	.port_ops = &amd100_port_ops
	449	},
	450	{ /* 5: AMD 8111*/
1d2808fd	451	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	452	.pio_mask = 0x1f,
669a5db4 JG	453	.mwdma_mask = 0x07,
bf6263a8	454	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	455	.port_ops = &amd133_port_ops
	456	},
	457	{ /* 6: AMD 8111 UDMA 100 (Serenade) */
1d2808fd	458	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	459	.pio_mask = 0x1f,
669a5db4 JG	460	.mwdma_mask = 0x07,
bf6263a8	461	.udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
669a5db4 JG	462	.port_ops = &amd133_port_ops
	463	},
	464	{ /* 7: Nvidia Nforce */
1d2808fd	465	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	466	.pio_mask = 0x1f,
669a5db4 JG	467	.mwdma_mask = 0x07,
bf6263a8	468	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	469	.port_ops = &nv100_port_ops
	470	},
	471	{ /* 8: Nvidia Nforce2 and later */
1d2808fd	472	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	473	.pio_mask = 0x1f,
669a5db4 JG	474	.mwdma_mask = 0x07,
bf6263a8	475	.udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
669a5db4 JG	476	.port_ops = &nv133_port_ops
	477	},
	478	{ /* 9: AMD CS5536 (Geode companion) */
1d2808fd	479	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	480	.pio_mask = 0x1f,
669a5db4 JG	481	.mwdma_mask = 0x07,
bf6263a8	482	.udma_mask = ATA_UDMA5, /* UDMA 100 */
669a5db4 JG	483	.port_ops = &amd100_port_ops
	484	}
	485	};
ce54d161 TH	486	struct ata_port_info pi;
ce54d161 TH	487	const struct ata_port_info *ppi[] = { &pi, NULL };
669a5db4 JG	488	static int printed_version;
669a5db4 JG	489	int type = id->driver_data;
669a5db4	490	u8 fifo;
f08048e9	491	int rc;
669a5db4 JG	492
	493	if (!printed_version++)
	494	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	495
f08048e9 TH	496	rc = pcim_enable_device(pdev);
	497	if (rc)
	498	return rc;
	499
669a5db4 JG	500	pci_read_config_byte(pdev, 0x41, &fifo);
	501
	502	/* Check for AMD7409 without swdma errata and if found adjust type */
44c10138	503	if (type == 1 && pdev->revision > 0x7)
669a5db4 JG	504	type = 2;
669a5db4 JG	505
ce54d161 TH	506	/* Serenade ? */
	507	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	508	pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	509	type = 6; /* UDMA 100 only */
	510
	511	/*
	512	* Okay, type is determined now. Apply type-specific workarounds.
	513	*/
	514	pi = info[type];
	515
	516	if (type < 3)
	517	ata_pci_clear_simplex(pdev);
	518
669a5db4 JG	519	/* Check for AMD7411 */
	520	if (type == 3)
	521	/* FIFO is broken */
	522	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	523	else
	524	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	525
ce54d161 TH	526	/* Cable detection on Nvidia chips doesn't work too well,
	527	* cache BIOS programmed UDMA mode.
	528	*/
	529	if (type == 7 \|\| type == 8) {
	530	u32 udma;
669a5db4	531
ce54d161 TH	532	pci_read_config_dword(pdev, 0x60, &udma);
	533	pi.private_data = (void *)(unsigned long)udma;
	534	}
669a5db4 JG	535
669a5db4 JG	536	/* And fire it up */
1bd5b715	537	return ata_pci_init_one(pdev, ppi, &amd_sht);
669a5db4 JG	538	}
669a5db4 JG	539
438ac6d5	540	#ifdef CONFIG_PM
c304193a A	541	static int amd_reinit_one(struct pci_dev *pdev)
c304193a A	542	{
f08048e9 TH	543	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	544	int rc;
	545
	546	rc = ata_pci_device_do_resume(pdev);
	547	if (rc)
	548	return rc;
	549
c304193a A	550	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
	551	u8 fifo;
	552	pci_read_config_byte(pdev, 0x41, &fifo);
	553	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
	554	/* FIFO is broken */
	555	pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
	556	else
	557	pci_write_config_byte(pdev, 0x41, fifo \| 0xF0);
	558	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 \|\|
	559	pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
	560	ata_pci_clear_simplex(pdev);
	561	}
f08048e9 TH	562
	563	ata_host_resume(host);
	564	return 0;
c304193a	565	}
438ac6d5	566	#endif
c304193a	567
669a5db4	568	static const struct pci_device_id amd[] = {
2d2744fc JG	569	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	570	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	571	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
	572	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
	573	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
	574	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
	575	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
	576	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
	577	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
	578	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
	579	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
	580	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
	581	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
	582	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
	583	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a PC	584	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
05e2867a PC	585	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
9f789755 PC	586	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
9f789755 PC	587	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
2d2744fc JG	588	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
	589
	590	{ },
669a5db4 JG	591	};
	592
	593	static struct pci_driver amd_pci_driver = {
2d2744fc	594	.name = DRV_NAME,
669a5db4 JG	595	.id_table = amd,
669a5db4 JG	596	.probe = amd_init_one,
c304193a	597	.remove = ata_pci_remove_one,
438ac6d5	598	#ifdef CONFIG_PM
c304193a A	599	.suspend = ata_pci_device_suspend,
c304193a A	600	.resume = amd_reinit_one,
438ac6d5	601	#endif
669a5db4 JG	602	};
	603
	604	static int __init amd_init(void)
	605	{
	606	return pci_register_driver(&amd_pci_driver);
	607	}
	608
	609	static void __exit amd_exit(void)
	610	{
	611	pci_unregister_driver(&amd_pci_driver);
	612	}
	613
669a5db4	614	MODULE_AUTHOR("Alan Cox");
c9544bcb	615	MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
669a5db4 JG	616	MODULE_LICENSE("GPL");
	617	MODULE_DEVICE_TABLE(pci, amd);
	618	MODULE_VERSION(DRV_VERSION);
	619
	620	module_init(amd_init);
	621	module_exit(amd_exit);