[deliverable/linux.git] / drivers / ata / pata_artop.c

/*
 *    pata_artop.c - ARTOP ATA controller driver
 *
 *	(C) 2006 Red Hat
 *	(C) 2007 Bartlomiej Zolnierkiewicz
 *
 *    Based in part on drivers/ide/pci/aec62xx.c
 *	Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *	865/865R fixes for Macintosh card version from a patch to the old
 *		driver by Thibaut VARENE <varenet@parisc-linux.org>
 *	When setting the PCI latency we must set 0x80 or higher for burst
 *		performance Alessandro Zummo <alessandro.zummo@towertech.it>
 *
 *	TODO
 *	Investigate no_dsc on 850R
 *	Clock detect
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_artop"
#define DRV_VERSION	"0.4.5"

/*
 *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
 *	get PCI bus speed functionality we leave this as 0. Its a variable
 *	for when we get the functionality and also for folks wanting to
 *	test stuff.
 */

static int clock = 0;

static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	artop6260_pre_reset	-	check for 40/80 pin
 *	@link: link
 *	@deadline: deadline jiffies for the operation
 *
 *	The ARTOP hardware reports the cable detect bits in register 0x49.
 *	Nothing complicated needed here.
 */

static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Odd numbered device ids are the units with enable bits (the -R cards) */
	if ((pdev->device & 1) &&
	    !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	artop6260_cable_detect	-	identify cable type
 *	@ap: Port
 *
 *	Identify the cable type for the ARTOP interface in question
 */

static int artop6260_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x49, &tmp);
	if (tmp & (1 << ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	artop6210_load_piomode - Load a set of PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. This
 *	is used both to set PIO timings in PIO mode and also to set the
 *	matching PIO clocking for UDMA, as well as the MWDMA timings.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u16 timing[2][5] = {
		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
}

/**
 *	artop6210_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_load_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u8 timing[2][5] = {
		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
}

/**
 *	artop6260_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6210_load_piomode(ap, adev, pio);

	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));

	/* Add ultra DMA bits if in UDMA mode */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (2 * dn));
	}
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6260_load_piomode(ap, adev, pio);

	/* Add ultra DMA bits if in UDMA mode */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (4 * adev->devno));
	}
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop_6210_qc_defer	-	implement serialization
 *	@qc: command
 *
 *	Issue commands per host on this chip.
 */

static int artop6210_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_host *host = qc->ap->host;
	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	int rc;

	/* First apply the usual rules */
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	/* Now apply serialization rules. Only allow a command if the
	   other channel state machine is idle */
	if (alt && alt->qc_active)
		return	ATA_DEFER_PORT;
	return 0;
}

static struct scsi_host_template artop_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations artop6210_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_40wire,
	.set_piomode		= artop6210_set_piomode,
	.set_dmamode		= artop6210_set_dmamode,
	.prereset		= artop6210_pre_reset,
	.qc_defer		= artop6210_qc_defer,
};

static struct ata_port_operations artop6260_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= artop6260_cable_detect,
	.set_piomode		= artop6260_set_piomode,
	.set_dmamode		= artop6260_set_dmamode,
	.prereset		= artop6260_pre_reset,
};


/**
 *	artop_init_one - Register ARTOP ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in artop_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_6210 = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA2,
		.port_ops	= &artop6210_ops,
	};
	static const struct ata_port_info info_626x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA5,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x_fast = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA6,
		.port_ops	= &artop6260_ops,
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	int rc;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0) {	/* 6210 variant */
		ppi[0] = &info_6210;
		/* BIOS may have left us in UDMA, clear it before libata probe */
		pci_write_config_byte(pdev, 0x54, 0);
	}
	else if (id->driver_data == 1)	/* 6260 */
		ppi[0] = &info_626x;
	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
		unsigned long io = pci_resource_start(pdev, 4);
		u8 reg;

		ppi[0] = &info_628x;
		if (inb(io) & 0x10)
			ppi[0] = &info_628x_fast;
		/* Mac systems come up with some registers not set as we
		   will need them */

		/* Clear reset & test bits */
		pci_read_config_byte(pdev, 0x49, &reg);
		pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);

		/* PCI latency must be > 0x80 for burst mode, tweak it
		 * if required.
		 */
		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
		if (reg <= 0x80)
			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);

		/* Enable IRQ output and burst mode */
		pci_read_config_byte(pdev, 0x4a, &reg);
		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);

	}

	BUG_ON(ppi[0] == NULL);

	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
}

static const struct pci_device_id artop_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },

	{ }	/* terminate list */
};

static struct pci_driver artop_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= artop_pci_tbl,
	.probe			= artop_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init artop_init(void)
{
	return pci_register_driver(&artop_pci_driver);
}

static void __exit artop_exit(void)
{
	pci_unregister_driver(&artop_pci_driver);
}

module_init(artop_init);
module_exit(artop_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_artop.c - ARTOP ATA controller driver
	3	*
ab771630	4	* (C) 2006 Red Hat
be456b77	5	* (C) 2007 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on drivers/ide/pci/aec62xx.c
	8	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	9	* 865/865R fixes for Macintosh card version from a patch to the old
	10	* driver by Thibaut VARENE <varenet@parisc-linux.org>
	11	* When setting the PCI latency we must set 0x80 or higher for burst
	12	* performance Alessandro Zummo <alessandro.zummo@towertech.it>
	13	*
	14	* TODO
669a5db4 JG	15	* Investigate no_dsc on 850R
	16	* Clock detect
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <linux/device.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28	#include <linux/ata.h>
	29
	30	#define DRV_NAME "pata_artop"
140d6fed	31	#define DRV_VERSION "0.4.5"
669a5db4 JG	32
	33	/*
	34	* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
	35	* get PCI bus speed functionality we leave this as 0. Its a variable
	36	* for when we get the functionality and also for folks wanting to
	37	* test stuff.
	38	*/
	39
	40	static int clock = 0;
	41
cc0680a5	42	static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	43	{
cc0680a5	44	struct ata_port *ap = link->ap;
669a5db4 JG	45	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	46	const struct pci_bits artop_enable_bits[] = {
	47	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	48	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	49	};
	50
c961922b AC	51	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b AC	52	return -ENOENT;
d4b2bab4	53
9363c382	54	return ata_sff_prereset(link, deadline);
669a5db4 JG	55	}
669a5db4 JG	56
669a5db4 JG	57	/**
669a5db4 JG	58	* artop6260_pre_reset - check for 40/80 pin
cc0680a5	59	* @link: link
d4b2bab4	60	* @deadline: deadline jiffies for the operation
669a5db4 JG	61	*
	62	* The ARTOP hardware reports the cable detect bits in register 0x49.
	63	* Nothing complicated needed here.
	64	*/
	65
cc0680a5	66	static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	67	{
	68	static const struct pci_bits artop_enable_bits[] = {
	69	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	70	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	71	};
	72
cc0680a5	73	struct ata_port *ap = link->ap;
669a5db4	74	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 JG	75
669a5db4 JG	76	/* Odd numbered device ids are the units with enable bits (the -R cards) */
673424c0 JD	77	if ((pdev->device & 1) &&
673424c0 JD	78	!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b	79	return -ENOENT;
27c78b37	80
9363c382	81	return ata_sff_prereset(link, deadline);
a73984a0	82	}
c961922b	83
a73984a0 JG	84	/**
	85	* artop6260_cable_detect - identify cable type
	86	* @ap: Port
	87	*
c343a839	88	* Identify the cable type for the ARTOP interface in question
a73984a0	89	*/
a617c09f	90
a73984a0 JG	91	static int artop6260_cable_detect(struct ata_port *ap)
	92	{
	93	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	94	u8 tmp;
669a5db4	95	pci_read_config_byte(pdev, 0x49, &tmp);
3f9dd27a	96	if (tmp & (1 << ap->port_no))
a73984a0 JG	97	return ATA_CBL_PATA40;
a73984a0 JG	98	return ATA_CBL_PATA80;
669a5db4 JG	99	}
669a5db4 JG	100
669a5db4 JG	101	/**
	102	* artop6210_load_piomode - Load a set of PATA PIO timings
	103	* @ap: Port whose timings we are configuring
	104	* @adev: Device
	105	* @pio: PIO mode
	106	*
	107	* Set PIO mode for device, in host controller PCI config space. This
	108	* is used both to set PIO timings in PIO mode and also to set the
	109	* matching PIO clocking for UDMA, as well as the MWDMA timings.
	110	*
	111	* LOCKING:
	112	* None (inherited from caller).
	113	*/
	114
	115	static void artop6210_load_piomode(struct ata_port ap, struct ata_device adev, unsigned int pio)
	116	{
	117	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	118	int dn = adev->devno + 2 * ap->port_no;
	119	const u16 timing[2][5] = {
	120	{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
	121	{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
	122
	123	};
	124	/* Load the PIO timing active/recovery bits */
	125	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
	126	}
	127
	128	/**
	129	* artop6210_set_piomode - Initialize host controller PATA PIO timings
	130	* @ap: Port whose timings we are configuring
	131	* @adev: Device we are configuring
	132	*
	133	* Set PIO mode for device, in host controller PCI config space. For
	134	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
	135	* the event UDMA is used the later call to set_dmamode will set the
	136	* bits as required.
	137	*
	138	* LOCKING:
	139	* None (inherited from caller).
	140	*/
	141
	142	static void artop6210_set_piomode(struct ata_port ap, struct ata_device adev)
	143	{
	144	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	145	int dn = adev->devno + 2 * ap->port_no;
	146	u8 ultra;
	147
	148	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	149
	150	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	151	pci_read_config_byte(pdev, 0x54, &ultra);
	152	ultra &= ~(3 << (2 * dn));
	153	pci_write_config_byte(pdev, 0x54, ultra);
	154	}
	155
	156	/**
	157	* artop6260_load_piomode - Initialize host controller PATA PIO timings
	158	* @ap: Port whose timings we are configuring
	159	* @adev: Device we are configuring
	160	* @pio: PIO mode
	161	*
	162	* Set PIO mode for device, in host controller PCI config space. The
	163	* ARTOP6260 and relatives store the timing data differently.
	164	*
165	* LOCKING:
166	* None (inherited from caller).
167	*/
168
169	static void artop6260_load_piomode (struct ata_port ap, struct ata_device adev, unsigned int pio)
170	{
171	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
172	int dn = adev->devno + 2 * ap->port_no;
173	const u8 timing[2][5] = {
174	{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
175	{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
176
177	};
178	/* Load the PIO timing active/recovery bits */
179	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
180	}
181
182	/**
183	* artop6260_set_piomode - Initialize host controller PATA PIO timings
184	* @ap: Port whose timings we are configuring
185	* @adev: Device we are configuring
186	*
187	* Set PIO mode for device, in host controller PCI config space. For
188	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
189	* the event UDMA is used the later call to set_dmamode will set the
190	* bits as required.
191	*
192	* LOCKING:
193	* None (inherited from caller).
194	*/
195
196	static void artop6260_set_piomode(struct ata_port ap, struct ata_device adev)
197	{
198	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
199	u8 ultra;
200
201	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
202
203	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
204	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
205	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
206	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
207	}
208
209	/**
210	* artop6210_set_dmamode - Initialize host controller PATA PIO timings
211	* @ap: Port whose timings we are configuring
a73984a0	212	* @adev: Device whose timings we are configuring
669a5db4 JG	213	*
	214	* Set DMA mode for device, in host controller PCI config space.
	215	*
	216	* LOCKING:
	217	* None (inherited from caller).
	218	*/
	219
	220	static void artop6210_set_dmamode (struct ata_port ap, struct ata_device adev)
	221	{
	222	unsigned int pio;
	223	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	224	int dn = adev->devno + 2 * ap->port_no;
	225	u8 ultra;
	226
	227	if (adev->dma_mode == XFER_MW_DMA_0)
	228	pio = 1;
	229	else
	230	pio = 4;
	231
	232	/* Load the PIO timing active/recovery bits */
	233	artop6210_load_piomode(ap, adev, pio);
	234
	235	pci_read_config_byte(pdev, 0x54, &ultra);
	236	ultra &= ~(3 << (2 * dn));
	237
	238	/* Add ultra DMA bits if in UDMA mode */
	239	if (adev->dma_mode >= XFER_UDMA_0) {
	240	u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
	241	if (mode == 0)
	242	mode = 1;
	243	ultra \|= (mode << (2 * dn));
	244	}
	245	pci_write_config_byte(pdev, 0x54, ultra);
	246	}
	247
	248	/**
	249	* artop6260_set_dmamode - Initialize host controller PATA PIO timings
	250	* @ap: Port whose timings we are configuring
	251	* @adev: Device we are configuring
	252	*
	253	* Set DMA mode for device, in host controller PCI config space. The
	254	* ARTOP6260 and relatives store the timing data differently.
	255	*
	256	* LOCKING:
	257	* None (inherited from caller).
	258	*/
	259
	260	static void artop6260_set_dmamode (struct ata_port ap, struct ata_device adev)
	261	{
	262	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	263	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	264	u8 ultra;
	265
	266	if (adev->dma_mode == XFER_MW_DMA_0)
	267	pio = 1;
	268	else
	269	pio = 4;
	270
	271	/* Load the PIO timing active/recovery bits */
	272	artop6260_load_piomode(ap, adev, pio);
	273
	274	/* Add ultra DMA bits if in UDMA mode */
	275	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	276	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
277	if (adev->dma_mode >= XFER_UDMA_0) {
278	u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
279	if (mode == 0)
280	mode = 1;
281	ultra \|= (mode << (4 * adev->devno));
282	}
283	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
284	}
285
140d6fed AC	286	/**
	287	* artop_6210_qc_defer - implement serialization
	288	* @qc: command
	289	*
	290	* Issue commands per host on this chip.
	291	*/
	292
	293	static int artop6210_qc_defer(struct ata_queued_cmd *qc)
	294	{
	295	struct ata_host *host = qc->ap->host;
	296	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	297	int rc;
	298
	299	/* First apply the usual rules */
	300	rc = ata_std_qc_defer(qc);
	301	if (rc != 0)
	302	return rc;
	303
	304	/* Now apply serialization rules. Only allow a command if the
	305	other channel state machine is idle */
	306	if (alt && alt->qc_active)
	307	return ATA_DEFER_PORT;
	308	return 0;
	309	}
	310
669a5db4	311	static struct scsi_host_template artop_sht = {
68d1d07b	312	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	313	};
669a5db4 JG	314
029cfd6b TH	315	static struct ata_port_operations artop6210_ops = {
	316	.inherits = &ata_bmdma_port_ops,
	317	.cable_detect = ata_cable_40wire,
669a5db4 JG	318	.set_piomode = artop6210_set_piomode,
669a5db4 JG	319	.set_dmamode = artop6210_set_dmamode,
a1efdaba	320	.prereset = artop6210_pre_reset,
140d6fed	321	.qc_defer = artop6210_qc_defer,
669a5db4 JG	322	};
669a5db4 JG	323
029cfd6b TH	324	static struct ata_port_operations artop6260_ops = {
	325	.inherits = &ata_bmdma_port_ops,
	326	.cable_detect = artop6260_cable_detect,
669a5db4 JG	327	.set_piomode = artop6260_set_piomode,
669a5db4 JG	328	.set_dmamode = artop6260_set_dmamode,
a1efdaba	329	.prereset = artop6260_pre_reset,
669a5db4 JG	330	};
	331
	332
	333	/**
	334	* artop_init_one - Register ARTOP ATA PCI device with kernel services
	335	* @pdev: PCI device to register
	336	* @ent: Entry in artop_pci_tbl matching with @pdev
	337	*
	338	* Called from kernel PCI layer.
	339	*
	340	* LOCKING:
	341	* Inherited from PCI layer (may sleep).
	342	*
	343	* RETURNS:
	344	* Zero on success, or -ERRNO value.
	345	*/
	346
	347	static int artop_init_one (struct pci_dev pdev, const struct pci_device_id id)
	348	{
1626aeb8	349	static const struct ata_port_info info_6210 = {
1d2808fd	350	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	351	.pio_mask = ATA_PIO4,
14bdef98 EIB	352	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	353	.udma_mask = ATA_UDMA2,
	354	.port_ops = &artop6210_ops,
	355	};
1626aeb8	356	static const struct ata_port_info info_626x = {
1d2808fd	357	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	358	.pio_mask = ATA_PIO4,
14bdef98 EIB	359	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	360	.udma_mask = ATA_UDMA4,
	361	.port_ops = &artop6260_ops,
	362	};
be456b77	363	static const struct ata_port_info info_628x = {
1d2808fd	364	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	365	.pio_mask = ATA_PIO4,
14bdef98 EIB	366	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	367	.udma_mask = ATA_UDMA5,
	368	.port_ops = &artop6260_ops,
	369	};
be456b77	370	static const struct ata_port_info info_628x_fast = {
be456b77	371	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	372	.pio_mask = ATA_PIO4,
14bdef98 EIB	373	.mwdma_mask = ATA_MWDMA2,
be456b77 BZ	374	.udma_mask = ATA_UDMA6,
	375	.port_ops = &artop6260_ops,
	376	};
1626aeb8	377	const struct ata_port_info *ppi[] = { NULL, NULL };
f08048e9	378	int rc;
669a5db4	379
06296a1e	380	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	381
f08048e9 TH	382	rc = pcim_enable_device(pdev);
	383	if (rc)
	384	return rc;
	385
669a5db4	386	if (id->driver_data == 0) { /* 6210 variant */
1626aeb8	387	ppi[0] = &info_6210;
669a5db4 JG	388	/* BIOS may have left us in UDMA, clear it before libata probe */
669a5db4 JG	389	pci_write_config_byte(pdev, 0x54, 0);
669a5db4 JG	390	}
669a5db4 JG	391	else if (id->driver_data == 1) /* 6260 */
1626aeb8	392	ppi[0] = &info_626x;
be456b77	393	else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
669a5db4 JG	394	unsigned long io = pci_resource_start(pdev, 4);
	395	u8 reg;
	396
be456b77	397	ppi[0] = &info_628x;
669a5db4	398	if (inb(io) & 0x10)
be456b77	399	ppi[0] = &info_628x_fast;
669a5db4 JG	400	/* Mac systems come up with some registers not set as we
	401	will need them */
	402
	403	/* Clear reset & test bits */
	404	pci_read_config_byte(pdev, 0x49, &reg);
	405	pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
	406
	407	/* PCI latency must be > 0x80 for burst mode, tweak it
	408	* if required.
	409	*/
	410	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
	411	if (reg <= 0x80)
	412	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
	413
	414	/* Enable IRQ output and burst mode */
	415	pci_read_config_byte(pdev, 0x4a, &reg);
	416	pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) \| 0x80);
	417
	418	}
15a7c3bb	419
1626aeb8	420	BUG_ON(ppi[0] == NULL);
15a7c3bb	421
1c5afdf7	422	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
669a5db4 JG	423	}
	424
	425	static const struct pci_device_id artop_pci_tbl[] = {
2d2744fc JG	426	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	427	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	428	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	429	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	430	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
	431
669a5db4 JG	432	{ } /* terminate list */
	433	};
	434
	435	static struct pci_driver artop_pci_driver = {
	436	.name = DRV_NAME,
	437	.id_table = artop_pci_tbl,
	438	.probe = artop_init_one,
	439	.remove = ata_pci_remove_one,
	440	};
	441
	442	static int __init artop_init(void)
	443	{
	444	return pci_register_driver(&artop_pci_driver);
	445	}
	446
	447	static void __exit artop_exit(void)
	448	{
	449	pci_unregister_driver(&artop_pci_driver);
	450	}
	451
669a5db4 JG	452	module_init(artop_init);
	453	module_exit(artop_exit);
	454
	455	MODULE_AUTHOR("Alan Cox");
	456	MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
	457	MODULE_LICENSE("GPL");
	458	MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
	459	MODULE_VERSION(DRV_VERSION);
	460