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669a5db4 JG |
1 | /* |
2 | * pata_artop.c - ARTOP ATA controller driver | |
3 | * | |
4 | * (C) 2006 Red Hat <alan@redhat.com> | |
5 | * | |
6 | * Based in part on drivers/ide/pci/aec62xx.c | |
7 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
8 | * 865/865R fixes for Macintosh card version from a patch to the old | |
9 | * driver by Thibaut VARENE <varenet@parisc-linux.org> | |
10 | * When setting the PCI latency we must set 0x80 or higher for burst | |
11 | * performance Alessandro Zummo <alessandro.zummo@towertech.it> | |
12 | * | |
13 | * TODO | |
14 | * 850 serialization once the core supports it | |
15 | * Investigate no_dsc on 850R | |
16 | * Clock detect | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/device.h> | |
26 | #include <scsi/scsi_host.h> | |
27 | #include <linux/libata.h> | |
28 | #include <linux/ata.h> | |
29 | ||
30 | #define DRV_NAME "pata_artop" | |
c961922b | 31 | #define DRV_VERSION "0.4.2" |
669a5db4 JG |
32 | |
33 | /* | |
34 | * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we | |
35 | * get PCI bus speed functionality we leave this as 0. Its a variable | |
36 | * for when we get the functionality and also for folks wanting to | |
37 | * test stuff. | |
38 | */ | |
39 | ||
40 | static int clock = 0; | |
41 | ||
42 | static int artop6210_pre_reset(struct ata_port *ap) | |
43 | { | |
44 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
45 | const struct pci_bits artop_enable_bits[] = { | |
46 | { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
47 | { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
48 | }; | |
49 | ||
c961922b AC |
50 | if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) |
51 | return -ENOENT; | |
669a5db4 JG |
52 | return ata_std_prereset(ap); |
53 | } | |
54 | ||
55 | /** | |
56 | * artop6210_error_handler - Probe specified port on PATA host controller | |
57 | * @ap: Port to probe | |
58 | * | |
59 | * LOCKING: | |
60 | * None (inherited from caller). | |
61 | */ | |
62 | ||
63 | static void artop6210_error_handler(struct ata_port *ap) | |
64 | { | |
65 | ata_bmdma_drive_eh(ap, artop6210_pre_reset, | |
66 | ata_std_softreset, NULL, | |
67 | ata_std_postreset); | |
68 | } | |
69 | ||
70 | /** | |
71 | * artop6260_pre_reset - check for 40/80 pin | |
72 | * @ap: Port | |
73 | * | |
74 | * The ARTOP hardware reports the cable detect bits in register 0x49. | |
75 | * Nothing complicated needed here. | |
76 | */ | |
77 | ||
78 | static int artop6260_pre_reset(struct ata_port *ap) | |
79 | { | |
80 | static const struct pci_bits artop_enable_bits[] = { | |
81 | { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
82 | { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
83 | }; | |
84 | ||
85 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
669a5db4 JG |
86 | |
87 | /* Odd numbered device ids are the units with enable bits (the -R cards) */ | |
c961922b AC |
88 | if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) |
89 | return -ENOENT; | |
a73984a0 JG |
90 | return ata_std_prereset(ap); |
91 | } | |
c961922b | 92 | |
a73984a0 JG |
93 | /** |
94 | * artop6260_cable_detect - identify cable type | |
95 | * @ap: Port | |
96 | * | |
97 | * Identify the cable type for the ARTOp interface in question | |
98 | */ | |
99 | ||
100 | static int artop6260_cable_detect(struct ata_port *ap) | |
101 | { | |
102 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
103 | u8 tmp; | |
669a5db4 | 104 | pci_read_config_byte(pdev, 0x49, &tmp); |
3f9dd27a | 105 | if (tmp & (1 << ap->port_no)) |
a73984a0 JG |
106 | return ATA_CBL_PATA40; |
107 | return ATA_CBL_PATA80; | |
669a5db4 JG |
108 | } |
109 | ||
110 | /** | |
111 | * artop6260_error_handler - Probe specified port on PATA host controller | |
112 | * @ap: Port to probe | |
113 | * | |
114 | * LOCKING: | |
115 | * None (inherited from caller). | |
116 | */ | |
117 | ||
118 | static void artop6260_error_handler(struct ata_port *ap) | |
119 | { | |
120 | ata_bmdma_drive_eh(ap, artop6260_pre_reset, | |
121 | ata_std_softreset, NULL, | |
122 | ata_std_postreset); | |
123 | } | |
124 | ||
125 | /** | |
126 | * artop6210_load_piomode - Load a set of PATA PIO timings | |
127 | * @ap: Port whose timings we are configuring | |
128 | * @adev: Device | |
129 | * @pio: PIO mode | |
130 | * | |
131 | * Set PIO mode for device, in host controller PCI config space. This | |
132 | * is used both to set PIO timings in PIO mode and also to set the | |
133 | * matching PIO clocking for UDMA, as well as the MWDMA timings. | |
134 | * | |
135 | * LOCKING: | |
136 | * None (inherited from caller). | |
137 | */ | |
138 | ||
139 | static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) | |
140 | { | |
141 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
142 | int dn = adev->devno + 2 * ap->port_no; | |
143 | const u16 timing[2][5] = { | |
144 | { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 }, | |
145 | { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 } | |
146 | ||
147 | }; | |
148 | /* Load the PIO timing active/recovery bits */ | |
149 | pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); | |
150 | } | |
151 | ||
152 | /** | |
153 | * artop6210_set_piomode - Initialize host controller PATA PIO timings | |
154 | * @ap: Port whose timings we are configuring | |
155 | * @adev: Device we are configuring | |
156 | * | |
157 | * Set PIO mode for device, in host controller PCI config space. For | |
158 | * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In | |
159 | * the event UDMA is used the later call to set_dmamode will set the | |
160 | * bits as required. | |
161 | * | |
162 | * LOCKING: | |
163 | * None (inherited from caller). | |
164 | */ | |
165 | ||
166 | static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
167 | { | |
168 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
169 | int dn = adev->devno + 2 * ap->port_no; | |
170 | u8 ultra; | |
171 | ||
172 | artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
173 | ||
174 | /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ | |
175 | pci_read_config_byte(pdev, 0x54, &ultra); | |
176 | ultra &= ~(3 << (2 * dn)); | |
177 | pci_write_config_byte(pdev, 0x54, ultra); | |
178 | } | |
179 | ||
180 | /** | |
181 | * artop6260_load_piomode - Initialize host controller PATA PIO timings | |
182 | * @ap: Port whose timings we are configuring | |
183 | * @adev: Device we are configuring | |
184 | * @pio: PIO mode | |
185 | * | |
186 | * Set PIO mode for device, in host controller PCI config space. The | |
187 | * ARTOP6260 and relatives store the timing data differently. | |
188 | * | |
189 | * LOCKING: | |
190 | * None (inherited from caller). | |
191 | */ | |
192 | ||
193 | static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio) | |
194 | { | |
195 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
196 | int dn = adev->devno + 2 * ap->port_no; | |
197 | const u8 timing[2][5] = { | |
198 | { 0x00, 0x0A, 0x08, 0x33, 0x31 }, | |
199 | { 0x70, 0x7A, 0x78, 0x43, 0x41 } | |
200 | ||
201 | }; | |
202 | /* Load the PIO timing active/recovery bits */ | |
203 | pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); | |
204 | } | |
205 | ||
206 | /** | |
207 | * artop6260_set_piomode - Initialize host controller PATA PIO timings | |
208 | * @ap: Port whose timings we are configuring | |
209 | * @adev: Device we are configuring | |
210 | * | |
211 | * Set PIO mode for device, in host controller PCI config space. For | |
212 | * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In | |
213 | * the event UDMA is used the later call to set_dmamode will set the | |
214 | * bits as required. | |
215 | * | |
216 | * LOCKING: | |
217 | * None (inherited from caller). | |
218 | */ | |
219 | ||
220 | static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
221 | { | |
222 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
223 | u8 ultra; | |
224 | ||
225 | artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
226 | ||
227 | /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ | |
228 | pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); | |
229 | ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ | |
230 | pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); | |
231 | } | |
232 | ||
233 | /** | |
234 | * artop6210_set_dmamode - Initialize host controller PATA PIO timings | |
235 | * @ap: Port whose timings we are configuring | |
a73984a0 | 236 | * @adev: Device whose timings we are configuring |
669a5db4 JG |
237 | * |
238 | * Set DMA mode for device, in host controller PCI config space. | |
239 | * | |
240 | * LOCKING: | |
241 | * None (inherited from caller). | |
242 | */ | |
243 | ||
244 | static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
245 | { | |
246 | unsigned int pio; | |
247 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
248 | int dn = adev->devno + 2 * ap->port_no; | |
249 | u8 ultra; | |
250 | ||
251 | if (adev->dma_mode == XFER_MW_DMA_0) | |
252 | pio = 1; | |
253 | else | |
254 | pio = 4; | |
255 | ||
256 | /* Load the PIO timing active/recovery bits */ | |
257 | artop6210_load_piomode(ap, adev, pio); | |
258 | ||
259 | pci_read_config_byte(pdev, 0x54, &ultra); | |
260 | ultra &= ~(3 << (2 * dn)); | |
261 | ||
262 | /* Add ultra DMA bits if in UDMA mode */ | |
263 | if (adev->dma_mode >= XFER_UDMA_0) { | |
264 | u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock; | |
265 | if (mode == 0) | |
266 | mode = 1; | |
267 | ultra |= (mode << (2 * dn)); | |
268 | } | |
269 | pci_write_config_byte(pdev, 0x54, ultra); | |
270 | } | |
271 | ||
272 | /** | |
273 | * artop6260_set_dmamode - Initialize host controller PATA PIO timings | |
274 | * @ap: Port whose timings we are configuring | |
275 | * @adev: Device we are configuring | |
276 | * | |
277 | * Set DMA mode for device, in host controller PCI config space. The | |
278 | * ARTOP6260 and relatives store the timing data differently. | |
279 | * | |
280 | * LOCKING: | |
281 | * None (inherited from caller). | |
282 | */ | |
283 | ||
284 | static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
285 | { | |
286 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
287 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
288 | u8 ultra; | |
289 | ||
290 | if (adev->dma_mode == XFER_MW_DMA_0) | |
291 | pio = 1; | |
292 | else | |
293 | pio = 4; | |
294 | ||
295 | /* Load the PIO timing active/recovery bits */ | |
296 | artop6260_load_piomode(ap, adev, pio); | |
297 | ||
298 | /* Add ultra DMA bits if in UDMA mode */ | |
299 | pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); | |
300 | ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ | |
301 | if (adev->dma_mode >= XFER_UDMA_0) { | |
302 | u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock; | |
303 | if (mode == 0) | |
304 | mode = 1; | |
305 | ultra |= (mode << (4 * adev->devno)); | |
306 | } | |
307 | pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); | |
308 | } | |
309 | ||
310 | static struct scsi_host_template artop_sht = { | |
311 | .module = THIS_MODULE, | |
312 | .name = DRV_NAME, | |
313 | .ioctl = ata_scsi_ioctl, | |
314 | .queuecommand = ata_scsi_queuecmd, | |
315 | .can_queue = ATA_DEF_QUEUE, | |
316 | .this_id = ATA_SHT_THIS_ID, | |
317 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
318 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
319 | .emulated = ATA_SHT_EMULATED, | |
320 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
321 | .proc_name = DRV_NAME, | |
322 | .dma_boundary = ATA_DMA_BOUNDARY, | |
323 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 324 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
325 | .bios_param = ata_std_bios_param, |
326 | }; | |
327 | ||
328 | static const struct ata_port_operations artop6210_ops = { | |
329 | .port_disable = ata_port_disable, | |
330 | .set_piomode = artop6210_set_piomode, | |
331 | .set_dmamode = artop6210_set_dmamode, | |
332 | .mode_filter = ata_pci_default_filter, | |
333 | ||
334 | .tf_load = ata_tf_load, | |
335 | .tf_read = ata_tf_read, | |
336 | .check_status = ata_check_status, | |
337 | .exec_command = ata_exec_command, | |
338 | .dev_select = ata_std_dev_select, | |
339 | ||
340 | .freeze = ata_bmdma_freeze, | |
341 | .thaw = ata_bmdma_thaw, | |
342 | .error_handler = artop6210_error_handler, | |
343 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a73984a0 | 344 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
345 | |
346 | .bmdma_setup = ata_bmdma_setup, | |
347 | .bmdma_start = ata_bmdma_start, | |
348 | .bmdma_stop = ata_bmdma_stop, | |
349 | .bmdma_status = ata_bmdma_status, | |
350 | .qc_prep = ata_qc_prep, | |
351 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 352 | |
0d5ff566 | 353 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
354 | |
355 | .irq_handler = ata_interrupt, | |
356 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
357 | .irq_on = ata_irq_on, |
358 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
359 | |
360 | .port_start = ata_port_start, | |
669a5db4 JG |
361 | }; |
362 | ||
363 | static const struct ata_port_operations artop6260_ops = { | |
364 | .port_disable = ata_port_disable, | |
365 | .set_piomode = artop6260_set_piomode, | |
366 | .set_dmamode = artop6260_set_dmamode, | |
367 | ||
368 | .tf_load = ata_tf_load, | |
369 | .tf_read = ata_tf_read, | |
370 | .check_status = ata_check_status, | |
371 | .exec_command = ata_exec_command, | |
372 | .dev_select = ata_std_dev_select, | |
373 | ||
374 | .freeze = ata_bmdma_freeze, | |
375 | .thaw = ata_bmdma_thaw, | |
376 | .error_handler = artop6260_error_handler, | |
377 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a73984a0 | 378 | .cable_detect = artop6260_cable_detect, |
669a5db4 JG |
379 | |
380 | .bmdma_setup = ata_bmdma_setup, | |
381 | .bmdma_start = ata_bmdma_start, | |
382 | .bmdma_stop = ata_bmdma_stop, | |
383 | .bmdma_status = ata_bmdma_status, | |
384 | .qc_prep = ata_qc_prep, | |
385 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 386 | .data_xfer = ata_data_xfer, |
669a5db4 | 387 | |
669a5db4 JG |
388 | .irq_handler = ata_interrupt, |
389 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
390 | .irq_on = ata_irq_on, |
391 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
392 | |
393 | .port_start = ata_port_start, | |
669a5db4 JG |
394 | }; |
395 | ||
396 | ||
397 | /** | |
398 | * artop_init_one - Register ARTOP ATA PCI device with kernel services | |
399 | * @pdev: PCI device to register | |
400 | * @ent: Entry in artop_pci_tbl matching with @pdev | |
401 | * | |
402 | * Called from kernel PCI layer. | |
403 | * | |
404 | * LOCKING: | |
405 | * Inherited from PCI layer (may sleep). | |
406 | * | |
407 | * RETURNS: | |
408 | * Zero on success, or -ERRNO value. | |
409 | */ | |
410 | ||
411 | static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) | |
412 | { | |
413 | static int printed_version; | |
414 | static struct ata_port_info info_6210 = { | |
415 | .sht = &artop_sht, | |
416 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
417 | .pio_mask = 0x1f, /* pio0-4 */ | |
418 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
419 | .udma_mask = ATA_UDMA2, | |
420 | .port_ops = &artop6210_ops, | |
421 | }; | |
422 | static struct ata_port_info info_626x = { | |
423 | .sht = &artop_sht, | |
424 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
425 | .pio_mask = 0x1f, /* pio0-4 */ | |
426 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
427 | .udma_mask = ATA_UDMA4, | |
428 | .port_ops = &artop6260_ops, | |
429 | }; | |
430 | static struct ata_port_info info_626x_fast = { | |
431 | .sht = &artop_sht, | |
432 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
433 | .pio_mask = 0x1f, /* pio0-4 */ | |
434 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
435 | .udma_mask = ATA_UDMA5, | |
436 | .port_ops = &artop6260_ops, | |
437 | }; | |
438 | struct ata_port_info *port_info[2]; | |
15a7c3bb | 439 | struct ata_port_info *info = NULL; |
669a5db4 JG |
440 | int ports = 2; |
441 | ||
442 | if (!printed_version++) | |
443 | dev_printk(KERN_DEBUG, &pdev->dev, | |
444 | "version " DRV_VERSION "\n"); | |
445 | ||
446 | if (id->driver_data == 0) { /* 6210 variant */ | |
447 | info = &info_6210; | |
448 | /* BIOS may have left us in UDMA, clear it before libata probe */ | |
449 | pci_write_config_byte(pdev, 0x54, 0); | |
450 | /* For the moment (also lacks dsc) */ | |
451 | printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n"); | |
452 | printk(KERN_WARNING "Secondary ATA ports will not be activated.\n"); | |
453 | ports = 1; | |
454 | } | |
455 | else if (id->driver_data == 1) /* 6260 */ | |
456 | info = &info_626x; | |
457 | else if (id->driver_data == 2) { /* 6260 or 6260 + fast */ | |
458 | unsigned long io = pci_resource_start(pdev, 4); | |
459 | u8 reg; | |
460 | ||
461 | info = &info_626x; | |
462 | if (inb(io) & 0x10) | |
463 | info = &info_626x_fast; | |
464 | /* Mac systems come up with some registers not set as we | |
465 | will need them */ | |
466 | ||
467 | /* Clear reset & test bits */ | |
468 | pci_read_config_byte(pdev, 0x49, ®); | |
469 | pci_write_config_byte(pdev, 0x49, reg & ~ 0x30); | |
470 | ||
471 | /* PCI latency must be > 0x80 for burst mode, tweak it | |
472 | * if required. | |
473 | */ | |
474 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); | |
475 | if (reg <= 0x80) | |
476 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90); | |
477 | ||
478 | /* Enable IRQ output and burst mode */ | |
479 | pci_read_config_byte(pdev, 0x4a, ®); | |
480 | pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); | |
481 | ||
482 | } | |
15a7c3bb JG |
483 | |
484 | BUG_ON(info == NULL); | |
485 | ||
669a5db4 JG |
486 | port_info[0] = port_info[1] = info; |
487 | return ata_pci_init_one(pdev, port_info, ports); | |
488 | } | |
489 | ||
490 | static const struct pci_device_id artop_pci_tbl[] = { | |
2d2744fc JG |
491 | { PCI_VDEVICE(ARTOP, 0x0005), 0 }, |
492 | { PCI_VDEVICE(ARTOP, 0x0006), 1 }, | |
493 | { PCI_VDEVICE(ARTOP, 0x0007), 1 }, | |
494 | { PCI_VDEVICE(ARTOP, 0x0008), 2 }, | |
495 | { PCI_VDEVICE(ARTOP, 0x0009), 2 }, | |
496 | ||
669a5db4 JG |
497 | { } /* terminate list */ |
498 | }; | |
499 | ||
500 | static struct pci_driver artop_pci_driver = { | |
501 | .name = DRV_NAME, | |
502 | .id_table = artop_pci_tbl, | |
503 | .probe = artop_init_one, | |
504 | .remove = ata_pci_remove_one, | |
505 | }; | |
506 | ||
507 | static int __init artop_init(void) | |
508 | { | |
509 | return pci_register_driver(&artop_pci_driver); | |
510 | } | |
511 | ||
512 | static void __exit artop_exit(void) | |
513 | { | |
514 | pci_unregister_driver(&artop_pci_driver); | |
515 | } | |
516 | ||
669a5db4 JG |
517 | module_init(artop_init); |
518 | module_exit(artop_exit); | |
519 | ||
520 | MODULE_AUTHOR("Alan Cox"); | |
521 | MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA"); | |
522 | MODULE_LICENSE("GPL"); | |
523 | MODULE_DEVICE_TABLE(pci, artop_pci_tbl); | |
524 | MODULE_VERSION(DRV_VERSION); | |
525 |