Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_atiixp.c - ATI PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based on | |
7 | * | |
8 | * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004 | |
9 | * | |
10 | * Copyright (C) 2003 ATI Inc. <hyu@ati.com> | |
11 | * Copyright (C) 2004 Bartlomiej Zolnierkiewicz | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/blkdev.h> | |
20 | #include <linux/delay.h> | |
21 | #include <scsi/scsi_host.h> | |
22 | #include <linux/libata.h> | |
23 | ||
24 | #define DRV_NAME "pata_atiixp" | |
2a3103ce | 25 | #define DRV_VERSION "0.4.6" |
669a5db4 JG |
26 | |
27 | enum { | |
28 | ATIIXP_IDE_PIO_TIMING = 0x40, | |
29 | ATIIXP_IDE_MWDMA_TIMING = 0x44, | |
30 | ATIIXP_IDE_PIO_CONTROL = 0x48, | |
31 | ATIIXP_IDE_PIO_MODE = 0x4a, | |
32 | ATIIXP_IDE_UDMA_CONTROL = 0x54, | |
33 | ATIIXP_IDE_UDMA_MODE = 0x56 | |
34 | }; | |
35 | ||
cc0680a5 | 36 | static int atiixp_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 37 | { |
cc0680a5 | 38 | struct ata_port *ap = link->ap; |
54494f3a | 39 | static const struct pci_bits atiixp_enable_bits[] = { |
669a5db4 JG |
40 | { 0x48, 1, 0x01, 0x00 }, |
41 | { 0x48, 1, 0x08, 0x00 } | |
42 | }; | |
84708606 | 43 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 44 | |
c961922b AC |
45 | if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no])) |
46 | return -ENOENT; | |
47 | ||
9363c382 | 48 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
49 | } |
50 | ||
84708606 AC |
51 | static int atiixp_cable_detect(struct ata_port *ap) |
52 | { | |
53 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
54 | u8 udma; | |
55 | ||
56 | /* Hack from drivers/ide/pci. Really we want to know how to do the | |
57 | raw detection not play follow the bios mode guess */ | |
58 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); | |
59 | if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40) | |
60 | return ATA_CBL_PATA80; | |
61 | return ATA_CBL_PATA40; | |
62 | } | |
63 | ||
669a5db4 JG |
64 | /** |
65 | * atiixp_set_pio_timing - set initial PIO mode data | |
66 | * @ap: ATA interface | |
67 | * @adev: ATA device | |
68 | * | |
69 | * Called by both the pio and dma setup functions to set the controller | |
70 | * timings for PIO transfers. We must load both the mode number and | |
71 | * timing values into the controller. | |
72 | */ | |
73 | ||
74 | static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio) | |
75 | { | |
76 | static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 }; | |
77 | ||
78 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
79 | int dn = 2 * ap->port_no + adev->devno; | |
80 | ||
81 | /* Check this is correct - the order is odd in both drivers */ | |
82 | int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); | |
83 | u16 pio_mode_data, pio_timing_data; | |
84 | ||
85 | pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); | |
86 | pio_mode_data &= ~(0x7 << (4 * dn)); | |
87 | pio_mode_data |= pio << (4 * dn); | |
88 | pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data); | |
89 | ||
90 | pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); | |
d7b5a23f JG |
91 | pio_timing_data &= ~(0xFF << timing_shift); |
92 | pio_timing_data |= (pio_timings[pio] << timing_shift); | |
669a5db4 JG |
93 | pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); |
94 | } | |
95 | ||
96 | /** | |
97 | * atiixp_set_piomode - set initial PIO mode data | |
98 | * @ap: ATA interface | |
99 | * @adev: ATA device | |
100 | * | |
101 | * Called to do the PIO mode setup. We use a shared helper for this | |
102 | * as the DMA setup must also adjust the PIO timing information. | |
103 | */ | |
104 | ||
105 | static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
106 | { | |
107 | atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0); | |
108 | } | |
109 | ||
110 | /** | |
111 | * atiixp_set_dmamode - set initial DMA mode data | |
112 | * @ap: ATA interface | |
113 | * @adev: ATA device | |
114 | * | |
115 | * Called to do the DMA mode setup. We use timing tables for most | |
116 | * modes but must tune an appropriate PIO mode to match. | |
117 | */ | |
118 | ||
119 | static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
120 | { | |
121 | static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 }; | |
122 | ||
123 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
124 | int dma = adev->dma_mode; | |
125 | int dn = 2 * ap->port_no + adev->devno; | |
126 | int wanted_pio; | |
127 | ||
128 | if (adev->dma_mode >= XFER_UDMA_0) { | |
129 | u16 udma_mode_data; | |
130 | ||
131 | dma -= XFER_UDMA_0; | |
132 | ||
133 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data); | |
134 | udma_mode_data &= ~(0x7 << (4 * dn)); | |
135 | udma_mode_data |= dma << (4 * dn); | |
136 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data); | |
137 | } else { | |
138 | u16 mwdma_timing_data; | |
139 | /* Check this is correct - the order is odd in both drivers */ | |
140 | int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); | |
141 | ||
142 | dma -= XFER_MW_DMA_0; | |
143 | ||
144 | pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data); | |
145 | mwdma_timing_data &= ~(0xFF << timing_shift); | |
146 | mwdma_timing_data |= (mwdma_timings[dma] << timing_shift); | |
147 | pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data); | |
148 | } | |
149 | /* | |
150 | * We must now look at the PIO mode situation. We may need to | |
151 | * adjust the PIO mode to keep the timings acceptable | |
152 | */ | |
153 | if (adev->dma_mode >= XFER_MW_DMA_2) | |
154 | wanted_pio = 4; | |
155 | else if (adev->dma_mode == XFER_MW_DMA_1) | |
156 | wanted_pio = 3; | |
157 | else if (adev->dma_mode == XFER_MW_DMA_0) | |
158 | wanted_pio = 0; | |
159 | else BUG(); | |
160 | ||
161 | if (adev->pio_mode != wanted_pio) | |
162 | atiixp_set_pio_timing(ap, adev, wanted_pio); | |
163 | } | |
164 | ||
165 | /** | |
166 | * atiixp_bmdma_start - DMA start callback | |
167 | * @qc: Command in progress | |
168 | * | |
169 | * When DMA begins we need to ensure that the UDMA control | |
170 | * register for the channel is correctly set. | |
21d2c925 AC |
171 | * |
172 | * Note: The host lock held by the libata layer protects | |
173 | * us from two channels both trying to set DMA bits at once | |
669a5db4 JG |
174 | */ |
175 | ||
176 | static void atiixp_bmdma_start(struct ata_queued_cmd *qc) | |
177 | { | |
178 | struct ata_port *ap = qc->ap; | |
179 | struct ata_device *adev = qc->dev; | |
180 | ||
181 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
182 | int dn = (2 * ap->port_no) + adev->devno; | |
183 | u16 tmp16; | |
184 | ||
185 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
186 | if (adev->dma_mode >= XFER_UDMA_0) | |
187 | tmp16 |= (1 << dn); | |
188 | else | |
189 | tmp16 &= ~(1 << dn); | |
190 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
191 | ata_bmdma_start(qc); | |
192 | } | |
193 | ||
194 | /** | |
195 | * atiixp_dma_stop - DMA stop callback | |
196 | * @qc: Command in progress | |
197 | * | |
198 | * DMA has completed. Clear the UDMA flag as the next operations will | |
199 | * be PIO ones not UDMA data transfer. | |
21d2c925 AC |
200 | * |
201 | * Note: The host lock held by the libata layer protects | |
202 | * us from two channels both trying to set DMA bits at once | |
669a5db4 JG |
203 | */ |
204 | ||
205 | static void atiixp_bmdma_stop(struct ata_queued_cmd *qc) | |
206 | { | |
207 | struct ata_port *ap = qc->ap; | |
208 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
209 | int dn = (2 * ap->port_no) + qc->dev->devno; | |
210 | u16 tmp16; | |
211 | ||
212 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
213 | tmp16 &= ~(1 << dn); | |
214 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
215 | ata_bmdma_stop(qc); | |
216 | } | |
217 | ||
218 | static struct scsi_host_template atiixp_sht = { | |
68d1d07b | 219 | ATA_BMDMA_SHT(DRV_NAME), |
635adc28 | 220 | .sg_tablesize = LIBATA_DUMB_MAX_PRD, |
669a5db4 JG |
221 | }; |
222 | ||
223 | static struct ata_port_operations atiixp_port_ops = { | |
029cfd6b | 224 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 225 | |
9363c382 | 226 | .qc_prep = ata_sff_dumb_qc_prep, |
669a5db4 JG |
227 | .bmdma_start = atiixp_bmdma_start, |
228 | .bmdma_stop = atiixp_bmdma_stop, | |
bda30288 | 229 | |
029cfd6b TH |
230 | .cable_detect = atiixp_cable_detect, |
231 | .set_piomode = atiixp_set_piomode, | |
232 | .set_dmamode = atiixp_set_dmamode, | |
a1efdaba | 233 | .prereset = atiixp_pre_reset, |
669a5db4 JG |
234 | }; |
235 | ||
236 | static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
237 | { | |
1626aeb8 | 238 | static const struct ata_port_info info = { |
1d2808fd | 239 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
240 | .pio_mask = 0x1f, |
241 | .mwdma_mask = 0x06, /* No MWDMA0 support */ | |
242 | .udma_mask = 0x3F, | |
243 | .port_ops = &atiixp_port_ops | |
244 | }; | |
1626aeb8 | 245 | const struct ata_port_info *ppi[] = { &info, NULL }; |
9363c382 | 246 | return ata_pci_sff_init_one(dev, ppi, &atiixp_sht, NULL); |
669a5db4 JG |
247 | } |
248 | ||
2d2744fc JG |
249 | static const struct pci_device_id atiixp[] = { |
250 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), }, | |
251 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), }, | |
252 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), }, | |
253 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), }, | |
1ca972c2 | 254 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), }, |
2d2744fc JG |
255 | |
256 | { }, | |
669a5db4 JG |
257 | }; |
258 | ||
259 | static struct pci_driver atiixp_pci_driver = { | |
260 | .name = DRV_NAME, | |
261 | .id_table = atiixp, | |
262 | .probe = atiixp_init_one, | |
30ced0f0 | 263 | .remove = ata_pci_remove_one, |
438ac6d5 | 264 | #ifdef CONFIG_PM |
30ced0f0 A |
265 | .resume = ata_pci_device_resume, |
266 | .suspend = ata_pci_device_suspend, | |
438ac6d5 | 267 | #endif |
669a5db4 JG |
268 | }; |
269 | ||
270 | static int __init atiixp_init(void) | |
271 | { | |
272 | return pci_register_driver(&atiixp_pci_driver); | |
273 | } | |
274 | ||
275 | ||
276 | static void __exit atiixp_exit(void) | |
277 | { | |
278 | pci_unregister_driver(&atiixp_pci_driver); | |
279 | } | |
280 | ||
669a5db4 JG |
281 | MODULE_AUTHOR("Alan Cox"); |
282 | MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400"); | |
283 | MODULE_LICENSE("GPL"); | |
284 | MODULE_DEVICE_TABLE(pci, atiixp); | |
285 | MODULE_VERSION(DRV_VERSION); | |
286 | ||
287 | module_init(atiixp_init); | |
288 | module_exit(atiixp_exit); |