Commit | Line | Data |
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669a5db4 | 1 | /* |
fb9f8905 | 2 | * pata_cmd64x.c - CMD64x PATA for new ATA layer |
669a5db4 | 3 | * (C) 2005 Red Hat Inc |
ab771630 | 4 | * Alan Cox <alan@lxorguk.ukuu.org.uk> |
a2bd6220 | 5 | * (C) 2009-2010 Bartlomiej Zolnierkiewicz |
8a686bc9 | 6 | * (C) 2012 MontaVista Software, LLC <source@mvista.com> |
669a5db4 JG |
7 | * |
8 | * Based upon | |
9 | * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 | |
10 | * | |
11 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
12 | * Note, this driver is not used at all on other systems because | |
13 | * there the "BIOS" has done all of the following already. | |
14 | * Due to massive hardware bugs, UltraDMA is only supported | |
15 | * on the 646U2 and not on the 646U. | |
16 | * | |
17 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
18 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
19 | * | |
20 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
21 | * | |
22 | * TODO | |
23 | * Testing work | |
24 | */ | |
85cd7251 | 25 | |
669a5db4 JG |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
669a5db4 JG |
29 | #include <linux/blkdev.h> |
30 | #include <linux/delay.h> | |
31 | #include <scsi/scsi_host.h> | |
32 | #include <linux/libata.h> | |
33 | ||
34 | #define DRV_NAME "pata_cmd64x" | |
b8cec3c2 | 35 | #define DRV_VERSION "0.2.18" |
669a5db4 JG |
36 | |
37 | /* | |
38 | * CMD64x specific registers definition. | |
39 | */ | |
85cd7251 | 40 | |
669a5db4 JG |
41 | enum { |
42 | CFR = 0x50, | |
03a849e6 | 43 | CFR_INTR_CH0 = 0x04, |
9281b16c JB |
44 | CNTRL = 0x51, |
45 | CNTRL_CH0 = 0x04, | |
46 | CNTRL_CH1 = 0x08, | |
669a5db4 JG |
47 | CMDTIM = 0x52, |
48 | ARTTIM0 = 0x53, | |
49 | DRWTIM0 = 0x54, | |
50 | ARTTIM1 = 0x55, | |
51 | DRWTIM1 = 0x56, | |
52 | ARTTIM23 = 0x57, | |
53 | ARTTIM23_DIS_RA2 = 0x04, | |
54 | ARTTIM23_DIS_RA3 = 0x08, | |
55 | ARTTIM23_INTR_CH1 = 0x10, | |
669a5db4 JG |
56 | DRWTIM2 = 0x58, |
57 | BRST = 0x59, | |
58 | DRWTIM3 = 0x5b, | |
59 | BMIDECR0 = 0x70, | |
60 | MRDMODE = 0x71, | |
61 | MRDMODE_INTR_CH0 = 0x04, | |
62 | MRDMODE_INTR_CH1 = 0x08, | |
669a5db4 JG |
63 | BMIDESR0 = 0x72, |
64 | UDIDETCR0 = 0x73, | |
65 | DTPR0 = 0x74, | |
66 | BMIDECR1 = 0x78, | |
67 | BMIDECSR = 0x79, | |
669a5db4 JG |
68 | UDIDETCR1 = 0x7B, |
69 | DTPR1 = 0x7C | |
70 | }; | |
71 | ||
a73984a0 | 72 | static int cmd648_cable_detect(struct ata_port *ap) |
669a5db4 JG |
73 | { |
74 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
75 | u8 r; | |
76 | ||
77 | /* Check cable detect bits */ | |
78 | pci_read_config_byte(pdev, BMIDECSR, &r); | |
79 | if (r & (1 << ap->port_no)) | |
a73984a0 JG |
80 | return ATA_CBL_PATA80; |
81 | return ATA_CBL_PATA40; | |
669a5db4 JG |
82 | } |
83 | ||
84 | /** | |
57242762 | 85 | * cmd64x_set_timing - set PIO and MWDMA timing |
669a5db4 JG |
86 | * @ap: ATA interface |
87 | * @adev: ATA device | |
05d1efff | 88 | * @mode: mode |
669a5db4 | 89 | * |
05d1efff | 90 | * Called to do the PIO and MWDMA mode setup. |
669a5db4 | 91 | */ |
85cd7251 | 92 | |
05d1efff | 93 | static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) |
669a5db4 JG |
94 | { |
95 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
96 | struct ata_timing t; | |
97 | const unsigned long T = 1000000 / 33; | |
98 | const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; | |
85cd7251 | 99 | |
669a5db4 | 100 | u8 reg; |
85cd7251 | 101 | |
669a5db4 | 102 | /* Port layout is not logical so use a table */ |
85cd7251 | 103 | const u8 arttim_port[2][2] = { |
669a5db4 JG |
104 | { ARTTIM0, ARTTIM1 }, |
105 | { ARTTIM23, ARTTIM23 } | |
106 | }; | |
107 | const u8 drwtim_port[2][2] = { | |
108 | { DRWTIM0, DRWTIM1 }, | |
109 | { DRWTIM2, DRWTIM3 } | |
110 | }; | |
85cd7251 | 111 | |
669a5db4 JG |
112 | int arttim = arttim_port[ap->port_no][adev->devno]; |
113 | int drwtim = drwtim_port[ap->port_no][adev->devno]; | |
85cd7251 | 114 | |
05d1efff AC |
115 | /* ata_timing_compute is smart and will produce timings for MWDMA |
116 | that don't violate the drives PIO capabilities. */ | |
117 | if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { | |
669a5db4 JG |
118 | printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); |
119 | return; | |
120 | } | |
121 | if (ap->port_no) { | |
122 | /* Slave has shared address setup */ | |
123 | struct ata_device *pair = ata_dev_pair(adev); | |
85cd7251 | 124 | |
669a5db4 JG |
125 | if (pair) { |
126 | struct ata_timing tp; | |
127 | ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); | |
128 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
129 | } | |
130 | } | |
85cd7251 | 131 | |
669a5db4 JG |
132 | printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", |
133 | t.active, t.recover, t.setup); | |
134 | if (t.recover > 16) { | |
135 | t.active += t.recover - 16; | |
136 | t.recover = 16; | |
137 | } | |
138 | if (t.active > 16) | |
139 | t.active = 16; | |
85cd7251 | 140 | |
669a5db4 JG |
141 | /* Now convert the clocks into values we can actually stuff into |
142 | the chip */ | |
85cd7251 | 143 | |
a2bd6220 BZ |
144 | if (t.recover == 16) |
145 | t.recover = 0; | |
146 | else if (t.recover > 1) | |
669a5db4 JG |
147 | t.recover--; |
148 | else | |
149 | t.recover = 15; | |
85cd7251 | 150 | |
669a5db4 JG |
151 | if (t.setup > 4) |
152 | t.setup = 0xC0; | |
153 | else | |
154 | t.setup = setup_data[t.setup]; | |
85cd7251 | 155 | |
669a5db4 | 156 | t.active &= 0x0F; /* 0 = 16 */ |
85cd7251 | 157 | |
669a5db4 JG |
158 | /* Load setup timing */ |
159 | pci_read_config_byte(pdev, arttim, ®); | |
160 | reg &= 0x3F; | |
161 | reg |= t.setup; | |
162 | pci_write_config_byte(pdev, arttim, reg); | |
85cd7251 | 163 | |
669a5db4 | 164 | /* Load active/recovery */ |
85cd7251 | 165 | pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); |
669a5db4 JG |
166 | } |
167 | ||
05d1efff AC |
168 | /** |
169 | * cmd64x_set_piomode - set initial PIO mode data | |
170 | * @ap: ATA interface | |
171 | * @adev: ATA device | |
172 | * | |
173 | * Used when configuring the devices ot set the PIO timings. All the | |
174 | * actual work is done by the PIO/MWDMA setting helper | |
175 | */ | |
176 | ||
177 | static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
178 | { | |
179 | cmd64x_set_timing(ap, adev, adev->pio_mode); | |
180 | } | |
181 | ||
669a5db4 JG |
182 | /** |
183 | * cmd64x_set_dmamode - set initial DMA mode data | |
184 | * @ap: ATA interface | |
185 | * @adev: ATA device | |
186 | * | |
187 | * Called to do the DMA mode setup. | |
188 | */ | |
85cd7251 | 189 | |
669a5db4 JG |
190 | static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
191 | { | |
192 | static const u8 udma_data[] = { | |
6a40da02 | 193 | 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 |
669a5db4 | 194 | }; |
85cd7251 | 195 | |
669a5db4 JG |
196 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
197 | u8 regU, regD; | |
198 | ||
199 | int pciU = UDIDETCR0 + 8 * ap->port_no; | |
200 | int pciD = BMIDESR0 + 8 * ap->port_no; | |
201 | int shift = 2 * adev->devno; | |
85cd7251 | 202 | |
669a5db4 JG |
203 | pci_read_config_byte(pdev, pciD, ®D); |
204 | pci_read_config_byte(pdev, pciU, ®U); | |
205 | ||
6a40da02 A |
206 | /* DMA bits off */ |
207 | regD &= ~(0x20 << adev->devno); | |
208 | /* DMA control bits */ | |
209 | regU &= ~(0x30 << shift); | |
210 | /* DMA timing bits */ | |
211 | regU &= ~(0x05 << adev->devno); | |
85cd7251 | 212 | |
6a40da02 | 213 | if (adev->dma_mode >= XFER_UDMA_0) { |
24b7ce98 | 214 | /* Merge the timing value */ |
669a5db4 | 215 | regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; |
6a40da02 A |
216 | /* Merge the control bits */ |
217 | regU |= 1 << adev->devno; /* UDMA on */ | |
509426bd | 218 | if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ |
6a40da02 | 219 | regU |= 4 << adev->devno; |
05d1efff AC |
220 | } else { |
221 | regU &= ~ (1 << adev->devno); /* UDMA off */ | |
222 | cmd64x_set_timing(ap, adev, adev->dma_mode); | |
223 | } | |
669a5db4 JG |
224 | |
225 | regD |= 0x20 << adev->devno; | |
226 | ||
227 | pci_write_config_byte(pdev, pciU, regU); | |
228 | pci_write_config_byte(pdev, pciD, regD); | |
229 | } | |
230 | ||
b8cec3c2 SS |
231 | /** |
232 | * cmd64x_sff_irq_check - check IDE interrupt | |
233 | * @ap: ATA interface | |
234 | * | |
235 | * Check IDE interrupt in CFR/ARTTIM23 registers. | |
236 | */ | |
237 | ||
238 | static bool cmd64x_sff_irq_check(struct ata_port *ap) | |
239 | { | |
240 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
241 | int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; | |
242 | int irq_reg = ap->port_no ? ARTTIM23 : CFR; | |
243 | u8 irq_stat; | |
244 | ||
245 | /* NOTE: reading the register should clear the interrupt */ | |
246 | pci_read_config_byte(pdev, irq_reg, &irq_stat); | |
247 | ||
248 | return irq_stat & irq_mask; | |
249 | } | |
250 | ||
669a5db4 | 251 | /** |
419fd246 SS |
252 | * cmd64x_sff_irq_clear - clear IDE interrupt |
253 | * @ap: ATA interface | |
8a686bc9 | 254 | * |
419fd246 | 255 | * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers. |
8a686bc9 SS |
256 | */ |
257 | ||
419fd246 | 258 | static void cmd64x_sff_irq_clear(struct ata_port *ap) |
8a686bc9 | 259 | { |
8a686bc9 SS |
260 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
261 | int irq_reg = ap->port_no ? ARTTIM23 : CFR; | |
262 | u8 irq_stat; | |
263 | ||
419fd246 | 264 | ata_bmdma_irq_clear(ap); |
8a686bc9 SS |
265 | |
266 | /* Reading the register should be enough to clear the interrupt */ | |
267 | pci_read_config_byte(pdev, irq_reg, &irq_stat); | |
268 | } | |
269 | ||
b8cec3c2 SS |
270 | /** |
271 | * cmd648_sff_irq_check - check IDE interrupt | |
272 | * @ap: ATA interface | |
273 | * | |
274 | * Check IDE interrupt in MRDMODE register. | |
275 | */ | |
276 | ||
277 | static bool cmd648_sff_irq_check(struct ata_port *ap) | |
278 | { | |
279 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
280 | unsigned long base = pci_resource_start(pdev, 4); | |
281 | int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; | |
282 | u8 mrdmode = inb(base + 1); | |
283 | ||
284 | return mrdmode & irq_mask; | |
285 | } | |
286 | ||
8a686bc9 | 287 | /** |
419fd246 SS |
288 | * cmd648_sff_irq_clear - clear IDE interrupt |
289 | * @ap: ATA interface | |
669a5db4 | 290 | * |
419fd246 | 291 | * Clear IDE interrupt in MRDMODE and DMA status registers. |
669a5db4 JG |
292 | */ |
293 | ||
419fd246 | 294 | static void cmd648_sff_irq_clear(struct ata_port *ap) |
669a5db4 | 295 | { |
669a5db4 | 296 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
8a686bc9 SS |
297 | unsigned long base = pci_resource_start(pdev, 4); |
298 | int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; | |
299 | u8 mrdmode; | |
85cd7251 | 300 | |
419fd246 | 301 | ata_bmdma_irq_clear(ap); |
85cd7251 | 302 | |
8a686bc9 SS |
303 | /* Clear this port's interrupt bit (leaving the other port alone) */ |
304 | mrdmode = inb(base + 1); | |
305 | mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1); | |
306 | outb(mrdmode | irq_mask, base + 1); | |
669a5db4 | 307 | } |
85cd7251 | 308 | |
669a5db4 | 309 | /** |
8a686bc9 | 310 | * cmd646r1_bmdma_stop - DMA stop callback |
669a5db4 JG |
311 | * @qc: Command in progress |
312 | * | |
06393afd | 313 | * Stub for now while investigating the r1 quirk in the old driver. |
669a5db4 JG |
314 | */ |
315 | ||
06393afd | 316 | static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) |
669a5db4 JG |
317 | { |
318 | ata_bmdma_stop(qc); | |
319 | } | |
85cd7251 | 320 | |
669a5db4 | 321 | static struct scsi_host_template cmd64x_sht = { |
68d1d07b | 322 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
323 | }; |
324 | ||
029cfd6b TH |
325 | static const struct ata_port_operations cmd64x_base_ops = { |
326 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
327 | .set_piomode = cmd64x_set_piomode, |
328 | .set_dmamode = cmd64x_set_dmamode, | |
85cd7251 | 329 | }; |
669a5db4 | 330 | |
029cfd6b TH |
331 | static struct ata_port_operations cmd64x_port_ops = { |
332 | .inherits = &cmd64x_base_ops, | |
b8cec3c2 | 333 | .sff_irq_check = cmd64x_sff_irq_check, |
419fd246 | 334 | .sff_irq_clear = cmd64x_sff_irq_clear, |
a73984a0 | 335 | .cable_detect = ata_cable_40wire, |
029cfd6b | 336 | }; |
669a5db4 | 337 | |
029cfd6b TH |
338 | static struct ata_port_operations cmd646r1_port_ops = { |
339 | .inherits = &cmd64x_base_ops, | |
b8cec3c2 | 340 | .sff_irq_check = cmd64x_sff_irq_check, |
419fd246 | 341 | .sff_irq_clear = cmd64x_sff_irq_clear, |
06393afd | 342 | .bmdma_stop = cmd646r1_bmdma_stop, |
029cfd6b | 343 | .cable_detect = ata_cable_40wire, |
85cd7251 | 344 | }; |
669a5db4 | 345 | |
8a686bc9 SS |
346 | static struct ata_port_operations cmd646r3_port_ops = { |
347 | .inherits = &cmd64x_base_ops, | |
b8cec3c2 | 348 | .sff_irq_check = cmd648_sff_irq_check, |
419fd246 | 349 | .sff_irq_clear = cmd648_sff_irq_clear, |
8a686bc9 SS |
350 | .cable_detect = ata_cable_40wire, |
351 | }; | |
352 | ||
669a5db4 | 353 | static struct ata_port_operations cmd648_port_ops = { |
029cfd6b | 354 | .inherits = &cmd64x_base_ops, |
b8cec3c2 | 355 | .sff_irq_check = cmd648_sff_irq_check, |
419fd246 | 356 | .sff_irq_clear = cmd648_sff_irq_clear, |
029cfd6b | 357 | .cable_detect = cmd648_cable_detect, |
85cd7251 JG |
358 | }; |
359 | ||
f4c6ae50 BZ |
360 | static void cmd64x_fixup(struct pci_dev *pdev) |
361 | { | |
362 | u8 mrdmode; | |
363 | ||
364 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); | |
365 | pci_read_config_byte(pdev, MRDMODE, &mrdmode); | |
366 | mrdmode &= ~0x30; /* IRQ set up */ | |
367 | mrdmode |= 0x02; /* Memory read line enable */ | |
368 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | |
369 | ||
370 | /* PPC specific fixup copied from old driver */ | |
371 | #ifdef CONFIG_PPC | |
372 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | |
373 | #endif | |
374 | } | |
375 | ||
669a5db4 JG |
376 | static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
377 | { | |
8a686bc9 | 378 | static const struct ata_port_info cmd_info[7] = { |
669a5db4 | 379 | { /* CMD 643 - no UDMA */ |
1d2808fd | 380 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
381 | .pio_mask = ATA_PIO4, |
382 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
383 | .port_ops = &cmd64x_port_ops |
384 | }, | |
385 | { /* CMD 646 with broken UDMA */ | |
1d2808fd | 386 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
387 | .pio_mask = ATA_PIO4, |
388 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
389 | .port_ops = &cmd64x_port_ops |
390 | }, | |
8a686bc9 SS |
391 | { /* CMD 646U with broken UDMA */ |
392 | .flags = ATA_FLAG_SLAVE_POSS, | |
393 | .pio_mask = ATA_PIO4, | |
394 | .mwdma_mask = ATA_MWDMA2, | |
395 | .port_ops = &cmd646r3_port_ops | |
396 | }, | |
397 | { /* CMD 646U2 with working UDMA */ | |
1d2808fd | 398 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
399 | .pio_mask = ATA_PIO4, |
400 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 401 | .udma_mask = ATA_UDMA2, |
8a686bc9 | 402 | .port_ops = &cmd646r3_port_ops |
669a5db4 JG |
403 | }, |
404 | { /* CMD 646 rev 1 */ | |
1d2808fd | 405 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
406 | .pio_mask = ATA_PIO4, |
407 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
408 | .port_ops = &cmd646r1_port_ops |
409 | }, | |
410 | { /* CMD 648 */ | |
1d2808fd | 411 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
412 | .pio_mask = ATA_PIO4, |
413 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 414 | .udma_mask = ATA_UDMA4, |
669a5db4 JG |
415 | .port_ops = &cmd648_port_ops |
416 | }, | |
417 | { /* CMD 649 */ | |
1d2808fd | 418 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
419 | .pio_mask = ATA_PIO4, |
420 | .mwdma_mask = ATA_MWDMA2, | |
dbf0c89c | 421 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
422 | .port_ops = &cmd648_port_ops |
423 | } | |
424 | }; | |
641589bf | 425 | const struct ata_port_info *ppi[] = { |
9281b16c JB |
426 | &cmd_info[id->driver_data], |
427 | &cmd_info[id->driver_data], | |
428 | NULL | |
429 | }; | |
f4c6ae50 | 430 | u8 reg; |
f08048e9 | 431 | int rc; |
9281b16c JB |
432 | struct pci_dev *bridge = pdev->bus->self; |
433 | /* mobility split bridges don't report enabled ports correctly */ | |
434 | int port_ok = !(bridge && bridge->vendor == | |
435 | PCI_VENDOR_ID_MOBILITY_ELECTRONICS); | |
436 | /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */ | |
437 | int cntrl_ch0_ok = (id->driver_data != 0); | |
f08048e9 TH |
438 | |
439 | rc = pcim_enable_device(pdev); | |
440 | if (rc) | |
441 | return rc; | |
85cd7251 | 442 | |
669a5db4 | 443 | if (id->driver_data == 0) /* 643 */ |
9363c382 | 444 | ata_pci_bmdma_clear_simplex(pdev); |
85cd7251 | 445 | |
8fcfa7bd SS |
446 | if (pdev->device == PCI_DEVICE_ID_CMD_646) |
447 | switch (pdev->revision) { | |
448 | /* UDMA works since rev 5 */ | |
449 | default: | |
8a686bc9 SS |
450 | ppi[0] = &cmd_info[3]; |
451 | ppi[1] = &cmd_info[3]; | |
8fcfa7bd | 452 | break; |
8a686bc9 | 453 | /* Interrupts in MRDMODE since rev 3 */ |
8fcfa7bd SS |
454 | case 3: |
455 | case 4: | |
8a686bc9 SS |
456 | ppi[0] = &cmd_info[2]; |
457 | ppi[1] = &cmd_info[2]; | |
8fcfa7bd SS |
458 | break; |
459 | /* Rev 1 with other problems? */ | |
460 | case 1: | |
8a686bc9 SS |
461 | ppi[0] = &cmd_info[4]; |
462 | ppi[1] = &cmd_info[4]; | |
8fcfa7bd SS |
463 | /* FALL THRU */ |
464 | /* Early revs have no CNTRL_CH0 */ | |
465 | case 2: | |
466 | case 0: | |
9281b16c | 467 | cntrl_ch0_ok = 0; |
8fcfa7bd SS |
468 | break; |
469 | } | |
669a5db4 | 470 | |
f4c6ae50 | 471 | cmd64x_fixup(pdev); |
85cd7251 | 472 | |
9281b16c JB |
473 | /* check for enabled ports */ |
474 | pci_read_config_byte(pdev, CNTRL, ®); | |
475 | if (!port_ok) | |
a52f514c | 476 | dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n"); |
9281b16c | 477 | if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) { |
a52f514c | 478 | dev_notice(&pdev->dev, "Primary port is disabled\n"); |
9281b16c | 479 | ppi[0] = &ata_dummy_port_info; |
641589bf | 480 | |
9281b16c JB |
481 | } |
482 | if (port_ok && !(reg & CNTRL_CH1)) { | |
a52f514c | 483 | dev_notice(&pdev->dev, "Secondary port is disabled\n"); |
9281b16c JB |
484 | ppi[1] = &ata_dummy_port_info; |
485 | } | |
486 | ||
1c5afdf7 | 487 | return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); |
669a5db4 JG |
488 | } |
489 | ||
58eb8cd5 | 490 | #ifdef CONFIG_PM_SLEEP |
7f72a379 A |
491 | static int cmd64x_reinit_one(struct pci_dev *pdev) |
492 | { | |
0a86e1c8 | 493 | struct ata_host *host = pci_get_drvdata(pdev); |
f08048e9 TH |
494 | int rc; |
495 | ||
496 | rc = ata_pci_device_do_resume(pdev); | |
497 | if (rc) | |
498 | return rc; | |
499 | ||
f4c6ae50 BZ |
500 | cmd64x_fixup(pdev); |
501 | ||
f08048e9 TH |
502 | ata_host_resume(host); |
503 | return 0; | |
7f72a379 | 504 | } |
438ac6d5 | 505 | #endif |
7f72a379 | 506 | |
2d2744fc JG |
507 | static const struct pci_device_id cmd64x[] = { |
508 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, | |
509 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, | |
8a686bc9 SS |
510 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 }, |
511 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 }, | |
2d2744fc JG |
512 | |
513 | { }, | |
669a5db4 JG |
514 | }; |
515 | ||
516 | static struct pci_driver cmd64x_pci_driver = { | |
2d2744fc | 517 | .name = DRV_NAME, |
669a5db4 JG |
518 | .id_table = cmd64x, |
519 | .probe = cmd64x_init_one, | |
7f72a379 | 520 | .remove = ata_pci_remove_one, |
58eb8cd5 | 521 | #ifdef CONFIG_PM_SLEEP |
7f72a379 A |
522 | .suspend = ata_pci_device_suspend, |
523 | .resume = cmd64x_reinit_one, | |
438ac6d5 | 524 | #endif |
669a5db4 JG |
525 | }; |
526 | ||
2fc75da0 | 527 | module_pci_driver(cmd64x_pci_driver); |
669a5db4 | 528 | |
669a5db4 JG |
529 | MODULE_AUTHOR("Alan Cox"); |
530 | MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); | |
531 | MODULE_LICENSE("GPL"); | |
532 | MODULE_DEVICE_TABLE(pci, cmd64x); | |
533 | MODULE_VERSION(DRV_VERSION); |