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669a5db4 JG |
1 | /* |
2 | * IDE tuning and bus mastering support for the CS5510/CS5520 | |
3 | * chipsets | |
4 | * | |
5 | * The CS5510/CS5520 are slightly unusual devices. Unlike the | |
6 | * typical IDE controllers they do bus mastering with the drive in | |
7 | * PIO mode and smarter silicon. | |
8 | * | |
9 | * The practical upshot of this is that we must always tune the | |
10 | * drive for the right PIO mode. We must also ignore all the blacklists | |
11 | * and the drive bus mastering DMA information. Also to confuse matters | |
12 | * further we can do DMA on PIO only drives. | |
13 | * | |
14 | * DMA on the 5510 also requires we disable_hlt() during DMA on early | |
15 | * revisions. | |
16 | * | |
17 | * *** This driver is strictly experimental *** | |
18 | * | |
19 | * (c) Copyright Red Hat Inc 2002 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify it | |
22 | * under the terms of the GNU General Public License as published by the | |
23 | * Free Software Foundation; either version 2, or (at your option) any | |
24 | * later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, but | |
27 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
29 | * General Public License for more details. | |
30 | * | |
31 | * Documentation: | |
32 | * Not publically available. | |
33 | */ | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <scsi/scsi_host.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "pata_cs5520" | |
cb48cab7 | 44 | #define DRV_VERSION "0.6.4" |
669a5db4 JG |
45 | |
46 | struct pio_clocks | |
47 | { | |
48 | int address; | |
49 | int assert; | |
50 | int recovery; | |
51 | }; | |
52 | ||
53 | static const struct pio_clocks cs5520_pio_clocks[]={ | |
54 | {3, 6, 11}, | |
55 | {2, 5, 6}, | |
56 | {1, 4, 3}, | |
57 | {1, 3, 2}, | |
58 | {1, 2, 1} | |
59 | }; | |
60 | ||
61 | /** | |
62 | * cs5520_set_timings - program PIO timings | |
63 | * @ap: ATA port | |
64 | * @adev: ATA device | |
65 | * | |
66 | * Program the PIO mode timings for the controller according to the pio | |
67 | * clocking table. | |
68 | */ | |
69 | ||
70 | static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) | |
71 | { | |
72 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
73 | int slave = adev->devno; | |
74 | ||
75 | pio -= XFER_PIO_0; | |
76 | ||
77 | /* Channel command timing */ | |
78 | pci_write_config_byte(pdev, 0x62 + ap->port_no, | |
79 | (cs5520_pio_clocks[pio].recovery << 4) | | |
80 | (cs5520_pio_clocks[pio].assert)); | |
81 | /* FIXME: should these use address ? */ | |
82 | /* Read command timing */ | |
83 | pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave, | |
84 | (cs5520_pio_clocks[pio].recovery << 4) | | |
85 | (cs5520_pio_clocks[pio].assert)); | |
86 | /* Write command timing */ | |
87 | pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave, | |
88 | (cs5520_pio_clocks[pio].recovery << 4) | | |
89 | (cs5520_pio_clocks[pio].assert)); | |
90 | } | |
91 | ||
92 | /** | |
93 | * cs5520_enable_dma - turn on DMA bits | |
94 | * | |
95 | * Turn on the DMA bits for this disk. Needed because the BIOS probably | |
96 | * has not done the work for us. Belongs in the core SATA code. | |
97 | */ | |
98 | ||
99 | static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) | |
100 | { | |
101 | /* Set the DMA enable/disable flag */ | |
0d5ff566 | 102 | u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02); |
669a5db4 | 103 | reg |= 1<<(adev->devno + 5); |
0d5ff566 | 104 | iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02); |
669a5db4 JG |
105 | } |
106 | ||
107 | /** | |
108 | * cs5520_set_dmamode - program DMA timings | |
109 | * @ap: ATA port | |
110 | * @adev: ATA device | |
111 | * | |
112 | * Program the DMA mode timings for the controller according to the pio | |
113 | * clocking table. Note that this device sets the DMA timings to PIO | |
114 | * mode values. This may seem bizarre but the 5520 architecture talks | |
115 | * PIO mode to the disk and DMA mode to the controller so the underlying | |
116 | * transfers are PIO timed. | |
117 | */ | |
118 | ||
119 | static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
120 | { | |
121 | static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; | |
122 | cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]); | |
123 | cs5520_enable_dma(ap, adev); | |
124 | } | |
125 | ||
126 | /** | |
127 | * cs5520_set_piomode - program PIO timings | |
128 | * @ap: ATA port | |
129 | * @adev: ATA device | |
130 | * | |
131 | * Program the PIO mode timings for the controller according to the pio | |
132 | * clocking table. We know pio_mode will equal dma_mode because of the | |
133 | * CS5520 architecture. At least once we turned DMA on and wrote a | |
134 | * mode setter. | |
135 | */ | |
136 | ||
137 | static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
138 | { | |
139 | cs5520_set_timings(ap, adev, adev->pio_mode); | |
140 | } | |
141 | ||
669a5db4 JG |
142 | static struct scsi_host_template cs5520_sht = { |
143 | .module = THIS_MODULE, | |
144 | .name = DRV_NAME, | |
145 | .ioctl = ata_scsi_ioctl, | |
146 | .queuecommand = ata_scsi_queuecmd, | |
147 | .can_queue = ATA_DEF_QUEUE, | |
148 | .this_id = ATA_SHT_THIS_ID, | |
149 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
150 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
151 | .emulated = ATA_SHT_EMULATED, | |
152 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
153 | .proc_name = DRV_NAME, | |
154 | .dma_boundary = ATA_DMA_BOUNDARY, | |
155 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 156 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 | 157 | .bios_param = ata_std_bios_param, |
438ac6d5 | 158 | #ifdef CONFIG_PM |
8501120f A |
159 | .resume = ata_scsi_device_resume, |
160 | .suspend = ata_scsi_device_suspend, | |
438ac6d5 | 161 | #endif |
669a5db4 JG |
162 | }; |
163 | ||
164 | static struct ata_port_operations cs5520_port_ops = { | |
165 | .port_disable = ata_port_disable, | |
166 | .set_piomode = cs5520_set_piomode, | |
167 | .set_dmamode = cs5520_set_dmamode, | |
168 | ||
169 | .tf_load = ata_tf_load, | |
170 | .tf_read = ata_tf_read, | |
171 | .check_status = ata_check_status, | |
172 | .exec_command = ata_exec_command, | |
173 | .dev_select = ata_std_dev_select, | |
174 | ||
175 | .freeze = ata_bmdma_freeze, | |
176 | .thaw = ata_bmdma_thaw, | |
a73984a0 | 177 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 178 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 179 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
180 | |
181 | .bmdma_setup = ata_bmdma_setup, | |
182 | .bmdma_start = ata_bmdma_start, | |
183 | .bmdma_stop = ata_bmdma_stop, | |
184 | .bmdma_status = ata_bmdma_status, | |
185 | .qc_prep = ata_qc_prep, | |
186 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 187 | .data_xfer = ata_data_xfer, |
669a5db4 | 188 | |
669a5db4 | 189 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 AI |
190 | .irq_on = ata_irq_on, |
191 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
192 | |
193 | .port_start = ata_port_start, | |
669a5db4 JG |
194 | }; |
195 | ||
5d728824 | 196 | static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
669a5db4 | 197 | { |
5d728824 TH |
198 | struct ata_port_info pi = { |
199 | .flags = ATA_FLAG_SLAVE_POSS, | |
200 | .pio_mask = 0x1f, | |
201 | .port_ops = &cs5520_port_ops, | |
202 | }; | |
203 | const struct ata_port_info *ppi[2]; | |
669a5db4 | 204 | u8 pcicfg; |
5d728824 TH |
205 | void *iomap[5]; |
206 | struct ata_host *host; | |
207 | struct ata_ioports *ioaddr; | |
208 | int i, rc; | |
669a5db4 JG |
209 | |
210 | /* IDE port enable bits */ | |
5d728824 | 211 | pci_read_config_byte(pdev, 0x60, &pcicfg); |
669a5db4 JG |
212 | |
213 | /* Check if the ATA ports are enabled */ | |
214 | if ((pcicfg & 3) == 0) | |
215 | return -ENODEV; | |
216 | ||
5d728824 TH |
217 | ppi[0] = ppi[1] = &ata_dummy_port_info; |
218 | if (pcicfg & 1) | |
219 | ppi[0] = π | |
220 | if (pcicfg & 2) | |
221 | ppi[1] = π | |
222 | ||
669a5db4 | 223 | if ((pcicfg & 0x40) == 0) { |
5d728824 TH |
224 | dev_printk(KERN_WARNING, &pdev->dev, |
225 | "DMA mode disabled. Enabling.\n"); | |
226 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); | |
669a5db4 JG |
227 | } |
228 | ||
5d728824 TH |
229 | pi.mwdma_mask = id->driver_data; |
230 | ||
231 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
232 | if (!host) | |
233 | return -ENOMEM; | |
234 | ||
669a5db4 | 235 | /* Perform set up for DMA */ |
5d728824 | 236 | if (pci_enable_device_bars(pdev, 1<<2)) { |
669a5db4 JG |
237 | printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); |
238 | return -ENODEV; | |
239 | } | |
5d728824 TH |
240 | |
241 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
669a5db4 JG |
242 | printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); |
243 | return -ENODEV; | |
244 | } | |
5d728824 | 245 | if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { |
669a5db4 JG |
246 | printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); |
247 | return -ENODEV; | |
248 | } | |
249 | ||
5d728824 TH |
250 | /* Map IO ports and initialize host accordingly */ |
251 | iomap[0] = devm_ioport_map(&pdev->dev, 0x1F0, 8); | |
252 | iomap[1] = devm_ioport_map(&pdev->dev, 0x3F6, 1); | |
253 | iomap[2] = devm_ioport_map(&pdev->dev, 0x170, 8); | |
254 | iomap[3] = devm_ioport_map(&pdev->dev, 0x376, 1); | |
255 | iomap[4] = pcim_iomap(pdev, 2, 0); | |
0d5ff566 TH |
256 | |
257 | if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) | |
258 | return -ENOMEM; | |
259 | ||
5d728824 TH |
260 | ioaddr = &host->ports[0]->ioaddr; |
261 | ioaddr->cmd_addr = iomap[0]; | |
262 | ioaddr->ctl_addr = iomap[1]; | |
263 | ioaddr->altstatus_addr = iomap[1]; | |
264 | ioaddr->bmdma_addr = iomap[4]; | |
265 | ata_std_ports(ioaddr); | |
266 | ||
267 | ioaddr = &host->ports[1]->ioaddr; | |
268 | ioaddr->cmd_addr = iomap[2]; | |
269 | ioaddr->ctl_addr = iomap[3]; | |
270 | ioaddr->altstatus_addr = iomap[3]; | |
271 | ioaddr->bmdma_addr = iomap[4] + 8; | |
272 | ata_std_ports(ioaddr); | |
273 | ||
274 | /* activate the host */ | |
275 | pci_set_master(pdev); | |
276 | rc = ata_host_start(host); | |
277 | if (rc) | |
278 | return rc; | |
279 | ||
280 | for (i = 0; i < 2; i++) { | |
281 | static const int irq[] = { 14, 15 }; | |
282 | struct ata_port *ap = host->ports[0]; | |
283 | ||
284 | if (ata_port_is_dummy(ap)) | |
285 | continue; | |
286 | ||
287 | rc = devm_request_irq(&pdev->dev, irq[ap->port_no], | |
288 | ata_interrupt, 0, DRV_NAME, host); | |
289 | if (rc) | |
290 | return rc; | |
291 | } | |
292 | ||
293 | return ata_host_register(host, &cs5520_sht); | |
669a5db4 JG |
294 | } |
295 | ||
296 | /** | |
297 | * cs5520_remove_one - device unload | |
298 | * @pdev: PCI device being removed | |
299 | * | |
300 | * Handle an unplug/unload event for a PCI device. Unload the | |
301 | * PCI driver but do not use the default handler as we manage | |
302 | * resources ourself and *MUST NOT* disable the device as it has | |
303 | * other functions. | |
304 | */ | |
305 | ||
306 | static void __devexit cs5520_remove_one(struct pci_dev *pdev) | |
307 | { | |
308 | struct device *dev = pci_dev_to_dev(pdev); | |
309 | struct ata_host *host = dev_get_drvdata(dev); | |
310 | ||
24dc5f33 | 311 | ata_host_detach(host); |
669a5db4 JG |
312 | } |
313 | ||
438ac6d5 | 314 | #ifdef CONFIG_PM |
8501120f A |
315 | /** |
316 | * cs5520_reinit_one - device resume | |
317 | * @pdev: PCI device | |
318 | * | |
319 | * Do any reconfiguration work needed by a resume from RAM. We need | |
320 | * to restore DMA mode support on BIOSen which disabled it | |
321 | */ | |
f20b16ff | 322 | |
8501120f A |
323 | static int cs5520_reinit_one(struct pci_dev *pdev) |
324 | { | |
325 | u8 pcicfg; | |
326 | pci_read_config_byte(pdev, 0x60, &pcicfg); | |
327 | if ((pcicfg & 0x40) == 0) | |
328 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); | |
329 | return ata_pci_device_resume(pdev); | |
330 | } | |
aa6de494 A |
331 | |
332 | /** | |
333 | * cs5520_pci_device_suspend - device suspend | |
334 | * @pdev: PCI device | |
335 | * | |
336 | * We have to cut and waste bits from the standard method because | |
337 | * the 5520 is a bit odd and not just a pure ATA device. As a result | |
338 | * we must not disable it. The needed code is short and this avoids | |
339 | * chip specific mess in the core code. | |
340 | */ | |
341 | ||
342 | static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
343 | { | |
344 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
345 | int rc = 0; | |
346 | ||
347 | rc = ata_host_suspend(host, mesg); | |
348 | if (rc) | |
349 | return rc; | |
350 | ||
351 | pci_save_state(pdev); | |
352 | return 0; | |
353 | } | |
438ac6d5 | 354 | #endif /* CONFIG_PM */ |
a84471fe | 355 | |
669a5db4 JG |
356 | /* For now keep DMA off. We can set it for all but A rev CS5510 once the |
357 | core ATA code can handle it */ | |
358 | ||
2d2744fc JG |
359 | static const struct pci_device_id pata_cs5520[] = { |
360 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, | |
361 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, | |
362 | ||
363 | { }, | |
669a5db4 JG |
364 | }; |
365 | ||
366 | static struct pci_driver cs5520_pci_driver = { | |
367 | .name = DRV_NAME, | |
368 | .id_table = pata_cs5520, | |
369 | .probe = cs5520_init_one, | |
8501120f | 370 | .remove = cs5520_remove_one, |
438ac6d5 | 371 | #ifdef CONFIG_PM |
aa6de494 | 372 | .suspend = cs5520_pci_device_suspend, |
8501120f | 373 | .resume = cs5520_reinit_one, |
438ac6d5 | 374 | #endif |
669a5db4 JG |
375 | }; |
376 | ||
669a5db4 JG |
377 | static int __init cs5520_init(void) |
378 | { | |
379 | return pci_register_driver(&cs5520_pci_driver); | |
380 | } | |
381 | ||
382 | static void __exit cs5520_exit(void) | |
383 | { | |
384 | pci_unregister_driver(&cs5520_pci_driver); | |
385 | } | |
386 | ||
387 | MODULE_AUTHOR("Alan Cox"); | |
388 | MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520"); | |
389 | MODULE_LICENSE("GPL"); | |
390 | MODULE_DEVICE_TABLE(pci, pata_cs5520); | |
391 | MODULE_VERSION(DRV_VERSION); | |
392 | ||
393 | module_init(cs5520_init); | |
394 | module_exit(cs5520_exit); | |
395 |