[deliverable/linux.git] / drivers / ata / pata_cs5520.c

/*
 *	IDE tuning and bus mastering support for the CS5510/CS5520
 *	chipsets
 *
 *	The CS5510/CS5520 are slightly unusual devices. Unlike the
 *	typical IDE controllers they do bus mastering with the drive in
 *	PIO mode and smarter silicon.
 *
 *	The practical upshot of this is that we must always tune the
 *	drive for the right PIO mode. We must also ignore all the blacklists
 *	and the drive bus mastering DMA information. Also to confuse matters
 *	further we can do DMA on PIO only drives.
 *
 *	DMA on the 5510 also requires we disable_hlt() during DMA on early
 *	revisions.
 *
 *	*** This driver is strictly experimental ***
 *
 *	(c) Copyright Red Hat Inc 2002
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * Documentation:
 *	Not publically available.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_cs5520"
#define DRV_VERSION	"0.6.6"

struct pio_clocks
{
	int address;
	int assert;
	int recovery;
};

static const struct pio_clocks cs5520_pio_clocks[]={
	{3, 6, 11},
	{2, 5, 6},
	{1, 4, 3},
	{1, 3, 2},
	{1, 2, 1}
};

/**
 *	cs5520_set_timings	-	program PIO timings
 *	@ap: ATA port
 *	@adev: ATA device
 *
 *	Program the PIO mode timings for the controller according to the pio
 *	clocking table.
 */

static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int slave = adev->devno;

	pio -= XFER_PIO_0;

	/* Channel command timing */
	pci_write_config_byte(pdev, 0x62 + ap->port_no,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
	/* FIXME: should these use address ? */
	/* Read command timing */
	pci_write_config_byte(pdev, 0x64 +  4*ap->port_no + slave,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
	/* Write command timing */
	pci_write_config_byte(pdev, 0x66 +  4*ap->port_no + slave,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
}

/**
 *	cs5520_enable_dma	-	turn on DMA bits
 *
 *	Turn on the DMA bits for this disk. Needed because the BIOS probably
 *	has not done the work for us. Belongs in the core SATA code.
 */

static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
{
	/* Set the DMA enable/disable flag */
	u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02);
	reg |= 1<<(adev->devno + 5);
	iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02);
}

/**
 *	cs5520_set_dmamode	-	program DMA timings
 *	@ap: ATA port
 *	@adev: ATA device
 *
 *	Program the DMA mode timings for the controller according to the pio
 *	clocking table. Note that this device sets the DMA timings to PIO
 *	mode values. This may seem bizarre but the 5520 architecture talks
 *	PIO mode to the disk and DMA mode to the controller so the underlying
 *	transfers are PIO timed.
 */

static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
	cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
	cs5520_enable_dma(ap, adev);
}

/**
 *	cs5520_set_piomode	-	program PIO timings
 *	@ap: ATA port
 *	@adev: ATA device
 *
 *	Program the PIO mode timings for the controller according to the pio
 *	clocking table. We know pio_mode will equal dma_mode because of the
 *	CS5520 architecture. At least once we turned DMA on and wrote a
 *	mode setter.
 */

static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cs5520_set_timings(ap, adev, adev->pio_mode);
}

static struct scsi_host_template cs5520_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
};

static struct ata_port_operations cs5520_port_ops = {
	.set_piomode		= cs5520_set_piomode,
	.set_dmamode		= cs5520_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_dumb_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,

	.port_start		= ata_sff_port_start,
};

static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
	static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
	struct ata_port_info pi = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,
		.port_ops	= &cs5520_port_ops,
	};
	const struct ata_port_info *ppi[2];
	u8 pcicfg;
	void __iomem *iomap[5];
	struct ata_host *host;
	struct ata_ioports *ioaddr;
	int i, rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* IDE port enable bits */
	pci_read_config_byte(pdev, 0x60, &pcicfg);

	/* Check if the ATA ports are enabled */
	if ((pcicfg & 3) == 0)
		return -ENODEV;

	ppi[0] = ppi[1] = &ata_dummy_port_info;
	if (pcicfg & 1)
		ppi[0] = &pi;
	if (pcicfg & 2)
		ppi[1] = &pi;

	if ((pcicfg & 0x40) == 0) {
		dev_printk(KERN_WARNING, &pdev->dev,
			   "DMA mode disabled. Enabling.\n");
		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
	}

	pi.mwdma_mask = id->driver_data;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;

	/* Perform set up for DMA */
	if (pci_enable_device_io(pdev)) {
		printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
		return -ENODEV;
	}

	if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
		printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
		return -ENODEV;
	}
	if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
		printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
		return -ENODEV;
	}

	/* Map IO ports and initialize host accordingly */
	iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
	iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
	iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
	iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
	iomap[4] = pcim_iomap(pdev, 2, 0);

	if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
		return -ENOMEM;

	ioaddr = &host->ports[0]->ioaddr;
	ioaddr->cmd_addr = iomap[0];
	ioaddr->ctl_addr = iomap[1];
	ioaddr->altstatus_addr = iomap[1];
	ioaddr->bmdma_addr = iomap[4];
	ata_std_ports(ioaddr);

	ata_port_desc(host->ports[0],
		      "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
	ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");

	ioaddr = &host->ports[1]->ioaddr;
	ioaddr->cmd_addr = iomap[2];
	ioaddr->ctl_addr = iomap[3];
	ioaddr->altstatus_addr = iomap[3];
	ioaddr->bmdma_addr = iomap[4] + 8;
	ata_std_ports(ioaddr);

	ata_port_desc(host->ports[1],
		      "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
	ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");

	/* activate the host */
	pci_set_master(pdev);
	rc = ata_host_start(host);
	if (rc)
		return rc;

	for (i = 0; i < 2; i++) {
		static const int irq[] = { 14, 15 };
		struct ata_port *ap = host->ports[i];

		if (ata_port_is_dummy(ap))
			continue;

		rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
				      ata_interrupt, 0, DRV_NAME, host);
		if (rc)
			return rc;

		ata_port_desc(ap, "irq %d", irq[i]);
	}

	return ata_host_register(host, &cs5520_sht);
}

#ifdef CONFIG_PM
/**
 *	cs5520_reinit_one	-	device resume
 *	@pdev: PCI device
 *
 *	Do any reconfiguration work needed by a resume from RAM. We need
 *	to restore DMA mode support on BIOSen which disabled it
 */

static int cs5520_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	u8 pcicfg;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	pci_read_config_byte(pdev, 0x60, &pcicfg);
	if ((pcicfg & 0x40) == 0)
		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);

	ata_host_resume(host);
	return 0;
}

/**
 *	cs5520_pci_device_suspend	-	device suspend
 *	@pdev: PCI device
 *
 *	We have to cut and waste bits from the standard method because
 *	the 5520 is a bit odd and not just a pure ATA device. As a result
 *	we must not disable it. The needed code is short and this avoids
 *	chip specific mess in the core code.
 */

static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc = 0;

	rc = ata_host_suspend(host, mesg);
	if (rc)
		return rc;

	pci_save_state(pdev);
	return 0;
}
#endif /* CONFIG_PM */

/* For now keep DMA off. We can set it for all but A rev CS5510 once the
   core ATA code can handle it */

static const struct pci_device_id pata_cs5520[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },

	{ },
};

static struct pci_driver cs5520_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pata_cs5520,
	.probe 		= cs5520_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= cs5520_pci_device_suspend,
	.resume		= cs5520_reinit_one,
#endif
};

static int __init cs5520_init(void)
{
	return pci_register_driver(&cs5520_pci_driver);
}

static void __exit cs5520_exit(void)
{
	pci_unregister_driver(&cs5520_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pata_cs5520);
MODULE_VERSION(DRV_VERSION);

module_init(cs5520_init);
module_exit(cs5520_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* IDE tuning and bus mastering support for the CS5510/CS5520
	3	* chipsets
	4	*
	5	* The CS5510/CS5520 are slightly unusual devices. Unlike the
	6	* typical IDE controllers they do bus mastering with the drive in
	7	* PIO mode and smarter silicon.
	8	*
	9	* The practical upshot of this is that we must always tune the
	10	* drive for the right PIO mode. We must also ignore all the blacklists
	11	* and the drive bus mastering DMA information. Also to confuse matters
	12	* further we can do DMA on PIO only drives.
	13	*
	14	* DMA on the 5510 also requires we disable_hlt() during DMA on early
	15	* revisions.
	16	*
	17	* * This driver is strictly experimental *
	18	*
	19	* (c) Copyright Red Hat Inc 2002
	20	*
	21	* This program is free software; you can redistribute it and/or modify it
	22	* under the terms of the GNU General Public License as published by the
	23	* Free Software Foundation; either version 2, or (at your option) any
	24	* later version.
	25	*
	26	* This program is distributed in the hope that it will be useful, but
	27	* WITHOUT ANY WARRANTY; without even the implied warranty of
	28	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	29	* General Public License for more details.
	30	*
	31	* Documentation:
	32	* Not publically available.
	33	*/
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_cs5520"
2a3103ce	44	#define DRV_VERSION "0.6.6"
669a5db4 JG	45
	46	struct pio_clocks
	47	{
	48	int address;
	49	int assert;
	50	int recovery;
	51	};
	52
	53	static const struct pio_clocks cs5520_pio_clocks[]={
	54	{3, 6, 11},
	55	{2, 5, 6},
	56	{1, 4, 3},
	57	{1, 3, 2},
	58	{1, 2, 1}
	59	};
	60
	61	/**
	62	* cs5520_set_timings - program PIO timings
	63	* @ap: ATA port
	64	* @adev: ATA device
	65	*
	66	* Program the PIO mode timings for the controller according to the pio
	67	* clocking table.
	68	*/
	69
	70	static void cs5520_set_timings(struct ata_port ap, struct ata_device adev, int pio)
	71	{
	72	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	73	int slave = adev->devno;
	74
	75	pio -= XFER_PIO_0;
	76
	77	/* Channel command timing */
	78	pci_write_config_byte(pdev, 0x62 + ap->port_no,
	79	(cs5520_pio_clocks[pio].recovery << 4) \|
	80	(cs5520_pio_clocks[pio].assert));
	81	/* FIXME: should these use address ? */
	82	/* Read command timing */
	83	pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
	84	(cs5520_pio_clocks[pio].recovery << 4) \|
	85	(cs5520_pio_clocks[pio].assert));
	86	/* Write command timing */
	87	pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
	88	(cs5520_pio_clocks[pio].recovery << 4) \|
	89	(cs5520_pio_clocks[pio].assert));
	90	}
	91
	92	/**
	93	* cs5520_enable_dma - turn on DMA bits
	94	*
	95	* Turn on the DMA bits for this disk. Needed because the BIOS probably
	96	* has not done the work for us. Belongs in the core SATA code.
	97	*/
	98
	99	static void cs5520_enable_dma(struct ata_port ap, struct ata_device adev)
	100	{
	101	/* Set the DMA enable/disable flag */
0d5ff566	102	u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02);
669a5db4	103	reg \|= 1<<(adev->devno + 5);
0d5ff566	104	iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02);
669a5db4 JG	105	}
	106
	107	/**
	108	* cs5520_set_dmamode - program DMA timings
	109	* @ap: ATA port
	110	* @adev: ATA device
	111	*
	112	* Program the DMA mode timings for the controller according to the pio
	113	* clocking table. Note that this device sets the DMA timings to PIO
	114	* mode values. This may seem bizarre but the 5520 architecture talks
	115	* PIO mode to the disk and DMA mode to the controller so the underlying
	116	* transfers are PIO timed.
	117	*/
	118
	119	static void cs5520_set_dmamode(struct ata_port ap, struct ata_device adev)
	120	{
	121	static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
	122	cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
	123	cs5520_enable_dma(ap, adev);
	124	}
	125
	126	/**
	127	* cs5520_set_piomode - program PIO timings
	128	* @ap: ATA port
	129	* @adev: ATA device
	130	*
	131	* Program the PIO mode timings for the controller according to the pio
	132	* clocking table. We know pio_mode will equal dma_mode because of the
	133	* CS5520 architecture. At least once we turned DMA on and wrote a
	134	* mode setter.
	135	*/
	136
	137	static void cs5520_set_piomode(struct ata_port ap, struct ata_device adev)
	138	{
	139	cs5520_set_timings(ap, adev, adev->pio_mode);
	140	}
	141
669a5db4	142	static struct scsi_host_template cs5520_sht = {
68d1d07b	143	ATA_BMDMA_SHT(DRV_NAME),
d26fc955	144	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
669a5db4 JG	145	};
	146
	147	static struct ata_port_operations cs5520_port_ops = {
669a5db4 JG	148	.set_piomode = cs5520_set_piomode,
669a5db4 JG	149	.set_dmamode = cs5520_set_dmamode,
6bd99b4e	150	.mode_filter = ata_pci_default_filter,
669a5db4 JG	151
	152	.tf_load = ata_tf_load,
	153	.tf_read = ata_tf_read,
	154	.check_status = ata_check_status,
	155	.exec_command = ata_exec_command,
	156	.dev_select = ata_std_dev_select,
	157
	158	.freeze = ata_bmdma_freeze,
	159	.thaw = ata_bmdma_thaw,
a73984a0	160	.error_handler = ata_bmdma_error_handler,
669a5db4	161	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	162	.cable_detect = ata_cable_40wire,
669a5db4 JG	163
	164	.bmdma_setup = ata_bmdma_setup,
	165	.bmdma_start = ata_bmdma_start,
	166	.bmdma_stop = ata_bmdma_stop,
	167	.bmdma_status = ata_bmdma_status,
d26fc955	168	.qc_prep = ata_dumb_qc_prep,
669a5db4	169	.qc_issue = ata_qc_issue_prot,
0d5ff566	170	.data_xfer = ata_data_xfer,
669a5db4	171
669a5db4	172	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	173	.irq_on = ata_irq_on,
669a5db4	174
81ad1837	175	.port_start = ata_sff_port_start,
669a5db4 JG	176	};
669a5db4 JG	177
5d728824	178	static int __devinit cs5520_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	179	{
cbcdd875 TH	180	static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
cbcdd875 TH	181	static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
5d728824 TH	182	struct ata_port_info pi = {
	183	.flags = ATA_FLAG_SLAVE_POSS,
	184	.pio_mask = 0x1f,
	185	.port_ops = &cs5520_port_ops,
	186	};
	187	const struct ata_port_info *ppi[2];
669a5db4	188	u8 pcicfg;
4ca4e439	189	void __iomem *iomap[5];
5d728824 TH	190	struct ata_host *host;
	191	struct ata_ioports *ioaddr;
	192	int i, rc;
669a5db4	193
f08048e9 TH	194	rc = pcim_enable_device(pdev);
	195	if (rc)
	196	return rc;
	197
669a5db4	198	/* IDE port enable bits */
5d728824	199	pci_read_config_byte(pdev, 0x60, &pcicfg);
669a5db4 JG	200
	201	/* Check if the ATA ports are enabled */
	202	if ((pcicfg & 3) == 0)
	203	return -ENODEV;
	204
5d728824 TH	205	ppi[0] = ppi[1] = &ata_dummy_port_info;
	206	if (pcicfg & 1)
	207	ppi[0] = π
	208	if (pcicfg & 2)
	209	ppi[1] = π
	210
669a5db4	211	if ((pcicfg & 0x40) == 0) {
5d728824 TH	212	dev_printk(KERN_WARNING, &pdev->dev,
	213	"DMA mode disabled. Enabling.\n");
	214	pci_write_config_byte(pdev, 0x60, pcicfg \| 0x40);
669a5db4 JG	215	}
669a5db4 JG	216
5d728824 TH	217	pi.mwdma_mask = id->driver_data;
	218
	219	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	220	if (!host)
	221	return -ENOMEM;
	222
669a5db4	223	/* Perform set up for DMA */
09483916	224	if (pci_enable_device_io(pdev)) {
669a5db4 JG	225	printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
	226	return -ENODEV;
	227	}
5d728824 TH	228
5d728824 TH	229	if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
669a5db4 JG	230	printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
	231	return -ENODEV;
	232	}
5d728824	233	if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
669a5db4 JG	234	printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
	235	return -ENODEV;
	236	}
	237
5d728824	238	/* Map IO ports and initialize host accordingly */
cbcdd875 TH	239	iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
	240	iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
	241	iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
	242	iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
5d728824	243	iomap[4] = pcim_iomap(pdev, 2, 0);
0d5ff566 TH	244
	245	if (!iomap[0] \|\| !iomap[1] \|\| !iomap[2] \|\| !iomap[3] \|\| !iomap[4])
	246	return -ENOMEM;
	247
5d728824 TH	248	ioaddr = &host->ports[0]->ioaddr;
	249	ioaddr->cmd_addr = iomap[0];
	250	ioaddr->ctl_addr = iomap[1];
	251	ioaddr->altstatus_addr = iomap[1];
	252	ioaddr->bmdma_addr = iomap[4];
	253	ata_std_ports(ioaddr);
	254
cbcdd875 TH	255	ata_port_desc(host->ports[0],
	256	"cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
	257	ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
	258
5d728824 TH	259	ioaddr = &host->ports[1]->ioaddr;
	260	ioaddr->cmd_addr = iomap[2];
	261	ioaddr->ctl_addr = iomap[3];
	262	ioaddr->altstatus_addr = iomap[3];
	263	ioaddr->bmdma_addr = iomap[4] + 8;
	264	ata_std_ports(ioaddr);
	265
cbcdd875 TH	266	ata_port_desc(host->ports[1],
	267	"cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
	268	ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
	269
5d728824 TH	270	/* activate the host */
	271	pci_set_master(pdev);
	272	rc = ata_host_start(host);
	273	if (rc)
	274	return rc;
	275
	276	for (i = 0; i < 2; i++) {
	277	static const int irq[] = { 14, 15 };
8c6b065b	278	struct ata_port *ap = host->ports[i];
5d728824 TH	279
	280	if (ata_port_is_dummy(ap))
	281	continue;
	282
	283	rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
	284	ata_interrupt, 0, DRV_NAME, host);
	285	if (rc)
	286	return rc;
4031826b	287
cbcdd875	288	ata_port_desc(ap, "irq %d", irq[i]);
5d728824 TH	289	}
	290
	291	return ata_host_register(host, &cs5520_sht);
669a5db4 JG	292	}
669a5db4 JG	293
438ac6d5	294	#ifdef CONFIG_PM
8501120f A	295	/**
	296	* cs5520_reinit_one - device resume
	297	* @pdev: PCI device
	298	*
	299	* Do any reconfiguration work needed by a resume from RAM. We need
	300	* to restore DMA mode support on BIOSen which disabled it
	301	*/
f20b16ff	302
8501120f A	303	static int cs5520_reinit_one(struct pci_dev *pdev)
8501120f A	304	{
f08048e9	305	struct ata_host *host = dev_get_drvdata(&pdev->dev);
8501120f	306	u8 pcicfg;
f08048e9 TH	307	int rc;
	308
	309	rc = ata_pci_device_do_resume(pdev);
	310	if (rc)
	311	return rc;
	312
8501120f A	313	pci_read_config_byte(pdev, 0x60, &pcicfg);
	314	if ((pcicfg & 0x40) == 0)
	315	pci_write_config_byte(pdev, 0x60, pcicfg \| 0x40);
f08048e9 TH	316
	317	ata_host_resume(host);
	318	return 0;
8501120f	319	}
aa6de494 A	320
	321	/**
	322	* cs5520_pci_device_suspend - device suspend
	323	* @pdev: PCI device
	324	*
	325	* We have to cut and waste bits from the standard method because
	326	* the 5520 is a bit odd and not just a pure ATA device. As a result
	327	* we must not disable it. The needed code is short and this avoids
	328	* chip specific mess in the core code.
	329	*/
	330
	331	static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
	332	{
	333	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	334	int rc = 0;
	335
	336	rc = ata_host_suspend(host, mesg);
	337	if (rc)
	338	return rc;
	339
	340	pci_save_state(pdev);
	341	return 0;
	342	}
438ac6d5	343	#endif /* CONFIG_PM */
a84471fe	344
669a5db4 JG	345	/* For now keep DMA off. We can set it for all but A rev CS5510 once the
	346	core ATA code can handle it */
	347
2d2744fc JG	348	static const struct pci_device_id pata_cs5520[] = {
	349	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	350	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
	351
	352	{ },
669a5db4 JG	353	};
	354
	355	static struct pci_driver cs5520_pci_driver = {
	356	.name = DRV_NAME,
	357	.id_table = pata_cs5520,
	358	.probe = cs5520_init_one,
2855568b	359	.remove = ata_pci_remove_one,
438ac6d5	360	#ifdef CONFIG_PM
aa6de494	361	.suspend = cs5520_pci_device_suspend,
8501120f	362	.resume = cs5520_reinit_one,
438ac6d5	363	#endif
669a5db4 JG	364	};
669a5db4 JG	365
669a5db4 JG	366	static int __init cs5520_init(void)
	367	{
	368	return pci_register_driver(&cs5520_pci_driver);
	369	}
	370
	371	static void __exit cs5520_exit(void)
	372	{
	373	pci_unregister_driver(&cs5520_pci_driver);
	374	}
	375
	376	MODULE_AUTHOR("Alan Cox");
	377	MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
	378	MODULE_LICENSE("GPL");
	379	MODULE_DEVICE_TABLE(pci, pata_cs5520);
	380	MODULE_VERSION(DRV_VERSION);
	381
	382	module_init(cs5520_init);
	383	module_exit(cs5520_exit);
	384