Commit | Line | Data |
---|---|---|
669a5db4 | 1 | /* |
0ca646db | 2 | * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. |
669a5db4 JG |
3 | * |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 11 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * | |
14 | * TODO | |
669a5db4 JG |
15 | * Work out best PLL policy |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt3x2n" | |
40d69ba0 | 28 | #define DRV_VERSION "0.3.14" |
669a5db4 JG |
29 | |
30 | enum { | |
31 | HPT_PCI_FAST = (1 << 31), | |
32 | PCI66 = (1 << 1), | |
33 | USE_DPLL = (1 << 0) | |
34 | }; | |
35 | ||
36 | struct hpt_clock { | |
37 | u8 xfer_speed; | |
38 | u32 timing; | |
39 | }; | |
40 | ||
41 | struct hpt_chip { | |
42 | const char *name; | |
43 | struct hpt_clock *clocks[3]; | |
44 | }; | |
45 | ||
46 | /* key for bus clock timings | |
47 | * bit | |
fd5e62e2 SS |
48 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
49 | * cycles = value + 1 | |
50 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
51 | * cycles = value + 1 | |
52 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 53 | * register access. |
fd5e62e2 | 54 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 55 | * register access. |
fd5e62e2 SS |
56 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
57 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
58 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
59 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 60 | * register access. |
fd5e62e2 SS |
61 | * 28 UDMA enable. |
62 | * 29 DMA enable. | |
63 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
64 | * PIO xfer. | |
65 | * 31 FIFO enable. Only for PIO. | |
669a5db4 | 66 | */ |
85cd7251 | 67 | |
669a5db4 JG |
68 | /* 66MHz DPLL clocks */ |
69 | ||
70 | static struct hpt_clock hpt3x2n_clocks[] = { | |
71 | { XFER_UDMA_7, 0x1c869c62 }, | |
72 | { XFER_UDMA_6, 0x1c869c62 }, | |
73 | { XFER_UDMA_5, 0x1c8a9c62 }, | |
74 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
75 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
76 | { XFER_UDMA_2, 0x1c929c62 }, | |
77 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
78 | { XFER_UDMA_0, 0x1c829c62 }, | |
79 | ||
80 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
81 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
d413ff3e | 82 | { XFER_MW_DMA_0, 0x2c829d2e }, |
669a5db4 JG |
83 | |
84 | { XFER_PIO_4, 0x0c829c62 }, | |
85 | { XFER_PIO_3, 0x0c829c84 }, | |
86 | { XFER_PIO_2, 0x0c829ca6 }, | |
87 | { XFER_PIO_1, 0x0d029d26 }, | |
88 | { XFER_PIO_0, 0x0d029d5e }, | |
669a5db4 JG |
89 | }; |
90 | ||
91 | /** | |
92 | * hpt3x2n_find_mode - reset the hpt3x2n bus | |
93 | * @ap: ATA port | |
94 | * @speed: transfer mode | |
95 | * | |
96 | * Return the 32bit register programming information for this channel | |
97 | * that matches the speed provided. For the moment the clocks table | |
98 | * is hard coded but easy to change. This will be needed if we use | |
99 | * different DPLLs | |
100 | */ | |
85cd7251 | 101 | |
669a5db4 JG |
102 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
103 | { | |
104 | struct hpt_clock *clocks = hpt3x2n_clocks; | |
85cd7251 | 105 | |
b197f13b | 106 | while (clocks->xfer_speed) { |
669a5db4 JG |
107 | if (clocks->xfer_speed == speed) |
108 | return clocks->timing; | |
109 | clocks++; | |
110 | } | |
111 | BUG(); | |
112 | return 0xffffffffU; /* silence compiler warning */ | |
113 | } | |
114 | ||
8e834c2e SS |
115 | /** |
116 | * hpt372n_filter - mode selection filter | |
117 | * @adev: ATA device | |
118 | * @mask: mode mask | |
119 | * | |
120 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
121 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
122 | */ | |
123 | static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) | |
124 | { | |
125 | if (ata_id_is_sata(adev->id)) | |
126 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
127 | ||
128 | return mask; | |
129 | } | |
130 | ||
669a5db4 | 131 | /** |
a0fcdc02 JG |
132 | * hpt3x2n_cable_detect - Detect the cable type |
133 | * @ap: ATA port to detect on | |
669a5db4 | 134 | * |
a0fcdc02 | 135 | * Return the cable type attached to this port |
669a5db4 | 136 | */ |
85cd7251 | 137 | |
a0fcdc02 | 138 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
669a5db4 JG |
139 | { |
140 | u8 scr2, ata66; | |
141 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 142 | |
669a5db4 JG |
143 | pci_read_config_byte(pdev, 0x5B, &scr2); |
144 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
145 | |
146 | udelay(10); /* debounce */ | |
147 | ||
669a5db4 JG |
148 | /* Cable register now active */ |
149 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
150 | /* Restore state */ | |
151 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 152 | |
f3b1cf40 | 153 | if (ata66 & (2 >> ap->port_no)) |
a0fcdc02 | 154 | return ATA_CBL_PATA40; |
669a5db4 | 155 | else |
a0fcdc02 JG |
156 | return ATA_CBL_PATA80; |
157 | } | |
158 | ||
159 | /** | |
160 | * hpt3x2n_pre_reset - reset the hpt3x2n bus | |
cc0680a5 | 161 | * @link: ATA link to reset |
28e21c8c | 162 | * @deadline: deadline jiffies for the operation |
a0fcdc02 JG |
163 | * |
164 | * Perform the initial reset handling for the 3x2n series controllers. | |
165 | * Reset the hardware and state machine, | |
166 | */ | |
669a5db4 | 167 | |
a1efdaba | 168 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
a0fcdc02 | 169 | { |
cc0680a5 | 170 | struct ata_port *ap = link->ap; |
a0fcdc02 | 171 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b197f13b | 172 | |
669a5db4 | 173 | /* Reset the state machine */ |
28e21c8c | 174 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 175 | udelay(100); |
d4b2bab4 | 176 | |
9363c382 | 177 | return ata_sff_prereset(link, deadline); |
669a5db4 | 178 | } |
85cd7251 | 179 | |
1a1b172b SS |
180 | static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, |
181 | u8 mode) | |
669a5db4 JG |
182 | { |
183 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
184 | u32 addr1, addr2; | |
1a1b172b | 185 | u32 reg, timing, mask; |
669a5db4 JG |
186 | u8 fast; |
187 | ||
188 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
189 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 190 | |
669a5db4 JG |
191 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
192 | pci_read_config_byte(pdev, addr2, &fast); | |
193 | fast &= ~0x07; | |
194 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 195 | |
1a1b172b SS |
196 | /* Determine timing mask and find matching mode entry */ |
197 | if (mode < XFER_MW_DMA_0) | |
198 | mask = 0xcfc3ffff; | |
199 | else if (mode < XFER_UDMA_0) | |
200 | mask = 0x31c001ff; | |
201 | else | |
202 | mask = 0x303c0000; | |
203 | ||
204 | timing = hpt3x2n_find_mode(ap, mode); | |
205 | ||
669a5db4 | 206 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
207 | reg = (reg & ~mask) | (timing & mask); |
208 | pci_write_config_dword(pdev, addr1, reg); | |
209 | } | |
210 | ||
211 | /** | |
212 | * hpt3x2n_set_piomode - PIO setup | |
213 | * @ap: ATA interface | |
214 | * @adev: device on the interface | |
215 | * | |
216 | * Perform PIO mode setup. | |
217 | */ | |
218 | ||
219 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
220 | { | |
221 | hpt3x2n_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
222 | } |
223 | ||
224 | /** | |
225 | * hpt3x2n_set_dmamode - DMA timing setup | |
226 | * @ap: ATA interface | |
227 | * @adev: Device being configured | |
228 | * | |
1a1b172b | 229 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 230 | */ |
85cd7251 | 231 | |
669a5db4 JG |
232 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
233 | { | |
1a1b172b | 234 | hpt3x2n_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
235 | } |
236 | ||
237 | /** | |
238 | * hpt3x2n_bmdma_end - DMA engine stop | |
239 | * @qc: ATA command | |
240 | * | |
241 | * Clean up after the HPT3x2n and later DMA engine | |
242 | */ | |
85cd7251 | 243 | |
669a5db4 JG |
244 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
245 | { | |
246 | struct ata_port *ap = qc->ap; | |
247 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
248 | int mscreg = 0x50 + 2 * ap->port_no; | |
249 | u8 bwsr_stat, msc_stat; | |
85cd7251 | 250 | |
669a5db4 JG |
251 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
252 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
253 | if (bwsr_stat & (1 << ap->port_no)) | |
254 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
255 | ata_bmdma_stop(qc); | |
256 | } | |
257 | ||
258 | /** | |
259 | * hpt3x2n_set_clock - clock control | |
260 | * @ap: ATA port | |
261 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock | |
262 | * | |
263 | * Switch the ATA bus clock between the PLL and PCI clock sources | |
264 | * while correctly isolating the bus and resetting internal logic | |
265 | * | |
266 | * We must use the DPLL for | |
267 | * - writing | |
268 | * - second channel UDMA7 (SATA ports) or higher | |
269 | * - 66MHz PCI | |
85cd7251 | 270 | * |
669a5db4 JG |
271 | * or we will underclock the device and get reduced performance. |
272 | */ | |
85cd7251 | 273 | |
669a5db4 JG |
274 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
275 | { | |
256ace9b | 276 | void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; |
85cd7251 | 277 | |
669a5db4 | 278 | /* Tristate the bus */ |
0d5ff566 TH |
279 | iowrite8(0x80, bmdma+0x73); |
280 | iowrite8(0x80, bmdma+0x77); | |
85cd7251 | 281 | |
669a5db4 | 282 | /* Switch clock and reset channels */ |
0d5ff566 TH |
283 | iowrite8(source, bmdma+0x7B); |
284 | iowrite8(0xC0, bmdma+0x79); | |
85cd7251 | 285 | |
256ace9b SS |
286 | /* Reset state machines, avoid enabling the disabled channels */ |
287 | iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); | |
288 | iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); | |
85cd7251 | 289 | |
669a5db4 | 290 | /* Complete reset */ |
0d5ff566 | 291 | iowrite8(0x00, bmdma+0x79); |
85cd7251 | 292 | |
669a5db4 | 293 | /* Reconnect channels to bus */ |
0d5ff566 TH |
294 | iowrite8(0x00, bmdma+0x73); |
295 | iowrite8(0x00, bmdma+0x77); | |
669a5db4 JG |
296 | } |
297 | ||
a52865c2 | 298 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
669a5db4 JG |
299 | { |
300 | long flags = (long)ap->host->private_data; | |
256ace9b | 301 | |
669a5db4 | 302 | /* See if we should use the DPLL */ |
a52865c2 | 303 | if (writing) |
669a5db4 JG |
304 | return USE_DPLL; /* Needed for write */ |
305 | if (flags & PCI66) | |
306 | return USE_DPLL; /* Needed at 66Mhz */ | |
85cd7251 | 307 | return 0; |
669a5db4 JG |
308 | } |
309 | ||
256ace9b SS |
310 | static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) |
311 | { | |
312 | struct ata_port *ap = qc->ap; | |
313 | struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; | |
314 | int rc, flags = (long)ap->host->private_data; | |
315 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); | |
316 | ||
317 | /* First apply the usual rules */ | |
318 | rc = ata_std_qc_defer(qc); | |
319 | if (rc != 0) | |
320 | return rc; | |
321 | ||
322 | if ((flags & USE_DPLL) != dpll && alt->qc_active) | |
323 | return ATA_DEFER_PORT; | |
324 | return 0; | |
325 | } | |
326 | ||
9363c382 | 327 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 | 328 | { |
669a5db4 JG |
329 | struct ata_port *ap = qc->ap; |
330 | int flags = (long)ap->host->private_data; | |
256ace9b | 331 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
85cd7251 | 332 | |
256ace9b SS |
333 | if ((flags & USE_DPLL) != dpll) { |
334 | flags &= ~USE_DPLL; | |
335 | flags |= dpll; | |
336 | ap->host->private_data = (void *)(long)flags; | |
337 | ||
338 | hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); | |
669a5db4 | 339 | } |
360ff783 | 340 | return ata_bmdma_qc_issue(qc); |
669a5db4 JG |
341 | } |
342 | ||
343 | static struct scsi_host_template hpt3x2n_sht = { | |
68d1d07b | 344 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
345 | }; |
346 | ||
347 | /* | |
8e834c2e | 348 | * Configuration for HPT302N/371N. |
669a5db4 | 349 | */ |
85cd7251 | 350 | |
8e834c2e | 351 | static struct ata_port_operations hpt3xxn_port_ops = { |
029cfd6b | 352 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 353 | |
669a5db4 | 354 | .bmdma_stop = hpt3x2n_bmdma_stop, |
256ace9b SS |
355 | |
356 | .qc_defer = hpt3x2n_qc_defer, | |
9363c382 | 357 | .qc_issue = hpt3x2n_qc_issue, |
bda30288 | 358 | |
029cfd6b TH |
359 | .cable_detect = hpt3x2n_cable_detect, |
360 | .set_piomode = hpt3x2n_set_piomode, | |
361 | .set_dmamode = hpt3x2n_set_dmamode, | |
a1efdaba | 362 | .prereset = hpt3x2n_pre_reset, |
85cd7251 | 363 | }; |
669a5db4 | 364 | |
8e834c2e SS |
365 | /* |
366 | * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. | |
367 | */ | |
368 | ||
369 | static struct ata_port_operations hpt372n_port_ops = { | |
370 | .inherits = &hpt3xxn_port_ops, | |
371 | .mode_filter = &hpt372n_filter, | |
372 | }; | |
373 | ||
669a5db4 JG |
374 | /** |
375 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 376 | * @dev: PCI device |
669a5db4 JG |
377 | * |
378 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this | |
379 | * succeeds | |
380 | */ | |
381 | ||
382 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) | |
383 | { | |
384 | u8 reg5b; | |
385 | u32 reg5c; | |
386 | int tries; | |
85cd7251 | 387 | |
b197f13b | 388 | for (tries = 0; tries < 0x5000; tries++) { |
669a5db4 JG |
389 | udelay(50); |
390 | pci_read_config_byte(dev, 0x5b, ®5b); | |
391 | if (reg5b & 0x80) { | |
392 | /* See if it stays set */ | |
b197f13b | 393 | for (tries = 0; tries < 0x1000; tries++) { |
669a5db4 JG |
394 | pci_read_config_byte(dev, 0x5b, ®5b); |
395 | /* Failed ? */ | |
396 | if ((reg5b & 0x80) == 0) | |
397 | return 0; | |
398 | } | |
399 | /* Turn off tuning, we have the DPLL set */ | |
400 | pci_read_config_dword(dev, 0x5c, ®5c); | |
b197f13b | 401 | pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db4 JG |
402 | return 1; |
403 | } | |
404 | } | |
405 | /* Never went stable */ | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) | |
410 | { | |
411 | unsigned long freq; | |
412 | u32 fcnt; | |
28e21c8c | 413 | unsigned long iobase = pci_resource_start(pdev, 4); |
85cd7251 | 414 | |
28e21c8c | 415 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
669a5db4 | 416 | if ((fcnt >> 12) != 0xABCDE) { |
dfc7e3e3 SS |
417 | int i; |
418 | u16 sr; | |
419 | u32 total = 0; | |
420 | ||
40d69ba0 | 421 | pr_warning(DRV_NAME ": BIOS clock data not set.\n"); |
dfc7e3e3 SS |
422 | |
423 | /* This is the process the HPT371 BIOS is reported to use */ | |
424 | for (i = 0; i < 128; i++) { | |
425 | pci_read_config_word(pdev, 0x78, &sr); | |
426 | total += sr & 0x1FF; | |
427 | udelay(15); | |
428 | } | |
429 | fcnt = total / 128; | |
669a5db4 JG |
430 | } |
431 | fcnt &= 0x1FF; | |
85cd7251 | 432 | |
669a5db4 | 433 | freq = (fcnt * 77) / 192; |
85cd7251 | 434 | |
669a5db4 JG |
435 | /* Clamp to bands */ |
436 | if (freq < 40) | |
437 | return 33; | |
438 | if (freq < 45) | |
439 | return 40; | |
440 | if (freq < 55) | |
441 | return 50; | |
442 | return 66; | |
443 | } | |
444 | ||
445 | /** | |
446 | * hpt3x2n_init_one - Initialise an HPT37X/302 | |
447 | * @dev: PCI device | |
448 | * @id: Entry in match table | |
449 | * | |
450 | * Initialise an HPT3x2n device. There are some interesting complications | |
451 | * here. Firstly the chip may report 366 and be one of several variants. | |
452 | * Secondly all the timings depend on the clock for the chip which we must | |
453 | * detect and look up | |
454 | * | |
455 | * This is the known chip mappings. It may be missing a couple of later | |
456 | * releases. | |
457 | * | |
458 | * Chip version PCI Rev Notes | |
459 | * HPT372 4 (HPT366) 5 Other driver | |
460 | * HPT372N 4 (HPT366) 6 UDMA133 | |
461 | * HPT372 5 (HPT372) 1 Other driver | |
462 | * HPT372N 5 (HPT372) 2 UDMA133 | |
463 | * HPT302 6 (HPT302) * Other driver | |
464 | * HPT302N 6 (HPT302) > 1 UDMA133 | |
465 | * HPT371 7 (HPT371) * Other driver | |
466 | * HPT371N 7 (HPT371) > 1 UDMA133 | |
467 | * HPT374 8 (HPT374) * Other driver | |
468 | * HPT372N 9 (HPT372N) * UDMA133 | |
469 | * | |
470 | * (1) UDMA133 support depends on the bus clock | |
669a5db4 | 471 | */ |
85cd7251 | 472 | |
669a5db4 JG |
473 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
474 | { | |
8e834c2e SS |
475 | /* HPT372N - UDMA133 */ |
476 | static const struct ata_port_info info_hpt372n = { | |
1d2808fd | 477 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
478 | .pio_mask = ATA_PIO4, |
479 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 480 | .udma_mask = ATA_UDMA6, |
8e834c2e | 481 | .port_ops = &hpt372n_port_ops |
669a5db4 | 482 | }; |
8e834c2e SS |
483 | /* HPT302N and HPT371N - UDMA133 */ |
484 | static const struct ata_port_info info_hpt3xxn = { | |
485 | .flags = ATA_FLAG_SLAVE_POSS, | |
486 | .pio_mask = ATA_PIO4, | |
487 | .mwdma_mask = ATA_MWDMA2, | |
488 | .udma_mask = ATA_UDMA6, | |
489 | .port_ops = &hpt3xxn_port_ops | |
490 | }; | |
491 | const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; | |
89d3b360 | 492 | u8 rev = dev->revision; |
669a5db4 | 493 | u8 irqmask; |
669a5db4 JG |
494 | unsigned int pci_mhz; |
495 | unsigned int f_low, f_high; | |
496 | int adjust; | |
28e21c8c | 497 | unsigned long iobase = pci_resource_start(dev, 4); |
256ace9b | 498 | void *hpriv = (void *)USE_DPLL; |
f08048e9 TH |
499 | int rc; |
500 | ||
501 | rc = pcim_enable_device(dev); | |
502 | if (rc) | |
503 | return rc; | |
85cd7251 | 504 | |
b197f13b SS |
505 | switch (dev->device) { |
506 | case PCI_DEVICE_ID_TTI_HPT366: | |
507 | /* 372N if rev >= 6 */ | |
508 | if (rev < 6) | |
509 | return -ENODEV; | |
510 | goto hpt372n; | |
511 | case PCI_DEVICE_ID_TTI_HPT371: | |
512 | /* 371N if rev >= 2 */ | |
513 | if (rev < 2) | |
514 | return -ENODEV; | |
515 | break; | |
516 | case PCI_DEVICE_ID_TTI_HPT372: | |
517 | /* 372N if rev >= 2 */ | |
518 | if (rev < 2) | |
519 | return -ENODEV; | |
520 | goto hpt372n; | |
521 | case PCI_DEVICE_ID_TTI_HPT302: | |
522 | /* 302N if rev >= 2 */ | |
523 | if (rev < 2) | |
669a5db4 | 524 | return -ENODEV; |
b197f13b SS |
525 | break; |
526 | case PCI_DEVICE_ID_TTI_HPT372N: | |
527 | hpt372n: | |
528 | ppi[0] = &info_hpt372n; | |
529 | break; | |
530 | default: | |
40d69ba0 | 531 | pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n", |
b197f13b SS |
532 | dev->device); |
533 | return -ENODEV; | |
669a5db4 JG |
534 | } |
535 | ||
536 | /* Ok so this is a chip we support */ | |
537 | ||
538 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
539 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
540 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
541 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
542 | ||
543 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
544 | irqmask &= ~0x10; | |
545 | pci_write_config_byte(dev, 0x5a, irqmask); | |
546 | ||
28e21c8c AC |
547 | /* |
548 | * HPT371 chips physically have only one channel, the secondary one, | |
549 | * but the primary channel registers do exist! Go figure... | |
550 | * So, we manually disable the non-existing channel here | |
551 | * (if the BIOS hasn't done this already). | |
552 | */ | |
553 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { | |
554 | u8 mcr1; | |
555 | pci_read_config_byte(dev, 0x50, &mcr1); | |
556 | mcr1 &= ~0x04; | |
557 | pci_write_config_byte(dev, 0x50, mcr1); | |
558 | } | |
559 | ||
b197f13b SS |
560 | /* |
561 | * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or | |
562 | * 50 for UDMA100. Right now we always use 66 | |
563 | */ | |
85cd7251 | 564 | |
669a5db4 | 565 | pci_mhz = hpt3x2n_pci_clock(dev); |
85cd7251 | 566 | |
669a5db4 JG |
567 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
568 | f_high = f_low + 2; /* Tolerance */ | |
85cd7251 | 569 | |
669a5db4 JG |
570 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
571 | /* PLL clock */ | |
572 | pci_write_config_byte(dev, 0x5B, 0x21); | |
85cd7251 | 573 | |
669a5db4 | 574 | /* Unlike the 37x we don't try jiggling the frequency */ |
b197f13b | 575 | for (adjust = 0; adjust < 8; adjust++) { |
669a5db4 JG |
576 | if (hpt3xn_calibrate_dpll(dev)) |
577 | break; | |
578 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
579 | } | |
28e21c8c | 580 | if (adjust == 8) { |
40d69ba0 | 581 | pr_err(DRV_NAME ": DPLL did not stabilize!\n"); |
28e21c8c AC |
582 | return -ENODEV; |
583 | } | |
669a5db4 | 584 | |
40d69ba0 | 585 | pr_info(DRV_NAME ": bus clock %dMHz, using 66MHz DPLL.\n", pci_mhz); |
b197f13b SS |
586 | |
587 | /* | |
588 | * Set our private data up. We only need a few flags | |
589 | * so we use it directly. | |
590 | */ | |
60661933 | 591 | if (pci_mhz > 60) |
256ace9b | 592 | hpriv = (void *)(PCI66 | USE_DPLL); |
60661933 SS |
593 | |
594 | /* | |
595 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
596 | * the MISC. register to stretch the UltraDMA Tss timing. | |
597 | * NOTE: This register is only writeable via I/O space. | |
598 | */ | |
599 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) | |
600 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); | |
85cd7251 | 601 | |
669a5db4 | 602 | /* Now kick off ATA set up */ |
1c5afdf7 | 603 | return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); |
669a5db4 JG |
604 | } |
605 | ||
2d2744fc JG |
606 | static const struct pci_device_id hpt3x2n[] = { |
607 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
28e21c8c | 608 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
2d2744fc JG |
609 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
610 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
611 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, | |
612 | ||
613 | { }, | |
669a5db4 JG |
614 | }; |
615 | ||
616 | static struct pci_driver hpt3x2n_pci_driver = { | |
b197f13b | 617 | .name = DRV_NAME, |
669a5db4 | 618 | .id_table = hpt3x2n, |
b197f13b | 619 | .probe = hpt3x2n_init_one, |
669a5db4 JG |
620 | .remove = ata_pci_remove_one |
621 | }; | |
622 | ||
623 | static int __init hpt3x2n_init(void) | |
624 | { | |
625 | return pci_register_driver(&hpt3x2n_pci_driver); | |
626 | } | |
627 | ||
669a5db4 JG |
628 | static void __exit hpt3x2n_exit(void) |
629 | { | |
630 | pci_unregister_driver(&hpt3x2n_pci_driver); | |
631 | } | |
632 | ||
669a5db4 | 633 | MODULE_AUTHOR("Alan Cox"); |
0ca646db | 634 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); |
669a5db4 JG |
635 | MODULE_LICENSE("GPL"); |
636 | MODULE_DEVICE_TABLE(pci, hpt3x2n); | |
637 | MODULE_VERSION(DRV_VERSION); | |
638 | ||
639 | module_init(hpt3x2n_init); | |
640 | module_exit(hpt3x2n_exit); |