Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
256ace9b | 11 | * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * | |
14 | * TODO | |
669a5db4 JG |
15 | * Work out best PLL policy |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt3x2n" | |
1a1b172b | 28 | #define DRV_VERSION "0.3.10" |
669a5db4 JG |
29 | |
30 | enum { | |
31 | HPT_PCI_FAST = (1 << 31), | |
32 | PCI66 = (1 << 1), | |
33 | USE_DPLL = (1 << 0) | |
34 | }; | |
35 | ||
36 | struct hpt_clock { | |
37 | u8 xfer_speed; | |
38 | u32 timing; | |
39 | }; | |
40 | ||
41 | struct hpt_chip { | |
42 | const char *name; | |
43 | struct hpt_clock *clocks[3]; | |
44 | }; | |
45 | ||
46 | /* key for bus clock timings | |
47 | * bit | |
48 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | |
49 | * DMA. cycles = value + 1 | |
50 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | |
51 | * DMA. cycles = value + 1 | |
52 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | |
53 | * register access. | |
54 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | |
55 | * register access. | |
56 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | |
57 | * during task file register access. | |
58 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | |
59 | * xfer. | |
60 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | |
61 | * register access. | |
62 | * 28 UDMA enable | |
63 | * 29 DMA enable | |
64 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | |
65 | * PIO. | |
66 | * 31 FIFO enable. | |
67 | */ | |
85cd7251 | 68 | |
669a5db4 JG |
69 | /* 66MHz DPLL clocks */ |
70 | ||
71 | static struct hpt_clock hpt3x2n_clocks[] = { | |
72 | { XFER_UDMA_7, 0x1c869c62 }, | |
73 | { XFER_UDMA_6, 0x1c869c62 }, | |
74 | { XFER_UDMA_5, 0x1c8a9c62 }, | |
75 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
76 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
77 | { XFER_UDMA_2, 0x1c929c62 }, | |
78 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
79 | { XFER_UDMA_0, 0x1c829c62 }, | |
80 | ||
81 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
82 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
d413ff3e | 83 | { XFER_MW_DMA_0, 0x2c829d2e }, |
669a5db4 JG |
84 | |
85 | { XFER_PIO_4, 0x0c829c62 }, | |
86 | { XFER_PIO_3, 0x0c829c84 }, | |
87 | { XFER_PIO_2, 0x0c829ca6 }, | |
88 | { XFER_PIO_1, 0x0d029d26 }, | |
89 | { XFER_PIO_0, 0x0d029d5e }, | |
669a5db4 JG |
90 | }; |
91 | ||
92 | /** | |
93 | * hpt3x2n_find_mode - reset the hpt3x2n bus | |
94 | * @ap: ATA port | |
95 | * @speed: transfer mode | |
96 | * | |
97 | * Return the 32bit register programming information for this channel | |
98 | * that matches the speed provided. For the moment the clocks table | |
99 | * is hard coded but easy to change. This will be needed if we use | |
100 | * different DPLLs | |
101 | */ | |
85cd7251 | 102 | |
669a5db4 JG |
103 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
104 | { | |
105 | struct hpt_clock *clocks = hpt3x2n_clocks; | |
85cd7251 | 106 | |
669a5db4 JG |
107 | while(clocks->xfer_speed) { |
108 | if (clocks->xfer_speed == speed) | |
109 | return clocks->timing; | |
110 | clocks++; | |
111 | } | |
112 | BUG(); | |
113 | return 0xffffffffU; /* silence compiler warning */ | |
114 | } | |
115 | ||
116 | /** | |
a0fcdc02 JG |
117 | * hpt3x2n_cable_detect - Detect the cable type |
118 | * @ap: ATA port to detect on | |
669a5db4 | 119 | * |
a0fcdc02 | 120 | * Return the cable type attached to this port |
669a5db4 | 121 | */ |
85cd7251 | 122 | |
a0fcdc02 | 123 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
669a5db4 JG |
124 | { |
125 | u8 scr2, ata66; | |
126 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 127 | |
669a5db4 JG |
128 | pci_read_config_byte(pdev, 0x5B, &scr2); |
129 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
130 | |
131 | udelay(10); /* debounce */ | |
132 | ||
669a5db4 JG |
133 | /* Cable register now active */ |
134 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
135 | /* Restore state */ | |
136 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 137 | |
f3b1cf40 | 138 | if (ata66 & (2 >> ap->port_no)) |
a0fcdc02 | 139 | return ATA_CBL_PATA40; |
669a5db4 | 140 | else |
a0fcdc02 JG |
141 | return ATA_CBL_PATA80; |
142 | } | |
143 | ||
144 | /** | |
145 | * hpt3x2n_pre_reset - reset the hpt3x2n bus | |
cc0680a5 | 146 | * @link: ATA link to reset |
28e21c8c | 147 | * @deadline: deadline jiffies for the operation |
a0fcdc02 JG |
148 | * |
149 | * Perform the initial reset handling for the 3x2n series controllers. | |
150 | * Reset the hardware and state machine, | |
151 | */ | |
669a5db4 | 152 | |
a1efdaba | 153 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
a0fcdc02 | 154 | { |
cc0680a5 | 155 | struct ata_port *ap = link->ap; |
a0fcdc02 | 156 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 157 | /* Reset the state machine */ |
28e21c8c | 158 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 159 | udelay(100); |
d4b2bab4 | 160 | |
9363c382 | 161 | return ata_sff_prereset(link, deadline); |
669a5db4 | 162 | } |
85cd7251 | 163 | |
1a1b172b SS |
164 | static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, |
165 | u8 mode) | |
669a5db4 JG |
166 | { |
167 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
168 | u32 addr1, addr2; | |
1a1b172b | 169 | u32 reg, timing, mask; |
669a5db4 JG |
170 | u8 fast; |
171 | ||
172 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
173 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 174 | |
669a5db4 JG |
175 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
176 | pci_read_config_byte(pdev, addr2, &fast); | |
177 | fast &= ~0x07; | |
178 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 179 | |
1a1b172b SS |
180 | /* Determine timing mask and find matching mode entry */ |
181 | if (mode < XFER_MW_DMA_0) | |
182 | mask = 0xcfc3ffff; | |
183 | else if (mode < XFER_UDMA_0) | |
184 | mask = 0x31c001ff; | |
185 | else | |
186 | mask = 0x303c0000; | |
187 | ||
188 | timing = hpt3x2n_find_mode(ap, mode); | |
189 | ||
669a5db4 | 190 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
191 | reg = (reg & ~mask) | (timing & mask); |
192 | pci_write_config_dword(pdev, addr1, reg); | |
193 | } | |
194 | ||
195 | /** | |
196 | * hpt3x2n_set_piomode - PIO setup | |
197 | * @ap: ATA interface | |
198 | * @adev: device on the interface | |
199 | * | |
200 | * Perform PIO mode setup. | |
201 | */ | |
202 | ||
203 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
204 | { | |
205 | hpt3x2n_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
206 | } |
207 | ||
208 | /** | |
209 | * hpt3x2n_set_dmamode - DMA timing setup | |
210 | * @ap: ATA interface | |
211 | * @adev: Device being configured | |
212 | * | |
1a1b172b | 213 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 214 | */ |
85cd7251 | 215 | |
669a5db4 JG |
216 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
217 | { | |
1a1b172b | 218 | hpt3x2n_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
219 | } |
220 | ||
221 | /** | |
222 | * hpt3x2n_bmdma_end - DMA engine stop | |
223 | * @qc: ATA command | |
224 | * | |
225 | * Clean up after the HPT3x2n and later DMA engine | |
226 | */ | |
85cd7251 | 227 | |
669a5db4 JG |
228 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
229 | { | |
230 | struct ata_port *ap = qc->ap; | |
231 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
232 | int mscreg = 0x50 + 2 * ap->port_no; | |
233 | u8 bwsr_stat, msc_stat; | |
85cd7251 | 234 | |
669a5db4 JG |
235 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
236 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
237 | if (bwsr_stat & (1 << ap->port_no)) | |
238 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
239 | ata_bmdma_stop(qc); | |
240 | } | |
241 | ||
242 | /** | |
243 | * hpt3x2n_set_clock - clock control | |
244 | * @ap: ATA port | |
245 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock | |
246 | * | |
247 | * Switch the ATA bus clock between the PLL and PCI clock sources | |
248 | * while correctly isolating the bus and resetting internal logic | |
249 | * | |
250 | * We must use the DPLL for | |
251 | * - writing | |
252 | * - second channel UDMA7 (SATA ports) or higher | |
253 | * - 66MHz PCI | |
85cd7251 | 254 | * |
669a5db4 JG |
255 | * or we will underclock the device and get reduced performance. |
256 | */ | |
85cd7251 | 257 | |
669a5db4 JG |
258 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
259 | { | |
256ace9b | 260 | void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; |
85cd7251 | 261 | |
669a5db4 | 262 | /* Tristate the bus */ |
0d5ff566 TH |
263 | iowrite8(0x80, bmdma+0x73); |
264 | iowrite8(0x80, bmdma+0x77); | |
85cd7251 | 265 | |
669a5db4 | 266 | /* Switch clock and reset channels */ |
0d5ff566 TH |
267 | iowrite8(source, bmdma+0x7B); |
268 | iowrite8(0xC0, bmdma+0x79); | |
85cd7251 | 269 | |
256ace9b SS |
270 | /* Reset state machines, avoid enabling the disabled channels */ |
271 | iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); | |
272 | iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); | |
85cd7251 | 273 | |
669a5db4 | 274 | /* Complete reset */ |
0d5ff566 | 275 | iowrite8(0x00, bmdma+0x79); |
85cd7251 | 276 | |
669a5db4 | 277 | /* Reconnect channels to bus */ |
0d5ff566 TH |
278 | iowrite8(0x00, bmdma+0x73); |
279 | iowrite8(0x00, bmdma+0x77); | |
669a5db4 JG |
280 | } |
281 | ||
a52865c2 | 282 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
669a5db4 JG |
283 | { |
284 | long flags = (long)ap->host->private_data; | |
256ace9b | 285 | |
669a5db4 | 286 | /* See if we should use the DPLL */ |
a52865c2 | 287 | if (writing) |
669a5db4 JG |
288 | return USE_DPLL; /* Needed for write */ |
289 | if (flags & PCI66) | |
290 | return USE_DPLL; /* Needed at 66Mhz */ | |
85cd7251 | 291 | return 0; |
669a5db4 JG |
292 | } |
293 | ||
256ace9b SS |
294 | static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) |
295 | { | |
296 | struct ata_port *ap = qc->ap; | |
297 | struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; | |
298 | int rc, flags = (long)ap->host->private_data; | |
299 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); | |
300 | ||
301 | /* First apply the usual rules */ | |
302 | rc = ata_std_qc_defer(qc); | |
303 | if (rc != 0) | |
304 | return rc; | |
305 | ||
306 | if ((flags & USE_DPLL) != dpll && alt->qc_active) | |
307 | return ATA_DEFER_PORT; | |
308 | return 0; | |
309 | } | |
310 | ||
9363c382 | 311 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 | 312 | { |
669a5db4 JG |
313 | struct ata_port *ap = qc->ap; |
314 | int flags = (long)ap->host->private_data; | |
256ace9b | 315 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
85cd7251 | 316 | |
256ace9b SS |
317 | if ((flags & USE_DPLL) != dpll) { |
318 | flags &= ~USE_DPLL; | |
319 | flags |= dpll; | |
320 | ap->host->private_data = (void *)(long)flags; | |
321 | ||
322 | hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); | |
669a5db4 | 323 | } |
9363c382 | 324 | return ata_sff_qc_issue(qc); |
669a5db4 JG |
325 | } |
326 | ||
327 | static struct scsi_host_template hpt3x2n_sht = { | |
68d1d07b | 328 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
329 | }; |
330 | ||
331 | /* | |
332 | * Configuration for HPT3x2n. | |
333 | */ | |
85cd7251 | 334 | |
669a5db4 | 335 | static struct ata_port_operations hpt3x2n_port_ops = { |
029cfd6b | 336 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 337 | |
669a5db4 | 338 | .bmdma_stop = hpt3x2n_bmdma_stop, |
256ace9b SS |
339 | |
340 | .qc_defer = hpt3x2n_qc_defer, | |
9363c382 | 341 | .qc_issue = hpt3x2n_qc_issue, |
bda30288 | 342 | |
029cfd6b TH |
343 | .cable_detect = hpt3x2n_cable_detect, |
344 | .set_piomode = hpt3x2n_set_piomode, | |
345 | .set_dmamode = hpt3x2n_set_dmamode, | |
a1efdaba | 346 | .prereset = hpt3x2n_pre_reset, |
85cd7251 | 347 | }; |
669a5db4 JG |
348 | |
349 | /** | |
350 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 351 | * @dev: PCI device |
669a5db4 JG |
352 | * |
353 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this | |
354 | * succeeds | |
355 | */ | |
356 | ||
357 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) | |
358 | { | |
359 | u8 reg5b; | |
360 | u32 reg5c; | |
361 | int tries; | |
85cd7251 | 362 | |
669a5db4 JG |
363 | for(tries = 0; tries < 0x5000; tries++) { |
364 | udelay(50); | |
365 | pci_read_config_byte(dev, 0x5b, ®5b); | |
366 | if (reg5b & 0x80) { | |
367 | /* See if it stays set */ | |
368 | for(tries = 0; tries < 0x1000; tries ++) { | |
369 | pci_read_config_byte(dev, 0x5b, ®5b); | |
370 | /* Failed ? */ | |
371 | if ((reg5b & 0x80) == 0) | |
372 | return 0; | |
373 | } | |
374 | /* Turn off tuning, we have the DPLL set */ | |
375 | pci_read_config_dword(dev, 0x5c, ®5c); | |
376 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
377 | return 1; | |
378 | } | |
379 | } | |
380 | /* Never went stable */ | |
381 | return 0; | |
382 | } | |
383 | ||
384 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) | |
385 | { | |
386 | unsigned long freq; | |
387 | u32 fcnt; | |
28e21c8c | 388 | unsigned long iobase = pci_resource_start(pdev, 4); |
85cd7251 | 389 | |
28e21c8c | 390 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
669a5db4 JG |
391 | if ((fcnt >> 12) != 0xABCDE) { |
392 | printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); | |
393 | return 33; /* Not BIOS set */ | |
394 | } | |
395 | fcnt &= 0x1FF; | |
85cd7251 | 396 | |
669a5db4 | 397 | freq = (fcnt * 77) / 192; |
85cd7251 | 398 | |
669a5db4 JG |
399 | /* Clamp to bands */ |
400 | if (freq < 40) | |
401 | return 33; | |
402 | if (freq < 45) | |
403 | return 40; | |
404 | if (freq < 55) | |
405 | return 50; | |
406 | return 66; | |
407 | } | |
408 | ||
409 | /** | |
410 | * hpt3x2n_init_one - Initialise an HPT37X/302 | |
411 | * @dev: PCI device | |
412 | * @id: Entry in match table | |
413 | * | |
414 | * Initialise an HPT3x2n device. There are some interesting complications | |
415 | * here. Firstly the chip may report 366 and be one of several variants. | |
416 | * Secondly all the timings depend on the clock for the chip which we must | |
417 | * detect and look up | |
418 | * | |
419 | * This is the known chip mappings. It may be missing a couple of later | |
420 | * releases. | |
421 | * | |
422 | * Chip version PCI Rev Notes | |
423 | * HPT372 4 (HPT366) 5 Other driver | |
424 | * HPT372N 4 (HPT366) 6 UDMA133 | |
425 | * HPT372 5 (HPT372) 1 Other driver | |
426 | * HPT372N 5 (HPT372) 2 UDMA133 | |
427 | * HPT302 6 (HPT302) * Other driver | |
428 | * HPT302N 6 (HPT302) > 1 UDMA133 | |
429 | * HPT371 7 (HPT371) * Other driver | |
430 | * HPT371N 7 (HPT371) > 1 UDMA133 | |
431 | * HPT374 8 (HPT374) * Other driver | |
432 | * HPT372N 9 (HPT372N) * UDMA133 | |
433 | * | |
434 | * (1) UDMA133 support depends on the bus clock | |
435 | * | |
436 | * To pin down HPT371N | |
437 | */ | |
85cd7251 | 438 | |
669a5db4 JG |
439 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
440 | { | |
441 | /* HPT372N and friends - UDMA133 */ | |
1626aeb8 | 442 | static const struct ata_port_info info = { |
1d2808fd | 443 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
444 | .pio_mask = ATA_PIO4, |
445 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 446 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
447 | .port_ops = &hpt3x2n_port_ops |
448 | }; | |
887125e3 | 449 | const struct ata_port_info *ppi[] = { &info, NULL }; |
89d3b360 | 450 | u8 rev = dev->revision; |
669a5db4 | 451 | u8 irqmask; |
669a5db4 JG |
452 | unsigned int pci_mhz; |
453 | unsigned int f_low, f_high; | |
454 | int adjust; | |
28e21c8c | 455 | unsigned long iobase = pci_resource_start(dev, 4); |
256ace9b | 456 | void *hpriv = (void *)USE_DPLL; |
f08048e9 TH |
457 | int rc; |
458 | ||
459 | rc = pcim_enable_device(dev); | |
460 | if (rc) | |
461 | return rc; | |
85cd7251 | 462 | |
669a5db4 JG |
463 | switch(dev->device) { |
464 | case PCI_DEVICE_ID_TTI_HPT366: | |
89d3b360 | 465 | if (rev < 6) |
669a5db4 JG |
466 | return -ENODEV; |
467 | break; | |
28e21c8c | 468 | case PCI_DEVICE_ID_TTI_HPT371: |
89d3b360 | 469 | if (rev < 2) |
28e21c8c AC |
470 | return -ENODEV; |
471 | /* 371N if rev > 1 */ | |
472 | break; | |
669a5db4 | 473 | case PCI_DEVICE_ID_TTI_HPT372: |
824cf333 | 474 | /* 372N if rev >= 2*/ |
89d3b360 | 475 | if (rev < 2) |
669a5db4 JG |
476 | return -ENODEV; |
477 | break; | |
478 | case PCI_DEVICE_ID_TTI_HPT302: | |
89d3b360 | 479 | if (rev < 2) |
669a5db4 JG |
480 | return -ENODEV; |
481 | break; | |
482 | case PCI_DEVICE_ID_TTI_HPT372N: | |
483 | break; | |
484 | default: | |
485 | printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); | |
486 | return -ENODEV; | |
487 | } | |
488 | ||
489 | /* Ok so this is a chip we support */ | |
490 | ||
491 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
492 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
493 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
494 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
495 | ||
496 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
497 | irqmask &= ~0x10; | |
498 | pci_write_config_byte(dev, 0x5a, irqmask); | |
499 | ||
28e21c8c AC |
500 | /* |
501 | * HPT371 chips physically have only one channel, the secondary one, | |
502 | * but the primary channel registers do exist! Go figure... | |
503 | * So, we manually disable the non-existing channel here | |
504 | * (if the BIOS hasn't done this already). | |
505 | */ | |
506 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { | |
507 | u8 mcr1; | |
508 | pci_read_config_byte(dev, 0x50, &mcr1); | |
509 | mcr1 &= ~0x04; | |
510 | pci_write_config_byte(dev, 0x50, mcr1); | |
511 | } | |
512 | ||
669a5db4 JG |
513 | /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or |
514 | 50 for UDMA100. Right now we always use 66 */ | |
85cd7251 | 515 | |
669a5db4 | 516 | pci_mhz = hpt3x2n_pci_clock(dev); |
85cd7251 | 517 | |
669a5db4 JG |
518 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
519 | f_high = f_low + 2; /* Tolerance */ | |
85cd7251 | 520 | |
669a5db4 JG |
521 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
522 | /* PLL clock */ | |
523 | pci_write_config_byte(dev, 0x5B, 0x21); | |
85cd7251 | 524 | |
669a5db4 JG |
525 | /* Unlike the 37x we don't try jiggling the frequency */ |
526 | for(adjust = 0; adjust < 8; adjust++) { | |
527 | if (hpt3xn_calibrate_dpll(dev)) | |
528 | break; | |
529 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
530 | } | |
28e21c8c | 531 | if (adjust == 8) { |
80b8987c | 532 | printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n"); |
28e21c8c AC |
533 | return -ENODEV; |
534 | } | |
669a5db4 | 535 | |
80b8987c SS |
536 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n", |
537 | pci_mhz); | |
669a5db4 JG |
538 | /* Set our private data up. We only need a few flags so we use |
539 | it directly */ | |
60661933 | 540 | if (pci_mhz > 60) |
256ace9b | 541 | hpriv = (void *)(PCI66 | USE_DPLL); |
60661933 SS |
542 | |
543 | /* | |
544 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
545 | * the MISC. register to stretch the UltraDMA Tss timing. | |
546 | * NOTE: This register is only writeable via I/O space. | |
547 | */ | |
548 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) | |
549 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); | |
85cd7251 | 550 | |
669a5db4 | 551 | /* Now kick off ATA set up */ |
9363c382 | 552 | return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv); |
669a5db4 JG |
553 | } |
554 | ||
2d2744fc JG |
555 | static const struct pci_device_id hpt3x2n[] = { |
556 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
28e21c8c | 557 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
2d2744fc JG |
558 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
559 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
560 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, | |
561 | ||
562 | { }, | |
669a5db4 JG |
563 | }; |
564 | ||
565 | static struct pci_driver hpt3x2n_pci_driver = { | |
2d2744fc | 566 | .name = DRV_NAME, |
669a5db4 JG |
567 | .id_table = hpt3x2n, |
568 | .probe = hpt3x2n_init_one, | |
569 | .remove = ata_pci_remove_one | |
570 | }; | |
571 | ||
572 | static int __init hpt3x2n_init(void) | |
573 | { | |
574 | return pci_register_driver(&hpt3x2n_pci_driver); | |
575 | } | |
576 | ||
669a5db4 JG |
577 | static void __exit hpt3x2n_exit(void) |
578 | { | |
579 | pci_unregister_driver(&hpt3x2n_pci_driver); | |
580 | } | |
581 | ||
669a5db4 JG |
582 | MODULE_AUTHOR("Alan Cox"); |
583 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x"); | |
584 | MODULE_LICENSE("GPL"); | |
585 | MODULE_DEVICE_TABLE(pci, hpt3x2n); | |
586 | MODULE_VERSION(DRV_VERSION); | |
587 | ||
588 | module_init(hpt3x2n_init); | |
589 | module_exit(hpt3x2n_exit); |