Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
80b8987c | 11 | * Portions Copyright (C) 2005-2007 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * | |
14 | * TODO | |
669a5db4 JG |
15 | * Work out best PLL policy |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt3x2n" | |
80b8987c | 28 | #define DRV_VERSION "0.3.4" |
669a5db4 JG |
29 | |
30 | enum { | |
31 | HPT_PCI_FAST = (1 << 31), | |
32 | PCI66 = (1 << 1), | |
33 | USE_DPLL = (1 << 0) | |
34 | }; | |
35 | ||
36 | struct hpt_clock { | |
37 | u8 xfer_speed; | |
38 | u32 timing; | |
39 | }; | |
40 | ||
41 | struct hpt_chip { | |
42 | const char *name; | |
43 | struct hpt_clock *clocks[3]; | |
44 | }; | |
45 | ||
46 | /* key for bus clock timings | |
47 | * bit | |
48 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | |
49 | * DMA. cycles = value + 1 | |
50 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | |
51 | * DMA. cycles = value + 1 | |
52 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | |
53 | * register access. | |
54 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | |
55 | * register access. | |
56 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | |
57 | * during task file register access. | |
58 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | |
59 | * xfer. | |
60 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | |
61 | * register access. | |
62 | * 28 UDMA enable | |
63 | * 29 DMA enable | |
64 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | |
65 | * PIO. | |
66 | * 31 FIFO enable. | |
67 | */ | |
85cd7251 | 68 | |
669a5db4 JG |
69 | /* 66MHz DPLL clocks */ |
70 | ||
71 | static struct hpt_clock hpt3x2n_clocks[] = { | |
72 | { XFER_UDMA_7, 0x1c869c62 }, | |
73 | { XFER_UDMA_6, 0x1c869c62 }, | |
74 | { XFER_UDMA_5, 0x1c8a9c62 }, | |
75 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
76 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
77 | { XFER_UDMA_2, 0x1c929c62 }, | |
78 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
79 | { XFER_UDMA_0, 0x1c829c62 }, | |
80 | ||
81 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
82 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
83 | { XFER_MW_DMA_0, 0x2c829d2c }, | |
84 | ||
85 | { XFER_PIO_4, 0x0c829c62 }, | |
86 | { XFER_PIO_3, 0x0c829c84 }, | |
87 | { XFER_PIO_2, 0x0c829ca6 }, | |
88 | { XFER_PIO_1, 0x0d029d26 }, | |
89 | { XFER_PIO_0, 0x0d029d5e }, | |
90 | { 0, 0x0d029d5e } | |
91 | }; | |
92 | ||
93 | /** | |
94 | * hpt3x2n_find_mode - reset the hpt3x2n bus | |
95 | * @ap: ATA port | |
96 | * @speed: transfer mode | |
97 | * | |
98 | * Return the 32bit register programming information for this channel | |
99 | * that matches the speed provided. For the moment the clocks table | |
100 | * is hard coded but easy to change. This will be needed if we use | |
101 | * different DPLLs | |
102 | */ | |
85cd7251 | 103 | |
669a5db4 JG |
104 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
105 | { | |
106 | struct hpt_clock *clocks = hpt3x2n_clocks; | |
85cd7251 | 107 | |
669a5db4 JG |
108 | while(clocks->xfer_speed) { |
109 | if (clocks->xfer_speed == speed) | |
110 | return clocks->timing; | |
111 | clocks++; | |
112 | } | |
113 | BUG(); | |
114 | return 0xffffffffU; /* silence compiler warning */ | |
115 | } | |
116 | ||
117 | /** | |
a0fcdc02 JG |
118 | * hpt3x2n_cable_detect - Detect the cable type |
119 | * @ap: ATA port to detect on | |
669a5db4 | 120 | * |
a0fcdc02 | 121 | * Return the cable type attached to this port |
669a5db4 | 122 | */ |
85cd7251 | 123 | |
a0fcdc02 | 124 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
669a5db4 JG |
125 | { |
126 | u8 scr2, ata66; | |
127 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 128 | |
669a5db4 JG |
129 | pci_read_config_byte(pdev, 0x5B, &scr2); |
130 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
131 | |
132 | udelay(10); /* debounce */ | |
133 | ||
669a5db4 JG |
134 | /* Cable register now active */ |
135 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
136 | /* Restore state */ | |
137 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 138 | |
f3b1cf40 | 139 | if (ata66 & (2 >> ap->port_no)) |
a0fcdc02 | 140 | return ATA_CBL_PATA40; |
669a5db4 | 141 | else |
a0fcdc02 JG |
142 | return ATA_CBL_PATA80; |
143 | } | |
144 | ||
145 | /** | |
146 | * hpt3x2n_pre_reset - reset the hpt3x2n bus | |
cc0680a5 | 147 | * @link: ATA link to reset |
28e21c8c | 148 | * @deadline: deadline jiffies for the operation |
a0fcdc02 JG |
149 | * |
150 | * Perform the initial reset handling for the 3x2n series controllers. | |
151 | * Reset the hardware and state machine, | |
152 | */ | |
669a5db4 | 153 | |
a1efdaba | 154 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
a0fcdc02 | 155 | { |
cc0680a5 | 156 | struct ata_port *ap = link->ap; |
a0fcdc02 | 157 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 158 | /* Reset the state machine */ |
28e21c8c | 159 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 160 | udelay(100); |
d4b2bab4 | 161 | |
9363c382 | 162 | return ata_sff_prereset(link, deadline); |
669a5db4 | 163 | } |
85cd7251 | 164 | |
669a5db4 JG |
165 | /** |
166 | * hpt3x2n_set_piomode - PIO setup | |
167 | * @ap: ATA interface | |
168 | * @adev: device on the interface | |
169 | * | |
85cd7251 | 170 | * Perform PIO mode setup. |
669a5db4 | 171 | */ |
85cd7251 | 172 | |
669a5db4 JG |
173 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) |
174 | { | |
175 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
176 | u32 addr1, addr2; | |
177 | u32 reg; | |
178 | u32 mode; | |
179 | u8 fast; | |
180 | ||
181 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
182 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 183 | |
669a5db4 JG |
184 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
185 | pci_read_config_byte(pdev, addr2, &fast); | |
186 | fast &= ~0x07; | |
187 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 188 | |
669a5db4 JG |
189 | pci_read_config_dword(pdev, addr1, ®); |
190 | mode = hpt3x2n_find_mode(ap, adev->pio_mode); | |
191 | mode &= ~0x8000000; /* No FIFO in PIO */ | |
192 | mode &= ~0x30070000; /* Leave config bits alone */ | |
193 | reg &= 0x30070000; /* Strip timing bits */ | |
194 | pci_write_config_dword(pdev, addr1, reg | mode); | |
195 | } | |
196 | ||
197 | /** | |
198 | * hpt3x2n_set_dmamode - DMA timing setup | |
199 | * @ap: ATA interface | |
200 | * @adev: Device being configured | |
201 | * | |
202 | * Set up the channel for MWDMA or UDMA modes. Much the same as with | |
203 | * PIO, load the mode number and then set MWDMA or UDMA flag. | |
204 | */ | |
85cd7251 | 205 | |
669a5db4 JG |
206 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
207 | { | |
208 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
209 | u32 addr1, addr2; | |
210 | u32 reg; | |
211 | u32 mode; | |
212 | u8 fast; | |
213 | ||
214 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
215 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 216 | |
669a5db4 JG |
217 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
218 | pci_read_config_byte(pdev, addr2, &fast); | |
219 | fast &= ~0x07; | |
220 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 221 | |
669a5db4 JG |
222 | pci_read_config_dword(pdev, addr1, ®); |
223 | mode = hpt3x2n_find_mode(ap, adev->dma_mode); | |
224 | mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ | |
225 | mode &= ~0xC0000000; /* Leave config bits alone */ | |
226 | reg &= 0xC0000000; /* Strip timing bits */ | |
227 | pci_write_config_dword(pdev, addr1, reg | mode); | |
228 | } | |
229 | ||
230 | /** | |
231 | * hpt3x2n_bmdma_end - DMA engine stop | |
232 | * @qc: ATA command | |
233 | * | |
234 | * Clean up after the HPT3x2n and later DMA engine | |
235 | */ | |
85cd7251 | 236 | |
669a5db4 JG |
237 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
238 | { | |
239 | struct ata_port *ap = qc->ap; | |
240 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
241 | int mscreg = 0x50 + 2 * ap->port_no; | |
242 | u8 bwsr_stat, msc_stat; | |
85cd7251 | 243 | |
669a5db4 JG |
244 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
245 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
246 | if (bwsr_stat & (1 << ap->port_no)) | |
247 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
248 | ata_bmdma_stop(qc); | |
249 | } | |
250 | ||
251 | /** | |
252 | * hpt3x2n_set_clock - clock control | |
253 | * @ap: ATA port | |
254 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock | |
255 | * | |
256 | * Switch the ATA bus clock between the PLL and PCI clock sources | |
257 | * while correctly isolating the bus and resetting internal logic | |
258 | * | |
259 | * We must use the DPLL for | |
260 | * - writing | |
261 | * - second channel UDMA7 (SATA ports) or higher | |
262 | * - 66MHz PCI | |
85cd7251 | 263 | * |
669a5db4 JG |
264 | * or we will underclock the device and get reduced performance. |
265 | */ | |
85cd7251 | 266 | |
669a5db4 JG |
267 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
268 | { | |
0d5ff566 | 269 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
85cd7251 | 270 | |
669a5db4 | 271 | /* Tristate the bus */ |
0d5ff566 TH |
272 | iowrite8(0x80, bmdma+0x73); |
273 | iowrite8(0x80, bmdma+0x77); | |
85cd7251 | 274 | |
669a5db4 | 275 | /* Switch clock and reset channels */ |
0d5ff566 TH |
276 | iowrite8(source, bmdma+0x7B); |
277 | iowrite8(0xC0, bmdma+0x79); | |
85cd7251 | 278 | |
669a5db4 | 279 | /* Reset state machines */ |
0d5ff566 TH |
280 | iowrite8(0x37, bmdma+0x70); |
281 | iowrite8(0x37, bmdma+0x74); | |
85cd7251 | 282 | |
669a5db4 | 283 | /* Complete reset */ |
0d5ff566 | 284 | iowrite8(0x00, bmdma+0x79); |
85cd7251 | 285 | |
669a5db4 | 286 | /* Reconnect channels to bus */ |
0d5ff566 TH |
287 | iowrite8(0x00, bmdma+0x73); |
288 | iowrite8(0x00, bmdma+0x77); | |
669a5db4 JG |
289 | } |
290 | ||
291 | /* Check if our partner interface is busy */ | |
292 | ||
293 | static int hpt3x2n_pair_idle(struct ata_port *ap) | |
294 | { | |
295 | struct ata_host *host = ap->host; | |
296 | struct ata_port *pair = host->ports[ap->port_no ^ 1]; | |
85cd7251 | 297 | |
669a5db4 JG |
298 | if (pair->hsm_task_state == HSM_ST_IDLE) |
299 | return 1; | |
300 | return 0; | |
301 | } | |
302 | ||
a52865c2 | 303 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
669a5db4 JG |
304 | { |
305 | long flags = (long)ap->host->private_data; | |
306 | /* See if we should use the DPLL */ | |
a52865c2 | 307 | if (writing) |
669a5db4 JG |
308 | return USE_DPLL; /* Needed for write */ |
309 | if (flags & PCI66) | |
310 | return USE_DPLL; /* Needed at 66Mhz */ | |
85cd7251 | 311 | return 0; |
669a5db4 JG |
312 | } |
313 | ||
9363c382 | 314 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
315 | { |
316 | struct ata_taskfile *tf = &qc->tf; | |
317 | struct ata_port *ap = qc->ap; | |
318 | int flags = (long)ap->host->private_data; | |
85cd7251 | 319 | |
669a5db4 JG |
320 | if (hpt3x2n_pair_idle(ap)) { |
321 | int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE)); | |
322 | if ((flags & USE_DPLL) != dpll) { | |
323 | if (dpll == 1) | |
324 | hpt3x2n_set_clock(ap, 0x21); | |
325 | else | |
326 | hpt3x2n_set_clock(ap, 0x23); | |
327 | } | |
328 | } | |
9363c382 | 329 | return ata_sff_qc_issue(qc); |
669a5db4 JG |
330 | } |
331 | ||
332 | static struct scsi_host_template hpt3x2n_sht = { | |
68d1d07b | 333 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
334 | }; |
335 | ||
336 | /* | |
337 | * Configuration for HPT3x2n. | |
338 | */ | |
85cd7251 | 339 | |
669a5db4 | 340 | static struct ata_port_operations hpt3x2n_port_ops = { |
029cfd6b | 341 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 342 | |
669a5db4 | 343 | .bmdma_stop = hpt3x2n_bmdma_stop, |
9363c382 | 344 | .qc_issue = hpt3x2n_qc_issue, |
bda30288 | 345 | |
029cfd6b TH |
346 | .cable_detect = hpt3x2n_cable_detect, |
347 | .set_piomode = hpt3x2n_set_piomode, | |
348 | .set_dmamode = hpt3x2n_set_dmamode, | |
a1efdaba | 349 | .prereset = hpt3x2n_pre_reset, |
85cd7251 | 350 | }; |
669a5db4 JG |
351 | |
352 | /** | |
353 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 354 | * @dev: PCI device |
669a5db4 JG |
355 | * |
356 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this | |
357 | * succeeds | |
358 | */ | |
359 | ||
360 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) | |
361 | { | |
362 | u8 reg5b; | |
363 | u32 reg5c; | |
364 | int tries; | |
85cd7251 | 365 | |
669a5db4 JG |
366 | for(tries = 0; tries < 0x5000; tries++) { |
367 | udelay(50); | |
368 | pci_read_config_byte(dev, 0x5b, ®5b); | |
369 | if (reg5b & 0x80) { | |
370 | /* See if it stays set */ | |
371 | for(tries = 0; tries < 0x1000; tries ++) { | |
372 | pci_read_config_byte(dev, 0x5b, ®5b); | |
373 | /* Failed ? */ | |
374 | if ((reg5b & 0x80) == 0) | |
375 | return 0; | |
376 | } | |
377 | /* Turn off tuning, we have the DPLL set */ | |
378 | pci_read_config_dword(dev, 0x5c, ®5c); | |
379 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
380 | return 1; | |
381 | } | |
382 | } | |
383 | /* Never went stable */ | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) | |
388 | { | |
389 | unsigned long freq; | |
390 | u32 fcnt; | |
28e21c8c | 391 | unsigned long iobase = pci_resource_start(pdev, 4); |
85cd7251 | 392 | |
28e21c8c | 393 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
669a5db4 JG |
394 | if ((fcnt >> 12) != 0xABCDE) { |
395 | printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); | |
396 | return 33; /* Not BIOS set */ | |
397 | } | |
398 | fcnt &= 0x1FF; | |
85cd7251 | 399 | |
669a5db4 | 400 | freq = (fcnt * 77) / 192; |
85cd7251 | 401 | |
669a5db4 JG |
402 | /* Clamp to bands */ |
403 | if (freq < 40) | |
404 | return 33; | |
405 | if (freq < 45) | |
406 | return 40; | |
407 | if (freq < 55) | |
408 | return 50; | |
409 | return 66; | |
410 | } | |
411 | ||
412 | /** | |
413 | * hpt3x2n_init_one - Initialise an HPT37X/302 | |
414 | * @dev: PCI device | |
415 | * @id: Entry in match table | |
416 | * | |
417 | * Initialise an HPT3x2n device. There are some interesting complications | |
418 | * here. Firstly the chip may report 366 and be one of several variants. | |
419 | * Secondly all the timings depend on the clock for the chip which we must | |
420 | * detect and look up | |
421 | * | |
422 | * This is the known chip mappings. It may be missing a couple of later | |
423 | * releases. | |
424 | * | |
425 | * Chip version PCI Rev Notes | |
426 | * HPT372 4 (HPT366) 5 Other driver | |
427 | * HPT372N 4 (HPT366) 6 UDMA133 | |
428 | * HPT372 5 (HPT372) 1 Other driver | |
429 | * HPT372N 5 (HPT372) 2 UDMA133 | |
430 | * HPT302 6 (HPT302) * Other driver | |
431 | * HPT302N 6 (HPT302) > 1 UDMA133 | |
432 | * HPT371 7 (HPT371) * Other driver | |
433 | * HPT371N 7 (HPT371) > 1 UDMA133 | |
434 | * HPT374 8 (HPT374) * Other driver | |
435 | * HPT372N 9 (HPT372N) * UDMA133 | |
436 | * | |
437 | * (1) UDMA133 support depends on the bus clock | |
438 | * | |
439 | * To pin down HPT371N | |
440 | */ | |
85cd7251 | 441 | |
669a5db4 JG |
442 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
443 | { | |
444 | /* HPT372N and friends - UDMA133 */ | |
1626aeb8 | 445 | static const struct ata_port_info info = { |
1d2808fd | 446 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
447 | .pio_mask = ATA_PIO4, |
448 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 449 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
450 | .port_ops = &hpt3x2n_port_ops |
451 | }; | |
887125e3 | 452 | const struct ata_port_info *ppi[] = { &info, NULL }; |
669a5db4 JG |
453 | |
454 | u8 irqmask; | |
455 | u32 class_rev; | |
85cd7251 | 456 | |
669a5db4 JG |
457 | unsigned int pci_mhz; |
458 | unsigned int f_low, f_high; | |
459 | int adjust; | |
28e21c8c | 460 | unsigned long iobase = pci_resource_start(dev, 4); |
887125e3 | 461 | void *hpriv = NULL; |
f08048e9 TH |
462 | int rc; |
463 | ||
464 | rc = pcim_enable_device(dev); | |
465 | if (rc) | |
466 | return rc; | |
85cd7251 | 467 | |
669a5db4 JG |
468 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); |
469 | class_rev &= 0xFF; | |
85cd7251 | 470 | |
669a5db4 JG |
471 | switch(dev->device) { |
472 | case PCI_DEVICE_ID_TTI_HPT366: | |
473 | if (class_rev < 6) | |
474 | return -ENODEV; | |
475 | break; | |
28e21c8c AC |
476 | case PCI_DEVICE_ID_TTI_HPT371: |
477 | if (class_rev < 2) | |
478 | return -ENODEV; | |
479 | /* 371N if rev > 1 */ | |
480 | break; | |
669a5db4 | 481 | case PCI_DEVICE_ID_TTI_HPT372: |
824cf333 AC |
482 | /* 372N if rev >= 2*/ |
483 | if (class_rev < 2) | |
669a5db4 JG |
484 | return -ENODEV; |
485 | break; | |
486 | case PCI_DEVICE_ID_TTI_HPT302: | |
487 | if (class_rev < 2) | |
488 | return -ENODEV; | |
489 | break; | |
490 | case PCI_DEVICE_ID_TTI_HPT372N: | |
491 | break; | |
492 | default: | |
493 | printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); | |
494 | return -ENODEV; | |
495 | } | |
496 | ||
497 | /* Ok so this is a chip we support */ | |
498 | ||
499 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
500 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
501 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
502 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
503 | ||
504 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
505 | irqmask &= ~0x10; | |
506 | pci_write_config_byte(dev, 0x5a, irqmask); | |
507 | ||
28e21c8c AC |
508 | /* |
509 | * HPT371 chips physically have only one channel, the secondary one, | |
510 | * but the primary channel registers do exist! Go figure... | |
511 | * So, we manually disable the non-existing channel here | |
512 | * (if the BIOS hasn't done this already). | |
513 | */ | |
514 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { | |
515 | u8 mcr1; | |
516 | pci_read_config_byte(dev, 0x50, &mcr1); | |
517 | mcr1 &= ~0x04; | |
518 | pci_write_config_byte(dev, 0x50, mcr1); | |
519 | } | |
520 | ||
669a5db4 JG |
521 | /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or |
522 | 50 for UDMA100. Right now we always use 66 */ | |
85cd7251 | 523 | |
669a5db4 | 524 | pci_mhz = hpt3x2n_pci_clock(dev); |
85cd7251 | 525 | |
669a5db4 JG |
526 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
527 | f_high = f_low + 2; /* Tolerance */ | |
85cd7251 | 528 | |
669a5db4 JG |
529 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
530 | /* PLL clock */ | |
531 | pci_write_config_byte(dev, 0x5B, 0x21); | |
85cd7251 | 532 | |
669a5db4 JG |
533 | /* Unlike the 37x we don't try jiggling the frequency */ |
534 | for(adjust = 0; adjust < 8; adjust++) { | |
535 | if (hpt3xn_calibrate_dpll(dev)) | |
536 | break; | |
537 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
538 | } | |
28e21c8c | 539 | if (adjust == 8) { |
80b8987c | 540 | printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n"); |
28e21c8c AC |
541 | return -ENODEV; |
542 | } | |
669a5db4 | 543 | |
80b8987c SS |
544 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n", |
545 | pci_mhz); | |
669a5db4 JG |
546 | /* Set our private data up. We only need a few flags so we use |
547 | it directly */ | |
28e21c8c | 548 | if (pci_mhz > 60) { |
887125e3 | 549 | hpriv = (void *)PCI66; |
28e21c8c AC |
550 | /* |
551 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
552 | * the MISC. register to stretch the UltraDMA Tss timing. | |
553 | * NOTE: This register is only writeable via I/O space. | |
554 | */ | |
555 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) | |
556 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); | |
557 | } | |
85cd7251 | 558 | |
669a5db4 | 559 | /* Now kick off ATA set up */ |
9363c382 | 560 | return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv); |
669a5db4 JG |
561 | } |
562 | ||
2d2744fc JG |
563 | static const struct pci_device_id hpt3x2n[] = { |
564 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
28e21c8c | 565 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
2d2744fc JG |
566 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
567 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
568 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, | |
569 | ||
570 | { }, | |
669a5db4 JG |
571 | }; |
572 | ||
573 | static struct pci_driver hpt3x2n_pci_driver = { | |
2d2744fc | 574 | .name = DRV_NAME, |
669a5db4 JG |
575 | .id_table = hpt3x2n, |
576 | .probe = hpt3x2n_init_one, | |
577 | .remove = ata_pci_remove_one | |
578 | }; | |
579 | ||
580 | static int __init hpt3x2n_init(void) | |
581 | { | |
582 | return pci_register_driver(&hpt3x2n_pci_driver); | |
583 | } | |
584 | ||
669a5db4 JG |
585 | static void __exit hpt3x2n_exit(void) |
586 | { | |
587 | pci_unregister_driver(&hpt3x2n_pci_driver); | |
588 | } | |
589 | ||
669a5db4 JG |
590 | MODULE_AUTHOR("Alan Cox"); |
591 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x"); | |
592 | MODULE_LICENSE("GPL"); | |
593 | MODULE_DEVICE_TABLE(pci, hpt3x2n); | |
594 | MODULE_VERSION(DRV_VERSION); | |
595 | ||
596 | module_init(hpt3x2n_init); | |
597 | module_exit(hpt3x2n_exit); |