[deliverable/linux.git] / drivers / ata / pata_it8213.c

/*
 *    pata_it8213.c - iTE Tech. Inc.  IT8213 PATA driver
 *
 *    The IT8213 is a very Intel ICH like device for timing purposes, having
 *    a similar register layout and the same split clock arrangement. Cable
 *    detection is different, and it does not have slave channels or all the
 *    clutter of later ICH/SATA setups.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_it8213"
#define DRV_VERSION	"0.0.2"

/**
 *	it8213_pre_reset	-	check for 40/80 pin
 *	@ap: Port
 *
 *	Filter out ports by the enable bits before doing the normal reset
 *	and probe.
 */

static int it8213_pre_reset(struct ata_port *ap)
{
	static const struct pci_bits it8213_enable_bits[] = {
		{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
	};
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
		return -ENOENT;
	return ata_std_prereset(ap);
}

/**
 *	it8213_error_handler - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void it8213_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, it8213_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	it8213_cable_detect	-	check for 40/80 pin
 *	@ap: Port
 *
 *	Perform cable detection for the 8213 ATA interface. This is
 *	different to the PIIX arrangement
 */

static int it8213_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x42, &tmp);
	if (tmp & 2)	/* The initial docs are incorrect */
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	it8213_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	u16 idetm_data;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. The 8213 is a clone so very similar
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	if (pio > 2)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))	/* PIO 3/4 require IORDY */
		control |= 2;	/* IORDY enable */
	/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
	if (adev->class != ATA_DEV_ATA)
		control |= 4;

	pci_read_config_word(dev, idetm_port, &idetm_data);

	/* Enable PPE, IE and TIME as appropriate */

	if (adev->devno == 0) {
		idetm_data &= 0xCCF0;
		idetm_data |= control;
		idetm_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	} else {
		u8 slave_data;

		idetm_data &= 0xCC0F;
		idetm_data |= (control << 4);

		/* Slave timing in seperate register */
		pci_read_config_byte(dev, 0x44, &slave_data);
		slave_data &= 0xF0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << 4;
		pci_write_config_byte(dev, 0x44, slave_data);
	}

	idetm_data |= 0x4000;	/* Ensure SITRE is enabled */
	pci_write_config_word(dev, idetm_port, idetm_data);
}

/**
 *	it8213_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set UDMA/MWDMA mode for device, in host controller PCI config space.
 *	This device is basically an ICH alike.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(dev, 0x40, &master_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (speed >= XFER_UDMA_0) {
		unsigned int udma = adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;
		u16 ideconf;
		int u_clock, u_speed;

		/* Clocks follow the PIIX style */
		u_speed = min(2 - (udma & 1), udma);
		if (udma == 5)
			u_clock = 0x1000;	/* 100Mhz */
		else if (udma > 2)
			u_clock = 1;		/* 66Mhz */
		else
			u_clock = 0;		/* 33Mhz */

		udma_enable |= (1 << devid);

		/* Load the UDMA mode number */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(3 << (4 * devid));
		udma_timing |= (udma & 3) << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);

		/* Load the clock selection */
		pci_read_config_word(dev, 0x54, &ideconf);
		ideconf &= ~(0x1001 << devid);
		ideconf |= u_clock << devid;
		pci_write_config_word(dev, 0x54, ideconf);
	} else {
		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		static const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;

		control = 3;	/* IORDY|TIME1 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */

		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (devid) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
			slave_data &= (0x0F + 0xE1 * ap->port_no);
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
		udma_enable &= ~(1 << devid);
		pci_write_config_word(dev, 0x40, master_data);
	}
	pci_write_config_byte(dev, 0x48, udma_enable);
}

static struct scsi_host_template it8213_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
#ifdef CONFIG_PM
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
#endif
};

static const struct ata_port_operations it8213_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= it8213_set_piomode,
	.set_dmamode		= it8213_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= it8213_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.cable_detect		= it8213_cable_detect,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};


/**
 *	it8213_init_one - Register 8213 ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in it8213_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	static struct ata_port_info info = {
		.sht		= &it8213_sht,
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= 0x1f, /* UDMA 100 */
		.port_ops	= &it8213_ops,
	};
	static struct ata_port_info *port_info[2] = { &info, &info };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	/* Current IT8213 stuff is single port */
	return ata_pci_init_one(pdev, port_info, 1);
}

static const struct pci_device_id it8213_pci_tbl[] = {
	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },

	{ }	/* terminate list */
};

static struct pci_driver it8213_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= it8213_pci_tbl,
	.probe			= it8213_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

static int __init it8213_init(void)
{
	return pci_register_driver(&it8213_pci_driver);
}

static void __exit it8213_exit(void)
{
	pci_unregister_driver(&it8213_pci_driver);
}

module_init(it8213_init);
module_exit(it8213_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
9b13b682 A	1	/*
	2	* pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
	3	*
	4	* The IT8213 is a very Intel ICH like device for timing purposes, having
	5	* a similar register layout and the same split clock arrangement. Cable
	6	* detection is different, and it does not have slave channels or all the
	7	* clutter of later ICH/SATA setups.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
	14	#include <linux/blkdev.h>
	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <scsi/scsi_host.h>
	18	#include <linux/libata.h>
	19	#include <linux/ata.h>
	20
	21	#define DRV_NAME "pata_it8213"
	22	#define DRV_VERSION "0.0.2"
	23
	24	/**
	25	* it8213_pre_reset - check for 40/80 pin
	26	* @ap: Port
	27	*
5816fbbf AC	28	* Filter out ports by the enable bits before doing the normal reset
5816fbbf AC	29	* and probe.
9b13b682 A	30	*/
	31
	32	static int it8213_pre_reset(struct ata_port *ap)
	33	{
	34	static const struct pci_bits it8213_enable_bits[] = {
	35	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	36	};
9b13b682	37	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
9b13b682 A	38	if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
9b13b682 A	39	return -ENOENT;
9b13b682 A	40	return ata_std_prereset(ap);
	41	}
	42
	43	/**
5816fbbf	44	* it8213_error_handler - Probe specified port on PATA host controller
9b13b682 A	45	* @ap: Port to probe
	46	*
	47	* LOCKING:
	48	* None (inherited from caller).
	49	*/
	50
	51	static void it8213_error_handler(struct ata_port *ap)
	52	{
	53	ata_bmdma_drive_eh(ap, it8213_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	54	}
	55
5816fbbf AC	56	/**
	57	* it8213_cable_detect - check for 40/80 pin
	58	* @ap: Port
	59	*
	60	* Perform cable detection for the 8213 ATA interface. This is
	61	* different to the PIIX arrangement
	62	*/
	63
	64	static int it8213_cable_detect(struct ata_port *ap)
	65	{
	66	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	67	u8 tmp;
	68	pci_read_config_byte(pdev, 0x42, &tmp);
	69	if (tmp & 2) /* The initial docs are incorrect */
	70	return ATA_CBL_PATA40;
	71	return ATA_CBL_PATA80;
	72	}
	73
9b13b682 A	74	/**
	75	* it8213_set_piomode - Initialize host controller PATA PIO timings
	76	* @ap: Port whose timings we are configuring
5816fbbf	77	* @adev: Device whose timings we are configuring
9b13b682 A	78	*
	79	* Set PIO mode for device, in host controller PCI config space.
	80	*
	81	* LOCKING:
	82	* None (inherited from caller).
	83	*/
	84
	85	static void it8213_set_piomode (struct ata_port ap, struct ata_device adev)
	86	{
	87	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	88	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	89	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	90	u16 idetm_data;
	91	int control = 0;
	92
	93	/*
	94	* See Intel Document 298600-004 for the timing programing rules
	95	* for PIIX/ICH. The 8213 is a clone so very similar
	96	*/
	97
	98	static const /* ISP RTC */
	99	u8 timings[][2] = { { 0, 0 },
	100	{ 0, 0 },
	101	{ 1, 0 },
	102	{ 2, 1 },
	103	{ 2, 3 }, };
	104
	105	if (pio > 2)
	106	control \|= 1; /* TIME1 enable */
	107	if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
	108	control \|= 2; /* IORDY enable */
	109	/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
	110	if (adev->class != ATA_DEV_ATA)
	111	control \|= 4;
	112
	113	pci_read_config_word(dev, idetm_port, &idetm_data);
	114
	115	/* Enable PPE, IE and TIME as appropriate */
	116
	117	if (adev->devno == 0) {
	118	idetm_data &= 0xCCF0;
	119	idetm_data \|= control;
	120	idetm_data \|= (timings[pio][0] << 12) \|
	121	(timings[pio][1] << 8);
	122	} else {
	123	u8 slave_data;
	124
	125	idetm_data &= 0xCC0F;
	126	idetm_data \|= (control << 4);
	127
	128	/* Slave timing in seperate register */
	129	pci_read_config_byte(dev, 0x44, &slave_data);
	130	slave_data &= 0xF0;
	131	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << 4;
	132	pci_write_config_byte(dev, 0x44, slave_data);
	133	}
	134
	135	idetm_data \|= 0x4000; /* Ensure SITRE is enabled */
	136	pci_write_config_word(dev, idetm_port, idetm_data);
	137	}
	138
	139	/**
	140	* it8213_set_dmamode - Initialize host controller PATA DMA timings
	141	* @ap: Port whose timings we are configuring
142	* @adev: Device to program
143	*
144	* Set UDMA/MWDMA mode for device, in host controller PCI config space.
145	* This device is basically an ICH alike.
146	*
147	* LOCKING:
148	* None (inherited from caller).
149	*/
150
151	static void it8213_set_dmamode (struct ata_port ap, struct ata_device adev)
152	{
153	struct pci_dev *dev = to_pci_dev(ap->host->dev);
154	u16 master_data;
155	u8 speed = adev->dma_mode;
156	int devid = adev->devno;
157	u8 udma_enable;
158
159	static const /* ISP RTC */
160	u8 timings[][2] = { { 0, 0 },
161	{ 0, 0 },
162	{ 1, 0 },
163	{ 2, 1 },
164	{ 2, 3 }, };
165
166	pci_read_config_word(dev, 0x40, &master_data);
167	pci_read_config_byte(dev, 0x48, &udma_enable);
168
169	if (speed >= XFER_UDMA_0) {
170	unsigned int udma = adev->dma_mode - XFER_UDMA_0;
171	u16 udma_timing;
172	u16 ideconf;
173	int u_clock, u_speed;
174
175	/* Clocks follow the PIIX style */
176	u_speed = min(2 - (udma & 1), udma);
177	if (udma == 5)
178	u_clock = 0x1000; /* 100Mhz */
179	else if (udma > 2)
180	u_clock = 1; /* 66Mhz */
181	else
182	u_clock = 0; /* 33Mhz */
183
184	udma_enable \|= (1 << devid);
185
186	/* Load the UDMA mode number */
187	pci_read_config_word(dev, 0x4A, &udma_timing);
188	udma_timing &= ~(3 << (4 * devid));
189	udma_timing \|= (udma & 3) << (4 * devid);
190	pci_write_config_word(dev, 0x4A, udma_timing);
191
192	/* Load the clock selection */
193	pci_read_config_word(dev, 0x54, &ideconf);
194	ideconf &= ~(0x1001 << devid);
195	ideconf \|= u_clock << devid;
196	pci_write_config_word(dev, 0x54, ideconf);
197	} else {
198	/*
199	* MWDMA is driven by the PIO timings. We must also enable
200	* IORDY unconditionally along with TIME1. PPE has already
201	* been set when the PIO timing was set.
202	*/
203	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
204	unsigned int control;
205	u8 slave_data;
206	static const unsigned int needed_pio[3] = {
207	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
208	};
209	int pio = needed_pio[mwdma] - XFER_PIO_0;
210
211	control = 3; /* IORDY\|TIME1 */
212
213	/* If the drive MWDMA is faster than it can do PIO then
214	we must force PIO into PIO0 */
215
216	if (adev->pio_mode < needed_pio[mwdma])
217	/* Enable DMA timing only */
218	control \|= 8; /* PIO cycles in PIO0 */
219
220	if (devid) { /* Slave */
221	master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
222	master_data \|= control << 4;
223	pci_read_config_byte(dev, 0x44, &slave_data);
224	slave_data &= (0x0F + 0xE1 * ap->port_no);
225	/* Load the matching timing */
226	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
227	pci_write_config_byte(dev, 0x44, slave_data);
228	} else { /* Master */
229	master_data &= 0xCCF4; /* Mask out IORDY\|TIME1\|DMAONLY
230	and master timing bits */
231	master_data \|= control;
232	master_data \|=
233	(timings[pio][0] << 12) \|
234	(timings[pio][1] << 8);
235	}
236	udma_enable &= ~(1 << devid);
237	pci_write_config_word(dev, 0x40, master_data);
238	}
239	pci_write_config_byte(dev, 0x48, udma_enable);
240	}
241
242	static struct scsi_host_template it8213_sht = {
243	.module = THIS_MODULE,
244	.name = DRV_NAME,
245	.ioctl = ata_scsi_ioctl,
246	.queuecommand = ata_scsi_queuecmd,
247	.can_queue = ATA_DEF_QUEUE,
248	.this_id = ATA_SHT_THIS_ID,
249	.sg_tablesize = LIBATA_MAX_PRD,
250	.max_sectors = ATA_MAX_SECTORS,
251	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
252	.emulated = ATA_SHT_EMULATED,
253	.use_clustering = ATA_SHT_USE_CLUSTERING,
254	.proc_name = DRV_NAME,
255	.dma_boundary = ATA_DMA_BOUNDARY,
256	.slave_configure = ata_scsi_slave_config,
257	.bios_param = ata_std_bios_param,
438ac6d5	258	#ifdef CONFIG_PM
9b13b682 A	259	.resume = ata_scsi_device_resume,
9b13b682 A	260	.suspend = ata_scsi_device_suspend,
438ac6d5	261	#endif
9b13b682 A	262	};
	263
	264	static const struct ata_port_operations it8213_ops = {
	265	.port_disable = ata_port_disable,
	266	.set_piomode = it8213_set_piomode,
	267	.set_dmamode = it8213_set_dmamode,
	268	.mode_filter = ata_pci_default_filter,
	269
	270	.tf_load = ata_tf_load,
	271	.tf_read = ata_tf_read,
	272	.check_status = ata_check_status,
	273	.exec_command = ata_exec_command,
	274	.dev_select = ata_std_dev_select,
	275
	276	.freeze = ata_bmdma_freeze,
	277	.thaw = ata_bmdma_thaw,
	278	.error_handler = it8213_error_handler,
	279	.post_internal_cmd = ata_bmdma_post_internal_cmd,
5816fbbf	280	.cable_detect = it8213_cable_detect,
9b13b682 A	281
	282	.bmdma_setup = ata_bmdma_setup,
	283	.bmdma_start = ata_bmdma_start,
	284	.bmdma_stop = ata_bmdma_stop,
	285	.bmdma_status = ata_bmdma_status,
	286	.qc_prep = ata_qc_prep,
	287	.qc_issue = ata_qc_issue_prot,
0d5ff566	288	.data_xfer = ata_data_xfer,
9b13b682 A	289
	290	.irq_handler = ata_interrupt,
	291	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	292	.irq_on = ata_irq_on,
246ce3b6 AI	293	.irq_ack = ata_irq_ack,
9b13b682 A	294
9b13b682 A	295	.port_start = ata_port_start,
9b13b682 A	296	};
	297
	298
	299	/**
	300	* it8213_init_one - Register 8213 ATA PCI device with kernel services
	301	* @pdev: PCI device to register
	302	* @ent: Entry in it8213_pci_tbl matching with @pdev
	303	*
	304	* Called from kernel PCI layer.
	305	*
	306	* LOCKING:
	307	* Inherited from PCI layer (may sleep).
	308	*
	309	* RETURNS:
	310	* Zero on success, or -ERRNO value.
	311	*/
	312
	313	static int it8213_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	314	{
	315	static int printed_version;
	316	static struct ata_port_info info = {
	317	.sht = &it8213_sht,
	318	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	319	.pio_mask = 0x1f, /* pio0-4 */
	320	.mwdma_mask = 0x07, /* mwdma0-2 */
	321	.udma_mask = 0x1f, /* UDMA 100 */
	322	.port_ops = &it8213_ops,
	323	};
	324	static struct ata_port_info *port_info[2] = { &info, &info };
	325
	326	if (!printed_version++)
	327	dev_printk(KERN_DEBUG, &pdev->dev,
	328	"version " DRV_VERSION "\n");
	329
	330	/* Current IT8213 stuff is single port */
	331	return ata_pci_init_one(pdev, port_info, 1);
	332	}
	333
	334	static const struct pci_device_id it8213_pci_tbl[] = {
	335	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
	336
	337	{ } /* terminate list */
	338	};
	339
	340	static struct pci_driver it8213_pci_driver = {
	341	.name = DRV_NAME,
	342	.id_table = it8213_pci_tbl,
	343	.probe = it8213_init_one,
	344	.remove = ata_pci_remove_one,
438ac6d5	345	#ifdef CONFIG_PM
9b13b682 A	346	.suspend = ata_pci_device_suspend,
9b13b682 A	347	.resume = ata_pci_device_resume,
438ac6d5	348	#endif
9b13b682 A	349	};
	350
	351	static int __init it8213_init(void)
	352	{
	353	return pci_register_driver(&it8213_pci_driver);
	354	}
	355
	356	static void __exit it8213_exit(void)
	357	{
	358	pci_unregister_driver(&it8213_pci_driver);
	359	}
	360
	361	module_init(it8213_init);
	362	module_exit(it8213_exit);
	363
	364	MODULE_AUTHOR("Alan Cox");
	365	MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
	366	MODULE_LICENSE("GPL");
	367	MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
	368	MODULE_VERSION(DRV_VERSION);